Optical image stabilization control chip

Abstract

The embodiment of the application provides an optical anti-shake control chip, comprising a sensing module, an operation module, an execution module, a storage module, a wake-up controller, a hardware state machine and a power management module. The power management module divides the chip into three power domains of a normal power domain, a maintainable domain and a shutoff domain, the wake-up controller is located in the normal power domain and maintains power supply in a sleep mode; the maintainable domain selectively maintains power supply to maintain firmware programs in a volatile memory; the processor and the compensation controller are located in the shutoff domain and are powered off in the sleep mode. The hardware state machine has a clock domain independent of the processor, reads algorithm parameters from the non-volatile memory and loads the algorithm parameters to the compensation controller in parallel with the start process of the processor when waking up. The embodiment of the application realizes extremely low standby power consumption by setting three power domain isolations, shortens the wake-up time by parallel starting of the hardware state machine and the processor, and simultaneously realizes low standby power consumption and fast wake-up response.

Description

Technical Field

[0001] This application relates to the field of optical image stabilization, and more particularly to an optical image stabilization control chip. Background Technology

[0002] Optical image stabilization (OIS) technology compensates for camera shake through physical means, solving the problem of image blur when shooting handheld. Traditional OIS systems typically consist of a gyroscope sensor, a processor, and a servo motor. The processor calculates the compensation displacement based on the shake signal detected by the gyroscope, and drives the servo motor to adjust the position of the lens optics or image sensor, thereby counteracting the image shift caused by hand shake.

[0003] Currently, optical image stabilization chips still have shortcomings in terms of system integration. Traditional solutions adopt a discrete design, with sensors, processors, and drivers operating independently. Modules need to communicate with each other through an external bus, which not only increases the complexity of peripheral circuits and system size but also introduces communication delays and additional power consumption between chips.

[0004] In terms of power consumption, optical image stabilization chips operate in a unique mode in consumer electronics devices, only needing to run when the user is taking a picture, and remaining in standby mode the rest of the time. However, existing chips still maintain a relatively high power consumption level in standby mode, making it difficult to meet the stringent low power consumption requirements of smartphones and other mobile devices.

[0005] Regarding wake-up speed, existing chips require the processor to reload the firmware from slow, non-volatile memory during wake-up, a process that is time-consuming. Simultaneously, sensor offset calibration must be performed serially after processor startup, further extending the time from wake-up to the start of the image stabilization algorithm. In shooting scenarios, excessive wake-up delays lead to delayed image stabilization response, resulting in a blurry initial frame. This stringent requirement for the quality of the first frame is a significant characteristic that distinguishes optical image stabilization chips from audio or general-purpose chips. Summary of the Invention

[0006] This application aims to solve the technical problems of high standby power consumption and long wake-up delay in existing optical image stabilization chips.

[0007] In a first aspect, this application provides an optical image stabilization control chip, comprising: a sensing module for acquiring position signals of a lens module and external shake signals, and converting the position signals and external shake signals into digital quantities; a computing module including a processor and a compensation controller, wherein the processor is used to run an image stabilization algorithm, and the compensation controller is used to calculate a compensation drive amount based on the digital quantities; an execution module for driving a motor to adjust the lens position based on the compensation drive amount; a storage module including volatile memory and non-volatile memory, wherein the volatile memory is used to store firmware programs, and the non-volatile memory is used to store algorithm parameters; a wake-up controller for listening to external wake-up signals and triggering a wake-up process in sleep mode; and a hardware state machine having a clock independent of the processor. The chip is divided into three power management modules: a constant power domain, a sustainable domain, and a power-off domain. The wake-up controller is located in the constant power domain and maintains power supply in sleep mode. The sustainable domain selectively maintains power supply in sleep mode to maintain the firmware program in the volatile memory. The processor and the compensation controller are located in the power-off domain and are powered off in sleep mode. The wake-up controller responds to the external wake-up signal and controls the three power domains to be powered on sequentially according to a preset timing sequence. The processor loads and executes the firmware program from the volatile memory and executes the anti-bounce algorithm after the hardware state machine completes parameter loading.

[0008] At least one advantage of the optical image stabilization control chip provided in this application is that it achieves extremely low standby power consumption by setting up three-level power domain isolation, and shortens the wake-up time by starting the hardware state machine in parallel with the processor, thus achieving both low standby power consumption and fast wake-up response. Attached Figure Description

[0009] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0010] Figure 1 A schematic diagram of the structure of an optical image stabilization control chip provided for an embodiment of the present invention; Figure 2 A schematic diagram of another optical image stabilization control chip provided for an embodiment of the present invention; Figure 3 Timing diagram of the power switch for the turn-off domain provided for embodiments of the present invention; Figure 4 A schematic diagram of the wake-up process of the wake-up controller provided for an embodiment of the present invention; Figure 5 A schematic diagram of the state transition of a hardware state machine provided for an embodiment of the present invention; Figure 6 A schematic diagram of the parallel startup process of the processor and hardware state machine provided for an embodiment of the present invention; Figure 7 A three-level power domain parallel wake-up timing diagram provided for embodiments of the present invention. Detailed Implementation

[0011] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0012] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0013] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0014] Please see Figure 1 , Figure 1 This is a schematic diagram of the optical image stabilization control chip provided in an embodiment of this application. The chip includes a sensing module 100, a computing module 200, an execution module 300, a storage module 400, a wake-up controller 500, a power management module 600, and a hardware state machine 700. The modules are interconnected via a communication bus 800. An external motor 20 is connected to the chip for adjusting the lens position under the control of the image stabilization algorithm.

[0015] The sensing module 100 is used to collect the position signal and external jitter signal of the lens module, and convert these two signals into digital quantities. The position signal refers to the signal reflecting the current physical position of the lens module, which can be generated by the position sensor built into the chip.

[0016] The so-called external jitter signal refers to the signal detected by external inertial sensors such as gyroscopes, which reflects the jitter state of the device. This signal is input from outside the chip to the sensing module 100. The sensing module 100 conditions and digitizes these two analog signals, and then outputs a digital value for use by the arithmetic module 200.

[0017] The arithmetic module 200 is the control center of the chip, including a processor 210 and a compensation controller 220. The processor 210 is used to run the firmware program for the image stabilization algorithm. The image stabilization algorithm refers to an algorithm that calculates the amount of compensation displacement based on the current position of the lens module and the shaking state of the device, so that the optical elements of the lens can counteract the image shift caused by shaking in real time.

[0018] The compensation controller 220 calculates the compensation drive quantity based on the digital quantity output by the sensing module 100 and outputs the compensation drive quantity to the execution module 300. The compensation drive quantity refers to the control signal required for the drive motor 20 to generate the corresponding displacement.

[0019] In one embodiment, the compensation controller 220 can be implemented using a PID controller, which calculates the control output through a weighted combination of proportional, integral, and derivative terms. Both the processor 210 and the compensation controller 220 interact with other modules within the chip via the communication bus 800.

[0020] The execution module 300 is used to drive the motor 20 to adjust the lens position according to the compensation drive amount output by the compensation controller 220. The digital control signal output by the compensation controller 220 is converted into a precise drive current by the execution module 300 after digital-to-analog conversion, which drives the motor 20 to generate a displacement of corresponding direction and amplitude, so that the lens optical elements are moved to the compensation position, thereby counteracting the effect of equipment shake on imaging.

[0021] The storage module 400 includes volatile memory 410 and non-volatile memory 420. The volatile memory 410 is used to store firmware programs. Firmware programs refer to the instruction code required for the processor 210 to start and run the anti-bounce algorithm. The volatile memory 410 is characterized by its fast read speed, but data is lost when power is off.

[0022] Non-volatile memory 420 is used to store algorithm parameters. Algorithm parameters refer to the configuration parameters required by the compensation controller 220 to execute the anti-jitter algorithm, such as the gain coefficient of the control loop. The characteristic of non-volatile memory 420 is that data is not lost after power failure, but its read speed is relatively slow.

[0023] The wake-up controller 500 is used to listen for external wake-up signals and trigger the wake-up process in sleep mode. An external wake-up signal refers to a signal sent by the device's main control chip that indicates the user needs to use the camera function. When the chip is in sleep mode, the wake-up controller 500 continuously listens for this signal, and once a valid wake-up signal is detected, it triggers the entire chip's wake-up process.

[0024] The hardware state machine 700 has a clock domain independent of the processor 210. An independent clock domain means that the hardware state machine 700 uses its own dedicated clock signal to drive its operation, and its operating cycle does not depend on the system clock of the processor 210. Therefore, the two can run simultaneously without affecting each other.

[0025] The function of the hardware state machine 700 is to read algorithm parameters from the non-volatile memory 420 and load them into the compensation controller 220 in parallel with the startup process of the processor 210 upon wake-up. For example... Figure 1 As shown, the non-volatile memory 420 is connected to the hardware state machine 700 via a communication bus 800.

[0026] In traditional solutions, reading algorithm parameters requires waiting for the processor 210 to start up before execution can proceed serially, resulting in a long wake-up latency. This application introduces a hardware state machine 700 with an independent clock domain, enabling parameter reading and processor startup to be executed in parallel. The total wake-up time is equal to the longer of the two paths, rather than the sum of the two, thus significantly reducing the wake-up latency.

[0027] The power management module 600 divides the chip into three power domains: a constant power domain, a retainable domain, and a power-off domain. The constant power domain is the area that maintains power supply in all operating states of the chip. The retainable domain is the area that can selectively maintain or disable power supply in sleep mode. The power-off domain is the area that is completely disconnected from power in sleep mode.

[0028] like Figure 1 As shown, the wake-up controller 500 and the power management module 600 are located in the constant power supply domain. The wake-up controller 500 must always be online to listen for external wake-up signals, and the power management module 600 must always be online to control the power switches of other power supply domains; therefore, both are located in the constant power supply domain.

[0029] The volatile memory 410 is located in the retainable domain. In hibernation mode, the retainable domain can selectively maintain power to preserve the firmware program in the volatile memory 410. If power is maintained, the processor 210 can directly read the firmware program from the volatile memory 410 and start up quickly after wake-up, without having to reload from the slower non-volatile memory 420, thereby significantly reducing the boot time.

[0030] If a power outage is selected in scenarios where power consumption is extremely sensitive, the firmware program needs to be moved from non-volatile memory 420 to volatile memory 410 after waking up, which increases the startup time accordingly. Whether to maintain power supply can be determined by the user through programming based on power consumption and wake-up speed requirements.

[0031] The processor 210 and compensation controller 220 are located in the shut-off domain. These modules operate at high frequencies and consume a lot of power. If they are kept powered on in sleep mode, leakage power consumption alone will consume a large amount of battery power. Therefore, their power is completely disconnected in sleep mode to reduce leakage power consumption to zero. Since the firmware program is pre-stored in the volatile memory 410 of the retainable domain and the algorithm parameters are permanently stored in the non-volatile memory 420, no critical information will be lost when the shut-off domain is powered off.

[0032] The three-level power domain structure minimizes the power consumption cost of "always online" through fine-grained power domain partitioning (extremely low leakage current in the constant power domain), while maintaining the ability to quickly start up by keeping the domains intact, thus achieving an optimal balance between low standby power consumption and fast wake-up.

[0033] The optical image stabilization control chip operates as follows: When the chip is in sleep mode, only the constant power supply domain maintains power, and the wake-up controller 500 continuously listens for external wake-up signals. When the user opens the camera application, the device's main control chip sends an external wake-up signal.

[0034] In response to the external wake-up signal, the wake-up controller 500 notifies the power management module 600 to control the three power domains to be powered on sequentially according to a preset timing sequence: first, power is supplied to the persistent domain to make the volatile memory 410 ready, and then power is supplied to the shut-off domain to make the processor 210 and the compensation controller 220 ready.

[0035] After power-on, two paths proceed in parallel: the processor 210 loads and executes the firmware program from the volatile memory 410 for initialization; the hardware state machine 700 simultaneously reads the algorithm parameters from the non-volatile memory 420 and loads them into the compensation controller 220.

[0036] Once the processor 210 has completed initialization and the hardware state machine 700 has completed parameter loading, the processor 210 begins to execute the anti-shake algorithm, and the optical image stabilization control chip enters the normal anti-shake control working mode.

[0037] In the image stabilization control mode, the sensing module 100 continuously collects position signals and external shake signals and converts them into digital quantities. The calculation module 200 calculates the compensation drive quantity in real time based on the digital quantity, and the execution module 300 drives the motor 20 to adjust the lens position according to the compensation drive quantity, forming a complete closed-loop control. When the user closes the camera application, the device's main control chip sends a sleep command, and the power management module 600 shuts down the power to the turn-off and hold-up domains according to a preset timing sequence, and the chip re-enters sleep mode.

[0038] Please see Figure 2 , Figure 2 This is a schematic diagram of another optical image stabilization control chip provided in an embodiment of this application. Figure 2 As shown, the sensing module 100 includes a position sensor 120, a signal conditioning circuit 110, and an analog-to-digital converter 130.

[0039] Position sensor 120 is used to detect the current physical position of the lens module and output a position signal. In one embodiment, position sensor 120 can be implemented as a Hall sensor, which uses the Hall effect to sense changes in the magnetic field strength generated by a permanent magnet fixed on the lens module, thereby indirectly calculating the displacement of the lens. In another embodiment, position sensor 120 can also be replaced by a magnetic sensor selected by the user. The output of position sensor 120 is connected to analog-to-digital converter 130.

[0040] The signal conditioning circuit 110 is used to preprocess jitter signals input from outside the chip. For example... Figure 2 As shown, the external jitter signal is input from outside the chip to the signal conditioning circuit 110, and after processing, it is also connected to the analog-to-digital converter 130.

[0041] The signal conditioning circuit 110 internally includes a low-noise amplifier, an anti-aliasing filter, and a temperature drift compensation circuit cascaded in sequence. The low-noise amplifier amplifies weak external jitter signals to an amplitude range suitable for quantization by the analog-to-digital converter 130, minimizing the introduction of additional noise during amplification. The anti-aliasing filter is a low-pass analog filter with a cutoff frequency set below half the sampling rate of the analog-to-digital converter 130 to prevent high-frequency noise from folding into the signal band during sampling and causing irreversible distortion. The temperature drift compensation circuit compensates for the effects of temperature variations on amplifier gain and bias voltage, ensuring consistent transmission characteristics of the signal conditioning link under different temperature conditions.

[0042] The analog-to-digital converter 130 aggregates the position signal from the position sensor 120 and the external jitter signal from the signal conditioning circuit 110, converting these two analog signals into digital quantities. In one embodiment, the analog-to-digital converter 130 employs a 12-16 bit SAR (Successive Approximation) architecture, which offers advantages such as low power consumption, small size, and moderate conversion speed, making it suitable for power-sensitive applications like optical image stabilization. The analog-to-digital converter 130 uses synchronous sampling for the two signals, sampling and quantizing them simultaneously to eliminate control errors caused by sampling time differences. The digital quantity output by the analog-to-digital converter 130 is transmitted to the arithmetic module 200 via the communication bus 800.

[0043] like Figure 2 As shown, the arithmetic module 200 includes a processor 210 and a compensation controller 220, both of which interact with other modules within the chip via a communication bus 800.

[0044] Processor 210 is responsible for running the firmware program of the image stabilization algorithm. In one embodiment, processor 210 is implemented using a microcontroller unit (MCU) core, which can run the complete image stabilization firmware algorithm and support user-customized calibration parameter adjustments, loop gain configuration, and function expansion. In another embodiment, processor 210 can also be replaced with a dedicated DSP (digital signal processor) according to user needs. DSPs are more efficient in repetitive mathematical operations and are suitable for scenarios with extreme requirements for algorithm performance.

[0045] The compensation controller 220 is used to calculate the compensation drive quantity based on the digital quantity output by the sensing module 100. In one embodiment, the compensation controller 220 is implemented using a PID controller. As mentioned earlier, the PID controller calculates the control output based on a weighted combination of the proportional term of the current position error, the integral term of the accumulated error history, and the derivative term of the error change trend. The proportional coefficient Kp determines the response speed, the integral coefficient Ki eliminates steady-state error, and the derivative coefficient Kd suppresses oscillations.

[0046] The proportional coefficient Kp, integral coefficient Ki, and differential coefficient Kd are the core components of the algorithm parameters stored in the non-volatile memory 420, and they need to be adjusted separately for different lens modules and motor characteristics. The compensation controller 220 can be implemented by hardware circuitry to achieve the lowest control latency, or by processor 210 through firmware software to achieve maximum flexibility, or a hybrid approach combining hardware accelerators and software can be used.

[0047] like Figure 2 As shown, the storage module 400 includes a volatile memory 410 and a non-volatile memory 420.

[0048] Volatile memory 410 is used to store the firmware program required by processor 210 to run the anti-bouncing algorithm. In one embodiment, volatile memory 410 is implemented using a 7T SRAM structure with a capacity of 4-8KB. Compared with standard 6T SRAM, 7T SRAM adds an isolation transistor for the read port. Its advantage is that read operations do not interfere with the data state of the storage node, so data can be reliably maintained at a lower voltage without bit flipping, thereby reducing the power consumption of the data holding state.

[0049] The volatile memory 410 is connected to the processor 210 via the communication bus 800 after signal isolation. As mentioned above, the volatile memory 410 is located in the retainable domain and can selectively maintain power supply in sleep mode to maintain the firmware program, so that the processor 210 can directly load the firmware program from it and start up quickly after waking up.

[0050] Non-volatile memory 420 is used to store data that needs to be permanently saved, such as algorithm parameters and temperature compensation coefficients required by the offset calibration module 1100. In one embodiment, non-volatile memory 420 is implemented using EFLASH with a capacity of 1-2KB. A key feature of non-volatile memory 420 is that data is not lost after power failure; therefore, power failure in the shutdown domain does not affect the data stored therein. Figure 2 As shown, the non-volatile memory 420 is connected to the processor 210 and the compensation controller 220 via the communication bus 800, and also to the hardware state machine 700. The hardware state machine 700 independently reads the algorithm parameters from the non-volatile memory 420 upon wake-up via this connection, without the need for the processor 210.

[0051] like Figure 2 As shown, the compensation drive quantity calculated by the compensation controller 220 is a digital signal, which needs to be converted into an analog control signal by the digital-to-analog converter 900 before it can drive the motor 20 to produce mechanical displacement. The output of the digital-to-analog converter 900 is connected to the execution module 300 after signal isolation.

[0052] In one embodiment, the execution module 300 is implemented using a multi-channel H-bridge constant current driver, integrating 2 to 4 independent H-bridge channels, each corresponding to compensation motion along different axes such as the X-axis and Y-axis. An H-bridge is a bridge circuit topology composed of four switching devices. By controlling the on / off combinations of the four switches, current can flow forward or backward through the motor 20, thereby driving the motor to move forward or backward. Each channel can output a precise constant current of ±100mA to ±200mA, adapting to the driving requirements of mainstream VCM voice coil motors, with an internal resistance as low as 1.8Ω to improve driving efficiency. The output of the execution module 300 is connected to the external motor 20.

[0053] like Figure 2 As shown, the wake-up controller 500 receives an external wake-up signal from outside the chip and connects to the power management module 600. When the wake-up controller 500 detects a valid external wake-up signal, it notifies the power management module 600 to start the wake-up process, controlling the three power domains to power on sequentially according to a preset timing sequence.

[0054] like Figure 2 As shown, the hardware state machine 700 is connected to the non-volatile memory 420 for independently reading algorithm parameters upon wake-up. The hardware state machine 700 has a clock domain independent of the processor 210, driven by a dedicated 50MHz clock in one embodiment. This independent clock domain allows the hardware state machine 700 to run independently before the processor 210 has finished booting, performing the reading and loading of algorithm parameters in parallel. After reading the algorithm parameters, the hardware state machine 700 loads them into the compensation controller 220.

[0055] like Figure 2 As shown, the offset calibration module 1100 is connected to the sensing module 100, the non-volatile memory 420, and the compensation controller 220, respectively. The offset calibration module 1100 obtains the current output signal and temperature signal from the sensing module 100, retrieves the pre-calibrated temperature compensation coefficient from the non-volatile memory 420, calculates the sensor offset based on these inputs, and writes the calibration result into the offset compensation register of the compensation controller 220. After calibration, the compensation controller 220 automatically subtracts the offset from the position feedback signal in subsequent control operations, ensuring that the controller receives calibrated, true displacement information.

[0056] like Figure 2 As shown, the communication bus 800 spans the entire chip, interconnecting modules such as the processor 210, compensation controller 220, analog-to-digital converter 130, and non-volatile memory 420. In one embodiment, the communication bus 800 is implemented using the AHB bus protocol, which supports burst transmission and pipelined operation to meet the data exchange needs between modules. In another embodiment, users can also use more complex AMBA bus protocols such as AXI or CHI, depending on their needs. Figure 2 As shown, the volatile memory 410 is connected to the communication bus 800 after signal isolation. The purpose of this signal isolation is to prevent interference caused by the transmission of signals across the power domain between the retainable domain and the turn-off domain.

[0057] like Figure 2As shown, the debug interface 1200 is connected to the communication bus 800 and externally connected to the control signals of the device's main control chip. The debug interface 1200 is used for communication between the chip and the main control chip, as well as for debugging and upgrading firmware programs. In one embodiment, the debug interface 1200 supports three communication protocols: I3C (up to 12.5MHz), SPI, and I2C. Users can select one or more protocols for communication according to their actual needs.

[0058] like Figure 1 and Figure 2 As shown, the always-on power domain includes a wake-up controller 500 and a power management module 600. Both modules must remain operational in all operating states of the chip; otherwise, the chip will be unable to respond to external wake-up signals or control the power switches of other power domains. Therefore, the design goal of the always-on power domain is to minimize the power consumption cost of "always-on" operation.

[0059] At the transistor level, the constant-supply domain uses a high-threshold-voltage standard cell library for design and synthesis. The subthreshold leakage current of a CMOS transistor is exponentially related to its threshold voltage; the higher the threshold voltage, the lower the subthreshold leakage current. The threshold voltage of the standard cell library used in the constant-supply domain is higher than that used in the turn-off domain, reducing the leakage current of the constant-supply domain by one to two orders of magnitude compared to the turn-off domain. The trade-off is slower switching speed and weaker drive capability for high-threshold-voltage devices. However, the logic functions of the wake-up controller 500 and power management module 600 in the constant-supply domain are simple, and speed is not a critical factor, making this trade-off acceptable.

[0060] At the supply voltage level, the supply voltage of the constant supply domain is lower than that of the turn-off domain. In one embodiment, the constant supply domain is supplied with 1.8V, and the turn-off domain is supplied with 5V. The static power consumption of CMOS circuits exhibits a superlinear relationship with the supply voltage; reducing the supply voltage can significantly reduce leakage power consumption.

[0061] At the clock frequency level, the wake-up controller 500 operates at a lower clock frequency than the processor 210. In one embodiment, the wake-up controller 500 is driven by a low-frequency clock of 8kHz, while the processor 210 operates at a clock frequency in the tens of MHz range. The dynamic power consumption of CMOS digital circuits is proportional to the clock frequency; 8kHz is more than three orders of magnitude lower than tens of MHz, making the dynamic power consumption almost negligible. Through this method, the quiescent current in the constantly powered domain can be controlled below 2μA.

[0062] like Figure 1 and Figure 2As shown, the retainable domain includes volatile memory 410. As previously mentioned, volatile memory 410 stores the firmware program required for the processor 210 to boot. The retainable domain is designed to retain data in sleep mode at extremely low power cost, enabling the processor 210 to directly read the firmware program from volatile memory 410 and boot quickly after waking up, without having to reload from the slower non-volatile memory 420.

[0063] In one embodiment, the volatile memory 410 employs a 7T SRAM structure, operates at 3.3V, and has a quiescent current of less than 1μA in data retention mode. Whether the retainable domain maintains power supply in sleep mode can be determined by the customer through programming, providing a flexible trade-off between power consumption and wake-up speed: for scenarios with extremely high requirements for the first frame image quality (such as the rear main camera of a smartphone), power supply can be maintained in exchange for extremely fast wake-up speed; for scenarios that are extremely sensitive to power consumption but can tolerate a slightly longer wake-up time (such as a low-end front camera), power can be cut off, and the firmware program can be reloaded from the non-volatile memory 420 upon wake-up.

[0064] like Figure 1 and Figure 2 As shown, the shutdown domain includes high-performance computing and data transmission modules such as processor 210, compensation controller 220, non-volatile memory 420, hardware state machine 700, and communication bus 800. These modules operate at high frequencies and are designed using a low threshold voltage standard cell library to meet timing requirements. Low threshold voltage devices have fast switching speeds, but their leakage current is one to two orders of magnitude higher than that of high threshold voltage devices. If power is maintained in sleep mode, leakage power consumption alone will consume a large amount of battery power.

[0065] Therefore, in sleep mode, the power supply to the shut-off domain is completely disconnected, reducing leakage power consumption to zero. As mentioned earlier, the firmware program is pre-stored in the volatile memory 410 of the retainable domain, while the algorithm parameters and temperature compensation coefficients are permanently stored in the non-volatile memory 420 (the non-volatile memory does not lose data when power is off). The shut-off domain will not lose any critical information when power is off, and it can resume operation upon power-on upon wake-up.

[0066] In one embodiment, the shut-off domain is powered by 3.3V or 5V, and the processor 210 operates at a clock frequency of tens of MHz.

[0067] In sleep mode, the quiescent current of the constantly powered domain is less than 2μA, the quiescent current of the power-on domain (if powered) is less than 1μA, and the power consumption of the power-off domain is zero when completely powered off. The total standby power consumption of the chip does not exceed 3μA (when the volatile memory is powered) or does not exceed 2μA (when the volatile memory is powered off). Compared with the standby power consumption of approximately 4.5μA of existing optical image stabilization chips, the standby power consumption of the optical image stabilization chip provided in this application is reduced by at least 40%, which can better meet the stringent low power requirements of mobile devices such as smartphones.

[0068] In a three-level power domain architecture, the turn-off domain is completely de-energized in sleep mode. When the power supply to the turn-off domain is cut off, the digital logic outputs of the modules in that domain are in an uncertain floating state, which may drift slowly or produce random jumps. If these uncertain signals are directly transmitted to the always-powered domain or the always-powered domain, they may trigger malfunctions in the wake-up controller 500 or the power management module 600 in the always-powered domain. Furthermore, during the transition from power-off to power-on in the turn-off domain, the signal level may jump from an uncertain state to a definite state, generating voltage surges that impact devices in the always-powered area. Therefore, all signals transmitted from the turn-off domain to other power domains need to be isolated.

[0069] like Figure 2 As shown, signal isolation is implemented in the chip for signal transmission paths across power domains. Signals transmitted from modules located in the turn-off domain to other power domains are output after logical operations are performed between logic gates and the power enable signal of the turn-off domain.

[0070] The so-called power enable signal refers to the control signal generated by the power management module 600, which represents the power on / off state of the turn-off domain. When the turn-off domain is powered on, the signal is at a high level, and when the turn-off domain is powered off, the signal is at a low level.

[0071] In one embodiment, the logic gate is implemented using an AND gate. One input of the AND gate is connected to the output signal of the module in the turn-off domain, the other input is connected to the power enable signal of the turn-off domain, and the output of the AND gate is connected to the target module in another power domain.

[0072] When the turn-off domain is powered normally, the power enable signal is high, and the AND gate transparently transmits the output signal of the turn-off domain module, without affecting signal transmission during normal operation. When the turn-off domain is powered off, the power enable signal goes low, and regardless of the uncertain state of the turn-off domain module's output signal, the AND gate's output is forced to a low level. This effectively isolates uncertain signals from propagating to the normally powered and holdable domains, while also preventing voltage surges during the power-off transition of the turn-off domain from power-off to power-on from impacting other power domain devices.

[0073] like Figure 2 As shown, there are two signal isolation points in the chip. One is located between the volatile memory 410 and the communication bus 800. Since the volatile memory 410 is located in the retainable domain and the communication bus 800 is located in the turn-off domain, they belong to different power domains, and cross-domain signals need to be isolated. The other is located between the digital-to-analog converter 900 and the execution module 300. The digital-to-analog converter 900 is located in the turn-off domain, and its output analog control signal needs to be isolated before it can be transmitted to the execution module 300 to drive the motor 20.

[0074] In another embodiment, the logic gate can also be implemented using other gate circuits such as NOR gates, as long as it can clamp the output to a fixed level when the turn-off domain is powered off. The specific logic polarity can be selected to clamp to a high level or a low level according to the circuit design requirements.

[0075] Please see Figure 3 , Figure 3 The timing diagram of the power switch for the turn-off domain provided in the embodiments of this application. Figure 3 The timing waveforms of four signals are shown from top to bottom: module working signal, reset signal, power enable signal, and external wake-up signal.

[0076] The module operating signal is a flag signal indicating that the module in the turn-off domain has entered normal operating state. A high level indicates the module is operating normally, and a low level indicates the module is in a non-operating state. The reset signal is a reset control signal sent by the power management module 600 to the module in the turn-off domain. A low level indicates the module is in a reset state, and a high level indicates the module has exited the reset state. The power enable signal is a signal used by the power management module 600 to control the power supply to the turn-off domain. As described in the signal isolation section above, a high level indicates the turn-off domain is powered on, and a low level indicates the turn-off domain is powered off.

[0077] When the device's main control chip sends a hibernation command, the power management module 600 controls the shut-off domain to enter hibernation mode according to the following timing sequence.

[0078] First, the module's operating signal goes low, causing the processor 210 and compensation controller 220 in the turn-off domain to stop their current computational tasks. Then, the power management module 600 sends a reset signal to the modules in the turn-off domain, causing the reset signal to go low and putting the processor 210, compensation controller 220, and other modules into a reset state. Entering the reset state means that all registers and outputs return to their defined initial values, and the module's output is no longer in an uncertain state. After confirming the reset is complete, the power management module 600 then disconnects the power supply to the turn-off domain, and the power enable signal goes low.

[0079] The aforementioned "reset first, then power off" sequence ensures that modules in the turn-off domain are in a known, definite state before the power is cut off. If the order is reversed, power off first and then reset, the module's output will be in an uncertain state at the moment of power off, potentially causing glitches through the transient window before signal isolation as described above, affecting modules still operating in the constant power supply domain and the holdable domain.

[0080] When the wake-up controller 500 detects a valid external wake-up signal, it notifies the power management module 600 to initiate the wake-up process. For example... Figure 3 As shown, after the external wake-up signal has a valid trigger edge, the power management module 600 controls the shutdown domain to resume operation according to the following timing sequence.

[0081] First, the power management module 600 connects the power supply to the turn-off domain, and the power enable signal goes high. At this time, the turn-off domain begins to power on, but the supply voltage needs to undergo a climb-up process from zero to a stable value. After the power management module 600 waits for the supply voltage of the turn-off domain to stabilize (in one embodiment, this waiting time is approximately 50 μs), the reset signal is withdrawn, and the reset signal goes high. The processor 210 and compensation controller 220 in the turn-off domain exit the reset state and begin operation, and the module operating signal subsequently goes high.

[0082] The above-described sequence of "powering on first and then releasing the reset signal" ensures that the supply voltage is sufficiently stable when the module in the turn-off domain starts operating. If the sequence is reversed and the reset signal is released before the voltage is stable, the module may start operating under insufficient power supply, potentially leading to metastability or logic errors, resulting in unpredictable system behavior.

[0083] The power switching sequence of the sustainable domain is similar to that of the shut-off domain, also following the principles of "reset before power off" and "power on before release reset." The difference lies in whether the sustainable domain is powered off in sleep mode, which is determined by the customer through programming. If the customer chooses to keep the sustainable domain powered during sleep, the domain's power supply remains on, and the power switching sequence is not affected. If the user chooses to disconnect the sustainable domain power during sleep, upon waking, the sustainable domain must be powered on first, and the voltage must be allowed to stabilize before powering on the shut-off domain.

[0084] In some embodiments of this application, the wake-up controller 500 includes a comparator and an address matching circuit. The comparator is used to detect level changes of the external interface, and the address matching circuit is used to receive address information via a bus protocol and match it with a preset address after the comparator detects a level change.

[0085] Please see Figure 4 , Figure 4 This is a schematic diagram of the wake-up process of the wake-up controller provided in an embodiment of this application. The wake-up process includes the following steps.

[0086] Step S100: Detect the level change of the external interface.

[0087] When the chip is in sleep mode, the device's main control chip is connected to the wake-up controller 500 via a GPIO interface. When the user opens the camera application, the main control chip pulls the voltage of the GPIO interface high. The comparator in the wake-up controller 500 continuously monitors the voltage level of this interface. When the comparator detects a change from low to high, it determines it as a valid wake-up trigger event and proceeds to the next step. Because the comparator is located in a constantly powered domain and driven by a low-frequency clock, the power consumption during its continuous monitoring process is extremely low. As described in the previous embodiment, the quiescent current of the entire constantly powered domain is less than 2μA.

[0088] Step S200: Detect whether a valid protocol timing sequence appears on the communication bus.

[0089] After the comparator detects a level change, the address matching circuit begins listening to signals on the communication bus. In one embodiment, this communication bus uses the I2C protocol, and the address matching circuit detects whether a start condition and clock signal conforming to the I2C protocol specification appear on the bus. If no valid protocol timing is detected, it is determined to be an interference signal, and the controller 500 is woken up and returns to step S100 to continue listening. If a valid protocol timing is detected, the process proceeds to the next step. The purpose of this step is to filter out false triggers of GPIO levels, ensuring that only genuine I2C communication from the main control chip can advance the wake-up process.

[0090] Step S300: Match the preset address.

[0091] The address matching circuit receives slave address information sent by the master control chip from the bus and compares it with a preset address pre-configured within the chip. The preset address is an address used to identify the chip, either at the factory or programmed by the customer. If the received address matches the preset address, the chip is confirmed as the wake-up target, triggering the wake-up process and notifying the power management module 600 to power on each power domain according to a preset timing sequence. If the address does not match, the chip does not respond and remains in sleep mode.

[0092] In smartphones and other multi-camera devices, separate optical image stabilization (OIS) chips are typically used for the front and rear cameras. If there is no mechanism to differentiate between them when the wake-up signal is activated, the user may accidentally wake up the front camera's OIS chip when opening the rear camera, resulting in unnecessary power consumption.

[0093] To solve this problem, such as Figure 4 As shown, the preset address is bound to the lens corresponding to the chip. Multiple optical image stabilization control chips correspond to different lenses and are configured with different preset addresses.

[0094] In one embodiment, the optical image stabilization control chip corresponding to the first lens (such as a rear camera) is configured with a first preset address, and the optical image stabilization control chip corresponding to the second lens (such as a front camera) is configured with a second preset address.

[0095] When the user turns on the rear camera, the main control chip sends a first preset address on the I2C bus. Each chip's address matching circuit independently compares the received address with its own preset address. If the chip corresponding to the first lens successfully matches (step S400), it triggers the wake-up process and enters working mode; if the chip corresponding to the second lens fails to match (step S500), it does not respond to the address information and continues to remain in sleep mode.

[0096] Conversely, when the user turns on the front-facing camera, the main control chip sends a second preset address, waking up only the chip corresponding to the second lens. Through this address-based selective wake-up mechanism, each chip independently responds to address information matching its own preset address, and does not respond to address information matching other chips, thus avoiding the problem of false wake-ups in multi-camera devices.

[0097] In one embodiment, the preset address is not limited to two, but can be extended to more different addresses, corresponding to multi-lens configurations such as triple-camera, quad-camera, etc. Each optical image stabilization control chip is configured with a unique preset address. The main control chip can accurately wake up the target chip by sending the corresponding address according to the camera selected by the user. After the wake-up controller 500 completes the address matching and triggers the wake-up process, the power management module 600 is powered on sequentially according to the preset timing sequence of the holdable domain and the turn-off domain as described in the previous embodiment. Subsequently, the processor 210 and the hardware state machine 700 start in parallel.

[0098] In some embodiments of this application, the hardware state machine 700 is a specific digital logic circuit consisting of a set of state registers and combinational logic gates. The state registers record the current state, and the combinational logic gates determine the next state and the control signal to be output based on the current state and external input signals. At each clock edge, the state register is updated to the next state, and the combinational logic gates generate a new output. This process continues step by step, automatically operating according to preset state transition rules, without the need for any instructions from the processor 210.

[0099] In one embodiment, the hardware state machine 700 is driven by an independent 50MHz clock. This clock is independent of the system clock of the processor 210, so the hardware state machine 700 can start working under its own clock while the processor 210 is still in the instruction fetch startup phase.

[0100] Please see Figure 5 , Figure 5This is a schematic diagram of the state transitions of a hardware state machine provided in an embodiment of this application. The hardware state machine 700, starting from receiving a wake-up signal, sequentially goes through the following states.

[0101] Idle State (S111): The initial state of the hardware state machine 700. After the power management module 600 completes the power-on of the turn-off domain, the hardware state machine 700 starts running from the idle state.

[0102] Power-on state (S112): The hardware state machine 700 waits for the supply voltage of the turn-off domain to stabilize. In one embodiment, the waiting time is approximately 50 μs. After the voltage stabilizes, it proceeds to the next state.

[0103] Non-volatile memory initialization state (S113): The hardware state machine 700 sends an initialization command to the non-volatile memory 420, causing it to exit the low-power mode and enter the readable state. The non-volatile memory 420 is in a power-off state during the power-off period of the turn-off domain, and needs to be initialized after power-on before it can respond to read operations.

[0104] Address setting state (S114): The hardware state machine 700 sets the starting storage address of the algorithm parameters in the non-volatile memory 420. As described in the previous embodiment, the non-volatile memory 420 stores various data such as algorithm parameters and temperature compensation coefficients. These data are stored in different address areas, and the hardware state machine 700 needs to position the read pointer to the starting address of the algorithm parameters.

[0105] Read command status (S115): The hardware state machine 700 sends a read command to the non-volatile memory 420, instructing it to start outputting data from the starting address.

[0106] Data Acquisition State (S116): The non-volatile memory 420 responds to the read command and outputs the algorithm parameter data byte by byte to the hardware state machine 700. Driven by its own 50MHz clock, the hardware state machine 700 receives data step by step and temporarily stores it in its internal cache register. This process runs completely independently of the processor 210, does not occupy the bandwidth of the communication bus 800, and does not compete for resources with the processor 210.

[0107] Verification State (S117): The hardware state machine 700 performs integrity verification on the read algorithm parameters. Integrity verification refers to verifying whether errors have occurred during data storage and retrieval using a specific verification algorithm. The non-volatile memory 420 may experience bit degradation after extreme temperatures or prolonged use. If erroneous algorithm parameters are loaded into the compensation controller 220, it will cause abnormal control behavior of the anti-bounce algorithm. In one embodiment, integrity verification is implemented using the Cyclic Redundancy Check (CRC) algorithm. The hardware state machine 700 calculates the CRC check value based on the read data and compares it with the standard check value pre-stored in the non-volatile memory 420.

[0108] After verifying the status, the path branches into two paths based on the verification result: Path verification passed: If the verification value matches, it means that the read algorithm parameters are complete and correct, and the hardware state machine 700 enters the data valid state (S121).

[0109] Path where verification fails: If the verification value does not match, it indicates that the data may be erroneous, and the hardware state machine 700 enters the retry state (S131). In the retry state, the hardware state machine 700 rereads the algorithm parameters from the non-volatile memory 420 and performs integrity verification again. In one embodiment, the maximum number of retries is 3. If the verification still fails after multiple retries, the hardware state machine 700 can notify the processor 210 to handle the exception via an interrupt.

[0110] Parameter loading state (S122): After successful verification, the hardware state machine 700 writes the algorithm parameters from the internal cache register into the configuration register of the compensation controller 220. As described in the previous implementation, the algorithm parameters include control loop parameters such as the proportional coefficient Kp, integral coefficient Ki, and derivative coefficient Kd of the PID controller. After loading is complete, the compensation controller 220 has the correct control parameters and can immediately start calculation after the processor 210 starts the anti-jitter algorithm.

[0111] Notifying the processor of the parameter ready state (S132): This is executed in parallel with the parameter loading state S122. The hardware state machine 700 sets the parameter ready flag in the status register and triggers an interrupt signal to the processor 210, notifying the processor 210 that the algorithm parameters have been loaded.

[0112] Completion State (S123): After the parameter loading state S122 is completed, the hardware state machine 700 sends a read completion signal and enters the completion state, ending the entire parameter reading and loading process.

[0113] After loading the aforementioned algorithm parameters, the hardware state machine 700 also performs sensor offset calibration in parallel during the startup process of the processor 210. As described in the previous embodiment, the output of the position sensor 120 is affected by environmental factors such as temperature and packaging stress, resulting in offset errors. If the anti-shake algorithm is started without calibrating this offset, the compensation controller 220 will calculate the compensation drive based on the position information containing the error, leading to a deterioration in the anti-shake effect of the first frame. Therefore, an offset calibration needs to be performed after each wake-up and before the anti-shake algorithm is started.

[0114] If the calibration operation is left to be performed serially by the processor 210 after startup, the time window during the processor 210 startup period is wasted, increasing the total latency from wake-up to the start of the debouncing algorithm. This application utilizes the time window during which the hardware state machine 700 is still active after parameter loading is completed and the processor 210 is not yet ready, so that the hardware state machine 700 automatically performs the calibration operation, completely hiding the calibration time within the startup time of the processor 210.

[0115] The specific calibration process is as follows: The hardware state machine 700 triggers the analog-to-digital converter 130 to sample the sensor output signal and temperature signal of the sensing module 100 through the control interface. The control interface refers to the hardware connection path between the hardware state machine 700 and the analog-to-digital converter 130, enabling the hardware state machine 700 to independently control the analog-to-digital converter 130 to perform sampling operations when the processor 210 is not ready. The analog-to-digital converter 130 samples four channels: the triaxial sensor output signal and the temperature signal. In one embodiment, with a sampling rate of 1 MS / s, the sampling time is approximately 4 μs.

[0116] After sampling is completed, the hardware state machine 700 calculates the sensor offset based on the temperature compensation coefficient read from the non-volatile memory 420 and the sampling result using its built-in multiply-accumulate unit. The multiply-accumulate unit refers to the fixed-point arithmetic circuit integrated inside the hardware state machine 700, which is capable of performing multiplication and accumulation operations.

[0117] As described in the previous embodiment, the temperature compensation coefficients have been read from the non-volatile memory 420 during the parameter loading phase, and the hardware state machine 700 can directly use these coefficients for calculation. The calculation of the three-axis offset requires a total of 34 fixed-point multiplication and addition operations, which takes less than 1 μs at a 50MHz clock. Including sampling time and state transition overhead, the entire calibration process can be completed in about 10~20 μs.

[0118] After calibration, the hardware state machine 700 writes the triaxial calibration results into the offset compensation register of the compensation controller 220. In subsequent control calculations, the compensation controller 220 automatically subtracts this offset from the position feedback signal, ensuring that the controller receives calibrated, true displacement information.

[0119] Comparing the above process with the startup process of processor 210, the process of processor 210 fetching instructions from volatile memory 410 to start up and initialize peripherals takes approximately 200μs. During this period, hardware state machine 700 sequentially completes non-volatile memory initialization, algorithm parameter reading, integrity verification, parameter loading, and offset calibration, which takes approximately 150μs in total. The two paths are executed in parallel, and the total time depends on the longer one, namely the startup time of processor 210, which is approximately 200μs. All the work of hardware state machine 700 is completely hidden within this time window, without adding any additional wake-up delay.

[0120] After the processor 210 completes initialization, it checks the parameter ready flag and calibration complete flag in the status register. Since the hardware state machine 700 has completed all its work in about 150μs, both flags are set when the processor 210 checks in about 200μs, and the system immediately enters the anti-bounce algorithm execution phase.

[0121] Please see Figure 6 , Figure 6 A schematic diagram of the parallel startup process of the processor and hardware state machine provided for the embodiments of this application.

[0122] After the wake-up signal is triggered (step S141), the power management module 600 initiates a three-level power domain power-on sequence (step S142). As described in the previous embodiment, the power management module 600 powers on the power domains sequentially according to a preset timing order of first the retainable domains and then the turn-off domains. After the power-on sequence is completed, the process branches into two parallel paths that proceed simultaneously.

[0123] Path 1 is the processor boot path, which begins execution immediately after the persistent domain is powered on, and includes: Step S151: The volatile memory 410 is powered by 3.3V. The power management module 600 first connects the power to the persistent domain, and the volatile memory 410 starts to power on.

[0124] Step S152: Wait 50μs for the voltage to stabilize. The supply voltage needs a certain amount of time to rise from zero to 3.3V; reading data before the voltage has stabilized may result in bit errors.

[0125] Step S153: The processor 210 fetches instructions from the volatile memory 410 to start. As described in the previous embodiments, if the volatile memory 410 is powered on in hibernation mode, the firmware data therein is intact, and the processor 210 can directly read instructions from it and begin execution, resulting in a much faster startup speed than the traditional method of loading from the non-volatile memory 420. If the volatile memory 410 is powered off during hibernation, the firmware needs to be transferred from the non-volatile memory 420 to the volatile memory 410 before fetching instructions, thus increasing the startup time.

[0126] Step S154: Processor 210 initializes peripherals. Processor 210 executes the initialization code in the firmware program to configure the operating parameters of each on-chip peripheral module, including the sampling rate of analog-to-digital converter 130, the output range of digital-to-analog converter 900, the drive parameters of execution module 300, and the communication protocol of debug interface 1200. After initialization, processor 210 has the basic conditions to run the anti-bounce algorithm, but it still needs to confirm whether the hardware state machine 700 has completed loading the algorithm parameters.

[0127] Path two is the hardware state machine parameter loading path, which begins execution immediately after the shut-off domain is powered on. It overlaps with the processor startup path in time and includes: Step S161: Power supply 5V to the shut-off domain. After the retainable domain is powered on, the power management module 600 connects the power supply to the shut-off domain.

[0128] Step S162: Wait 50μs for the voltage to stabilize. Similar to step S152, the modules can only operate reliably after the supply voltage of the turn-off domain has stabilized.

[0129] Step S163: Hardware state machine 700 starts. After the shut-off domain voltage stabilizes, hardware state machine 700 automatically starts running from the idle state under its independent 50MHz clock drive, without the processor 210 issuing any start command.

[0130] Steps S164 to S166: The hardware state machine 700, following the state transition process described in Part VII above, sequentially completes the operations of reading algorithm parameters from the non-volatile memory 420 (step S164), integrity verification (step S165), and loading the algorithm parameters into the compensation controller 220 (step S166). As described in the previous embodiments, this process is entirely completed independently by the hardware state machine 700, without consuming any resources or time of the processor 210.

[0131] Step S167: The hardware state machine 700 sends a completion signal, indicating that the algorithm parameters have been successfully loaded into the compensation controller 220.

[0132] Step S168: Hardware state machine 700 sets the parameter ready flag in the status register to be valid.

[0133] Step S169: The hardware state machine 700 triggers an interrupt in the processor 210, notifying the processor 210 that parameter loading and offset calibration have been completed. As described in the previous embodiment, after completing parameter loading, the hardware state machine 700 also performs sensor offset calibration in parallel, and the calibration result has been written to the offset compensation register of the compensation controller 220. Therefore, the interrupt triggered in step S169 means that both parameter loading and offset calibration have been completed.

[0134] The processor boot path and hardware state machine parameter loading path are merged and synchronized. The following steps are then performed: Step S170: Processor 210 queries the status register. After completing peripheral initialization, processor 210 reads the status register set by hardware state machine 700 and checks the status of parameter ready flag.

[0135] Steps S181 / S191: Determine if the algorithm parameters are ready. If the parameter ready flag is valid (step S181), it indicates that the hardware state machine 700 has completed the algorithm parameter loading and offset calibration, and the system has all the conditions to run the anti-bouncing algorithm, entering the system ready state. If the parameter ready flag is not yet valid (step S191), it indicates that the work of the hardware state machine 700 has not yet been completed, and the processor 210 enters a waiting loop until it receives the interrupt triggered by step S169 or detects that the flag has become valid.

[0136] Step S182: Execute the image stabilization algorithm. After the system is ready, the processor 210 begins to execute the image stabilization algorithm, and the compensation controller 220 performs real-time control calculations using the loaded algorithm parameters and calibrated offsets. The chip then formally enters the image stabilization control working mode. As described in the aforementioned implementation, the sensing module 100 then continuously collects signals, the calculation module 200 calculates the compensation drive amount in real time, and the execution module 300 drives the motor 20 to adjust the lens position, forming a closed-loop control.

[0137] Please see Figure 7 , Figure 7 A three-level power domain parallel wake-up timing diagram provided for the implementation of this application. Figure 7 Five swimlanes are used to represent the activities of the constantly powered domain, the maintainable domain, the turn-off domain, the processor 210, and the hardware state machine 700 on the time axis. The time start point T0 is the moment when the wake-up signal is triggered.

[0138] At time T0, an external wake-up signal arrives at the wake-up controller 500. As described in the previous embodiment, after the comparator in the wake-up controller 500 detects the level change of the external interface, the address matching circuit completes address matching and confirms that this chip is the wake-up target. This wake-up detection process takes approximately 0 to 5 μs. After the wake-up detection is completed, the wake-up controller 500 notifies the power management module 600 to issue a power enable signal at 5 μs, initiating the power-on process of the subsequent power domain. Throughout the wake-up process, the constant power domain always operates at a low-frequency clock of 8 kHz, and there is no power-on waiting issue.

[0139] Upon receiving the power enable signal, the power management module 600 first powers on the persistent domain. The volatile memory 410 then powers on at 3.3V, a process that lasts approximately 50μs (5μs to 55μs). After power-on, it waits approximately 10μs (55μs to 65μs) for the supply voltage to stabilize sufficiently, preventing data read errors caused by voltage fluctuations. At 65μs, the volatile memory 410 is ready, and the pre-stored firmware program can be reliably read by the processor 210.

[0140] It should be noted that if the volatile memory 410 is selected to keep powered in hibernation mode, the power-on process of the aforementioned keepable domain can be omitted. The volatile memory 410 is always in a ready state, and the processor 210 can start fetching instructions immediately after the voltage of the turn-off domain stabilizes, further shortening the wake-up time.

[0141] After the power-on domain is powered on, the power management module 600 immediately connects the power to the power-off domain. The power-on processes of the two power domains overlap in time. The 5V power-on process of the power-off domain lasts approximately 50μs (55μs to 105μs), and after power-on, it also waits approximately 10μs (105μs to 115μs) for the supply voltage to stabilize. As described in the aforementioned embodiment, the power management module 600 only removes the reset signal after the supply voltage of the power-off domain has stabilized, allowing the module in the power-off domain to exit the reset state and begin operation. At 115μs, the power-off domain is ready.

[0142] Once the sustainable and shut-off domains are ready, the processor 210 and the hardware state machine 700 begin to work, with the two paths proceeding in parallel over time.

[0143] The processor 210 starts fetching instructions from the volatile memory 410 at 65μs (as described in step S153 above), and then performs peripheral initialization (as described in step S154 above). Since the processor 210 directly obtains the firmware program from the fast-reading volatile memory 410, instead of loading it from the slow-reading non-volatile memory 420, the instruction fetch and initialization process is completed at approximately 265μs.

[0144] The hardware state machine 700 automatically starts at 115μs (after the shut-off domain is ready) driven by its independent 50MHz clock. Following the state transition process described in the previous embodiment, it sequentially completes the following: reading algorithm parameters from the non-volatile memory 420 (115μs to 215μs, approximately 100μs), integrity verification (215μs to 225μs, approximately 10μs), and loading the algorithm parameters into the compensation controller 220 (225μs to 245μs, approximately 20μs). As described in the previous embodiment, after loading the parameters, the hardware state machine 700 also performs sensor offset calibration in parallel. This calibration process requires only 34 fixed-point multiplication and addition operations, taking less than 1μs at a 50MHz clock, which is negligible in time. At 245μs, the hardware state machine 700 issues a parameter-ready interrupt, notifying the processor 210 that both the algorithm parameters and offset calibration are complete. Subsequently, the hardware state machine 700 enters a standby state.

[0145] from Figure 7 It can be clearly seen that there is a significant overlap in timing between the instruction fetching start of processor 210 (starting at 65μs) and the parameter reading of hardware state machine 700 (starting at 115μs). When hardware state machine 700 completes all its work in 245μs, processor 210 is still in the initialization process; when processor 210 completes initialization in 265μs, hardware state machine 700 has already completed parameter loading and issued an interrupt. The two paths proceed independently without waiting for each other.

[0146] After the processor 210 completes peripheral initialization at 265μs, it queries the status register set by the hardware state machine 700 (from 265μs to 280μs). Since the hardware state machine 700 had already set the parameter ready flag at 245μs, the flag is already valid when the processor 210 queries it, and the system immediately enters the ready state.

[0147] At approximately 280μs (i.e., time T1), the system is ready, and the processor 210 begins executing the anti-shake algorithm, officially entering the anti-shake control mode. From the T0 wake-up signal trigger to the T1 system readiness, the electronic system's readiness time is approximately 280μs.

[0148] It should be noted that electronic system readiness means that processor 210 has started running the image stabilization algorithm, and compensation controller 220 has the correct algorithm parameters and calibrated offset, and can start outputting compensation drive quantity. However, from the output of compensation drive quantity to the actual arrival of the lens module at the compensation position, there is still a conversion delay of digital-to-analog converter 900, drive response of execution module 300, and mechanical movement of motor 20. At the same time, the PID control loop of compensation controller 220 also needs several control cycles to converge to steady state. Taking all the above processes into account, the total time from the T0 wake-up signal trigger to complete image stabilization is controlled within 10ms, which is significantly shortened compared to the wake-up delay of tens or even hundreds of milliseconds in traditional solutions.

[0149] As described in the aforementioned embodiments, the position sensor 120 (such as a Hall sensor) in the sensing module 100 calculates the displacement of the lens by sensing changes in magnetic field strength. However, the sensor's raw output is not directly equal to the actual displacement, and the mapping relationship between the two is affected by various environmental factors.

[0150] Specifically, the magnetism of a magnet weakens as temperature increases, the sensitivity of the Hall element itself changes with temperature, the thermal expansion of the chip packaging material alters the relative position of the sensor and the magnet, and factors such as humidity can introduce additional offset. The combined effect of these factors is that even if the lens does not actually shift, the sensor output may deviate from zero, and the degree of deviation varies with temperature.

[0151] If the compensation controller 220 starts the anti-shake algorithm without offset calibration, it will calculate the compensation drive amount based on the position information containing errors, causing the motor 20 to produce incorrect compensation displacement, resulting in severe degradation of the anti-shake effect in the initial frame and even the first few frames. Therefore, an offset calibration must be performed every time the chip is woken up and before the anti-shake algorithm starts.

[0152] This application provides a fast temperature-adaptive three-dimensional position offset algorithm. The algorithm directly establishes a mapping relationship between the original sensor output and the position offset, and describes this mapping using a polynomial model that includes a temperature coupling term.

[0153] For each coordinate axis i (i ∈ {x, y, z}), the position offset Δ i The calculation formula is:

[0154] It contains two normalized variables.

[0155] The normalized temperature θ = (T - 25) / 100, where T is the current temperature in degrees Celsius. This normalization uses 25°C as the preset reference temperature and is scaled by dividing by 100. The preset reference temperature refers to the temperature value used as the zero point for temperature normalization, which is 25°C (room temperature) in this embodiment. After normalization, θ ranges from -0.5 to 0.6 within the chip's operating temperature range (-25°C to 85°C), a moderate magnitude that is beneficial for the precision control of fixed-point arithmetic.

[0156] Normalized sensor output v = (v i - v 25 ) / v 25 , where v i v is the actual output value of the sensor at the current temperature. 25 This is the standard output value calibrated at the chip's factory at a preset reference temperature of 25°C. This normalization eliminates the influence of individual differences between different sensors, making the temperature compensation coefficient universal.

[0157] Expanding the above formula, we get: The physical meanings of each term are as follows: ki1·v is the basic sensitivity term. k i1 The unit is μm / V, which represents how many micrometers of displacement corresponds to one normalized unit change in the sensor output. Under ideal conditions with a preset reference temperature and no other interference, this single term can provide a basic estimate of the displacement.

[0158] ki1·ki2·v·θ is the first-order temperature compensation term. The sensor's sensitivity itself changes linearly with temperature. For example, as the temperature rises, the magnetism weakens, resulting in a smaller sensor output for the same displacement. If the sensitivity is still calculated based on the preset reference temperature, the displacement will be underestimated. This term is calculated using k... i2 The coefficient is used to correct the sensitivity for temperature in the first order, and the unit of ki2 is 1 / °C.

[0159] ki1·ki3·v·θ 2 This is a temperature-secondary compensation term. The temperature dependence of the sensitivity is not strictly linear, exhibiting a nonlinear component over a wide temperature range. This term is calculated via θ. 2 To capture this nonlinearity, ki3 is expressed in units of 1 / °C. 2 Second-order polynomials can well approximate the temperature characteristics of most magnetic materials in the range of -25°C to 85°C.

[0160] Ki4·θ is the pure temperature drift term. Even if the lens does not shift at all (v = 0), temperature changes themselves will cause a shift in the sensor output, which may be due to temperature drift of the Hall element's bias voltage, temperature drift of the signal conditioning circuit 110, etc. This term is independent of the sensor signal v and purely compensates for the zero-point shift caused by temperature itself. The unit of Ki4 is μm / °C.

[0161] Ki5·v·θ represents the cross-coupling term between temperature and signal. The degree to which temperature affects the sensor output may be related to the signal amplitude; for example, the temperature effect is more significant during large displacements. This term captures this cross-coupling effect, k i5 The unit is μm / (V·°C). The so-called cross-coupling term refers to a term that simultaneously includes the product of two variables: the normalized output v and the normalized temperature θ, reflecting the mutual influence between temperature and signal amplitude. Existing simple temperature compensation schemes typically only contain a simple superposition of a pure temperature compensation term and a pure signal linear mapping term, failing to capture the interactive influence between temperature and signal amplitude. Under conditions where the temperature deviates significantly from the reference temperature and the displacement amplitude is large, the compensation accuracy decreases significantly.

[0162] Each coordinate axis has 5 independent temperature compensation coefficients (ki1 to ki5), for a total of 15 coefficients across the three axes. The physical meaning, unit, and number of each coefficient are summarized below: ki1 is the basic sensitivity, in μm / V, with 3 coefficients in total; ki2 is the primary temperature compensation coefficient, in 1 / °C, with 3 coefficients in total; ki3 is the secondary temperature compensation coefficient, in 1 / °C², with 3 coefficients in total; ki4 is the pure temperature drift coefficient, in μm / °C, with 3 coefficients in total; and ki5 is the temperature signal coupling coefficient, in μm / (V·°C), with 3 coefficients in total.

[0163] The 15 temperature compensation coefficients mentioned above are pre-calibrated and stored in the non-volatile memory 420 as solidified parameters. The calibration method of the temperature compensation coefficients is explained below using the X-axis as an example.

[0164] Step 1: Prepare the calibration environment.

[0165] The chip and precision displacement calibration fixture are placed in a temperature-controlled chamber, and multiple different precise temperature points are prepared. In one embodiment, five temperature points are selected: -20°C, 0°C, 25°C, 60°C, and 85°C, covering the entire operating temperature range of the chip (-25°C to 85°C). The distribution of the five temperature points is not uniform; the lower temperature range is more closely spaced (-20°C to 0°C to 25°C), while the higher temperature range is more widely spaced (25°C to 60°C to 85°C). This distribution is because the nonlinear characteristics of magnetic materials are usually more pronounced at low temperatures, requiring denser sampling points to improve fitting accuracy. Users can also flexibly select different temperature points for calibration based on the characteristics of the selected magnetic sensor.

[0166] Step 2: Measurement data acquisition.

[0167] At each temperature point, the lens module was positioned at two known displacements of 0 μm and 100 μm using a precision displacement stage, and the corresponding sensor output values ​​were recorded. A total of 10 sets of data (temperature, displacement, and sensor output) were obtained for five temperature points and two displacement positions at each temperature point. Taking the X-axis as an example, the measurement data is as follows: At -20°C, a displacement of 0 μm corresponds to sensor output V1, and a displacement of 100 μm corresponds to sensor output V2; at 0°C, a displacement of 0 μm corresponds to sensor output V3, and a displacement of 100 μm corresponds to sensor output V4; at 25°C, a displacement of 0 μm corresponds to sensor output V5 (this value is the standard output value v). 25 A displacement of 100 μm corresponds to sensor output V6; a displacement of 0 μm at 60°C corresponds to sensor output V7, and a displacement of 100 μm corresponds to sensor output V8; a displacement of 0 μm at 85°C corresponds to sensor output V9, and a displacement of 100 μm corresponds to sensor output V... 10 .

[0168] Step 3: Normalization.

[0169] Calculate the normalized variable for each set of measurement data. Normalized temperature θ i = (T i - 25) / 100, normalized sensor output v i = (V i - V5) / V5, where V5 is the sensor output value at 25°C with a displacement of 0 μm, i.e., the standard output value v. 25 .

[0170] Step 4: Construct an overdetermined system of equations.

[0171] Expand the offset calculation formula as follows: Substitute the normalized data for each set into the equations. Since the displacement Δx and normalized variables v and θ are known quantities for each set of data, and the unknowns are five coefficients, substituting the 10 sets of data yields an overdetermined system of equations with 10 equations and 5 unknowns. An overdetermined system of equations is one where the number of equations exceeds the number of unknowns; it usually does not have an exact solution, but an optimal approximate solution that minimizes the residuals can be found.

[0172] Represented in matrix form as VK = x, where V is a 10×5 coefficient matrix, with each row consisting of [v...]. i , v i θ i , v i θ i2 ,θ i , v i θ iK is a 5×1 vector of unknown coefficients [k1, k1k2, k1k3, k4, k5]. T ; x is a known displacement vector [Δx1, Δx2, ..., Δx] of 10 × 1. 10 ] T .

[0173] Step 5: Solve using the least squares method.

[0174] Since the system of equations is overdetermined, the least squares method is used to find the optimal solution that minimizes the sum of squared residuals: K = (V T V) -1 V T x. The advantage of the least squares method is that it can automatically smooth the measurement noise at each measurement point, and the deviation of individual data points will not excessively affect the final result. The algorithm seeks the optimal combination of fitting coefficients for all 10 data points.

[0175] Extract the coefficients from the K vector obtained from the solution: k1= K[1], k2= K[2] / k1, k3= K[3] / k1, k4= K[4], k5= K[5].

[0176] Step Six: Repeat the measurement and calculation process from Steps Two to Five for the Y-axis and Z-axis respectively to obtain five temperature compensation coefficients for each axis. A total of 15 coefficients for the three axes are written into the non-volatile memory 420 before the chip leaves the factory and permanently stored as hardened parameters.

[0177] After each chip wake-up, the hardware state machine 700 performs an offset calibration in parallel after loading the algorithm parameters: it reads 15 temperature compensation coefficients from the non-volatile memory 420, triggers the analog-to-digital converter 130 to sample the current sensor output and temperature, calculates the normalized variables, substitutes them into the formula to calculate the triaxial offset, and writes the calibration result into the offset compensation register of the compensation controller 220. The entire process requires only 34 fixed-point multiply-accumulate operations, taking less than 1μs at a 50MHz clock speed. It is completely automated by the multiply-accumulate unit in the hardware state machine 700, without consuming processor 210 resources. After calibration, the compensation controller 220 automatically subtracts the offset from the position feedback signal in subsequent control operations, ensuring that it receives calibrated, true displacement information, thus ensuring accurate anti-shake performance in the first frame.

[0178] Once the chip enters the anti-shake control mode, calibration is not required for every control cycle. Temperature changes are typically slow, with noticeable variations only occurring on timescales of seconds to minutes. The offset calibration module 1100 continuously monitors temperature changes during chip operation. When the temperature change exceeds a preset threshold, it triggers a polynomial model to recalculate the sensor offset and update the calibration results in the compensation controller 220. When the temperature change does not exceed the preset threshold, the previous calibration result is used, and no calculation is performed. The preset threshold refers to the temperature change threshold set by the user based on the accuracy requirements of the application scenario, for example, set to 2°C. This on-demand calibration strategy avoids unnecessary recalculation and further reduces the chip's power consumption during operation.

[0179] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An optical image stabilization control chip, characterized in that, include: The sensing module is used to collect the position signal and external jitter signal of the lens module, and convert the position signal and the external jitter signal into digital quantities; The computing module includes a processor and a compensation controller, wherein the processor is used to run the anti-shake algorithm and the compensation controller is used to calculate the compensation drive amount based on the digital quantity; The execution module is used to drive the motor to adjust the lens position according to the compensation drive amount; The storage module includes volatile memory and non-volatile memory, wherein the volatile memory is used to store firmware programs and the non-volatile memory is used to store algorithm parameters; The wake-up controller is used to listen for external wake-up signals and trigger the wake-up process while in sleep mode; A hardware state machine, having a clock domain independent of the processor, is used to read algorithm parameters from the non-volatile memory and load them into the compensation controller in parallel with the processor's startup process upon wake-up. The power management module divides the chip into a constant power domain, a retainable domain, and a power-off domain. The wake-up controller is located in the constant power domain and maintains power supply in sleep mode. The retainable domain selectively maintains power supply in sleep mode to maintain the firmware program in the volatile memory. The processor and the compensation controller are located in the power-off domain and are powered off in sleep mode. The wake-up controller responds to the external wake-up signal by controlling the constantly powered domain, the retainable domain, and the turn-off domain to be powered on sequentially according to a preset timing sequence. The processor loads and executes the firmware program from the volatile memory and executes the debouncing algorithm after the hardware state machine has completed parameter loading.

2. The chip according to claim 1, characterized in that, The threshold voltage of the standard cell library used in the constant power supply domain is higher than the threshold voltage of the standard cell library used in the turn-off domain, the power supply voltage of the constant power supply domain is lower than the power supply voltage of the turn-off domain, and the operating clock frequency of the wake-up controller is lower than the operating clock frequency of the processor.

3. The chip according to claim 2, characterized in that, The wake-up controller includes a comparator and an address matching circuit. The comparator is used to detect level changes of the external interface. After the comparator detects a level change, the address matching circuit receives address information through the bus protocol and matches it with a preset address. When the match is successful, the wake-up process is triggered.

4. The chip according to claim 1, characterized in that, The signal transmitted from the module located in the turn-off domain to other power domains is output after being logically operated by the logic gate and the power enable signal of the turn-off domain. When the turn-off domain is de-energized, the power enable signal clamps the output of the logic gate to a fixed level.

5. The chip according to claim 1, characterized in that, After reading the algorithm parameters from the non-volatile memory, the hardware state machine performs an integrity check on the algorithm parameters. If the check passes, the algorithm parameters are loaded into the compensation controller. If the verification fails, the hardware state machine reads the algorithm parameters from the non-volatile memory again and performs the integrity verification again.

6. The chip according to claim 5, characterized in that, After loading the algorithm parameters, the hardware state machine also performs sensor offset calibration in parallel during the processor's startup process; the sensor offset calibration includes: The analog-to-digital converter is triggered by the control interface to sample the sensor output signal and temperature signal of the sensing module. The built-in multiply-accumulate unit calculates the sensor offset based on the temperature compensation coefficient read from the non-volatile memory and the sampling result, and writes the calibration result into the offset compensation register of the compensation controller.

7. The chip according to claim 1, characterized in that, When the power management module enters sleep mode, it first sends a reset signal to the modules in the shut-off domain to put them into a reset state, and then disconnects the power supply to the shut-off domain. Upon wake-up, the power supply to the turn-off domain is first turned on. After the power supply voltage of the turn-off domain stabilizes, the reset signal is then removed, causing the module in the turn-off domain to exit the reset state and begin operation.

8. The chip according to claim 1, characterized in that, Also includes: The offset calibration module uses a polynomial model that includes a temperature compensation term to calculate the sensor offset. The polynomial model uses the sensor's normalized output and normalized temperature as input variables. The normalized output is normalized based on the sensor's standard output value at a preset reference temperature, and the normalized temperature is normalized with the preset reference temperature as the center. The polynomial model includes cross-coupling terms between the normalized output and the normalized temperature.

9. The chip according to claim 8, characterized in that, The temperature compensation coefficient of the polynomial model is a pre-calibrated and solidified parameter stored in the non-volatile memory; The temperature compensation coefficient is calibrated in the following manner: The sensor output values ​​corresponding to known displacements are measured at multiple different temperature points. After normalizing the measurement data, an overdetermined equation system is constructed. The temperature compensation coefficients of each axis are obtained by solving the overdetermined equation system using the least squares method.

10. The chip according to claim 8, characterized in that, The offset calibration module monitors temperature changes during chip operation. When the temperature change exceeds a preset threshold, the polynomial model is triggered to recalculate the sensor offset. When the temperature change does not exceed the preset threshold, the previous calibration result is used.

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