A method for overcharge protection of a laptop battery and related equipment.

Abstract

This application discloses an overcharge protection method and related equipment for a laptop battery. The method includes: real-time monitoring of the continuous charging time and battery level of the laptop battery; if the continuous charging time reaches a preset time and the battery level exceeds an overcharge threshold, controlling the battery to stop charging and sending a discharge level signal to a hardware discharge control circuit to discharge the battery to a balance charge value; when the battery level drops to or below the balance charge value, sending a stop discharge level signal to the hardware discharge control circuit to stop discharging the battery. Therefore, by real-time monitoring of charging time and battery level, and accurately triggering charging stop and hardware discharge, long-term high-charge overcharging of the battery can be effectively avoided in scenarios such as laptop hibernation / shutdown, slowing lithium-ion degradation, eliminating the risk of bulging, and extending battery life; the discharge process is fast and controllable with extremely low standby power consumption, without affecting the user experience.

Description

Technical Field

[0001] This application relates to the field of device charging technology, and more specifically, to an overcharge protection method for a laptop battery and related equipment. Background Technology

[0002] Laptops are commonly used electronic devices, and it's very common for them to be used with an adapter for extended periods. In this scenario, the battery of a traditional laptop often remains at a high charge level (95%-100%). This state accelerates the degradation of lithium-ion activity, significantly increasing the risk of battery swelling and capacity decline, and seriously affecting battery life and safety.

[0003] Existing battery protection solutions mostly rely on software voltage limiting mechanisms, such as setting a preset percentage to stop charging. However, such solutions have significant limitations. When the laptop is powered off or in sleep mode, the software function is disabled, and if the adapter remains connected for an extended period, the battery still faces the risk of overcharging, failing to provide effective protection across all scenarios.

[0004] How to avoid overcharging the laptop battery after connecting it to the adapter, thus extending the battery's lifespan, is an issue that needs attention. Summary of the Invention

[0005] In view of the above problems, this application provides an overcharge protection method and related equipment for a laptop battery to prevent overcharging of the battery after the laptop is connected to the adapter for charging, thereby extending the lifespan of the laptop battery.

[0006] To achieve the above objectives, the following specific solutions are proposed:

[0007] An overcharge protection method for a laptop battery, applied to a controller, the method comprising:

[0008] Monitor the continuous charging time and battery level of your laptop in real time;

[0009] If the continuous charging time reaches the preset time and the power is greater than the overcharge threshold, the battery is controlled to stop charging and a discharge level signal is sent to the hardware discharge control circuit so that the hardware discharge control circuit can discharge the battery to the balance power value.

[0010] When the battery level drops to or below the equilibrium battery level, a stop discharge level signal is sent to the hardware discharge control circuit to stop the hardware discharge control circuit from discharging the battery.

[0011] Optionally, the hardware discharge control circuit includes a P-channel MOSFET, an N-channel MOSFET, a pull-up resistor, a pull-down resistor, a discharge load resistor, and a voltage divider resistor.

[0012] The gate of the N-channel MOSFET is electrically connected to the power enable pin of the controller. The gate of the N-channel MOSFET is grounded through the pull-down resistor. The source of the N-channel MOSFET is grounded. The drain of the N-channel MOSFET is electrically connected to the drain of the P-channel MOSFET through the discharge load resistor.

[0013] The gate of the P-channel MOSFET is electrically connected to the drain of the N-channel MOSFET through the voltage divider resistor, the gate of the P-channel MOSFET is electrically connected to the battery through the pull-up resistor, and the battery is electrically connected to the source of the P-channel MOSFET.

[0014] Optionally, the hardware discharge control circuit further includes a gate drive resistor;

[0015] The gate of the N-channel MOSFET is grounded via the gate drive resistor and the pull-down resistor in sequence.

[0016] Optionally, the hardware discharge control circuit may also include a fuse;

[0017] The source of the P-channel MOSFET is electrically connected to the battery through the fuse, and the gate of the P-channel MOSFET is electrically connected to the battery through the pull-up resistor and the fuse in sequence.

[0018] Optionally, this method is enabled in the laptop's hibernation / shutdown / normal operation state.

[0019] An overcharge protection device for a laptop battery, applied to a controller, the device comprising:

[0020] The real-time monitoring unit is used to monitor the continuous charging time and battery level of the laptop in real time.

[0021] A discharge signal triggering unit is used to control the battery to stop charging if the continuous charging time reaches a preset time and the charge is greater than the overcharge threshold, and to send a discharge level signal to the hardware discharge control circuit so that the hardware discharge control circuit can discharge the battery to a balanced charge value.

[0022] A stop discharge signal triggering unit is used to send a stop discharge level signal to the hardware discharge control circuit when the battery level drops to or below the balance battery level, so that the hardware discharge control circuit stops discharging the battery.

[0023] Optionally, the hardware discharge control circuit includes a P-channel MOSFET, an N-channel MOSFET, a pull-up resistor, a pull-down resistor, a discharge load resistor, and a voltage divider resistor.

[0024] The gate of the N-channel MOSFET is electrically connected to the power enable pin of the controller. The gate of the N-channel MOSFET is grounded through the pull-down resistor. The source of the N-channel MOSFET is grounded. The drain of the N-channel MOSFET is electrically connected to the drain of the P-channel MOSFET through the discharge load resistor.

[0025] The gate of the P-channel MOSFET is electrically connected to the drain of the N-channel MOSFET through the voltage divider resistor, the gate of the P-channel MOSFET is electrically connected to the battery through the pull-up resistor, and the battery is electrically connected to the source of the P-channel MOSFET.

[0026] Optionally, the hardware discharge control circuit may further include a gate drive resistor and a fuse;

[0027] The gate of the N-channel MOSFET is grounded through the gate drive resistor and the pull-down resistor in sequence.

[0028] The source of the P-channel MOSFET is electrically connected to the battery through the fuse, and the gate of the P-channel MOSFET is electrically connected to the battery through the pull-up resistor and the fuse in sequence.

[0029] An overcharge protection system for a laptop battery includes a controller as described in claim 1, and a hardware discharge control circuit as described in claim 1.

[0030] An overcharge protection device for a laptop battery, comprising a memory and a processor;

[0031] The memory is used to store programs;

[0032] The processor is used to execute the program to implement the various steps of the overcharge protection method for a laptop battery as described above.

[0033] A storage medium having a computer program stored thereon, which, when executed by a processor, implements the various steps of the overcharge protection method for a laptop battery as described above.

[0034] By employing the above technical solution, this application monitors the continuous charging time and battery level of a laptop battery in real time. If the continuous charging time reaches a preset duration and the battery level exceeds an overcharge threshold, the battery is controlled to stop charging, and a discharge level signal is sent to the hardware discharge control circuit. This allows the hardware discharge control circuit to discharge the battery to a balanced charge level. When the battery level drops to or below the balanced charge level, a stop discharge level signal is sent to the hardware discharge control circuit to stop discharging the battery. Therefore, by monitoring the charging time and battery level in real time and accurately triggering charging stop and hardware discharge, long-term high-charge overcharging of the battery can be effectively avoided in scenarios such as laptop hibernation / shutdown, slowing down lithium-ion degradation, eliminating the risk of bulging, and extending battery life. The discharge process is fast and controllable with extremely low standby power consumption, without affecting the user experience. Attached Figure Description

[0035] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0036] Figure 1 This is a schematic diagram illustrating a process for implementing overcharge protection for a laptop battery, as provided in an embodiment of this application.

[0037] Figure 2 A schematic diagram of a control circuit for overcharge protection of a laptop battery provided in an embodiment of this application;

[0038] Figure 3 A schematic diagram of a device for overcharge protection of a laptop battery provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of a device for overcharge protection of a laptop battery, provided as an embodiment of this application. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] This application solution can be implemented based on a terminal with data processing capabilities. This terminal can be a controller, specifically an embedded controller (EC). The EC is the core control unit integrating an intelligent decision-making module. It runs continuously in the laptop's sleep / shutdown state, responsible for real-time monitoring of battery level and adapter connection status. By determining whether the conditions are met—battery level exceeding a preset high threshold and adapter connection time exceeding a preset time—it outputs a control signal to trigger or shut down the hardware discharge circuit. Simultaneously, it continuously monitors the battery level during the discharge process to ensure it remains stable within a safe threshold.

[0042] EC can be connected to an adapter used for charging laptops to control the adapter to stop charging when a power outage occurs.

[0043] Next, combined Figure 1 The overcharge protection method for a laptop battery described in this application may include the following steps:

[0044] Step S110: Monitor the continuous charging time and battery level of the laptop's battery in real time.

[0045] Specifically, the EC can continuously monitor the laptop in all working states (normal operation, hibernation, and shutdown). It can collect the adapter's presence signal through the signal isolation module, accumulate the charging time of the battery continuously connected to the adapter in real time, and ensure that the time statistics are accurate to the hour. The EC reads the battery power data in real time through battery management related interfaces and dynamically obtains the state of charge (SOC) value.

[0046] Step S120: If the continuous charging time reaches the preset time and the power is greater than the overcharge threshold, control the battery to stop charging and send a discharge level signal to the hardware discharge control circuit so that the hardware discharge control circuit can discharge the battery to the balance power value.

[0047] The overcharge threshold indicates the battery level at which a continuous charge exceeding this threshold will accelerate lithium-ion degradation and increase the risk of battery swelling. The balanced charge level indicates the battery level at which a laptop can run for an extended period without causing battery damage.

[0048] For example, when the battery is detected to have been continuously connected to the adapter for charging for a preset duration (e.g., 48 hours) and the current charge level has exceeded the overcharge threshold (e.g., 90%), the EC immediately initiates coordinated control. First, it sends a command to the Charger on the laptop motherboard, configuring it to learnmode. At this point, the adapter stops supplying power to the laptop system and battery, cutting off the charging circuit. Subsequently, the EC can send a high-level discharge signal (PWR_EN = 3.3V) to the hardware discharge control circuit via a general-purpose input / output pin (GPIO), allowing the hardware discharge control circuit to discharge the battery to a balanced charge level (e.g., 80%), completing the discharge phase control.

[0049] Understandably, cutting off the charging circuit before initiating discharge avoids energy waste and circuit conflicts caused by parallel charging and discharging, ensuring efficient and controllable discharge. It also prevents failures in sleep or shutdown states. Under the trigger control of the EC (Electronic Control Unit), the hardware discharge control circuit can actively reduce the battery's charge level from exceeding the overcharge threshold to the equilibrium charge level, fundamentally slowing electrolyte decomposition and lithium dendrite growth, thus extending battery life.

[0050] Step S130: When the battery level drops to or below the equilibrium battery level, a stop discharge level signal is sent to the hardware discharge control circuit to stop the hardware discharge control circuit from discharging the battery.

[0051] Specifically, the EC continuously and dynamically monitors the battery's state of charge, thus tracking the charge change trend during discharge in real time. When the EC detects that the battery charge has decreased and fallen to or below the equilibrium charge level, further discharge control is unnecessary. It can then send a stop-discharge level signal to the hardware discharge control circuit, for example, by switching the discharge control signal output from the GPIO pin to the stop-discharge level (PWR_EN=0V). Simultaneously, the EC sends a command to the Charger IC on the laptop motherboard, causing it to exit learnmode mode and configure the charging current to 0. Upon receiving the signal, the hardware discharge control circuit stops discharging the battery and stabilizes it within the equilibrium charge range.

[0052] Understandably, the EC real-time monitoring and threshold triggering mechanism ensures that the battery level does not fall below the safe range, preventing irreversible capacity degradation caused by over-discharge, while also protecting against overcharging and over-discharging. Through the rapid response of the hardware discharge control circuit and the precise regulation of the EC, the battery ultimately stabilizes at its ideal balanced charge level, thus slowing down battery aging and preventing excessive discharge from affecting subsequent user experience.

[0053] The overcharge protection method for laptop batteries provided in this embodiment monitors the continuous charging time and battery level of the laptop battery in real time. If the continuous charging time reaches a preset duration and the battery level exceeds an overcharge threshold, the battery is stopped from charging, and a discharge level signal is sent to the hardware discharge control circuit to discharge the battery to a balance charge level. When the battery level drops to or below the balance charge level, a stop discharge level signal is sent to the hardware discharge control circuit to stop discharging the battery. Therefore, by monitoring the charging time and battery level in real time and accurately triggering the stop charging and hardware discharge, long-term high-charge overcharging of the battery can be effectively avoided in scenarios such as laptop hibernation / shutdown, slowing down lithium-ion degradation, eliminating the risk of bulging, and extending battery life. The discharge process is fast and controllable with extremely low standby power consumption, without affecting the user experience.

[0054] In some embodiments of this application, the hardware discharge control circuit mentioned in the above embodiments is further described, such as... Figure 2 As shown, the hardware discharge control circuit may include a P-channel MOSFET, an N-channel MOSFET, a pull-up resistor, a pull-down resistor, a discharge load resistor, and a voltage divider resistor.

[0055] Figure 2 In this configuration, the P-channel MOSFET is Q1, with its source (S), gate (G), and drain (D) terminals being the source, gate, and drain, respectively. The N-channel MOSFET is Q2, with its source, gate, and drain terminals being the source, gate, and drain, respectively. The pull-up resistor is R_pullup, with a value of 47kΩ. The pull-down resistor is R_pulldown, with a value of 1MΩ. The discharge load resistor is R_Load, with a value of 200Ω. The voltage divider resistor is R_pgate_P, with a value of 100kΩ. In terms of connections, the gate of the N-channel MOSFET is electrically connected to the power enable pin of the controller, the gate of the N-channel MOSFET is grounded through the pull-down resistor, the source of the N-channel MOSFET is grounded, and the drain of the N-channel MOSFET is electrically connected to the drain of the P-channel MOSFET through the discharge load resistor. The gate of the P-channel MOSFET is electrically connected to the drain of the N-channel MOSFET through a voltage divider resistor. The gate of the P-channel MOSFET is electrically connected to the battery (VBAT) through a pull-up resistor. The battery is electrically connected to the source of the P-channel MOSFET.

[0056] In terms of operating logic, when EC sends a PWR_EN (3.3V high-level signal), Q2 turns on, pulling down the gate voltage of Q1, forming an effective V_gs voltage difference. Q1 then turns on, establishing a closed discharge loop from battery to Q1 to R_load to ground. When PWR_EN is low, R_pullup pulls the gate voltage of Q1 close to its source, V_gs≈0V, forcibly turning off Q1 and cutting off the discharge loop. Therefore, Q1 precisely responds to the control signal, switching the discharge loop on and off to ensure controllable release of battery energy. Simultaneously, leveraging its power device characteristics, it withstands the discharge current, ensuring stable loop operation.

[0057] Q2, acting as the pre-driver for Q1, possesses a low-voltage control and high-voltage drive function similar to a relay. Q2's gate receives the PWR_EN control signal output from the EC and is grounded via a pull-down resistor. Q2's source is directly grounded, and its drain is electrically connected to R_Pgate and R_load, which are respectively connected to the gate and drain of Q1. During operation, when PWR_EN is high (3.3V), Q2's gate is energized and conducts, pulling its drain voltage low, which in turn quickly pulls down Q1's gate voltage, triggering its conduction. When PWR_EN is low (0V), R_pulldown pulls Q2's gate to 0V, turning Q2 off and releasing Q1's gate, restoring it to its off state. Thus, Q2 achieves electrical isolation between the control signal and the high-voltage discharge circuit, preventing high-voltage interference to the EC, while simultaneously amplifying the driving capability of the control signal, ensuring Q1's rapid and reliable state switching, and guaranteeing the accurate execution of the control logic.

[0058] The pull-up resistor R_pullup is a core protective component that ensures the default safety of the discharge circuit. In scenarios such as power-on, invalid EC control signal (e.g., high impedance state), program abnormality, or electrostatic interference, it forces the gate voltage of Q1 to a level close to that of the source (VBAT), making V_gs≈0V, ensuring that Q1 is in an absolutely off state, thereby avoiding the risk of the discharge circuit being accidentally turned on in the sleep / shutdown state.

[0059] The pull-down resistor R_pulldown is a key component in constructing the second-level hardware default shutdown mechanism. When the EC control signal is abnormal (such as uninitialized, high impedance state, or program crash), it forcibly pulls the gate voltage of Q2 down to 0V, ensuring that Q2 is in a stable shutdown state. R_pulldown and R_pullup form a hardware redundancy interlock system, and the probability of both shutdown mechanisms failing simultaneously is close to zero. From a hardware design perspective, this completely eliminates the risk of Q2 being mis-turned on due to abnormal control signals, which in turn causes Q1 to unexpectedly start discharging. This enhances the safety of the hardware discharge control loop and ensures the electrical safety of the device under various extreme operating conditions.

[0060] The discharge load resistor R_load is a core component for battery energy consumption and circuit regulation. When Q1 is turned on, the battery energy is released controllably as heat through R_load, enabling the battery charge to drop rapidly from the high threshold to the safe threshold. The resistance value can be adjusted according to the discharge rate requirements. With the selection of a resistor with an accuracy of ±1%, the discharge current accuracy is better than ±2%. As the gate charge discharge path of Q1, R_load can provide a low-impedance discharge channel to ground for the charge stored in the gate of Q1 when Q1 needs to be turned off, accelerating the turn-off process of Q1, reducing turn-off delay, and thus ensuring timely termination of discharge and avoiding the risk of over-discharge.

[0061] The voltage divider resistor R_pgate_P is an auxiliary control element that optimizes the conduction state of Q1. R_pgate_P, together with R_pullup, forms a voltage divider circuit, thereby precisely adjusting the amplitude of the Q1 gate voltage. When Q2 turns on and pulls down the drain voltage, the voltage divider effect of R_pgate_P and R_pullup ensures a stable gate voltage for Q1, preventing insufficient conduction and excessive heat generation caused by excessively low or high gate voltage, or damage due to voltage exceeding the device's tolerance range. Simultaneously, the voltage divider structure buffers sudden changes in gate voltage, further suppressing oscillations during switching, improving the stability and reliability of Q1 operation, ensuring a stable discharge current, and preventing abnormal discharge rates caused by gate voltage fluctuations.

[0062] In some embodiments of this application, the hardware discharge control circuit mentioned in the above embodiments is further described, such as... Figure 2 As shown, the hardware discharge control circuit may also include a gate drive resistor R_gate with a resistance of 100Ω. The gate of the N-channel MOSFET Q2 can be grounded in sequence through the gate drive resistor R_gate and the pull-down resistor R_pulldown.

[0063] Understandably, the gate drive resistor R_gate, connected in series with the gate of Q2, is a key component for optimizing the switching characteristics of Q2. R_gate limits the peak value of the gate charging current of Q2, preventing instantaneous large currents from impacting the gate oxide layer of Q2 and extending the device's lifespan. R_gate also dampens LC oscillations (ringing) caused by the parasitic inductance and capacitance of the Q2 gate, reducing electromagnetic interference generated during switching and ensuring smooth, jitter-free switching of Q2. By precisely controlling the rate of change of the gate current, R_gate makes the turn-on and turn-off processes of Q2 more controllable, significantly shortening the switching time, improving the response speed of the discharge circuit, reducing the impact of electromagnetic interference on other components of the device, and ensuring the electromagnetic compatibility and operational stability of the entire system.

[0064] In some embodiments of this application, the hardware discharge control circuit mentioned in the above embodiments is further described, such as... Figure 2As shown, the hardware discharge control circuit may also include a fuse. The source of the P-channel MOSFET Q1 is electrically connected to the battery VBAT through the fuse, and the gate of the P-channel MOSFET Q1 is electrically connected to the battery VBAT through the pull-up resistor R_pullup and the fuse.

[0065] Understandably, the fuse is the final safety barrier in the hardware discharge control circuit. Connected in series between the battery's VBAT and the source of Q1, it is a one-time overcurrent protection component. The fuse is designed to handle severe fault scenarios in the discharge circuit. When a short circuit occurs in Q1, R_load, or other anomalies causing an excessively large current in the circuit, the fuse will melt within milliseconds, physically severing the connection between the battery and the discharge circuit, completely blocking the current path. This design effectively prevents the risk of thermal runaway, such as battery overheating, fire, and explosion, caused by abnormally large currents. It complies with electronic equipment safety regulations, providing ultimate safety protection for the battery and the entire discharge device, preventing the fault from escalating and causing more serious equipment damage or safety accidents.

[0066] The overcharge protection device for a laptop battery provided in the embodiments of this application will be described below. The overcharge protection device for a laptop battery described below can be referred to in correspondence with the overcharge protection method for a laptop battery described above.

[0067] See Figure 3 , Figure 3 This is a schematic diagram of an overcharge protection device for a laptop battery disclosed in an embodiment of this application.

[0068] like Figure 3 As shown, the device may include:

[0069] The real-time monitoring unit 11 is used to monitor the continuous charging time and battery level of the laptop in real time.

[0070] The discharge signal triggering unit 12 is used to control the battery to stop charging if the continuous charging time reaches a preset time and the power is greater than the overcharge threshold, and to send a discharge level signal to the hardware discharge control circuit so that the hardware discharge control circuit can discharge the battery to a balanced power value.

[0071] The stop discharge signal triggering unit 13 is used to send a stop discharge level signal to the hardware discharge control circuit when the battery level drops to or below the balance battery level, so that the hardware discharge control circuit stops discharging the battery.

[0072] Optionally, the hardware discharge control circuit includes a P-channel MOSFET, an N-channel MOSFET, a pull-up resistor, a pull-down resistor, a discharge load resistor, and a voltage divider resistor.

[0073] The gate of the N-channel MOSFET is electrically connected to the power enable pin of the controller. The gate of the N-channel MOSFET is grounded through the pull-down resistor. The source of the N-channel MOSFET is grounded. The drain of the N-channel MOSFET is electrically connected to the drain of the P-channel MOSFET through the discharge load resistor.

[0074] The gate of the P-channel MOSFET is electrically connected to the drain of the N-channel MOSFET through the voltage divider resistor, the gate of the P-channel MOSFET is electrically connected to the battery through the pull-up resistor, and the battery is electrically connected to the source of the P-channel MOSFET.

[0075] Optionally, the hardware discharge control circuit may further include a gate drive resistor and a fuse;

[0076] The gate of the N-channel MOSFET is grounded through the gate drive resistor and the pull-down resistor in sequence.

[0077] The source of the P-channel MOSFET is electrically connected to the battery through the fuse, and the gate of the P-channel MOSFET is electrically connected to the battery through the pull-up resistor and the fuse in sequence.

[0078] This application also provides an overcharge protection system for a laptop battery, including a controller and a hardware discharge control circuit. The control relationship between the controller and the hardware discharge control circuit, the control logic of the controller to implement overcharge protection for the laptop battery, and the circuit control logic of the hardware discharge control circuit to implement overcharge protection for the laptop battery are described in the foregoing embodiments and will not be repeated here.

[0079] The overcharge protection device for laptop batteries provided in this application embodiment can be applied to overcharge protection devices for laptop batteries, such as a controller, which can be an EC chip on the laptop motherboard. Optionally, Figure 4 The diagram shows the hardware structure of an overcharge protection device for a laptop battery. Figure 4 The hardware structure of an overcharge protection device for a laptop battery may include: at least one processor 1, at least one communication interface 2, at least one memory 3, and at least one communication bus 4.

[0080] In this embodiment of the application, the number of processor 1, communication interface 2, memory 3, and communication bus 4 is at least one, and processor 1, communication interface 2, and memory 3 communicate with each other through communication bus 4;

[0081] Processor 1 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0082] Memory 3 may include high-speed RAM, and may also include non-volatile memory, such as at least one disk storage device;

[0083] The memory stores a program, which the processor can call. The program is used for:

[0084] Monitor the continuous charging time and battery level of your laptop in real time;

[0085] If the continuous charging time reaches the preset time and the power is greater than the overcharge threshold, the battery is controlled to stop charging and a discharge level signal is sent to the hardware discharge control circuit so that the hardware discharge control circuit can discharge the battery to the balance power value.

[0086] When the battery level drops to or below the equilibrium battery level, a stop discharge level signal is sent to the hardware discharge control circuit to stop the hardware discharge control circuit from discharging the battery.

[0087] Optionally, the refined and extended functions of the program can be found in the description above.

[0088] This application embodiment also provides a storage medium that can store a program suitable for execution by a processor, the program being used for:

[0089] Monitor the continuous charging time and battery level of your laptop in real time;

[0090] If the continuous charging time reaches the preset time and the power is greater than the overcharge threshold, the battery is controlled to stop charging and a discharge level signal is sent to the hardware discharge control circuit so that the hardware discharge control circuit can discharge the battery to the balance power value.

[0091] When the battery level drops to or below the equilibrium battery level, a stop discharge level signal is sent to the hardware discharge control circuit to stop the hardware discharge control circuit from discharging the battery.

[0092] Optionally, the refined and extended functions of the program can be found in the description above.

[0093] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0094] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can be referred to each other.

[0095] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for overcharge protection of a laptop battery, characterized in that, Applied to a controller, the method includes: Monitor the continuous charging time and battery level of your laptop in real time; If the continuous charging time reaches the preset time and the power is greater than the overcharge threshold, the battery is controlled to stop charging and a discharge level signal is sent to the hardware discharge control circuit so that the hardware discharge control circuit can discharge the battery to the balance power value. When the battery level drops to or below the equilibrium battery level, a stop discharge level signal is sent to the hardware discharge control circuit to stop the hardware discharge control circuit from discharging the battery.

2. The method according to claim 1, characterized in that, The hardware discharge control circuit includes a P-channel MOSFET, an N-channel MOSFET, a pull-up resistor, a pull-down resistor, a discharge load resistor, and a voltage divider resistor. The gate of the N-channel MOSFET is electrically connected to the power enable pin of the controller. The gate of the N-channel MOSFET is grounded through the pull-down resistor. The source of the N-channel MOSFET is grounded. The drain of the N-channel MOSFET is electrically connected to the drain of the P-channel MOSFET through the discharge load resistor. The gate of the P-channel MOSFET is electrically connected to the drain of the N-channel MOSFET through the voltage divider resistor, the gate of the P-channel MOSFET is electrically connected to the battery through the pull-up resistor, and the battery is electrically connected to the source of the P-channel MOSFET.

3. The method according to claim 2, characterized in that, The hardware discharge control circuit also includes a gate drive resistor. The gate of the N-channel MOSFET is grounded via the gate drive resistor and the pull-down resistor in sequence.

4. The method according to claim 2, characterized in that, The hardware discharge control circuit also includes a fuse; The source of the P-channel MOSFET is electrically connected to the battery through the fuse, and the gate of the P-channel MOSFET is electrically connected to the battery through the pull-up resistor and the fuse in sequence.

5. The method according to any one of claims 1-4, characterized in that, This method is enabled in the laptop's hibernation / shutdown / normal operation states.

6. An overcharge protection device for a laptop battery, characterized in that, Applied to a controller, the device includes: The real-time monitoring unit is used to monitor the continuous charging time and battery level of the laptop in real time. A discharge signal triggering unit is used to control the battery to stop charging if the continuous charging time reaches a preset time and the charge is greater than the overcharge threshold, and to send a discharge level signal to the hardware discharge control circuit so that the hardware discharge control circuit can discharge the battery to a balanced charge value. A stop discharge signal triggering unit is used to send a stop discharge level signal to the hardware discharge control circuit when the battery level drops to or below the balance battery level, so that the hardware discharge control circuit stops discharging the battery.

7. The apparatus according to claim 6, characterized in that, The hardware discharge control circuit includes a P-channel MOSFET, an N-channel MOSFET, a pull-up resistor, a pull-down resistor, a discharge load resistor, and a voltage divider resistor. The gate of the N-channel MOSFET is electrically connected to the power enable pin of the controller. The gate of the N-channel MOSFET is grounded through the pull-down resistor. The source of the N-channel MOSFET is grounded. The drain of the N-channel MOSFET is electrically connected to the drain of the P-channel MOSFET through the discharge load resistor. The gate of the P-channel MOSFET is electrically connected to the drain of the N-channel MOSFET through the voltage divider resistor, the gate of the P-channel MOSFET is electrically connected to the battery through the pull-up resistor, and the battery is electrically connected to the source of the P-channel MOSFET.

8. An overcharge protection system for a laptop battery, characterized in that, It includes the controller as described in claim 1, and the hardware discharge control circuit as described in claim 1.

9. An overcharge protection device for a laptop battery, characterized in that, Including memory and processor; The memory is used to store programs; The processor is configured to execute the program to implement the steps of the overcharge protection method for a laptop battery as described in any one of claims 1-4.

10. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the overcharge protection method for a laptop battery as described in any one of claims 1-4.

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