Semiconductor device and method of forming the same
By employing discrete electrode and sidewall electrode structures in polysilicon-insulator-polysilicon capacitors, the dent problem was solved, device reliability was improved, and capacitance was increased.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GIGADEVICE SEMICON SHANGHAI INC
- Filing Date
- 2024-11-29
- Publication Date
- 2026-05-29
AI Technical Summary
The planar structure of existing polysilicon-insulator-polysilicon capacitors is prone to depressions after chemical mechanical polishing, which leads to a reduction in the thickness of the floating gate, affecting device reliability and limiting capacitance value.
A capacitor with a larger capacitance area is formed by using multiple independent first electrode structures and forming second electrode structures and dielectric layers on their sidewalls and top surfaces to isolate adjacent electrode structures.
It reduces denting, improves device reliability, and increases capacitance without increasing device area.
Smart Images
Figure CN122121177A_ABST
Abstract
Description
Technical Field
[0001] This application relates generally to the field of semiconductors, and more specifically to a semiconductor device and a method for forming the same. Background Technology
[0002] Poly-Insulator-Poly (PIP) capacitors are parasitic capacitors provided by floating-gate memory process platforms. They are capacitors that connect the capacitance corresponding to the inter-gate dielectric layer and the capacitance corresponding to the tunnel oxide layer of the floating-gate memory in parallel to provide a high capacitance efficiency capacitor. They are mainly used in charge pump boost circuits or filter circuits.
[0003] Existing polycrystalline silicon-insulator-polycrystalline silicon capacitors are mostly planar structures, which have the advantages of simple structure and relatively simple manufacturing process. However, due to the large overall area of this planar structure, large depressions are easily generated in this area after chemical mechanical polishing, resulting in a reduction in the thickness of the floating gate. This has a significant impact on subsequent processes of the floating gate and can easily lead to capacitor reliability problems in severe cases. Summary of the Invention
[0004] The purpose of this application is to provide a semiconductor device and a method for forming the same, which aims to reduce the depression phenomenon of the first electrode structure and improve the reliability of the device.
[0005] This application provides a semiconductor device, comprising: a substrate including a capacitor region; a plurality of first electrode structures located on the surface of the substrate, the plurality of first electrode structures being discrete from each other and arranged along a first direction parallel to the surface of the substrate; a second electrode structure located on the sidewall surface and top surface of the plurality of first electrode structures; and a first dielectric layer located between the second electrode structure and the first electrode structure, and isolating the first electrode structure from the second electrode structure.
[0006] In some embodiments, the extension direction of a plurality of the first electrode structures is parallel to a second direction, which is parallel to the substrate surface, and the second direction is different from the first direction.
[0007] In some embodiments, the first electrode structure includes a first side and a second side opposite to each other along the first direction, and the second electrode structure is located on the first side and the second side.
[0008] In some embodiments, the first electrode structure further includes a third side and a fourth side opposite to each other along the second direction, and the second electrode structure is also located on the third side and / or the fourth side.
[0009] In some embodiments, it also includes:
[0010] A first contact structure extends in a direction perpendicular to the substrate surface and is electrically connected to the first electrode structure.
[0011] In some embodiments, the first electrode structure includes two ends opposite each other along the second direction;
[0012] The first contact structure is connected to at least one of the ends.
[0013] In some embodiments, it further includes a second contact structure electrically connected to the second electrode structure.
[0014] In some embodiments, the second electrode structure includes a first region and a second region, the second region being located on both sides of the first region along the first direction; the second contact structure is located on the surface of the second region or the surface of the first region, and the second contact structure is uniformly distributed.
[0015] In some embodiments, the substrate includes a plurality of active regions and an isolation structure, the isolation structure being located between adjacent active regions, the active regions extending in a direction parallel to the second direction and arranged along the first direction; each of the first electrode structures is located on the surface of one of the active region substrates.
[0016] In some embodiments, the active region includes a third region and a fourth region opposite each other along the second direction; at least one of the third region and the fourth region extends beyond the first electrode structure along the second direction.
[0017] In some embodiments, it also includes:
[0018] The third contact structure is located in the third region and / or the fourth region.
[0019] In some embodiments, the substrate further includes:
[0020] The first connection area connects to a plurality of the third areas along the first direction.
[0021] In some embodiments, the substrate further includes a second connection region that connects a plurality of the fourth regions along the first direction.
[0022] In some embodiments, the method further includes a second dielectric layer located between the first electrode structure and the active region substrate.
[0023] In some embodiments, the substrate further includes a memory array region; the semiconductor device further includes a memory structure located on the surface of the substrate of the memory array region; the memory structure includes a floating gate structure, a control gate structure, and a memory layer located between the floating gate structure and the control gate structure;
[0024] The floating gate structure is disposed on the same layer as the first electrode structure, the storage layer is disposed on the same layer as the first dielectric layer, and the control gate structure is disposed on the same layer as the second electrode structure.
[0025] In some embodiments, the semiconductor device further includes a tunneling layer located between the floating gate structure and the substrate.
[0026] This application also provides a method for forming a semiconductor device, comprising: forming a substrate, the substrate including a capacitor region; forming a plurality of first electrode structures on the surface of the substrate in the capacitor region, the plurality of first electrode structures being discrete from each other and arranged along a first direction, the first direction being parallel to the surface of the substrate; forming a first dielectric layer on the sidewall surface and top surface of the plurality of first electrode structures; forming a second electrode structure on the surface of the first dielectric layer, the first dielectric layer being located between the second electrode structure and the first electrode structure, and isolating the first electrode structure from the second electrode structure.
[0027] In some embodiments, the substrate further includes a memory array region, and the method of forming the semiconductor device further includes: in a process of forming a plurality of first electrode structures, forming a plurality of floating gate structures located on the surface of the substrate of the memory array region; in a process of forming the first dielectric layer, forming a memory layer located on the sidewall surface and the top surface of the floating gate structure; in a process of forming the second electrode structure, forming a control gate structure located on the surface of the memory layer, wherein the memory layer is located between the floating gate structure and the control gate structure and isolates the floating gate structure from the control gate structure.
[0028] In some embodiments, the method further includes: forming a mask layer on the substrate; forming a trench through the mask layer and the substrate; and forming an isolation structure within the trench.
[0029] In some embodiments, a method for forming a plurality of first electrode structures on the surface of the capacitor region substrate includes: after forming the isolation structure, removing the mask layer to form a first groove located between adjacent isolation structures; and forming the first electrode structure within the first groove.
[0030] In some embodiments, the method of forming the first dielectric layer and the second electrode structure includes: removing a portion of the isolation structure located between adjacent first electrode structures to form a second groove; forming the first dielectric layer on the inner wall of the second groove and the surface of the first electrode structure; forming the second electrode structure on the surface of the first dielectric layer, wherein a portion of the second electrode structure fills the gap between adjacent first electrode structures.
[0031] In some embodiments, the method further includes forming a second dielectric layer at the bottom of the first groove before forming the first electrode structure within the first groove.
[0032] This application provides a semiconductor device and a method for forming the same. By setting multiple mutually discrete first electrode structures, the recess phenomenon caused by the large-area first electrode structure in the planar structure during the manufacturing process can be reduced, thereby improving the reliability of the device. In addition, since the second electrode structure can form a capacitor between the top surface and the two sides of the first electrode structure, the surface area of the first electrode structure is fully utilized, increasing the capacitance area relative to the planar structure, thereby increasing the capacitance value without increasing the device area. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0035] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in one embodiment;
[0036] Figure 2 This is a front view of the cross-sectional structure of a semiconductor device provided in some embodiments of this application;
[0037] Figure 3 This application Figure 2 Another cross-sectional front view of the semiconductor device provided in the embodiment;
[0038] Figure 4 This application Figure 2 A top view of the semiconductor device provided in the embodiment;
[0039] Figure 5 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application;
[0040] Figure 6 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application;
[0041] Figure 7 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application;
[0042] Figure 8This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application;
[0043] Figure 9 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in some embodiments of this application;
[0044] Figures 10-16 This application Figure 1 A schematic diagram of the semiconductor structure during the formation process of the embodiment.
[0045] Explanation of reference numerals in the attached figures:
[0046] 100. Semiconductor devices;
[0047] 1. Substrate; 101. Active region; 1011. Third region; 1012. Fourth region; 102. Isolation structure; 103. Fifth region; 104. Sixth region; 105. First connection region; 106. Second connection region; 11. Memory array region; 12. Capacitor region;
[0048] 2. Floating grid structure; 201. Floating grid;
[0049] 20. First electrode structure; 21. Sidewall surface; 211. First side surface; 212. Second side surface; 213. Third side surface; 22. Top surface; 23. End;
[0050] 30. Second electrode structure; 31. First region; 32. Second region;
[0051] 41. First dielectric layer; 42. Second dielectric layer;
[0052] 51. First contact structure; 52. Second contact structure; 53. Third contact structure;
[0053] 60. Mask layer; 61. Silicon oxide layer; 62. Silicon nitride layer; T. Trench; 63. First groove; 64. Second groove. Detailed Implementation
[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0055] Please see Figure 1 , Figure 1This is a schematic cross-sectional view of a semiconductor device provided in one embodiment. It should be noted that, in order to show the effect of the chemical mechanical polishing process on the floating gate structure, this embodiment omits the control gate structure and the dielectric layer between the floating gate structure and the control gate structure.
[0056] The semiconductor device includes a substrate 1, a floating gate structure 2 on the substrate 1, a dielectric layer (not shown) on the floating gate structure 2, and a control gate structure (not shown) on the dielectric layer. The substrate 1 includes a memory array region 11 and a capacitor region 12. The floating gate structure 2 includes multiple discrete floating gates 201 in the memory array region 11, while the floating gate structure 2 is a single unit in the capacitor region 12. The control gate structure is a single unit in both the memory array region 11 and the capacitor region 12. The floating gate structure 2, the dielectric layer, and the control gate structure in the capacitor region 12 constitute a capacitor. The floating gates 201 in the capacitor region 12 are a single unit, i.e., a planar structure.
[0057] Because of the significant difference in pattern density between the floating gate structure 2 in capacitor region 12 and the floating gate 201 in memory array region 11, the chemical mechanical polishing process for forming the floating gate structure 2 can easily cause large depressions in the floating gate structure 2 in capacitor region 12. This results in a thinner floating gate structure 2 in this area, which significantly impacts subsequent processes and can even lead to capacitor reliability issues in severe cases. Furthermore, the capacitance value of this type of planar capacitor is limited by the contact area, making it difficult to increase.
[0058] Based on the above reasons, this application provides a semiconductor device comprising: a substrate including a capacitor region; a plurality of first electrode structures located on the surface of the substrate, the plurality of first electrode structures being discrete from each other and arranged along a first direction parallel to the surface of the substrate; a second electrode structure located on the sidewall surface and top surface of the plurality of first electrode structures; and a first dielectric layer located between the second electrode structure and the first electrode structure, and isolating the first electrode structure from the second electrode structure.
[0059] By setting multiple independent first electrode structures, the denting phenomenon caused by the large-area first electrode structure in the planar structure during the manufacturing process can be reduced, thereby improving the reliability of the device. In addition, since the second electrode structure can form a capacitor with the top surface and two sides of the first electrode structure, the surface area of the first electrode structure (especially the area of the sides) is fully utilized, increasing the capacitance area compared to the planar structure, thereby increasing the capacitance value without increasing the device area.
[0060] The semiconductor devices provided in the embodiments of this application will be described below with reference to the accompanying drawings.
[0061] Please see Figures 2 to 4 , Figure 2This is a front view of the cross-sectional structure of a semiconductor device provided in some embodiments of this application. Figure 3 This application Figure 2 Another cross-sectional front view of the semiconductor device provided in the embodiment. Figure 4 This application Figure 2 A top view schematic diagram of the semiconductor device provided in the embodiment. Wherein, Figure 2 yes Figure 4 A cross-sectional view of a semiconductor device along the A-A1 direction. Figure 3 yes Figure 4 A cross-sectional view of a semiconductor device along the B-B1 direction.
[0062] Understandably, although Figure 4 The second electrode structure 30 is not present in the cross-section at position A-A1, but it can be seen in the front view (i.e., sectional view) of this cross-section. The direction perpendicular to the surface of substrate 1 can be represented by a third direction Z, that is, the direction perpendicular to the first direction X and the second direction Y can be represented by a third direction Z.
[0063] The semiconductor device 100 includes a substrate 1, a plurality of first electrode structures 20, a second electrode structure 30, and a first dielectric layer 41. The substrate 1 includes a capacitor region 12. The plurality of first electrode structures 20 are located on the surface of the substrate 1 of the capacitor region 12. The plurality of first electrode structures 20 are discretely arranged along a first direction X, which is parallel to the surface of the substrate 1. The second electrode structures 30 are located on the sidewall surfaces 21 and top surfaces 22 of the plurality of first electrode structures 20. The first dielectric layer 41 is located between the second electrode structures 30 and the first electrode structures 20, and isolates the first electrode structures 20 from the second electrode structures 30.
[0064] It is understood that, since the second electrode structure 30 is located on the sidewall surface 21 and top surface 22 of the first electrode structure 20, and the first dielectric layer 41 isolates the first electrode structure 20 and the second electrode structure 30, the first dielectric layer 41 is also located on the sidewall surface 21 and top surface 22 of the first electrode structure 20. Here, "top surface 22" refers to the surface of the first electrode structure 20 away from the substrate 1, and "sidewall surface 21" refers to the surface of the first electrode structure 20 perpendicular to the substrate 1.
[0065] In some embodiments, the first dielectric layers 41 on the surfaces of adjacent first electrode structures 20 can be connected (see [reference]). Figure 16 ).
[0066] The first electrode structure 20, the first dielectric layer 41, and the second electrode structure 30 constitute a capacitor, and the relative area of the capacitor includes the area of the sidewall surface 21 and the top surface 22 of the first electrode structure 20, that is, the capacitor utilizes the sidewall surface 21 and the top surface 22 of the first electrode structure 20.
[0067] In some embodiments, the materials of the first electrode structure 20 and the second electrode structure 30 may both include polycrystalline silicon, the first dielectric layer 41 may include a silicon oxide layer or a silicon nitride layer, and the first dielectric layer 41 may also include a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked together.
[0068] like Figure 4 As shown, the extension direction of the plurality of first electrode structures 20 is parallel to the second direction Y, that is, the first electrode structure 20 extends along the second direction Y. The second direction Y is parallel to the surface of the substrate 1, and the second direction Y is different from the first direction X. For example, the first direction X may be perpendicular to the second direction Y, or they may intersect at a certain angle.
[0069] like Figure 2 and Figure 4 As shown, the first electrode structure 20 includes a first side surface 211 and a second side surface 212 opposite to each other along the first direction X, and the second electrode structure 30 is located on the first side surface 211 and the second side surface 212. That is, the second electrode structure 30 can cover the first side surface 211 and the second side surface 212 of the first electrode structure 20.
[0070] The semiconductor device 100 may further include a first contact structure 51, which extends along a direction perpendicular to the surface of the substrate 1 (i.e., the Z direction) and is electrically connected to the first electrode structure 20.
[0071] In some embodiments, the first electrode structure 20 extends beyond the second electrode structure 30 along the second direction Y, the first dielectric layer 41 may also extend beyond the second electrode structure 30 along the second direction Y, the first contact structure 51 may penetrate the first dielectric layer 41 along the third direction Z, and the bottom of the first contact structure 51 is connected to the first electrode structure 20.
[0072] In some embodiments, the first electrode structure 20 may include two ends 23 opposite each other along the second direction Y, the second electrode structure 30 exposes the ends 23, and the first contact structure 51 is connected to at least one of the ends 23.
[0073] like Figure 4 As shown, the first contact structure 51 is connected to the two ends 23.
[0074] The semiconductor device 100 may further include a second contact structure 52 electrically connected to the second electrode structure 30, so as to apply a voltage to the second electrode structure 30 through the second contact structure 52.
[0075] In some embodiments, the second electrode structure 30 includes a first region 31 and a second region 32, the second region 32 being located on both sides of the first region 31 along the first direction X. The second contact structure 52 is located on the surface of the second region 32 or the surface of the first region 31, and the second contact structure 52 is uniformly distributed.
[0076] like Figure 4 As shown, the second contact structure 52 is located on the surface of the first region 31 and is evenly distributed on the surface of the first region 31.
[0077] In some embodiments, such as Figure 2 As shown, the substrate 1 includes a plurality of active regions 101 and isolation structures 102. The isolation structures 102 are located between adjacent active regions 101. The extending direction of the active regions 101 is parallel to the second direction Y and arranged along the first direction X. Each first electrode structure 20 is located on the surface of one of the active regions 101 on the substrate 1. That is, the first electrode structure 20 corresponds to the active region 101, and the spacing region between the first electrode structures 20 corresponds to the isolation structure 102.
[0078] In some embodiments, the second electrode structure 30 extends out of the active region 101 along the first direction X, and the second electrode structure 30 extends out of the first electrode structure 20 along the first direction X, so that the second electrode structure 30 can cover the first side 211 and the second side 212 of the first electrode structure 20.
[0079] The semiconductor device 100 may further include a second dielectric layer 42 located between the first electrode structure 20 and the active region 101 substrate 1, thereby forming another capacitor between the first electrode structure 20, the second dielectric layer 42 and the active region 101 substrate 1.
[0080] In some embodiments, the isolation structure 102 may extend along a first direction X between adjacent first electrode structures 20, thereby improving the isolation effect of adjacent first electrode structures 20. For example... Figure 2 As shown, the isolation structure 102 is also located between adjacent second dielectric layers 42, and the upper surface of the isolation structure 102 is higher than the upper surface of the second dielectric layer 42.
[0081] In some embodiments, the active region 101 includes a third region 1011 and a fourth region 1012 opposite each other along the second direction Y, at least one of the third region 1011 and the fourth region 1012 extending beyond the first electrode structure 20 along the second direction Y. That is, the first electrode structure 20 exposes at least one of the third region 1011 and the fourth region 1012.
[0082] like Figure 4 As shown, the first electrode structure 20 exposes the third region 1011 and the fourth region 1012.
[0083] The semiconductor device 100 may further include a third contact structure 53 connected to the substrate 1, the third contact structure 53 being located in the third region 1011 and / or the fourth region 1012. In other words, the third contact structure 53 may be located in the third region 1011 or the fourth region 1012, or may be located in both the third region 1011 and the fourth region 1012.
[0084] In some embodiments, such as Figure 4 As shown, the substrate 1 may include a fifth region 103 and a sixth region 104 extending along a first direction X to both sides of the second electrode structure 30, and the third contact structure 53 is also located in the fifth region 103 and the sixth region 104. In other words, in a top view, the third contact structure 53 is disposed around the first electrode structure 20 and the second electrode structure 30.
[0085] In some embodiments, the substrate 1 further includes a first connection region 105, which connects a plurality of the third regions 1011 along the first direction X, i.e., the same end of the plurality of active regions 101 is connected through the first connection region 105.
[0086] In some embodiments, the substrate 1 further includes a second connection region 106, which connects a plurality of the fourth regions 1012 along the first direction X, i.e., the other ends of the plurality of active regions 101 are connected through the second connection region 106.
[0087] In some embodiments, substrate 1 may further include a memory array region (not shown).
[0088] The semiconductor device 100 may further include a memory structure (not shown) located on the surface of the substrate 1 of the memory array region. The memory structure includes a floating gate structure, a control gate structure, and a memory layer located between the floating gate structure and the control gate structure. The floating gate structure is disposed in the same layer as the first electrode structure 20, the memory layer is disposed in the same layer as the first dielectric layer 41, and the control gate structure is disposed in the same layer as the second electrode structure 30.
[0089] The floating gate structure can be the same as the first electrode structure 20, the control gate structure can be the same as the second electrode structure 30, and the storage layer and the first dielectric layer 41 have the same structure. The multiple floating gate structures are independent of each other and arranged along a first direction X. The control gate structure is located on the sidewall and top surfaces of the multiple floating gate structures. The storage layer is located between the control gate structure and the floating gate structure, and isolates the floating gate structure from the control gate structure.
[0090] The semiconductor device 100 may further include a tunneling layer (not shown) located between the floating gate structure and the substrate 1. The tunneling layer may be disposed on the same layer as the second dielectric layer 42.
[0091] Please see Figure 5 , Figure 5 This is a top view schematic diagram of a semiconductor device provided in some embodiments of this application, mainly showing the layout of the first electrode structure 20, the second electrode structure 30, the first contact structure 51, the second contact structure 52 and the third contact structure 53.
[0092] Figure 5 The embodiments are the same as those described above. Figure 4 The difference in the embodiment is that the third contact structure 53 is located only in the third region 1011 and the fourth region 1012 of the active region 101.
[0093] Understandable, Figure 5 Only the active region 101 and the isolation structure 102 of substrate 1 are shown, while other parts of substrate 1 are omitted. Figure 5 In this embodiment, the portion of the second electrode structure 30 extending out of the active region 101 along the first direction X is located on the surface of the other portion of the substrate 1, meaning that the left and right sides of the second electrode structure 30 are not suspended. In some embodiments, the active region 101 substrate 1 and the other portion of the substrate 1 are made of the same material.
[0094] Please see Figure 6 , Figure 6 This is a top view schematic diagram of a semiconductor device provided in some embodiments of this application, mainly showing the layout of the first electrode structure 20, the second electrode structure 30, the first contact structure 51, the second contact structure 52 and the third contact structure 53.
[0095] Figure 6 The embodiments are the same as those described above. Figure 5 The difference in the embodiment is that the substrate 1 does not include the first connection region 105 and the second connection region 106, that is, the ends of the active region 101 are not connected to each other.
[0096] In some embodiments, substrate 1 may include a first connection region 105 but not a second connection region 106; or substrate 1 may include a second connection region 106 but not a first connection region 105.
[0097] Please see Figure 7 , Figure 7 This is a top view schematic diagram of a semiconductor device provided in some embodiments of this application, mainly showing the layout of the first electrode structure 20, the second electrode structure 30, the first contact structure 51, the second contact structure 52 and the third contact structure 53.
[0098] Figure 7 The embodiments are the same as those described above. Figure 5 The difference in the embodiments is that the first electrode structure 20 further includes a third side 213 and a fourth side (not shown) opposite each other along the second direction Y, and the second electrode structure 30 is also located on the third side 213 and / or the fourth side.
[0099] In some examples, the second electrode structure 30 may be located on the first side 211, the second side 212 and the third side 213 of the first electrode structure 20, or on the first side 211, the second side 212 and the fourth side of the first electrode structure 20, or on the first side 211, the second side 212, the third side 213 and the fourth side of the first electrode structure 20.
[0100] like Figure 7 As shown, the second electrode structure 30 can be located on the first side 211, the second side 212 and the fourth side of the first electrode structure 20.
[0101] In some embodiments, the first contact structure 51 is connected to one end 23 of the first electrode structure 20 (the end 23 near the third side 213), that is, the first contact structure 51 is located only at one end of the first electrode structure 20.
[0102] In some embodiments, the first contact structure 51 may also be connected to the end of the first electrode structure 20 near the fourth side. Since the second electrode structure 30 covers the end of the first electrode structure 20 near the fourth side, the first contact structure 51 near the fourth side can penetrate the second electrode structure 30 and the first dielectric layer 41 in the third direction Z, and is electrically isolated from the second electrode structure 30.
[0103] In some embodiments, the second electrode structure 30 is located on the first side 211, the second side 212, the third side 213 and the fourth side of the first electrode structure 20. Then, the first contact structure 51 penetrates the second electrode structure 30 and the first dielectric layer 41 along the third direction Z and is electrically isolated from the second electrode structure 30.
[0104] Please see Figure 8 , Figure 8This is a top view schematic diagram of a semiconductor device provided in some embodiments of this application, mainly showing the layout of the first electrode structure 20, the second electrode structure 30, the first contact structure 51, the second contact structure 52 and the third contact structure 53.
[0105] Figure 8 The embodiments are the same as those described above. Figure 5 The difference in the embodiment is that the second contact structure 52 is located on the surface of the second region 32 of the second electrode structure 30.
[0106] Accordingly, this application also provides a method for fabricating the semiconductor structure in any of the above embodiments. Please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic flowchart of a method for fabricating a semiconductor structure according to some embodiments of this application. The fabrication method includes:
[0107] Step S1: Forming a substrate, the substrate including a capacitor region;
[0108] Step S2: A plurality of first electrode structures are formed on the surface of the substrate of the capacitor region. The plurality of first electrode structures are discrete from each other and arranged along a first direction, which is parallel to the surface of the substrate.
[0109] Step S3: A first dielectric layer is formed on the sidewall surface and top surface of the plurality of first electrode structures;
[0110] Step S4: A second electrode structure is formed on the surface of the first dielectric layer, wherein the first dielectric layer is located between the second electrode structure and the first electrode structure, and isolates the first electrode structure from the second electrode structure.
[0111] This fabrication method can form the semiconductor structure described in any of the above embodiments. By forming multiple discrete first electrode structures, the recess phenomenon caused by the large-area first electrode structure in the planar structure during the manufacturing process can be reduced, thereby improving the reliability of the device. Furthermore, since the second electrode structure can form a capacitor between the top surface and the two side surfaces of the first electrode structure, the surface area of the first electrode structure (especially the sidewall area) is fully utilized, increasing the capacitance area relative to the planar structure, thus increasing the capacitance value without increasing the device area.
[0112] The following combination Figures 10-16 The method for forming this semiconductor structure is described. Figures 10-16 This application Figure 1 A schematic diagram of the semiconductor structure during the formation process of the embodiment.
[0113] Step S1: Forming substrate 1, wherein substrate 1 includes a capacitor region 12. See also Figure 10 .
[0114] The substrate 1 may include a memory array region (not shown) and a capacitor region 12, wherein the memory array region is used to form a memory structure and the capacitor region 12 is used to form a capacitor.
[0115] After forming substrate 1, the method for forming this semiconductor device further includes the following processes, see [link to documentation]. Figures 10 to 12 .
[0116] See Figure 10 A mask layer 60 is formed on the substrate 1. The process for forming the mask layer 60 may include a deposition process, and the material of the mask layer 60 may include a silicon oxide layer 61 and a silicon nitride layer 62 stacked together.
[0117] See Figure 11 A trench T is formed that penetrates the mask layer 60 and the substrate 1. The process for forming the trench T may include a dry etching process.
[0118] See Figure 12 An isolation structure 102 is formed within the trench T.
[0119] The method for forming the isolation structure 102 may include: forming an isolation material layer within the trench T and on the surface of the mask layer 60; and performing a planarization process on the isolation material layer until the surface of the mask layer 60 is exposed. The process for forming the isolation material layer may include a deposition process, the material of the isolation material layer may include silicon oxide, and the planarization process may include a chemical mechanical polishing process. An active region 101 is formed between two adjacent isolation structures 102.
[0120] Step S2: A plurality of first electrode structures 20 are formed on the surface of the substrate 1 in the capacitor region 12. The plurality of first electrode structures 20 are discrete from each other and arranged along a first direction X, which is parallel to the surface of the substrate 1. See also Figures 13 to 14 .
[0121] See Figure 13 After forming the isolation structure 102, the mask layer 60 is removed to form a first groove 63 located between adjacent isolation structures 102. The process of removing the mask layer 60 includes a wet etching process.
[0122] See Figure 14 The first electrode structure 20 is formed in the first groove 63.
[0123] The method of forming the first electrode structure 20 includes: forming a first electrode material layer in the first groove 63 and on the surface of the isolation structure 102; and performing a planarization process on the first electrode material layer until the isolation structure 102 is exposed.
[0124] The process for forming the first electrode material layer includes one of various deposition processes and an etching process. The material of the first electrode material layer may include polycrystalline silicon, and the planarization process includes chemical mechanical polishing. The etching process can be performed according to the desired pattern of the first electrode structure 20 in the top view provided in any of the above embodiments.
[0125] The method for forming the semiconductor device may further include: forming a plurality of floating gate structures located on the surface of the substrate 1 of the memory array region in the process of forming a plurality of the first electrode structures 20.
[0126] In some embodiments, a second dielectric layer 42 is formed at the bottom of the first groove 63 before the first electrode structure 20 is formed in the first groove 63.
[0127] In some embodiments, the method of forming the second dielectric layer 42 includes forming a second dielectric material layer at the bottom and sidewalls of the first groove 63, wherein the second dielectric material layer at the bottom of the first groove 63 forms the second dielectric layer 42, and the second dielectric material layer at the sidewalls of the first groove 63 may be part of the isolation structure 102. The process of forming the second dielectric material layer includes a deposition process, and the material of the second dielectric material layer may include silicon oxide.
[0128] Step S3: A first dielectric layer 41 is formed on the sidewall surfaces 21 and top surfaces 22 of the plurality of first electrode structures 20. See also Figures 15 to 16 .
[0129] See Figure 15 The portion of the isolation structure 102 located between adjacent first electrode structures 20 is removed to form a second groove 64. The process of removing the portion of the isolation structure 102 includes a wet etching process, and the bottom surface of the second groove 64 may be higher than the top surface of the second dielectric layer 42.
[0130] See Figure 16 The first dielectric layer 41 is formed on the inner wall of the second groove 64 and the surface of the first electrode structure 20. The process of forming the first dielectric layer 41 may include a deposition process. The first dielectric layer 41 may include a silicon oxide layer 61 or a silicon nitride layer 62, or may include a silicon oxide layer 61, a silicon nitride layer 62 and a silicon oxide layer 61 stacked together.
[0131] The method for forming the semiconductor device may further include: forming a storage layer located on the sidewall surface 21 and the top surface 22 of the floating gate structure in the process of forming the first dielectric layer 41.
[0132] Step S4: A second electrode structure 30 is formed on the surface of the first dielectric layer 41. The first dielectric layer 41 is located between the second electrode structure 30 and the first electrode structure 20, and isolates the first electrode structure 20 from the second electrode structure 30. See also Figure 16 .
[0133] In some embodiments, during the process of forming the second electrode structure 30, a portion of the second electrode structure 30 fills the gap between adjacent first electrode structures 20.
[0134] The method for forming the second electrode structure 30 includes: forming a second electrode material layer on the surface of the first dielectric layer 41; and performing an etching process on the second electrode material layer to form the second electrode structure 30. The material of the second electrode material layer may include polysilicon, and the etching process may be performed according to the desired pattern of the second electrode structure 30 in the top view provided in any of the above embodiments.
[0135] The method for forming the semiconductor device may further include: in the process of forming the second electrode structure 30, forming a control gate structure located on the surface of the memory layer, wherein the memory layer is located between the floating gate structure and the control gate structure, and isolates the floating gate structure from the control gate structure.
[0136] Therefore, the semiconductor device formation method provided in this application embodiment can be compatible with the processes of memory structures and capacitors, and can solve the problem of the depression of the first electrode structure 20 and increase the capacitance value of the capacitor.
[0137] You can refer to Figure 4 The method for forming the semiconductor device may further include: forming a first contact structure 51 electrically connected to the first electrode structure 20; forming a second contact structure 52 electrically connected to the second electrode structure 30; and forming a third contact structure 53 electrically connected to the substrate. The material of the contact structure may include tungsten, and the process for forming the contact structure may include etching and deposition processes, which will not be elaborated here.
[0138] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0139] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0140] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0141] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A semiconductor device, characterized in that, include: Substrate, including the capacitor region; A plurality of first electrode structures are located on the substrate surface of the capacitor region. The plurality of first electrode structures are discrete from each other and arranged along a first direction, which is parallel to the substrate surface. The second electrode structure is located on the sidewall surface and top surface of a plurality of first electrode structures; A first dielectric layer is located between the second electrode structure and the first electrode structure, and isolates the first electrode structure from the second electrode structure.
2. The semiconductor device according to claim 1, characterized in that, The extension direction of the plurality of first electrode structures is parallel to a second direction, which is parallel to the substrate surface and is different from the first direction.
3. The semiconductor device according to claim 2, characterized in that, The first electrode structure includes a first side and a second side opposite to each other along the first direction, and the second electrode structure is located on the first side and the second side.
4. The semiconductor device according to claim 2, characterized in that, The first electrode structure further includes a third side and a fourth side opposite to each other along the second direction, and the second electrode structure is also located on the third side and / or the fourth side.
5. The semiconductor device according to claim 2, characterized in that, Also includes: A first contact structure extends in a direction perpendicular to the substrate surface and is electrically connected to the first electrode structure.
6. The semiconductor device according to claim 5, characterized in that, The first electrode structure includes two ends opposite each other along the second direction; The first contact structure is connected to at least one of the ends.
7. The semiconductor device according to claim 1, characterized in that, Also includes: A second contact structure electrically connected to the second electrode structure.
8. The semiconductor device according to claim 7, characterized in that, The second electrode structure includes a first region and a second region, wherein the second region is located on both sides of the first region along the first direction; The second contact structure is located on the surface of the second region or the surface of the first region, and the second contact structure is evenly distributed.
9. The semiconductor device according to claim 2, characterized in that, The substrate includes a plurality of active regions and an isolation structure, the isolation structure being located between adjacent active regions, and the extension direction of the active regions being parallel to the second direction and arranged along the first direction; Each of the first electrode structures is located on the surface of one of the active region substrates.
10. The semiconductor device according to claim 9, characterized in that, The active region includes a third region and a fourth region that are opposite each other along the second direction; At least one of the third and fourth regions extends beyond the first electrode structure along the second direction.
11. The semiconductor device according to claim 10, characterized in that, Also includes: The third contact structure is located in the third region and / or the fourth region.
12. The semiconductor device according to claim 10, characterized in that, The substrate further includes: The first connection area connects to a plurality of the third areas along the first direction.
13. The semiconductor device according to claim 10, characterized in that, The substrate further includes: The second connection region connects multiple fourth regions along the first direction.
14. The semiconductor device according to claim 9, characterized in that, Also includes: A second dielectric layer is located between the first electrode structure and the active region substrate.
15. The semiconductor device according to claim 1, characterized in that, The substrate further includes a storage array region; The semiconductor device further includes: a memory structure located on the surface of the substrate of the memory array region; the memory structure includes: a floating gate structure, a control gate structure, and a memory layer located between the floating gate structure and the control gate structure; The floating gate structure is disposed on the same layer as the first electrode structure, the storage layer is disposed on the same layer as the first dielectric layer, and the control gate structure is disposed on the same layer as the second electrode structure.
16. The semiconductor device according to claim 15, characterized in that, The semiconductor device further includes a tunneling layer located between the floating gate structure and the substrate.
17. A method for forming a semiconductor device, characterized in that, include: A substrate is formed, the substrate including a capacitance region; A plurality of first electrode structures are formed on the surface of the substrate in the capacitor region. The plurality of first electrode structures are discrete from each other and arranged along a first direction, which is parallel to the surface of the substrate. A first dielectric layer is formed on the sidewall surface and top surface of a plurality of the first electrode structures; A second electrode structure is formed on the surface of the first dielectric layer, the first dielectric layer being located between the second electrode structure and the first electrode structure, and isolating the first electrode structure from the second electrode structure.
18. The method for forming a semiconductor device according to claim 17, characterized in that, The substrate further includes a memory array region, and the method for forming the semiconductor device further includes: In the process of forming multiple first electrode structures, multiple floating gate structures are formed on the surface of the substrate of the memory array region; In the process of forming the first dielectric layer, a storage layer is formed on the sidewall surface and top surface of the floating gate structure; In the process of forming the second electrode structure, a control gate structure is formed on the surface of the storage layer, the storage layer being located between the floating gate structure and the control gate structure, and isolating the floating gate structure from the control gate structure.
19. The method for forming a semiconductor device according to claim 17, characterized in that, Also includes: A mask layer is formed on the substrate; A trench is formed that penetrates the mask layer and the substrate; An isolation structure is formed within the trench.
20. The method for forming a semiconductor device according to claim 19, characterized in that, A method for forming a plurality of first electrode structures on the surface of the capacitor region substrate includes: After the isolation structure is formed, the mask layer is removed to form a first groove located between adjacent isolation structures; The first electrode structure is formed within the first groove.
21. The method for forming a semiconductor device according to claim 20, characterized in that, The method for forming the first dielectric layer and the second electrode structure includes: A portion of the isolation structure located between adjacent first electrode structures is removed to form a second groove; The first dielectric layer is formed on the inner wall of the second groove and on the surface of the first electrode structure; A second electrode structure is formed on the surface of the first dielectric layer, and a portion of the second electrode structure fills the gap between adjacent first electrode structures.
22. The method for forming a semiconductor device according to claim 20, characterized in that, Also includes: Before forming the first electrode structure in the first groove, a second dielectric layer is formed at the bottom of the first groove.