A trench power mosfet and a method of manufacturing the same

Abstract

The application discloses a kind of trench power MOSFET and its preparation method, specific steps include: S1) P well region and patterned field oxide layer pattern are formed;S2) side wall silicon nitride is formed in field oxide layer pattern side wall;S3) with both as mask etching groove and forming gate oxide layer;S4) in the trench filling conductive material, form gate;S5) after removing side wall silicon nitride, with field oxide layer pattern as mask carries out N+ source region injection;S6) deposition and planarization dielectric layer;S7) remove field oxide layer and carry out over-etching to its lower silicon, form contact window;S8) by the window carries out P+ contact region injection;S9) fill metal layer, complete device production.The application fundamentally eliminates the overlaying error between trench mask and contact hole mask in conventional process to limit cell size.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices, and specifically relates to a trench power MOSFET and its fabrication method. Background Technology

[0002] Power MOSFETs are the core switching devices in modern power electronic systems, and improvements in their performance and reductions in cost have always been key drivers of industry development. One effective way to reduce device costs is to increase wafer utilization, that is, to manufacture more chips on a unit area of ​​wafer, which requires continuously shrinking the cell size of devices.

[0003] In the manufacturing process of traditional trench power MOSFETs, the miniaturization of cell size is mainly limited by two key photolithography layers—the trench and the contact via. This is not only because the dimensions of these two layers are limited by the photolithography process, but also because there are physical limits to the overlay precision between them. To ensure device reliability and avoid short circuits between the contact via and the trench gate or poor contact with the source region due to misalignment, sufficient overlay tolerance must be maintained between them in the design. This safety clearance directly increases the lateral dimension of the cell, thus becoming a major bottleneck restricting further cell miniaturization and moving towards smaller design rules.

[0004] In existing technologies, complex structures such as superjunctions or shielded gates are often introduced to improve performance or density. However, this usually involves an increase in process steps and the number of photomask layers, leading to a significant increase in manufacturing costs and partially offsetting the benefits of increased density. Therefore, there is an urgent need for a solution that can effectively overcome the limitations of cell size imposed by overlay accuracy without significantly increasing process complexity and the number of photomasks. Summary of the Invention

[0005] To address the problems of existing technologies, this invention provides a trench power MOSFET and its fabrication method. Through innovative process integration design, it uses only one photolithography-defined field oxide layer pattern and utilizes residual sidewall silicon nitride to complete the trench process. This eliminates the photolithography size limitations required for a single trench and uses the field oxide layer pattern as the sole positional reference to guide the entire process of subsequent trench etching, source implantation, and contact hole formation, thereby achieving self-alignment between the contact hole, trench, and source region. This method fundamentally eliminates the limitations on cell size caused by the overlay error between the trench mask and the contact hole mask in traditional processes.

[0006] The main technical solution adopted in this invention is as follows: A method for fabricating a trench power MOSFET includes the following steps: S1: A P-well region is formed in the N-type epitaxial layer, and a field oxide layer is deposited on the N-type epitaxial layer. The field oxide layer is patterned by a single photolithography process to form a field oxide layer pattern. S2: Deposit a silicon nitride layer and etch it to form sidewall silicon nitride on both sides of the field oxide layer pattern; S3: Using the field oxide layer pattern and sidewall silicon nitride as a mask, the N-type epitaxial layer is etched to form a trench, and a gate oxide layer is grown on the inner wall of the trench; S4: Fill the trench with conductive material to form a gate; S5: After removing the sidewall silicon nitride, N-type ion implantation is performed using the field oxide layer pattern as a mask to form an N+ source region on the surface of the P-well region. S6: Deposit a dielectric layer and planarize it until the top surface of the field oxide pattern is exposed; S7: Remove the field oxide layer pattern and over-etch the N-type epitaxial layer below it to form a contact window. The position of the contact window is defined by the pattern of the field oxide layer pattern. S8: P-type ion implantation is performed through the contact window to form a P+ contact region in the P-trap region; S9: Fill the contact window with a metal layer and cover it with a dielectric layer to form an electrical connection, thus obtaining a trench power MOSFET.

[0007] Preferably, in step S1, the deposition thickness of the field oxide layer is 0.6-1.5 μm.

[0008] Preferably, in step S2, the deposition thickness of the silicon nitride layer is 0.5-1.2 μm.

[0009] Preferably, in step S3, the growth thickness of the gate oxide layer is 0.02-0.1 μm.

[0010] Preferably, the conductive material being filled is N-type doped polycrystalline silicon, with an overall concentration ≥ 5 × 10⁻⁶. 18 cm -3 .

[0011] Preferably, the deposition thickness of the dielectric layer is greater than the thickness of the field oxide layer.

[0012] Preferably, the over-etching depth of the N-type epitaxial layer is 0.02-0.05 μm, so that the bottom surface of the contact window is lower than the original top surface of the N-type epitaxial layer.

[0013] A trench power MOSFET, comprising: N-type epitaxial layer; The P-well region is located in the epitaxial layer; An N+ source region and a P+ contact region are provided on the surface of the P-well region, with the N+ source region located on both sides of the P+ contact region; A trench penetrating the P-well region has a gate oxide layer grown on its inner wall and is filled with conductive material to form a gate. The N+ source region is in contact with the sidewall of the trench. A dielectric layer covering the N-type epitaxial layer, wherein the dielectric layer has contact windows that expose the N+ source region and the P+ contact region; and a metal layer that covers the surface of the dielectric layer and fills the contact window; The relative positions of the contact window, the N+ source region, and the trench in the horizontal direction are formed by the graphic definition of the same oxide layer pattern.

[0014] Preferably, the bottom surface of the contact window is lower than the surface of the N-type epitaxial layer.

[0015] Beneficial effects: This invention provides a trench power MOSFET and its fabrication method, which has the following advantages: (1) The present invention combines the definition of groove and metal buckle contact hole into a single photomask, directly saving an expensive photolithography process step and related mask costs.

[0016] (2) Since the present invention eliminates the need for a layer of photolithography and its inherent alignment tolerance requirements, it fundamentally eliminates the limitation of the minimum cell size by the alignment error, so that the cell size can be further reduced and is only limited by the limit resolution of a single photolithography, thereby obtaining more bare dies on the same area of ​​wafer and effectively reducing the unit chip cost.

[0017] (3) The self-aligned structure based on the field oxide layer pattern of the present invention ensures the precise positional relationship between the contact window, the trench and the source region, avoiding the risk of failure due to increased contact resistance in the source region or gate-source short circuit caused by misalignment, thereby improving the consistency of device performance and production yield. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of step S1 in Example 1; Figure 2 This is a schematic diagram of step S2 in Example 1. Figure I ; Figure 3 This is a schematic diagram of step S2 in Example 1. Figure II ; Figure 4 This is a schematic diagram of step S3 in Example 1; Figure 5 This is a schematic diagram of step S4 in Example 1; Figure 6This is a schematic diagram of step S5 in Example 1; Figure 7 This is a schematic diagram of step S6 in Example 1. Figure I ; Figure 8 This is a schematic diagram of step S6 in Example 1. Figure II ; Figure 9 This is a schematic diagram of steps S7 and S8 in Example 1; Figure 10 This is a schematic diagram of the device structure in Example 1; In the figure: N-type epitaxial layer 100, P-well region 101, field oxide pattern 102a, gate oxide layer 102b, silicon nitride layer 103, sidewall silicon nitride 103a, gate 104, N+ source region 105, dielectric layer 106, P+ contact region 107, metal layer 108, trench 109, contact window 110. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application are clearly and completely described below. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application. Example 1

[0020] This embodiment provides a method for fabricating a trench power MOSFET, the specific steps of which are as follows: S1: A P-well region 101 is formed within the N-type epitaxial layer 100, and a field oxide layer is deposited and patterned on the N-type epitaxial layer 100; specifically, as shown... Figure 1 As shown, firstly, a P-type dopant (e.g., boron ions) is directly implanted into the N-type epitaxial layer 100 using an ion implantation process, and then diffused at a high temperature (e.g., 1000℃~1100℃) to form a P-well region 101. Next, a field oxide layer is formed on the N-type epitaxial layer 100. This field oxide layer can be formed by thermal oxidation, chemical vapor deposition (CVD), or other suitable deposition processes. The thickness of the field oxide layer is preferably 1.0 μm, and its thickness can be adjusted between 0.6-1.5 μm. Subsequently, the field oxide layer is patterned using a single photolithography process to form a field oxide layer pattern 102a. This field oxide layer pattern 102a serves as a mask for subsequent steps.

[0021] S2: On the structure obtained in step S1, a silicon nitride layer is deposited and etched to form sidewall silicon nitride 103a on both sides of the field oxide pattern 102a; specifically, as shown... Figure 2 and Figure 3 As shown, a silicon nitride layer 103 can be deposited using low-pressure chemical vapor deposition (LPCVD), with a preferred deposition thickness of 0.8 μm, which can be adjusted between 0.5 and 1.2 μm. Next, anisotropic dry etching (such as reactive ion etching, RIE) is used to etch back the silicon nitride layer 103 across the entire surface, retaining silicon nitride only on the two sidewalls of the field oxide pattern 102a, forming sidewall silicon nitride 103a.

[0022] S3: As Figure 4 As shown, using the field oxide pattern 102a and sidewall silicon nitride 103a as a mask, the N-type epitaxial layer 100 is etched to form a trench 109. Subsequently, a gate oxide layer 102b is grown on the inner wall of the trench 109. In one example, the gate oxide layer 102b is grown using a thermal oxidation process (e.g., in an oxygen-containing atmosphere at 900°C–1000°C). Its thickness is, for example, 0.02–0.1 μm, and can be adjusted according to the device threshold voltage requirements. In this step, the etching process may include dry etching, such as fluorine-based plasma etching.

[0023] S4: As Figure 5 As shown, a conductive material is filled within the trench 109 to form the gate 104. In one example, the conductive material is N-type doped polysilicon with an overall concentration ≥ 5 × 10⁻⁶. 18 cm -3 To ensure low gate resistance. After filling, excess conductive material outside the trench can be removed by planarization processes such as chemical mechanical polishing (CMP) or etching back, so that the conductive material is confined within the trench 109.

[0024] S5: After removing the sidewall silicon nitride 103a, N-type ion implantation is performed using the field oxide pattern 102a as a mask to form the N+ source region 105. Specifically, as follows... Figure 6 As shown, the sidewall silicon nitride 103a, which serves as a temporary mask, is selectively removed (e.g., using a hot phosphoric acid wet etching process with high selectivity for silicon nitride). Then, using the remaining field oxide pattern 102a as an implantation mask, N-type ion implantation (such as arsenic or phosphorus) is performed. The N-type ions enter the region not covered by the field oxide pattern 102a, forming an N+ source region 105 on the surface of the P-well region 101. Due to the presence of the mask, the N+ source region 105 is aligned with the trench sidewall.

[0025] S6: Deposit a dielectric layer and planarize it until the top surface of the field oxide pattern is exposed; specifically, as shown in... Figure 7 and Figure 8As shown, a dielectric layer 106 is deposited across the entire device surface, and its deposition thickness must be greater than the thickness of the field oxide pattern 102a. Subsequently, the dielectric layer 106 is planarized, for example by chemical mechanical polishing (CMP), until the top surface of the field oxide pattern 102a is exposed.

[0026] S7: As Figure 9 As shown, the field oxide pattern 102a is first removed, followed by over-etching of the underlying epitaxial layer to form a contact window 110, the position of which is uniquely determined by the field oxide pattern. For example, a wet etchant such as diluted hydrofluoric acid (DHF) can be used to selectively remove the oxide pattern 102a. During this process, the etchant will over-etch the exposed silicon (the surface of the N-type epitaxial layer 100 / N+ source region 105) to a certain extent. The over-etching depth is preferably 0.03 μm, and the over-etching depth range can be between 0.02 and 0.05 μm, thereby forming a contact window 110 whose bottom surface is slightly lower than the original silicon surface (i.e., the surface of the N-type epitaxial layer 100). The position of this contact window 110 is precisely determined by the position of the removed field oxide pattern 102a.

[0027] S8: As Figure 9 As shown, P-type ions (such as boron) are implanted through the contact window 110 to form a P+ contact region 107; the P+ contact region 107 is formed in the central region at the bottom of the contact window 110.

[0028] S9: Fill the contact window 110 with a metal layer 108 and cover it with a dielectric layer 106 to form an electrical connection, thus completing the fabrication of the device. Figure 10 As shown.

[0029] Based on the above preparation method, this embodiment yields a trench power MOSFET, the structure of which is as follows: Figure 10 As shown, the device structure includes: The N-type epitaxial layer 100 has an overall concentration ≥1e16cm⁻¹. -3 The doping ion is phosphorus; The P-well region 101 in the N-type epitaxial layer 100 is doped with boron ions at a concentration of 3e12~3e13 cm⁻¹. -2 ; An N+ source region 105 and a P+ contact region 107 are disposed on the surface of the P-well region 101. Specifically, the N+ source region 105 is located on both sides of the P+ contact region 107 and contacts the sidewalls of the trench to be formed subsequently. The dopant ions in the N+ source region 105 are arsenic ions or phosphorus ions, and the doping concentration is 5e14~1e16cm. -2The P+ contact region 107 is used to reduce the contact resistance of the P-well region 101, ensuring stable device operation. The doping ions in the P+ contact region 107 are boron ions or boron difluoride, with a doping concentration of 1e14~1e15cm. -2 .

[0030] A trench 109 extends through the P-well region 101 and into the N-type epitaxial layer 100. A gate oxide layer 102b is grown on the inner wall of the trench 109, and the trench 109 is filled with conductive material to form a gate 104. A dielectric layer 106 is provided on top of the N-type epitaxial layer 100 (i.e., device structure), and a contact window 110 is provided in the dielectric layer 106 to expose the N+ source region 105 and the P+ contact region 107. A metal layer 108 covering the surface of the dielectric layer 106 and filling the contact window 110 forms a source metal interconnect for realizing the electrical connection between the N+ source region 105 and the P+ contact region 107.

[0031] In this embodiment 1, the position and size of the contact window 110 in the horizontal direction (i.e., the direction parallel to the semiconductor surface) are not defined by a single photolithography process, but are defined and formed by a pre-formed field oxide layer pattern in a single photolithography step. This makes the alignment accuracy between the contact window 110 and the active area (especially the trench) no longer limited by the overlay accuracy of the contact hole photolithography, thereby improving integration density and reliability.

[0032] In a preferred embodiment, the bottom surface of the contact window 110 is lower than the original upper surface of the N-type epitaxial layer 100. This "recessed" structure design increases the contact area between the metal layer 108 and the source / contact region, further reducing the contact resistance.

[0033] In a preferred embodiment, the thickness of the dielectric layer 106 is 0.8 μm to 1.5 μm.

[0034] In a preferred embodiment, the thickness of the silicon nitride layer 103 is 0.5 μm to 1.2 μm.

[0035] Through the above process, the present invention uses the field oxide layer pattern defined by a single photolithography as a mask, which runs through multiple key steps such as trench etching, source injection and contact hole definition. This greatly reduces the number of alignment photolithography steps, reduces yield loss caused by overlay errors, and achieves smaller cell design, thereby improving the power density and performance consistency of power MOSFETs.

[0036] It should be noted that the above embodiments are provided only to clearly and completely illustrate the technical solution of the present invention, and are not intended to limit the scope of protection of the present invention. After understanding the technical solution of the present invention, those skilled in the art can make various modifications, substitutions, or variations to the specific materials, process steps, process parameters, and conditions described.

[0037] For example, but not limited to: The specific methods for forming the N-type epitaxial layer and P-well region are not limited to ion implantation and diffusion, but can also employ techniques such as epitaxial growth; the doping concentration and dosage can be flexibly adjusted according to the device's withstand voltage level and target on-resistance.

[0038] The materials of the field oxide layer, gate oxide layer and dielectric layer are not limited to silicon oxide, but may include silicon nitride, silicon oxynitride or their composite stacked structure; and different thermal growth or deposition techniques may be used to form them.

[0039] The gate material is not limited to N-type heavily doped polysilicon; P-type doped polysilicon, metal, metal silicide, or other conductive materials may also be used.

[0040] Planarization processes are not limited to chemical mechanical polishing (CMP), but can also employ etching-back processes or combinations thereof.

[0041] The metal layer can be made of interconnecting materials such as aluminum, copper, cobalt or their alloys, and corresponding barrier / adhesive layer structures.

[0042] The specific process parameters (such as temperature, time, thickness, and concentration) in each step can be optimized and adjusted within the range required to achieve the process objective.

[0043] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a trench power MOSFET, characterized in that, Includes the following steps: S1: A P-well region is formed in the N-type epitaxial layer, and a field oxide layer is deposited on the N-type epitaxial layer. The field oxide layer is patterned by a single photolithography process to form a field oxide layer pattern. S2: Deposit a silicon nitride layer and etch it to form sidewall silicon nitride on both sides of the field oxide layer pattern; S3: Using the field oxide layer pattern and sidewall silicon nitride as a mask, the N-type epitaxial layer is etched to form a trench, and a gate oxide layer is grown on the inner wall of the trench; S4: Fill the trench with conductive material to form a gate; S5: After removing the sidewall silicon nitride, N-type ion implantation is performed using the field oxide layer pattern as a mask to form an N+ source region on the surface of the P-well region. S6: Deposit a dielectric layer and planarize it until the top surface of the field oxide pattern is exposed; S7: Remove the field oxide layer pattern and over-etch the N-type epitaxial layer below it to form a contact window. The position of the contact window is defined by the pattern of the field oxide layer pattern. S8: P-type ion implantation is performed through the contact window to form a P+ contact region in the P-trap region; S9: Fill the contact window with a metal layer and cover it with a dielectric layer to form an electrical connection, thus obtaining a trench power MOSFET.

2. The preparation method according to claim 1, characterized in that, In step S1, the deposition thickness of the field oxide layer is 0.6-1.5 μm.

3. The preparation method according to claim 1, characterized in that, In step S2, the deposition thickness of the silicon nitride layer is 0.5-1.2 μm.

4. The preparation method according to claim 1, characterized in that, In step S3, the growth thickness of the gate oxide layer is 0.02-0.1 μm.

5. The preparation method according to claim 1, characterized in that, In step S4, the conductive material used for filling is N-type doped polycrystalline silicon, with an overall concentration ≥ 5 × 10⁻⁶. 18 cm -3 .

6. The preparation method according to claim 1, characterized in that, In step S6, the deposition thickness of the dielectric layer is greater than the thickness of the field oxide layer.

7. The preparation method according to claim 1, characterized in that, In step S7, the over-etching depth of the N-type epitaxial layer is 0.02-0.05 μm, so that the bottom surface of the contact window is lower than the original top surface of the N-type epitaxial layer.

8. A trench power MOSFET, characterized in that, The power MOSFET is prepared by the method according to any one of claims 1 to 7, and comprises: N-type epitaxial layer; The P-well region is located in the epitaxial layer; An N+ source region and a P+ contact region are provided on the surface of the P-well region, with the N+ source region located on both sides of the P+ contact region; A trench penetrating the P-well region has a gate oxide layer grown on its inner wall and is filled with conductive material to form a gate. The N+ source region is in contact with the sidewall of the trench. A dielectric layer covering the N-type epitaxial layer, wherein the dielectric layer has contact windows that expose the N+ source region and the P+ contact region; and a metal layer that covers the surface of the dielectric layer and fills the contact window; The relative positions of the contact window, the N+ source region, and the trench in the horizontal direction are formed by the graphic definition of the same oxide layer pattern.

9. The trench power MOSFET according to claim 8, characterized in that, The bottom surface of the contact window is lower than the surface of the N-type epitaxial layer.

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