A silicon carbide mosfet device and method of manufacturing the same

Abstract

The application relates to the technical field of power electronic devices, and provides a silicon carbide MOSFET device and a manufacturing method thereof. The source region structure of the silicon carbide MOSFET device comprises: a first n-type region, which is a nitrogen ion implantation region, and the lateral boundary of which is self-aligned with the boundary of a p-type well region; a second n-type region, which is a phosphorus ion implantation region, and is located in the first n-type region; the lateral extension width of the first n-type region is greater than the lateral extension width of the second n-type region, and the lateral boundaries of the two have a fixed lateral offset; the lateral boundary of the second n-type region is inwardly recessed relative to the edge of a polysilicon gate, thereby forming a lateral buffer gap, which is used for deviating a high-concentration phosphorus implantation damage region of the second n-type region from a gate oxide layer; and a metal silicide layer is located above the second n-type region, and is used for forming a source region contact. The application realizes inward retraction of the phosphorus implantation region through a self-alignment process, and reduces the contact resistance by using the high solid solubility of phosphorus while protecting the gate oxide layer.

Description

Technical Field

[0001] This application relates to the field of power electronic device technology, specifically to a silicon carbide MOSFET device and its manufacturing method. Background Technology

[0002] Figure 1 A silicon carbide (SiC)-based metal-oxide-semiconductor field-effect transistor (MOSFET) structure is shown, comprising, from bottom to top: an N-type heavily doped silicon carbide substrate 9, an N-type silicon carbide epitaxial layer 8, a P-type well region 7, and an isolation oxide layer 6. The gate structure consists of a gate oxide layer 5 and a polysilicon gate 4 located above the P-type well region, with an interlayer dielectric layer 3 and a gate metal layer 2 covering the gate. In the source region, the structure includes a metal silicide 11 located above the heavily doped P-type region 12, and contacts are achieved through the source metal layer 1; furthermore, a guard ring (GR) structure for edge termination (i.e., Figure 1 (The four adjacent narrow blue rectangles on the left and the one wide blue rectangle immediately next to these four narrow blue rectangles).

[0003] 1. In the SiC MOSFET structure, n-type doping of the source region with N14 has the advantages of mature process and stable diffusion, but the solid solubility is limited and the contact resistance is high. 2. The n-type doped P31 source region has high solid solution and activation efficiency, which can significantly reduce Rc, but the lattice damage is severe and the diffusion is slightly stronger than that of N14. 3. When administering N14 and P31 simultaneously, the dosage ratio and energy position must be precisely controlled. Otherwise, the gate oxide above the P31 area may be defective, raising concerns about reliability failure. Summary of the Invention

[0004] To help solve the above-mentioned technical problems, this application provides a silicon carbide MOSFET device and a method for manufacturing the same, using the following technical solution: In a first aspect, this application provides a silicon carbide MOSFET device, which includes a source region structure formed in a p-type well region, wherein the source region structure includes: A first n-type region is a nitrogen ion implantation region, and the lateral boundary of the first n-type region is self-aligned with the boundary of the p-type well region. A second n-type region is a phosphorus ion implantation region, and the second n-type region is located within the first n-type region; Wherein, the horizontal extension width of the first n-type region is greater than the horizontal extension width of the second n-type region, so that there is a fixed horizontal offset between the horizontal boundary of the first n-type region and the horizontal boundary of the second n-type region. The lateral boundary of the second n-type region is recessed inward relative to the edge of the polysilicon gate above the p-type well region to form a lateral buffer gap between the second n-type region and the polysilicon gate. The lateral buffer gap is used to deflect the high-concentration phosphorus implantation damage region of the second n-type region away from the gate oxide layer below the polysilicon gate. A metal silicide layer is located above the second n-type region and the p-type heavily doped region to form the source region contact.

[0005] Also includes: An N-type heavily doped silicon carbide substrate; An N-type silicon carbide epitaxial layer is located on the N-type heavily doped silicon carbide substrate; The p-type well region is formed on the upper part of the N-type silicon carbide epitaxial layer; A gate oxide layer is located above the N-type silicon carbide epitaxial layer and above the p-type well region; The polysilicon gate is located above the gate oxide layer; A dielectric layer is used to cover the polysilicon gate; A source metal layer is formed on the interlayer dielectric layer and electrically connected to the metal silicide layer; A drain metal layer is formed on the back side of the N-type heavily doped silicon carbide substrate; A heavily doped p-type region is formed within the p-type well region to provide an electrical connection between the p-type well region and the source metal layer.

[0006] Secondly, this application provides a method for manufacturing a silicon carbide MOSFET device, wherein the method for manufacturing the silicon carbide MOSFET device as described in the first aspect includes the following steps: A hard mask for defining a p-type well injection region is formed on a semiconductor, and a p-type conductor is injected at a predetermined angle to form the p-type well region; A first sidewall is formed in the opening area of ​​the hard mask, and then nitrogen ions are injected to form the first n-type region, so that the lateral boundary of the first n-type region is self-aligned with the boundary of the p-type well region; After the first sidewall is formed, a second sidewall is formed in the opening area of ​​the hard mask, and then phosphorus ions are injected to form the second n-type region, such that the second n-type region is located within the first n-type region, and the lateral extension width of the first n-type region is greater than the lateral extension width of the second n-type region, and the lateral boundary of the second n-type region has a fixed lateral offset between the lateral boundary of the first n-type region and the lateral boundary of the first n-type region, wherein the fixed lateral offset is determined by the thickness of the second sidewall. A metal silicide layer is formed above the second n-type region to reduce the contact resistance of the source region structure.

[0007] The first sidewall formation step includes: depositing oxide and polysilicon at the edge of the hard mask opening area and then etching to form the first sidewall; the second sidewall formation step includes: after the first sidewall is formed, depositing polysilicon in the hard mask opening area and then etching to form the second sidewall.

[0008] It also includes the following steps: After the second sidewall is formed, a p-type heavily doped region is implanted using another hard mask to form a p-type heavily doped region. After injection, tempering and activation are performed at a preset temperature; Growing gate oxide and polysilicon to form the polysilicon gate; Interlayer dielectric layer; A contact window is formed to expose the second n-type region and the p-type heavily doped region, forming a metal silicide layer; A source metal layer is deposited to fill the contact window and cover the interlayer dielectric layer; Crystal back grinding is performed to deposit nickel silicide and drain metal layer on the back side of the semiconductor substrate.

[0009] Thirdly, this application provides a silicon carbide MOSFET device, which includes a source region structure formed within a multilayer p-type well region, wherein the source region structure includes: A first n-type region is a nitrogen ion implantation region, and the lateral boundary of the first n-type region is self-aligned with the boundary of a first p-type well region. A second n-type region is a phosphorus ion implantation region, and the second n-type region is located within the first n-type region; Wherein, the horizontal extension width of the first n-type region is greater than the horizontal extension width of the second n-type region, so that there is a fixed horizontal offset between the horizontal boundary of the first n-type region and the horizontal boundary of the second n-type region. The lateral boundary of the second n-type region is recessed inward relative to the edge of the polysilicon gate above the first p-type well region to form a lateral buffer gap between the second n-type region and the polysilicon gate. The lateral buffer gap is used to deflect the high-concentration phosphorus implantation damage region of the second n-type region away from the gate oxide layer below the polysilicon gate. A metal silicide layer is located above the second n-type region and the p-type heavily doped region to form the source region contact; A second p-type well region is located below the first n-type region; A third p-type well region is located below the second n-type region.

[0010] Also includes: An N-type heavily doped silicon carbide substrate; An N-type silicon carbide epitaxial layer is located on the N-type heavily doped silicon carbide substrate; The first p-type well region is formed on the upper part of the N-type silicon carbide epitaxial layer; The second p-type well region is formed below the first n-type region and overlaps the first n-type region perpendicularly; The third p-type well region is formed below the second n-type region and overlaps vertically with the second n-type region; A gate oxide layer is located above the N-type silicon carbide epitaxial layer and above the first p-type well region; The polysilicon gate is located above the gate oxide layer; A dielectric layer is used to cover the polysilicon gate; A source metal layer is formed on the interlayer dielectric layer and electrically connected to the metal silicide layer; A drain metal layer is formed on the back side of the N-type heavily doped silicon carbide substrate; A heavily doped p-type region is formed within the first p-type well region to provide an electrical connection between the first p-type well region and the source metal layer.

[0011] Fourthly, this application provides a method for manufacturing a silicon carbide MOSFET device, wherein the method for manufacturing the silicon carbide MOSFET device as described in the third aspect includes the following steps: A hard mask for defining a p-type well injection region is formed on a semiconductor, and a first p-type conductor is injected at a preset angle to form the first p-type well region; A first sidewall is formed in the opening area of ​​the hard mask, and then nitrogen ions and a second p-type conductor are implanted to form the first n-type region and the second p-type well region, respectively, so that the lateral boundary of the first n-type region is self-aligned with the boundary of the first p-type well region, and the second p-type well region is located below the first n-type region. After the first sidewall is formed, a second sidewall is formed in the opening area of ​​the hard mask. Then, phosphorus ions and a third p-type conductor are implanted to form the second n-type region and the third p-type well region, respectively. The second n-type region is located within the first n-type region, and the lateral extension width of the first n-type region is greater than the lateral extension width of the second n-type region. A fixed lateral offset is made between the lateral boundary of the second n-type region and the lateral boundary of the first n-type region. The fixed lateral offset is determined by the thickness of the second sidewall. The third p-type well region is located below the second n-type region. A metal silicide layer is formed above the second n-type region to reduce the contact resistance of the source region structure.

[0012] The first sidewall formation step includes: depositing oxide and polysilicon at the edge of the hard mask opening area and then etching to form the first sidewall; the second sidewall formation step includes: after the first sidewall is formed, depositing polysilicon in the hard mask opening area and then etching to form the second sidewall.

[0013] It also includes the following steps: After the second sidewall is formed, a p-type heavily doped region is implanted using another hard mask to form a p-type heavily doped region. After injection, tempering and activation are performed at a preset temperature; Growing gate oxide and polysilicon to form the polysilicon gate; Interlayer dielectric layer; A contact window is formed to expose the second n-type region and the p-type heavily doped region, forming a metal silicide layer; A source metal layer is deposited to fill the contact window and cover the interlayer dielectric layer; Crystal back grinding is performed to deposit nickel silicide and drain metal layer on the back side of the semiconductor substrate.

[0014] In summary, this application utilizes a double-layer sidewall (spacer) self-alignment process to shrink the phosphorus implantation region (second n-type region) inward, maintaining a lateral gap with the edge of the polysilicon gate. This effectively protects the gate oxide layer from phosphorus implantation damage while utilizing the high solid solubility of phosphorus to reduce the source region contact resistance. Simultaneously, the self-alignment process eliminates the impact of photolithographic alignment deviations on device performance, supporting device miniaturization. Attached Figure Description

[0015] Figure 1 The accompanying drawings are related to the background technology. Figure 2 This is a schematic diagram of the structure of a first embodiment of a silicon carbide MOSFET device according to this application; Figure 3 for Figure 2 A schematic flowchart of the manufacturing method of the embodiment shown; Figure 4 for Figure 3 A schematic diagram of the status of the second process node in the process; Figure 5 for Figure 3 A schematic diagram of the status of the third process node in the process; Figure 6 for Figure 3 A status diagram of the fourth process node in the process; Figure 7 for Figure 3 A status diagram of the fifth process node in the process; Figure 8 for Figure 3A status diagram of the sixth and seventh process nodes in the process; Figure 9 for Figure 3 A status diagram of the eighth process node in the process; Figure 10 for Figure 3 A status diagram of the ninth process node in the process; Figure 11 This is a schematic diagram of the structure of a second embodiment of a silicon carbide MOSFET device according to this application; Figure 12 for Figure 11 A schematic flowchart of the manufacturing method of the embodiment shown.

[0016] Reference numerals: 1-Source metal layer; 2-Gate metal layer; 3-Interlayer dielectric layer; 4-Polysilicon gate; 5-Gate oxide layer; 6-Isolation oxide layer; 7-P-type well region; 8-N-type silicon carbide epitaxial layer; 9-N-type heavily doped silicon carbide substrate; 10-N-type region; 11A-Source metal silicide layer; 11B-Drain metal silicide layer; 12-Heavily doped p-type region; 13-First n-type region; 14-Second n-type region; 15-First p-type well region; 16-Second p-type well region; 17-Third p-type well region; 18-Drain metal layer; 19-Hard mask; 20-Hard mask opening region; 21-First sidewall; 22-Second sidewall. Detailed Implementation

[0017] The present application will be further described below with reference to the accompanying drawings. The principles of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0018] To facilitate understanding of the technical solution of this application, the main English terms involved in this application and their Chinese translations are explained below: Source metal, gate metal, inter-layer dielectric (ILD), polysilicon gate, gate oxide, field oxide, p-well, N-SiC epitaxial layer, N-SiC substrate, Ni silicide, p-doped region (p+), hard mask (HM).

[0019] In the field of semiconductor device manufacturing, "self-aligned" refers to using the existing structure of the device itself, such as sidewalls or hard masks, as a mask to automatically define the position of subsequent process steps, such as ion implantation and etching, so as not to rely on photolithography alignment accuracy to ensure the relative positional relationship between the structures.

[0020] In traditional processes, alignment between different layers relies on the alignment precision of the lithography machine. As device dimensions continue to shrink, lithographic alignment errors have become a significant factor limiting device performance uniformity and yield. Self-alignment technology, through structural design, allows critical dimensions to be determined by film thickness rather than lithographic precision, fundamentally eliminating the impact of alignment errors.

[0021] In this application, the self-alignment technique is implemented in the following ways: 1. First layer self-alignment: self-alignment of the first n-type region 13 and the p-type well region 7.

[0022] After forming the p-type well region 7, oxide and polysilicon are deposited at the edge of the hard mask opening region 20 and etched to form a first sidewall 21. The position of the outer sidewall of the first sidewall 21 is precisely determined by the deposition thickness and is independent of photolithography alignment. Subsequently, nitrogen ion implantation is performed using the first sidewall 21 as a mask to form the first n-type region 13. Since the lateral boundary of the first n-type region 13 is defined by the outer sidewall of the first sidewall 21, the lateral boundary of the first n-type region 13 automatically maintains a fixed distance from the boundary of the p-type well region 7, achieving self-alignment.

[0023] 2. Second layer self-alignment: self-alignment between the second n-type region 14 and the first n-type region 13.

[0024] After the first sidewall 21 is formed, polysilicon is deposited and etched in the hard mask opening region 20 to form a second sidewall 22. This second sidewall 22 is formed on the outer sidewall of the first sidewall 21, and its position is determined by the deposition thickness of the second sidewall 22. Subsequently, phosphorus ion implantation is performed using the second sidewall 22 as a mask to form a second n-type region 14. Since the lateral boundary of the second n-type region 14 is defined by the outer sidewall of the second sidewall 22, and the second sidewall 22 and the first sidewall 21 have a fixed thickness, a fixed lateral offset is automatically maintained between the second n-type region 14 and the first n-type region 13, achieving self-alignment. This fixed lateral offset is determined by the thickness of the second sidewall 22.

[0025] It should be noted that the spacing between the first n-type region 13 and the polysilicon gate 4 in this application is not a fixed spacing, nor is it formed using a self-aligned method. This is because in the SiC MOSFET process, the polysilicon gate is formed only after source region implantation and high-temperature tempering (above 1600°C), and cannot be self-aligned with the source region structure. Therefore, this spacing is achieved through photolithographic alignment.

[0026] The technical solution of this application will be described in detail below. Figure 2 The diagram shown is a schematic representation of the structure of a silicon carbide MOSFET device according to the first embodiment of this application. The silicon carbide MOSFET device includes: an N-type heavily doped silicon carbide substrate 9, which serves as the drain region of the device and provides mechanical support; and an N-type silicon carbide epitaxial layer 8, located on the N-type heavily doped silicon carbide substrate 9, which serves as the drift region of the device.

[0027] A p-type well region 7 is formed on the upper part of the N-type silicon carbide epitaxial layer 8. A gate oxide layer 5 is located on the N-type silicon carbide epitaxial layer 8 and above the p-type well region 7. A polysilicon gate 4 is located on the gate oxide layer 5.

[0028] A first sidewall 21 is formed on the sidewall of the hard mask 19. A second sidewall 22 is formed on the outer sidewall of the first sidewall 21.

[0029] A source region structure is formed within the p-type well region 7. This source region structure includes a first n-type region 13 and a second n-type region 14. The first n-type region 13 is a nitrogen ion implantation region, and its lateral boundary is defined by the outer wall of the first sidewall 21, such that the lateral boundary of the first n-type region 13 is self-aligned with the boundary of the p-type well region 7. The second n-type region 14 is a phosphorus ion implantation region, and the second n-type region 14 is located within the first n-type region 13; the lateral boundary of the second n-type region 14 is defined by the outer wall of the second sidewall 22, such that the second n-type region 14 is self-aligned with the first n-type region 13.

[0030] Since the second n-shaped region 14 is defined by the outer wall of the second sidewall 22, which is formed on the outer wall of the first sidewall 21, the lateral boundary of the second n-shaped region 14 is recessed inward relative to the lateral boundary of the first n-shaped region 13. The lateral extension width of the first n-shaped region 13 is greater than the lateral extension width of the second n-shaped region 14, such that there is a fixed lateral offset between the lateral boundary of the first n-shaped region 13 and the lateral boundary of the second n-shaped region 14, which is determined by the thickness of the second sidewall 22.

[0031] The lateral boundary of the second n-type region 14 is recessed inward relative to the edge of the polysilicon gate 4 to form a lateral buffer gap between the second n-type region 14 and the polysilicon gate 4. The width of the lateral buffer gap is determined by the thickness of the second sidewall 22. In this embodiment, the width of the lateral buffer gap is positively correlated with the thickness of the second sidewall 22, approximately equal to the thickness of the second sidewall 22. This lateral buffer gap is used to deflect the high-concentration phosphorus implantation damage region of the second n-type region 14 away from the gate oxide layer 5 below the polysilicon gate 4. Through this spatial isolation, even if phosphorus ion implantation has strong diffusion characteristics, it will not cause lattice damage or defects to the gate oxide layer 5, solving the gate oxide layer reliability failure problem that may be caused by phosphorus implantation. The existence of this lateral gap ensures that the second n-type region 14 and the polysilicon gate 4 maintain a sufficient physical distance, thereby forming effective electrical isolation. Through this spatial isolation, even if phosphorus ion implantation has strong diffusion characteristics, it will not cause lattice damage or defects to the gate oxide layer 5, solving the gate oxide layer reliability failure problem that may be caused by phosphorus implantation.

[0032] It should be noted that one of the objectives of this application is to address the problems of high contact resistance and wafer resistance caused by N14 implantation in existing technologies, resulting in high on-resistance of the device, and severe lattice damage caused by P31 implantation, leading to gate oxide quality defects and affecting reliability. In SiC MOS power device structures, polysilicon must cross a certain distance (e.g., 0.05-0.3um) across the n-type region to form a channel. The solution is to combine the advantages of both and avoid their disadvantages by shrinking the P31 implantation region inward and leaving a non-P31 implantation region, i.e., a non-lattice damage region, for polysilicon to cross to form a MOS channel. This distance is crucial. It can also be implemented using photolithography alignment, but the device miniaturization will be limited due to alignment errors. The embodiments of this application use self-alignment to make the spacing more precise.

[0033] The width of the first n-shaped region 13 is greater than the width of the second n-shaped region 14, and there is a fixed lateral offset between the first n-shaped region 13 and the second n-shaped region 14, which is determined by the thickness of the second sidewall 22.

[0034] A metal silicide layer is located above the second n-type region 14. This metal silicide layer is formed through a metal silicide reaction. Since the second n-type region 14 is formed by phosphorus ion implantation, phosphorus has high solid solubility and activation efficiency in silicon carbide, providing a high carrier concentration, thereby significantly reducing the contact resistance between the metal silicide layer and the second n-type region 14. This results in a substantial reduction in the overall contact resistance of the source region structure, improving the device's conduction performance.

[0035] In this embodiment, the metal silicide layer can be a nickel silicide layer. In other optional embodiments, those skilled in the art can select other metal silicide layers based on actual conditions. A higher concentration of SiC will narrow the metal interface barrier, forming an ohmic contact through tunneling. In this application, the second n-type region 14 doped with P31 has high solid solution and activation efficiency, which reduces Rc. Ni metal is commonly used to form silicide in N-type SiC contacts because the reaction of Ni metal with SiC to form silicide will generate a large number of carbon vacancies, resulting in a higher concentration of n+ regions at the interface. This will make it easier for the band to form a tunneling effect, thus forming a better ohmic contact and a lower Rc.

[0036] In this embodiment, the metal silicide layer may include a source metal silicide layer 11A and a drain metal silicide layer 11B. The source metal silicide layer 11A is located above the source region (second n-type region 14 and p-type heavily doped region 12) at the top of the device and is directly electrically connected to the source metal layer 1 above it. Its horizontal position is defined by a contact window, and its vertical direction is located between the second n-type region 14 and the source metal layer 1. The drain metal silicide layer 11B is located between the N-type heavily doped silicon carbide substrate 9 and the drain metal layer 18 at the bottom of the device. Its lower surface is in contact with the drain metal layer 18, and its upper surface is in contact with the N-type heavily doped silicon carbide substrate 9, thereby achieving an ohmic contact for the drain.

[0037] A source metal silicide layer 11A is formed above the second n-type region 14 and the heavily p-type doped region 12. This source metal silicide layer 11A is located at the bottom of the contact window and is in direct contact with the upper surfaces of the second n-type region 14 and the heavily p-type doped region 12. This source metal silicide layer 11A is used to reduce the source contact resistance and is electrically connected to the source metal layer 1 above it. Because the second n-type region 14 is implanted with phosphorus ions and has a high carrier concentration, a good ohmic contact can be formed between the source metal silicide layer 11A and the second n-type region 14.

[0038] An interlayer dielectric layer 3 covers the polysilicon gate 4. A source metal layer 1 is formed on the interlayer dielectric layer 3 and is electrically connected to the metal silicide layer. A p-type heavily doped region 12 is formed in the p-type well region 7 to provide electrical connection between the p-type well region 7 and the source metal layer 1. A drain metal layer 18 is formed on the back side of the N-type heavily doped silicon carbide substrate 9.

[0039] Figures 3 to 10 This is a schematic flowchart illustrating a method for manufacturing a silicon carbide MOSFET device according to the first embodiment of this application. The manufacturing method will be described in detail below.

[0040] First, a hard mask 19 is formed on a semiconductor to define the p-type well injection region, and a p-type conductor is injected at a 04° angle to form the p-type well region 7.

[0041] At the edge of the hard mask opening region 20, oxide and polysilicon are deposited and then etched to form a first sidewall 21. Nitrogen ions are then implanted to form a first n-type region 13. Due to the shielding effect of the first sidewall 21, the lateral boundary of the first n-type region 13 is defined by the outer sidewall of the first sidewall 21, so that the lateral boundary of the first n-type region 13 is self-aligned with the boundary of the p-type well region 7.

[0042] like Figure 5 As shown, after the first sidewall 21 is formed, polysilicon is deposited in the hard mask opening region 20 and then etched to form the second sidewall 22. Phosphorus ions are then implanted to form the second n-type region 14. Due to the shielding effect of the second sidewall 22, the lateral boundary of the second n-type region 14 is defined by the outer sidewall of the second sidewall 22, allowing the second n-type region 14 to self-align with the first n-type region 13. The width of the second n-type region 14 is smaller than the width of the first n-type region 13, and there is a fixed lateral offset between the second n-type region 14 and the first n-type region 13, which is determined by the thickness of the second sidewall 22. The lateral boundary of the second n-type region 14 forms a lateral buffer gap with the lateral boundary of the subsequently formed polysilicon gate 4, which is determined by the thickness of the second sidewall 22.

[0043] After the second sidewall 22 is formed, p-type heavily doped ions are implanted using another hard mask to form a p-type heavily doped region 12. After implantation, tempering activation is performed at a temperature of 1500°C to 2000°C to activate the implanted impurity ions. Gate oxide and polysilicon are grown to form a gate oxide layer 5 and a polysilicon gate 4. An interlayer dielectric layer 3 is deposited to cover the polysilicon gate 4. A contact window is formed to expose the second n-type region 14.

[0044] A metal silicide layer is formed above the second n-type region 14. This metal silicide layer is formed through a metal silicide reaction. Since the second n-type region 14 is formed by phosphorus ion implantation, it has a high carrier concentration, thus significantly reducing the contact resistance of the source region structure. Then, a source metal layer 1 is deposited to fill the contact window and cover the interlayer dielectric layer 3.

[0045] The N-type heavily doped silicon carbide substrate 9 is thinned by back grinding, and then a drain metal silicide layer 11B is deposited on the back side of the N-type heavily doped silicon carbide substrate 9. This drain metal silicide layer 11B is in direct contact with the back side of the N-type heavily doped silicon carbide substrate 9 to reduce drain contact resistance. A titanium / nickel / silver stack is further deposited below the drain metal silicide layer 11B to form a drain metal layer 18. The drain metal layer 18 is electrically connected to the drain metal silicide layer 11B.

[0046] likeFigure 11 The diagram shown is a schematic representation of a silicon carbide MOSFET device according to a second embodiment of this application. The difference between this embodiment and the first embodiment lies in the use of a multilayer p-well structure to further reduce the on-resistance of the device.

[0047] The silicon carbide MOSFET device includes: an N-type heavily doped silicon carbide substrate 9; and an N-type silicon carbide epitaxial layer 8 located on the N-type heavily doped silicon carbide substrate 9.

[0048] A first p-type well region 15 is formed on the upper part of the N-type silicon carbide epitaxial layer 8. A second p-type well region 16 is located below the first n-type region 13 and vertically overlaps with the first n-type region 13. A third p-type well region 17 is located below the second n-type region 14 and vertically overlaps with the second n-type region 14.

[0049] A gate oxide layer 5 is located above the N-type silicon carbide epitaxial layer 8 and above the first p-type well region 15. A polysilicon gate 4 is located above the gate oxide layer 5.

[0050] A first sidewall 21 is formed on the sidewall of the hard mask 19. A second sidewall 22 is formed on the outer sidewall of the first sidewall 21.

[0051] A source region structure is formed within a multilayer p-type well region. This source region structure includes a first n-type region 13 and a second n-type region 14. The first n-type region 13 is a nitrogen ion implantation region, and its lateral boundary is defined by the outer wall of the first sidewall 21, such that the lateral boundary of the first n-type region 13 is self-aligned with the boundary of the first p-type well region 15. The second n-type region 14 is a phosphorus ion implantation region, and the second n-type region 14 is located within the first n-type region 13; the lateral boundary of the second n-type region 14 is defined by the outer wall of the second sidewall 22, such that the second n-type region 14 is self-aligned with the first n-type region 13.

[0052] Since the second n-shaped region 14 is defined by the outer wall of the second sidewall 22, which is formed on the outer wall of the first sidewall 21, the lateral boundary of the second n-shaped region 14 is recessed inward relative to the lateral boundary of the first n-shaped region 13. The lateral extension width of the first n-shaped region 13 is greater than the lateral extension width of the second n-shaped region 14, such that there is a fixed lateral offset between the lateral boundary of the first n-shaped region 13 and the lateral boundary of the second n-shaped region 14, which is determined by the thickness of the second sidewall 22.

[0053] The lateral boundary of the second n-type region 14 is recessed inward relative to the edge of the polysilicon gate 4 to form a lateral buffer gap between the second n-type region 14 and the polysilicon gate 4. The width of the lateral buffer gap is determined by the thickness of the second sidewall 22. This lateral buffer gap is used to deflect the high-concentration phosphorus implantation damage region of the second n-type region 14 away from the gate oxide layer 5 below the polysilicon gate 4. Through this spatial isolation, even if phosphorus ion implantation has strong diffusion characteristics, it will not cause lattice damage or defects to the gate oxide layer 5, effectively protecting the gate oxide layer 5 from lattice damage caused by phosphorus implantation. The presence of this lateral gap ensures that the second n-type region 14 and the polysilicon gate 4 maintain a sufficient physical distance, thereby forming effective electrical isolation and effectively protecting the gate oxide layer 5 from lattice damage caused by phosphorus implantation.

[0054] The width of the first n-shaped region 13 is greater than the width of the second n-shaped region 14, and there is a fixed lateral offset between the first n-shaped region 13 and the second n-shaped region 14, which is determined by the thickness of the second sidewall 22.

[0055] A metal silicide layer is located above the second n-type region 14. Since the second n-type region 14 is formed by phosphorus ion implantation and has a high carrier concentration, the contact resistance of the source region structure can be significantly reduced.

[0056] A source metal silicide layer 11A is formed above the second n-type region 14 and the heavily p-type doped region 12. This source metal silicide layer 11A is located at the bottom of the contact window and is in direct contact with the upper surfaces of the second n-type region 14 and the heavily p-type doped region 12. This source metal silicide layer 11A is used to reduce the source contact resistance and is electrically connected to the source metal layer 1 above it. Because the second n-type region 14 is implanted with phosphorus ions and has a high carrier concentration, a good ohmic contact can be formed between the source metal silicide layer 11A and the second n-type region 14.

[0057] An interlayer dielectric layer 3 covers the polysilicon gate 4. A source metal layer 1 is formed on the interlayer dielectric layer 3 and is electrically connected to the metal silicide layer. A heavily p-type doped region 12 is formed within the first p-type well region 15 to provide an electrical connection between the first p-type well region 15 and the source metal layer 1. A drain metal layer 18 is formed on the back side of the heavily N-type doped silicon carbide substrate 9.

[0058] Figure 12 This is a schematic flowchart illustrating the manufacturing method of a silicon carbide MOSFET device according to the second embodiment of this application.

[0059] First, a hard mask 19 for defining the p-type well injection region is formed on a semiconductor, and a first p-type conductor is injected at a 0° angle to form a first p-type well region 15.

[0060] At the edge of the hard mask opening region 20, oxide and polysilicon are deposited and then etched to form a first sidewall 21. Nitrogen ions and a second p-type conductor are then implanted to form a first n-type region 13 and a second p-type well region 16, respectively. The first n-type region 13 is self-aligned with the first p-type well region 15, and the second p-type well region 16 is located below the first n-type region 13.

[0061] After the first sidewall 21 is formed, polysilicon is deposited in the hard mask opening region 20, followed by etching to form the second sidewall 22. Then, phosphorus ions and a third p-type conductor are implanted to form the second n-type region 14 and the third p-type well region 17, respectively. The width of the second n-type region 14 is smaller than the width of the first n-type region 13, and there is a fixed lateral offset between the second n-type region 14 and the first n-type region 13. This fixed lateral offset is determined by the thickness of the second sidewall 22. The lateral boundary of the second n-type region 14 and the lateral boundary of the subsequently formed polysilicon gate 4 form a lateral buffer gap, which is determined by the thickness of the second sidewall 22. The third p-type well region 17 is located below the second n-type region 14.

[0062] After the second sidewall 22 is formed, p-type heavily doped ions are implanted using another hard mask to form the p-type heavily doped region 12.

[0063] After injection, tempering activation is performed at a temperature of 1500℃ to 2000℃.

[0064] A gate oxide and polysilicon are grown to form a gate oxide layer 5 and a polysilicon gate 4.

[0065] A dielectric layer 3 is deposited between the layers to form a contact window, exposing the second n-type region 14.

[0066] A metal silicide layer is formed above the second n-type region 14 to reduce the contact resistance of the source region structure.

[0067] A source metal layer 1 is deposited to fill the contact window and cover the interlayer dielectric layer 3.

[0068] The N-type heavily doped silicon carbide substrate 9 is thinned by back grinding, and then a drain metal silicide layer 11B is deposited on the back side of the N-type heavily doped silicon carbide substrate 9. This drain metal silicide layer 11B is in direct contact with the back side of the N-type heavily doped silicon carbide substrate 9 to reduce drain contact resistance. A titanium / nickel / silver stack is further deposited below the drain metal silicide layer 11B to form a drain metal layer 18. The drain metal layer 18 is electrically connected to the drain metal silicide layer 11B.

[0069] The technical scope of this application is not limited to the contents of the above specification. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this application, and all such modifications and variations should fall within the scope of this application.

Claims

1. A silicon carbide MOSFET device, comprising a source region structure formed within a p-type well region, characterized in that, The source region structure includes: A first n-type region is a nitrogen ion implantation region, and the lateral boundary of the first n-type region is self-aligned with the boundary of the p-type well region. A second n-type region is a phosphorus ion implantation region, and the second n-type region is located within the first n-type region; Wherein, the horizontal extension width of the first n-type region is greater than the horizontal extension width of the second n-type region, so that there is a fixed horizontal offset between the horizontal boundary of the first n-type region and the horizontal boundary of the second n-type region. The lateral boundary of the second n-type region is recessed inward relative to the edge of the polysilicon gate above the p-type well region to form a lateral buffer gap between the second n-type region and the polysilicon gate. The lateral buffer gap is used to deflect the high-concentration phosphorus implantation damage region of the second n-type region away from the gate oxide layer below the polysilicon gate. A metal silicide layer is located above the second n-type region and is used to form the source region contact.

2. The silicon carbide MOSFET device according to claim 1, characterized in that, Also includes: An N-type heavily doped silicon carbide substrate; An N-type silicon carbide epitaxial layer is located on the N-type heavily doped silicon carbide substrate; The p-type well region is formed on the upper part of the N-type silicon carbide epitaxial layer; A gate oxide layer is located above the N-type silicon carbide epitaxial layer and above the p-type well region; The polysilicon gate is located above the gate oxide layer; A dielectric layer is used to cover the polysilicon gate; A source metal layer is formed on the interlayer dielectric layer and electrically connected to the metal silicide layer; A drain metal layer is formed on the back side of the N-type heavily doped silicon carbide substrate; A heavily doped p-type region is formed within the p-type well region to provide an electrical connection between the p-type well region and the source metal layer.

3. A method for manufacturing a silicon carbide MOSFET device, characterized in that, The method for manufacturing a silicon carbide MOSFET device as described in claim 1 or 2 includes the following steps: A hard mask for defining a p-type well injection region is formed on a semiconductor, and a p-type conductor is injected at a predetermined angle to form the p-type well region; A first sidewall is formed in the opening area of ​​the hard mask, and then nitrogen ions are injected to form the first n-type region, so that the lateral boundary of the first n-type region is self-aligned with the boundary of the p-type well region; After the first sidewall is formed, a second sidewall is formed in the opening area of ​​the hard mask, and then phosphorus ions are injected to form the second n-type region, such that the second n-type region is located within the first n-type region, and the lateral extension width of the first n-type region is greater than the lateral extension width of the second n-type region, and the lateral boundary of the second n-type region has a fixed lateral offset between the lateral boundary of the first n-type region and the lateral boundary of the first n-type region, wherein the fixed lateral offset is determined by the thickness of the second sidewall. A metal silicide layer is formed above the second n-type region to reduce the contact resistance of the source region structure.

4. The manufacturing method according to claim 3, characterized in that, The first sidewall formation step includes: depositing oxide and polysilicon at the edge of the hard mask opening area and then etching to form the first sidewall; the second sidewall formation step includes: after the first sidewall is formed, depositing polysilicon in the hard mask opening area and then etching to form the second sidewall.

5. The manufacturing method according to claim 3 or 4, characterized in that, It also includes the following steps: After the second sidewall is formed, a p-type heavily doped region is implanted using another hard mask to form a p-type heavily doped region. After injection, tempering and activation are performed at a preset temperature; Growing gate oxide and polysilicon to form the polysilicon gate; Interlayer dielectric layer; A contact window is formed to expose the second n-type region and the p-type heavily doped region, forming a metal silicide layer; A source metal layer is deposited to fill the contact window and cover the interlayer dielectric layer; Crystal back grinding is performed to deposit nickel silicide and drain metal layer on the back side of the semiconductor substrate.

6. A silicon carbide MOSFET device, comprising a source region structure formed within a multilayer p-type well region, characterized in that, The source region structure includes: A first n-type region is a nitrogen ion implantation region, and the lateral boundary of the first n-type region is self-aligned with the boundary of a first p-type well region. A second n-type region is a phosphorus ion implantation region, and the second n-type region is located within the first n-type region; Wherein, the horizontal extension width of the first n-type region is greater than the horizontal extension width of the second n-type region, so that there is a fixed horizontal offset between the horizontal boundary of the first n-type region and the horizontal boundary of the second n-type region. The lateral boundary of the second n-type region is recessed inward relative to the edge of the polysilicon gate above the first p-type well region to form a lateral buffer gap between the second n-type region and the polysilicon gate. The lateral buffer gap is used to deflect the high-concentration phosphorus implantation damage region of the second n-type region away from the gate oxide layer below the polysilicon gate. A metal silicide layer is located above the second n-type region and the p-type heavily doped region to form the source region contact; A second p-type well region is located below the first n-type region; A third p-type well region is located below the second n-type region.

7. The silicon carbide MOSFET device according to claim 6, characterized in that, Also includes: An N-type heavily doped silicon carbide substrate; An N-type silicon carbide epitaxial layer is located on the N-type heavily doped silicon carbide substrate; The first p-type well region is formed on the upper part of the N-type silicon carbide epitaxial layer; The second p-type well region is formed below the first n-type region and overlaps the first n-type region perpendicularly; The third p-type well region is formed below the second n-type region and overlaps vertically with the second n-type region; A gate oxide layer is located above the N-type silicon carbide epitaxial layer and above the first p-type well region; The polysilicon gate is located above the gate oxide layer; A dielectric layer is used to cover the polysilicon gate; A source metal layer is formed on the interlayer dielectric layer and electrically connected to the metal silicide layer; A drain metal layer is formed on the back side of the N-type heavily doped silicon carbide substrate; A heavily doped p-type region is formed within the first p-type well region to provide an electrical connection between the first p-type well region and the source metal layer.

8. A method for manufacturing a silicon carbide MOSFET device, characterized in that, The method for manufacturing a silicon carbide MOSFET device as described in claim 6 or 7 includes the following steps: A hard mask for defining a p-type well injection region is formed on a semiconductor, and a first p-type conductor is injected at a preset angle to form the first p-type well region; A first sidewall is formed in the opening area of ​​the hard mask, and then nitrogen ions and a second p-type conductor are implanted to form the first n-type region and the second p-type well region, respectively, so that the lateral boundary of the first n-type region is self-aligned with the boundary of the first p-type well region, and the second p-type well region is located below the first n-type region. After the first sidewall is formed, a second sidewall is formed in the opening area of ​​the hard mask. Then, phosphorus ions and a third p-type conductor are implanted to form the second n-type region and the third p-type well region, respectively. The second n-type region is located within the first n-type region, and the lateral extension width of the first n-type region is greater than the lateral extension width of the second n-type region. A fixed lateral offset is made between the lateral boundary of the second n-type region and the lateral boundary of the first n-type region. The fixed lateral offset is determined by the thickness of the second sidewall. The third p-type well region is located below the second n-type region. A metal silicide layer is formed above the second n-type region to reduce the contact resistance of the source region structure.

9. The manufacturing method according to claim 8, characterized in that, The first sidewall formation step includes: depositing oxide and polysilicon at the edge of the hard mask opening area and then etching to form the first sidewall; the second sidewall formation step includes: after the first sidewall is formed, depositing polysilicon in the hard mask opening area and then etching to form the second sidewall.

10. The manufacturing method according to claim 8 or 9, characterized in that, It also includes the following steps: After the second sidewall is formed, a p-type heavily doped region is implanted using another hard mask to form a p-type heavily doped region. After injection, tempering and activation are performed at a preset temperature; Growing gate oxide and polysilicon to form the polysilicon gate; Interlayer dielectric layer; A contact window is formed to expose the second n-type region and the p-type heavily doped region, forming a metal silicide layer; A source metal layer is deposited to fill the contact window and cover the interlayer dielectric layer; Crystal back grinding is performed to deposit nickel silicide and drain metal layer on the back side of the semiconductor substrate.

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