Semiconductor device and method of manufacturing the same
By simultaneously forming a medium-voltage gate dielectric layer on the semiconductor substrate in the medium-voltage region and the high-resistivity region, and using the medium-voltage gate dielectric layer in the high-resistivity region as a metal silicide barrier layer, the problems of large number of photomasks, complex process steps, and high manufacturing cost of existing high-voltage integrated HKMG devices are solved, achieving the effect of simplifying the process flow and reducing production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2026-03-06
- Publication Date
- 2026-05-29
AI Technical Summary
The existing high-voltage process for integrating HKMG devices suffers from problems such as a large number of photomasks, complex process steps, and high manufacturing costs.
A medium-voltage gate dielectric layer is simultaneously formed on the semiconductor substrate in the medium-voltage region and the high-resistivity region, while the medium-voltage gate dielectric layer in the high-resistivity region is retained as a metal silicide barrier layer, replacing the SAB layer that needs to be formed separately by photolithography and etching in the existing process.
By simplifying the process flow, reducing the number of photomasks, and lowering production costs, HKMG devices can be integrated into high-voltage processes, resulting in simplification and cost reduction.
Smart Images
Figure CN122121256A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] In the semiconductor manufacturing field, high-k dielectric metal gate (HKMG) technology has been widely used in medium-voltage and high-voltage process platforms. High-voltage processes are primarily used in screen driver chips, encompassing low-voltage, medium-voltage, and high-voltage devices. Medium-voltage processes are mainly used for brightness adjustment of the screen's light-emitting units, while high-voltage processes are primarily used for screen illumination. Compared to standard HKMG processes, the HKMG medium-voltage and high-voltage integrated process flow is more complex, requiring multiple additional photomasks. Reducing the number of photomasks has always been a key focus of this technology's development and a crucial indicator of the competitiveness of each process.
[0003] like Figures 1 to 4 The diagram illustrates a fabrication method for a high-voltage integrated HKMG device. The device includes a low-voltage region 101, a medium-voltage region 102, and a non-metallic silicide region 103. The non-metallic silicide region 103 includes a low-resistivity region 104 and a high-resistivity region 105. To meet specific functional requirements, a specialized metal silicide barrier (SAB) process is needed to achieve high resistance performance. This process includes depositing an SAB layer 12, photolithography, etching, and resist removal. The SAB layer 12 covers the area to prevent the formation of metal silicide 19, thereby achieving high resistance performance in the covered area. However, this process requires a specialized SAB photomask, further increasing the process complexity and manufacturing cost. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and its fabrication method, which solves the problems of large number of photomasks, complex process steps, and high manufacturing cost in the HKMG medium-voltage high-voltage integrated process.
[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device, the method comprising:
[0006] A semiconductor substrate is provided, the semiconductor substrate including a low-voltage region, a medium-voltage region and a non-metallic silicide region, wherein the non-metallic silicide region includes a low-resistance region and a high-resistance region;
[0007] A medium-voltage gate dielectric layer is formed on the semiconductor substrate in the medium-voltage region and the high-resistivity region;
[0008] A low-voltage gate dielectric layer is formed at a predetermined location on the semiconductor substrate in the low-voltage region;
[0009] A low-voltage pseudo-gate structure is formed on the low-voltage gate dielectric layer, and a medium-voltage pseudo-gate structure is formed at a predetermined position on the medium-voltage gate dielectric layer in the medium-voltage region;
[0010] Remove the medium-voltage gate dielectric layer outside the medium-voltage dummy gate structure in the medium-voltage region to expose the semiconductor substrate in the medium-voltage region;
[0011] Ion implantation is performed on the predetermined source / drain regions of the semiconductor substrate in the low-pressure region to form low-pressure source / drain electrodes; ion implantation is performed on the predetermined source / drain regions of the semiconductor substrate in the medium-pressure region to form medium-pressure source / drain electrodes; ion implantation is performed on the semiconductor substrate from the upper surface of the medium-pressure gate dielectric layer in the high-resistivity region and the upper surface of the semiconductor substrate in the low-resistivity region downwards to form an ion implantation layer;
[0012] A metal silicide layer is formed on the ion implantation layer of the low-voltage source / drain, the medium-voltage source / drain, and the low-resistivity region using a self-aligned metal silicide process.
[0013] Optionally, a plurality of shallow trench isolation structures are formed within the semiconductor substrate, the shallow trench isolation structures isolating the low-voltage region, the medium-voltage region and the non-metallic silicide region.
[0014] Optionally, the method of forming the medium-voltage gate dielectric layer on the semiconductor substrate in the medium-voltage region and the high-resistivity region includes:
[0015] The medium-voltage gate dielectric layer is formed on the semiconductor substrate using a thermal oxidation process;
[0016] The medium-voltage gate dielectric layer on the semiconductor substrate in the low-voltage region and the low-resistivity region is removed by photolithography and etching processes, while the medium-voltage gate dielectric layer on the semiconductor substrate in the medium-voltage region and the high-resistivity region is retained.
[0017] Optionally, the method of forming the low-voltage pseudo-gate structure on the low-voltage gate dielectric layer and forming the medium-voltage pseudo-gate structure at a predetermined position on the medium-voltage gate dielectric layer in the medium-voltage region includes:
[0018] A high-K dielectric layer and a polysilicon pseudo-gate layer are sequentially formed on the semiconductor substrate, covering the low-voltage gate dielectric layer and the medium-voltage gate dielectric layer.
[0019] A hard mask layer is formed on the polysilicon dummy gate layer and then patterned.
[0020] Based on the patterned hard mask layer, the polysilicon dummy gate layer and the high-k dielectric layer not covered by the patterned hard mask layer are etched away to retain the polysilicon dummy gate layer and the high-k dielectric layer at a predetermined position on the low-voltage gate dielectric layer and the medium-voltage region. The polysilicon dummy gate layer, the high-k dielectric layer and the hard mask layer on the low-voltage gate dielectric layer constitute the low-voltage dummy gate structure, and the polysilicon dummy gate layer, the high-k dielectric layer and the hard mask layer at the predetermined position on the medium-voltage gate dielectric layer in the medium-voltage region constitute the medium-voltage dummy gate structure.
[0021] Optionally, after forming the low-voltage pseudo-gate structure on the low-voltage gate dielectric layer and forming the medium-voltage pseudo-gate structure at a preset position on the medium-voltage gate dielectric layer in the medium-voltage region, the method further includes forming sidewalls on the outer walls of the low-voltage pseudo-gate structure and the medium-voltage pseudo-gate structure, respectively.
[0022] Furthermore, the sidewall includes a single-layer structure or a stacked structure of two or more layers.
[0023] Optionally, a method for removing the medium-voltage gate dielectric layer outside the medium-voltage dummy gate structure in the medium-voltage region to expose the semiconductor substrate in the medium-voltage region includes:
[0024] A photoresist layer is formed covering the semiconductor substrate, the medium-voltage gate dielectric layer, the low-voltage dummy gate structure, and the medium-voltage dummy gate structure, and is patterned thereon. The patterned photoresist layer at least exposes the medium-voltage gate dielectric layer outside the medium-voltage dummy gate structure in the medium-voltage region.
[0025] Based on the patterned photoresist layer, the medium-voltage gate dielectric layer outside the medium-voltage pseudo-gate structure in the medium-voltage region is etched away, while the medium-voltage gate dielectric layer between the medium-voltage pseudo-gate structure and the semiconductor substrate in the medium-voltage region and the medium-voltage gate dielectric layer in the high-resistivity region are retained.
[0026] Remove the patterned photoresist layer.
[0027] Optionally, after forming the metal silicide layer on the ion implantation layer of the low-voltage source / drain, the medium-voltage source / drain, and the low-resistivity region using a self-aligned metal silicide process, the method further includes the steps of forming a low-voltage gate structure and a medium-voltage gate structure.
[0028] Furthermore, after forming the low-voltage gate structure and the medium-voltage gate structure, the method further includes forming a first lead-out structure that contacts the metal silicide layer on the low-voltage source and drain, a second lead-out structure that contacts the metal silicide layer on the medium-voltage source and drain, and a third lead-out structure that contacts the metal silicide layer in the low-resistance region.
[0029] The present invention also provides a semiconductor device, which is prepared by the semiconductor device preparation method described in any one of the above claims.
[0030] As described above, the semiconductor device and its fabrication method of the present invention have the following beneficial effects: by simultaneously forming a medium-voltage gate dielectric layer on the semiconductor substrate in the medium-voltage region and the high-resistivity region, and retaining the medium-voltage gate dielectric layer in the high-resistivity region as a metal silicide barrier layer, the SAB layer that needs to be formed separately by photolithography and etching in the existing process is replaced. This solves the problems of large number of photomasks, complex process steps, and high manufacturing cost of the existing high-voltage integrated HKMG device, and achieves the beneficial effects of simplifying the process flow, reducing the number of photomasks, and reducing production costs. Attached Figure Description
[0031] Figures 1 to 4 The diagram shows a cross-sectional structure of each step in the fabrication process of a high-voltage integrated HKMG device as an example.
[0032] Figure 5 The diagram shows a flow chart of the method for fabricating the semiconductor device of the present invention.
[0033] Figures 6 to 13 The diagram shows a cross-sectional structure of each step in the fabrication method of the semiconductor device of the present invention.
[0034] Component labeling explanation: 10, 20 Semiconductor substrate; 101, 201 Low-voltage region; 102, 202 Medium-voltage region; 103, 203 Non-metallic silicide region; 104, 204 Low-resistance region; 105, 205 High-resistance region; 206 Shallow trench isolation structure; 21 Medium-voltage gate dielectric layer; 12 SAB layer; 22 Low-voltage gate dielectric layer; 13, 23 Low-voltage dummy gate structure; 231 Low-voltage dummy gate structure sidewall; 232 Dielectric layer; 233 Polysilicon dummy gate layer; 234 Hard mask layer; 14, 24 Medium-voltage dummy gate structure; 241 Medium-voltage dummy gate structure sidewall; 25 Photoresist layer; 26 Low-voltage source / drain; 261 Low-voltage source; 262 Low-voltage drain; 27 Medium-voltage source / drain; 271 Medium-voltage source; 272 Medium-voltage drain, 18, 28 ion implantation layers, 19, 29 metal silicide layers, 30 low-voltage gate structure, 31 medium-voltage gate structure, 32 first lead-out structure, 33 second lead-out structure, 34 third lead-out structure, steps S1~S7. Detailed Implementation
[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0036] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0037] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.
[0038] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0039] Comparative Example
[0040] This comparative example provides a fabrication process for an exemplified high-voltage integrated HKMG device. The following section combines... Figures 1-4 Describe the technological process.
[0041] See Figure 1Step S11 is executed to provide a semiconductor structure with completed front-end processes, including a semiconductor substrate 10. The semiconductor substrate 10 includes a low-voltage region 101, a medium-voltage region 102, and a non-metallic silicide region 103, wherein the non-metallic silicide region 103 includes a low-resistance region 104 and a high-resistance region 105. A plurality of shallow trench isolation structures 106 are formed within the semiconductor substrate 10, and the shallow trench isolation structures 106 isolate the low-voltage region 101, the medium-voltage region 102, and the non-metallic silicide region 103. A low-voltage dummy gate structure 13 is formed on the semiconductor substrate 10 in the low-voltage region 101, and a medium-voltage dummy gate structure 14 is formed on the semiconductor substrate 10 in the medium-voltage region 102. The semiconductor substrate 10 in the low-voltage dummy gate structure 13, the medium-voltage dummy gate structure 14, and the non-metallic silicide region 103 have ion implantation layers 18 implanted from a predetermined depth on the upper surface. A medium-voltage gate dielectric layer 11 is formed between the medium-voltage pseudo-gate structure 14 and the semiconductor substrate 10. The medium-voltage gate dielectric layer 11 is formed by independent photolithography and etching processes.
[0042] See Figure 2 Step S12 is executed to form SAB layer 12, which covers the following: Figure 1 The image shows the upper surface of a semiconductor structure after the front-end process has been completed.
[0043] See Figure 3 In step S13, the SAB layer 12 is patterned using photolithography and etching processes based on a specialized SAB photomask, so that the SAB layer 12 is retained only on the ion implantation layer 18 in the high-resistivity region 105.
[0044] See Figure 4 In step S14, a self-aligned metal silicide process is used to form a metal silicide layer 19 on the ion implantation layer 18 that is not covered by the SAB layer 12.
[0045] Therefore, this example requires the use of a special SAB photomask to form the patterned SAB layer 12. The SAB layer 12 is used as a metal silicide barrier layer to form a metal silicide layer 19 on the ion implantation layer 18 that is not covered by the SAB layer 12, thereby achieving high resistance performance in the high resistance region 105.
[0046] Example
[0047] This embodiment provides a method for fabricating a semiconductor device, such as... Figure 5 As shown, the preparation method includes:
[0048] S1, providing a semiconductor substrate, the semiconductor substrate including a low-voltage region, a medium-voltage region and a non-metallic silicide region, wherein the non-metallic silicide region includes a low-resistance region and a high-resistance region;
[0049] S2, a medium-voltage gate dielectric layer is formed on the semiconductor substrate in the medium-voltage region and the high-resistivity region;
[0050] S3, a low-voltage gate dielectric layer is formed at a predetermined position on the semiconductor substrate in the low-voltage region;
[0051] S4, a low-voltage pseudo-gate structure is formed on the low-voltage gate dielectric layer, and a medium-voltage pseudo-gate structure is formed at a preset position of the medium-voltage gate dielectric layer in the medium-voltage region;
[0052] S5, Remove the medium-voltage gate dielectric layer outside the medium-voltage pseudo-gate structure to expose the semiconductor substrate in the medium-voltage region, while retaining the medium-voltage gate dielectric layer in the high-resistivity region as a metal silicide barrier layer;
[0053] S6, Ion implantation is performed on the preset source / drain region of the semiconductor substrate in the low-pressure region to form a low-pressure source / drain electrode; ion implantation is performed on the preset source / drain region of the semiconductor substrate in the medium-pressure region to form a medium-pressure source / drain electrode; ion implantation is performed on the semiconductor substrate from the upper surface of the medium-pressure gate dielectric layer in the high-resistivity region and the upper surface of the semiconductor substrate in the low-resistivity region downwards to form an ion implantation layer;
[0054] S7. A self-aligned metal silicide process is used to form a metal silicide layer on the ion implantation layer of the low-voltage source / drain, the medium-voltage source / drain, and the low-resistivity region.
[0055] The semiconductor device fabrication method of this embodiment simultaneously forms a medium-voltage gate dielectric layer on the semiconductor substrate in the medium-voltage region and the high-resistivity region, and retains the medium-voltage gate dielectric layer in the high-resistivity region as a metal silicide barrier layer, replacing the SAB layer that needs to be formed separately by photolithography and etching in the existing process. This solves the problems of large number of photomasks, complex process steps and high manufacturing cost in the existing high-voltage integrated HKMG device process, and achieves the beneficial effects of simplifying the process flow, reducing the number of photomasks and reducing production costs.
[0056] The fabrication method of the semiconductor device in this embodiment will be described in detail below with reference to the specific accompanying drawings.
[0057] like Figure 6 As shown, step S1 is performed first, providing a semiconductor substrate 20, which includes a low-voltage region 201, a medium-voltage region 202 and a non-metallic silicide region 203, wherein the non-metallic silicide region 203 includes a low-resistance region 204 and a high-resistance region 205.
[0058] Specifically, a plurality of shallow trench isolation structures 206 are formed in the semiconductor substrate 20, which isolate the low-voltage region 201, the medium-voltage region 202 and the non-metallic silicide region 203.
[0059] like Figure 7 As shown, step S2 is then performed, in which a medium-voltage gate dielectric layer 21 is formed on the semiconductor substrate 20 of the medium-voltage region 202 and the high-resistivity region 205.
[0060] As a specific example, the method of forming the medium-voltage gate dielectric layer 21 on the semiconductor substrate 20 of the medium-voltage region 202 and the high-resistance region 205 includes:
[0061] S21, as Figure 6 As shown, the medium-voltage gate dielectric layer 21 is formed on the semiconductor substrate 10 using a thermal oxidation process.
[0062] S22, as Figure 7 As shown, the medium-voltage gate dielectric layer 21 on the semiconductor substrate 20 of the low-voltage region 201 and the low-resistivity region 204 is removed by photolithography and etching processes, while the medium-voltage gate dielectric layer 21 on the semiconductor substrate 20 of the medium-voltage region 202 and the high-resistivity region 205 is retained.
[0063] Specifically, the medium-voltage gate dielectric layer 21 formed on the semiconductor substrate 20 in the high-resistivity region 205 can serve as a metal silicide barrier layer in the subsequent metal silicide layer formation process, eliminating the need for the photomask used in the prior art to form the SAB layer 12.
[0064] like Figure 8 As shown, step S3 is then performed, in which a low-voltage gate dielectric layer 22 is formed at a preset position on the semiconductor substrate 20 in the low-voltage region 201.
[0065] like Figure 8 As shown, step S4 is then performed, in which a low-voltage pseudo-gate structure 23 is formed on the low-voltage gate dielectric layer 22, and a medium-voltage pseudo-gate structure 24 is formed at a preset position on the medium-voltage gate dielectric layer 21 in the medium-voltage region 202.
[0066] As a specific example, the method of forming the low-voltage pseudo-gate structure 23 on the low-voltage gate dielectric layer 22 and forming the medium-voltage pseudo-gate structure 24 at a predetermined position on the medium-voltage gate dielectric layer 21 in the medium-voltage region 202 includes:
[0067] S41, a high-k dielectric layer 232 and a polysilicon dummy gate layer 233 are sequentially formed on the semiconductor substrate 20, covering the low-voltage gate dielectric layer 22 and the medium-voltage gate dielectric layer 21. The high-k dielectric layer 232 refers to a dielectric material layer with a dielectric constant greater than that of conventional silicon dioxide.
[0068] S42, a hard mask layer 234 is formed on the polysilicon pseudo gate layer 233 and patterned thereon.
[0069] S43, based on the patterned hard mask layer 234, the polysilicon dummy gate layer 233 and the high-K dielectric layer 232 not covered by the patterned hard mask layer 234 are etched away to retain the polysilicon dummy gate layer 233 and the high-K dielectric layer 231 on the low-voltage gate dielectric layer 22 and at a predetermined position on the medium-voltage gate dielectric layer 21 in the medium-voltage region 202. The polysilicon dummy gate layer 233, the high-K dielectric layer 232 and the hard mask layer 234 on the low-voltage gate dielectric layer 22 constitute the low-voltage dummy gate structure 23, and the polysilicon dummy gate layer 233, the high-K dielectric layer 232 and the hard mask layer 234 at a predetermined position on the medium-voltage gate dielectric layer 21 in the medium-voltage region 202 constitute the medium-voltage dummy gate structure 24.
[0070] As a better example, such as Figure 8 The process of forming the low-voltage pseudo-gate structure 23 on the low-voltage gate dielectric layer 22 and the medium-voltage pseudo-gate structure 24 at a predetermined position on the medium-voltage gate dielectric layer 21 in the medium-voltage region 202 further includes the step of forming sidewalls on the outer walls of the low-voltage pseudo-gate structure 23 and the medium-voltage pseudo-gate structure 24, respectively. Specifically, a low-voltage pseudo-gate structure sidewall 231 is formed on the outer wall of the low-voltage pseudo-gate structure 23, and a medium-voltage pseudo-gate structure sidewall 241 is formed on the outer wall of the medium-voltage pseudo-gate structure 24. As a further example, the sidewalls may include a single-layer structure or a stacked structure of two or more layers. This embodiment does not limit the specific structure and formation method; it can be reasonably set according to actual needs.
[0071] like Figure 10 As shown, step S5 is then performed to remove the medium-voltage gate dielectric layer 21 outside the medium-voltage pseudo-gate structure 24 in the medium-voltage region 202 to expose the semiconductor substrate 20 of the medium-voltage region 202.
[0072] As an example, photolithography and etching processes are used to remove the medium-voltage gate dielectric layer outside the medium-voltage pseudo-gate structure to expose the semiconductor substrate in the medium-voltage region, while retaining the medium-voltage gate dielectric layer in the high-resistivity region as the metal silicide barrier layer.
[0073] As a specific example, a method for removing the medium-voltage gate dielectric layer 21 outside the medium-voltage pseudo-gate structure 24 in the medium-voltage region 202 to expose the semiconductor substrate 20 of the medium-voltage region 202 includes:
[0074] S51, such as Figure 9 As shown, a photoresist layer 25 is formed covering the semiconductor substrate 20, the medium-voltage gate dielectric layer 21, the low-voltage pseudo-gate structure 23 and the medium-voltage pseudo-gate structure 24, and is patterned thereon. The patterned photoresist layer 25 at least exposes the medium-voltage gate dielectric layer 21 outside the medium-voltage pseudo-gate structure 24 in the medium-voltage region 202.
[0075] S52, such as Figure 10 As shown, based on the patterned photoresist layer 25, the medium-voltage gate dielectric layer 21 outside the medium-voltage pseudo-gate structure 24 in the medium-voltage region 202 is etched away, while the medium-voltage gate dielectric layer 21 between the medium-voltage pseudo-gate structure 24 and the semiconductor substrate 20 in the medium-voltage region 202 and the medium-voltage gate dielectric layer 21 in the high-resistivity region 205 are retained.
[0076] S53, Remove the patterned photoresist layer 25.
[0077] like Figure 11 As shown, step S6 is then performed, where ion implantation is performed on the preset source / drain regions of the semiconductor substrate 20 in the low-voltage region 201 to form low-voltage source / drain electrodes 26; ion implantation is performed on the preset source / drain regions of the semiconductor substrate 20 in the medium-voltage region 202 to form medium-voltage source / drain electrodes 27; and ion implantation is performed on the semiconductor substrate 20 from the upper surface of the medium-voltage gate dielectric layer 21 in the high-resistivity region 205 and the upper surface of the semiconductor substrate 20 in the low-resistivity region 204 downwards to form an ion implantation layer 28.
[0078] Specifically, the semiconductor substrate 20 of the low-voltage region 201 has a preset source / drain region located on both sides of the low-voltage pseudo-gate structure 23, and the low-voltage source / drain electrode 26 includes a low-voltage source electrode 261 and a low-voltage drain electrode 262; the semiconductor substrate 20 of the medium-voltage region 27 has a preset source / drain region located on both sides of the medium-voltage pseudo-gate structure 24, and the medium-voltage source / drain electrode 27 includes a medium-voltage source electrode 271 and a medium-voltage drain electrode 272.
[0079] like Figure 11 As shown, step S7 is then performed, in which a self-aligned metal silicide process is used to form a metal silicide layer 29 on the low-voltage source / drain 26, the medium-voltage source / drain 27 and the ion implantation layer 28 of the low-resistivity region 204.
[0080] Specifically, the medium-voltage gate dielectric layer 21 formed on the semiconductor substrate 20 of the high-resistivity region 205 in step S2 above serves as a metal silicide barrier layer in step S7. Compared with the SAB layer 12, which also has the function of a metal silicide barrier layer in the prior art, the photomask for forming the SAB layer 12 can be omitted, and the process flow is simplified, thereby reducing production costs.
[0081] As an example, such as Figure 13 As shown, after forming the metal silicide layer 29 on the low-voltage source / drain 26, the medium-voltage source / drain 27, and the ion implantation layer 28 of the low-resistivity region 204 using a self-aligned metal silicide process, the process further includes the step of forming a low-voltage gate structure 30 and a medium-voltage gate structure 31. Specifically, the low-voltage gate structure 30 and the medium-voltage gate structure 31 can be formed using methods known in the art, which will not be elaborated here for the sake of simplicity.
[0082] As a further example, such as Figure 13 As shown, after forming the low-voltage gate structure 30 and the medium-voltage gate structure 31, the method further includes forming a first lead-out structure 32 that contacts the metal silicide layer 29 on the low-voltage source / drain 26, a second lead-out structure 33 that contacts the metal silicide layer 29 on the medium-voltage source / drain 27, and a third lead-out structure 34 that contacts the metal silicide layer 29 on the low-resistance region 204.
[0083] The preparation method provided in this application does not impose any restrictions on the order of steps and can be reasonably adjusted as needed. Furthermore, certain steps may be added as needed, and the method is not limited to only the steps described above.
[0084] This embodiment also provides a semiconductor device, which is prepared by the semiconductor device preparation method in the above embodiment. The beneficial effects it can achieve can be found in the specific description of the preparation method, and will not be repeated here.
[0085] In summary, the semiconductor device and its fabrication method of the present invention, by simultaneously forming a medium-voltage gate dielectric layer on the semiconductor substrate in the medium-voltage region and the high-resistivity region, and retaining the medium-voltage gate dielectric layer in the high-resistivity region as a metal silicide barrier layer, replaces the SAB layer that needs to be formed separately by photolithography and etching in the existing process. This solves the problems of large number of photomasks, complex process steps, and high manufacturing cost in the existing high-voltage integrated HKMG device process, and achieves the beneficial effects of simplifying the process flow, reducing the number of photomasks, and reducing production costs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0086] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A semiconductor substrate is provided, the semiconductor substrate including a low-voltage region, a medium-voltage region and a non-metallic silicide region, wherein the non-metallic silicide region includes a low-resistance region and a high-resistance region; A medium-voltage gate dielectric layer is formed on the semiconductor substrate in the medium-voltage region and the high-resistivity region; A low-voltage gate dielectric layer is formed at a predetermined location on the semiconductor substrate in the low-voltage region; A low-voltage pseudo-gate structure is formed on the low-voltage gate dielectric layer, and a medium-voltage pseudo-gate structure is formed at a predetermined position on the medium-voltage gate dielectric layer in the medium-voltage region; Remove the medium-voltage gate dielectric layer outside the medium-voltage pseudo-gate structure in the medium-voltage region to expose the semiconductor substrate in the medium-voltage region; Ion implantation is performed on the predetermined source / drain regions of the semiconductor substrate in the low-pressure region to form low-pressure source / drain electrodes; ion implantation is performed on the predetermined source / drain regions of the semiconductor substrate in the medium-pressure region to form medium-pressure source / drain electrodes; ion implantation is performed on the semiconductor substrate from the upper surface of the medium-pressure gate dielectric layer in the high-resistivity region and the upper surface of the semiconductor substrate in the low-resistivity region downwards to form an ion implantation layer; A metal silicide layer is formed on the ion implantation layer of the low-voltage source / drain, the medium-voltage source / drain, and the low-resistivity region using a self-aligned metal silicide process.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that: A plurality of shallow trench isolation structures are formed within the semiconductor substrate, the shallow trench isolation structures isolating the low-voltage region, the medium-voltage region and the non-metallic silicide region.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that: The method of forming the medium-voltage gate dielectric layer on the semiconductor substrate in the medium-voltage region and the high-resistivity region includes: The medium-voltage gate dielectric layer is formed on the semiconductor substrate using a thermal oxidation process; The medium-voltage gate dielectric layer on the semiconductor substrate in the low-voltage region and the low-resistivity region is removed by photolithography and etching processes, while the medium-voltage gate dielectric layer on the semiconductor substrate in the medium-voltage region and the high-resistivity region is retained.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method for forming the low-voltage pseudo-gate structure on the low-voltage gate dielectric layer and forming the medium-voltage pseudo-gate structure at a predetermined position on the medium-voltage gate dielectric layer in the medium-voltage region includes: A high-K dielectric layer and a polysilicon pseudo-gate layer are sequentially formed on the semiconductor substrate, covering the low-voltage gate dielectric layer and the medium-voltage gate dielectric layer. A hard mask layer is formed on the polysilicon dummy gate layer and then patterned. Based on the patterned hard mask layer, the polysilicon dummy gate layer and the high-k dielectric layer not covered by the patterned hard mask layer are etched away to retain the polysilicon dummy gate layer and the high-k dielectric layer at a predetermined position on the low-voltage gate dielectric layer and the medium-voltage region. The polysilicon dummy gate layer, the high-k dielectric layer and the hard mask layer on the low-voltage gate dielectric layer constitute the low-voltage dummy gate structure, and the polysilicon dummy gate layer, the high-k dielectric layer and the hard mask layer at the predetermined position on the medium-voltage gate dielectric layer in the medium-voltage region constitute the medium-voltage dummy gate structure.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that: After forming the low-voltage pseudo-gate structure on the low-voltage gate dielectric layer and the medium-voltage pseudo-gate structure at a predetermined position on the medium-voltage gate dielectric layer in the medium-voltage region, the method further includes forming sidewalls on the outer walls of the low-voltage pseudo-gate structure and the medium-voltage pseudo-gate structure, respectively.
6. The method for fabricating a semiconductor device according to claim 5, characterized in that: The sidewalls may be single-layer structures or stacked structures of two or more layers.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that: A method for removing the medium-voltage gate dielectric layer outside the medium-voltage dummy gate structure in the medium-voltage region to expose the semiconductor substrate in the medium-voltage region includes: A photoresist layer is formed covering the semiconductor substrate, the medium-voltage gate dielectric layer, the low-voltage dummy gate structure, and the medium-voltage dummy gate structure, and is patterned thereon. The patterned photoresist layer at least exposes the medium-voltage gate dielectric layer outside the medium-voltage dummy gate structure in the medium-voltage region. Based on the patterned photoresist layer, the medium-voltage gate dielectric layer outside the medium-voltage pseudo-gate structure in the medium-voltage region is etched away, while the medium-voltage gate dielectric layer between the medium-voltage pseudo-gate structure and the semiconductor substrate in the medium-voltage region and the medium-voltage gate dielectric layer in the high-resistivity region are retained. Remove the patterned photoresist layer.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that: After forming the metal silicide layer on the ion implantation layer of the low-voltage source / drain, the medium-voltage source / drain, and the low-resistivity region using a self-aligned metal silicide process, the method further includes the steps of forming a low-voltage gate structure and a medium-voltage gate structure.
9. The method for fabricating a semiconductor device according to claim 8, characterized in that: After forming the low-voltage gate structure and the medium-voltage gate structure, the method further includes forming a first lead-out structure that contacts the metal silicide layer on the low-voltage source and drain, a second lead-out structure that contacts the metal silicide layer on the medium-voltage source and drain, and a third lead-out structure that contacts the metal silicide layer in the low-resistance region.
10. A semiconductor device, characterized in that: It is prepared by the method of preparing a semiconductor device as described in any one of claims 1 to 9.