Semiconductor device based on aln / gan carrier selective transport structure and method of fabrication thereof

Abstract

The application discloses a semiconductor device based on an AlN / GaN carrier selective transmission structure and a preparation method thereof. The device comprises, from bottom to top, a sapphire substrate, an AlN nucleation layer, an n-type AlGaN layer, an n-type AlN / GaN hole blocking layer, an AlGaN multi-quantum well active region, an AlGaN electron blocking layer and a p-type AlGaN / GaN doped layer. An upper surface of the n-type AlGaN layer is provided with an n-type electrode in a region not covered by the n-type AlN / GaN hole blocking layer, and the n-type electrode is arranged in a spaced manner with the n-type AlN / GaN hole blocking layer. An upper surface of the p-type AlGaN / GaN doped layer is provided with a p-type electrode. The n-type AlN / GaN hole blocking layer is formed by the growth of multiple periods of m electron layers of AlN and n electron layers of GaN in an alternating manner. The AlN / GaN carrier selective transmission structure formed by the introduction of a specific AlN / GaN short-period superlattice can realize effective blocking of holes by utilizing the strong localization effect jointly induced by the hole localized orbital and the polarization electric field.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a semiconductor device based on an AlN / GaN carrier selective transport structure and its fabrication method. Background Technology

[0002] In the field of modern semiconductor optoelectronics and power electronic devices, precise control of the transport and distribution of charge carriers (electrons and holes) is a core technology determining device performance. Taking light-emitting diodes (LEDs) and laser diodes (LDs) as examples in optoelectronic devices, to achieve high quantum efficiency, electrons and holes must be effectively confined within the active region to prevent radiative recombination. Therefore, device structure design typically requires an electron blocking layer between the p-type region and the active region to prevent electron overflow; similarly, a hole blocking layer is often required between the n-type region and the active region to ensure that holes are confined within the active region, preventing their diffusion into the n-region and non-radiative recombination. Currently, electron blocking layer technology is relatively mature, typically employing wide-bandgap inorganic semiconductor materials (such as AlGaN). Electron barriers are constructed through heterojunction bandgap engineering, effectively blocking electrons while allowing holes to transport through traditional bandgap transport mechanisms, maintaining good injection efficiency. In the field of power electronic devices, as power electronic systems develop towards miniaturization, high frequency, and high energy efficiency, two-dimensional hole gas (2DHG) devices based on third-generation semiconductors such as gallium nitride (GaN) have attracted much attention. These devices utilize two-dimensional hole gas formed by spatial confinement at semiconductor heterojunctions. Due to their extremely high carrier density and mobility, they can provide excellent switching characteristics and conduction capabilities, making them key components for building high-efficiency power supply components.

[0003] Although electron blocking technology is relatively mature, existing technical solutions still have obvious shortcomings in the efficient design of hole blocking layers (HBLs) and the effective confinement of holes under high temperature conditions. These shortcomings are mainly reflected in the following three aspects: (1) Hole blocking layers based on organic semiconductors. Currently, the mainstream implementation scheme in the industry for constructing hole blocking layers is to introduce organic semiconductor materials. This scheme utilizes the characteristic that specific organic semiconductor materials have deep highest occupied molecular orbitals (HOMO) energy levels to form a large hole barrier at the heterojunction, thereby blocking the transmission of holes to the n-type region at the energy level. (2) Hole blocking layers based on aluminum gallium nitride alloys with high aluminum content. By utilizing the large band gap introduced by the high aluminum content, a large band level is achieved at the interface, and the hole barrier formed can suppress hole transmission and exhibit a blocking effect. (3) Carrier leakage problem of conventional inorganic heterojunctions at high temperatures. For power electronic devices based on 2DHG, existing technical solutions mostly use conventional heterojunction structures (such as AlGaN / GaN heterojunctions) to confine holes. Two-dimensional cavitation gas is trapped by forming a potential well at the interface, allowing it to propagate in the in-plane direction within the interface.

[0004] For technologies using organic semiconductors as hole-blocking layers, there are fundamental differences in carrier transport mechanisms between organic and inorganic semiconductors. Carrier transport in organic materials primarily relies on the hopping mechanism, unlike band transport in inorganic materials. This results in carrier mobility in organic semiconductor layers typically being much lower than in inorganic semiconductors (often several orders of magnitude lower). While this approach achieves hole blocking to some extent, its low electron mobility severely hinders the injection efficiency of electrons from the n-region to the active region, leading to increased series resistance and heat generation, thus limiting the overall photoelectric conversion efficiency of the device. For technologies using high-aluminum-content aluminum-gallium-nitrogen alloys as hole-blocking layers, large band divisions exist not only in the valence band where holes reside but also in the conduction band where electrons reside, causing a simultaneous decrease in electron transport efficiency and deteriorating the filtering effect of the hole-blocking layer. For traditional inorganic heterojunction semiconductors, their physical confinement capability is greatly affected by temperature. Under high-temperature operating conditions (common operating conditions for power devices), holes acquire higher thermal energy. At this point, holes have a high probability of escaping from the interface potential well region via thermal emission, escaping along the interface normal (out-of-plane direction) and entering the bulk material. This out-of-plane carrier leakage directly leads to a sharp increase in device leakage current, which not only reduces power conversion efficiency but may also cause the device to fail to turn off effectively at high temperatures, severely affecting the stability and reliability of the system. Using an AlGaN ternary disordered alloy as a back barrier can improve the leakage current situation, but the random arrangement of atoms disrupts the lattice periodic potential field, inducing strong alloy scattering, resulting in extremely low electron mobility, increased heat generation, and inability to support high-efficiency operation of the device at high current densities.

[0005] In summary, current technologies lack an ideal material structure that can achieve both high electron mobility transport based on inorganic semiconductor systems and strong anisotropic hole transport (i.e., high in-plane mobility and zero out-of-plane mobility) through structural design. Designing a structure at the inorganic semiconductor level that can balance efficient electron transport with hole blocking (especially high-temperature resistance) is one of the current research focuses in semiconductor materials and device technologies. Summary of the Invention

[0006] To address the aforementioned problems in existing technologies, this invention, based on the physical characteristics of nitride semiconductor band structures where the valence band is primarily composed of localized p orbitals and the conduction band is primarily composed of delocalized s orbitals, proposes a method to utilize the strong coupling between s orbitals within a finite thickness to ensure conduction band electron transport, while simultaneously leveraging the relatively localized p orbitals in a specific structure to induce weak coupling and mitigate the difficulty of valence band hole transport. This leads to the design of an AlN / GaN carrier selective transport structure, and the proposal of a semiconductor device based on this structure and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a semiconductor device based on an AlN / GaN carrier selective transport structure, comprising, from bottom to top, a sapphire substrate, an AlN nucleation layer, an n-type AlGaN layer, an n-type AlN / GaN hole blocking layer, an AlGaN multiple quantum well active region, an AlGaN electron blocking layer, and a p-type AlGaN / GaN doped layer, wherein... An n-type electrode is disposed on the upper surface of the n-type AlGaN layer in a region not covered by the n-type AlN / GaN hole blocking layer. The n-type electrode is disposed at a distance from the n-type AlN / GaN hole blocking layer, and the n-type electrode forms an n-type ohmic contact with the n-type AlGaN layer. A p-type electrode is disposed on the upper surface of the p-type AlGaN / GaN doped layer, and the p-type electrode forms a p-type ohmic contact with the p-type AlGaN / GaN doped layer; The n-type AlN / GaN hole blocking layer is formed by alternating growth of m-electron-layer AlN and n-electron-layer GaN over multiple cycles, where m and n are both less than or equal to 5.

[0007] In one embodiment of the present invention, the n-type AlN / GaN hole blocking layer is formed by alternating growth of AlN with 5 electron layers and GaN with 1 electron layer for multiple cycles.

[0008] In one embodiment of the present invention, the AlGaN multi-quantum-well active region includes, from bottom to top, a first quantum barrier layer, a first quantum well layer, a second quantum barrier layer, a second quantum well layer, and a third quantum barrier layer, wherein, The first quantum barrier layer, the second quantum barrier layer, and the third quantum barrier layer are all undoped Al with a thickness of 10-20 nm. 0.68 Ga 0.32 N, where both the first and second quantum well layers are undoped Al with a thickness of 1-5 nm. 0.58 Ga 0.42 N.

[0009] This invention provides a method for fabricating a semiconductor device based on an AlN / GaN carrier selective transport structure, the method comprising: S1: Select a sapphire substrate with the (0001) facet and perform pretreatment; S2: An AlN nucleation layer and an n-type AlGaN layer are sequentially grown on the sapphire substrate; S3: Grow an n-type AlN / GaN hole blocking layer on the n-type AlGaN layer; S4: Grow an AlGaN multi-quantum-well active region on the n-type AlN / GaN hole-blocking layer; S5: An AlGaN electron blocking layer and a p-type AlGaN / GaN doped layer are sequentially grown on the AlGaN multi-quantum-well active region; S6: Etch downwards from the upper surface of the p-type AlGaN / GaN doped layer to expose a portion of the upper surface of the n-type AlGaN layer, grow an n-type electrode on the n-type AlGaN layer, and grow a p-type electrode on the p-type AlGaN / GaN doped layer.

[0010] In one embodiment of the present invention, S3 includes: In the MOCVD reaction chamber, 20 sccm of SiH4 and 2 slm of NH3 were continuously introduced to maintain an n-type and nitrogen-rich environment. TMGa was introduced at a flow rate of 15 μmol / min and the time was controlled to grow 1 atomic layer of GaN. Then TMGa was turned off and TMAl was introduced at a flow rate of 30 μmol / min and the time was controlled to grow 5 atomic layers of AlN. The alternating growth process of 1 atomic layer of GaN and 5 atomic layers of AlN is repeated multiple times to form the n-type AlN / GaN hole blocking layer.

[0011] This invention provides a semiconductor device based on an AlN / GaN carrier selective transport structure, comprising, from bottom to top, an AlN substrate, an AlN / GaN back barrier layer, an AlN / GaN channel layer, and a p-type doped GaN barrier layer, wherein, The upper surface of the p-type doped GaN barrier layer is further provided with an anode metal layer and a cathode metal layer spaced apart from each other. The anode metal layer forms a p-type ohmic contact with the p-type doped GaN barrier layer, and the cathode metal layer forms a Schottky contact with the p-type doped GaN barrier layer. The AlN / GaN back barrier layer (202) is formed by alternating growth of m1 atomic layers of AlN and n1 atomic layers of GaN, where m1 and n1 are both less than or equal to 5; The AlN / GaN channel layer (203) is formed by alternating growth of m2 atomic layers of AlN and n2 atomic layers of GaN, where m2 and n2 are both less than or equal to 5.

[0012] In one embodiment of the present invention, the AlN / GaN back barrier layer includes a first digital alloy layer, a second digital alloy layer, a third digital alloy layer, and a fourth digital alloy layer disposed sequentially from bottom to top, wherein, The first digital alloy layer is formed by alternating growth of 5 atomic layers of AlN and 1 atomic layer of GaN; the second digital alloy layer is formed by alternating growth of 4 atomic layers of AlN and 2 atomic layers of GaN; the third digital alloy layer is formed by alternating growth of 3 atomic layers of AlN and 3 atomic layers of GaN; and the fourth digital alloy layer is formed by alternating growth of 2 atomic layers of AlN and 4 atomic layers of GaN.

[0013] In one embodiment of the present invention, the AlN / GaN channel layer is formed by alternating growth of one atomic layer of AlN and five atomic layers of GaN.

[0014] This invention provides a method for fabricating a semiconductor device based on an AlN / GaN carrier selective transport structure, the method comprising: S1: Select an AlN single crystal substrate and perform pretreatment; S2: An AlN / GaN back barrier layer is grown on the AlN single crystal substrate; S3: Grow an AlN / GaN channel layer on the AlN / GaN back barrier layer; S4: Grow a p-type doped GaN barrier layer on the AlN / GaN channel layer; S5: An anode metal layer and a cathode metal layer spaced apart are grown on the upper surface of the p-type doped GaN barrier layer.

[0015] In one embodiment of the present invention, S2 includes: Using the MOCVD process, a first digital alloy layer was grown on the AlN single crystal substrate, consisting of 5 atomic layers of AlN and 1 atomic layer of GaN growing alternately for 60 cycles. A second digital alloy layer is grown on the first digital alloy layer, consisting of 4 atomic layers of AlN and 2 atomic layers of GaN grown alternately for 60 cycles. A third digital alloy layer is grown on the second digital alloy layer, consisting of alternating growth of 3 atomic layers of AlN and 3 atomic layers of GaN for 60 cycles. A fourth digital alloy layer is grown on the third digital alloy layer, which is formed by alternating growth of 2 atomic layers of AlN and 4 atomic layers of GaN for 60 cycles.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: The semiconductor device of the present invention, by introducing a specific AlN / GaN short-period superlattice (digital alloy) structure, has the following significant improvements and beneficial effects compared to existing AlGaN disordered alloys and traditional long-period superlattices: 1. By periodically arranging AlN / GaN atomic layers, a microstrip transport mechanism is effectively induced, significantly reducing the driving voltage and solving the problem of poor conductivity in high-Al compositions: Traditional high-Al-composed AlGaN disordered alloys are severely limited by "alloy scattering," resulting in extremely low electron mobility. This invention eliminates alloy scattering through atomically ordered arrangement and utilizes the strong coupling effect of the ultrathin barrier to form a continuous electron microstrip in the conduction band direction. This enables electrons to achieve Bloch transport similar to bulk materials in the vertical direction, greatly improving the vertical electron mobility. This significantly reduces the series resistance of the electron transport layer in semiconductor devices and the turn-on voltage of the devices, thereby reducing Joule heating and improving power conversion efficiency.

[0017] 2. By setting the periodic arrangement of AlN / GaN atomic layers, the strong localization effect induced by the localized orbits of holes and the polarization electric field can effectively block holes. At the same time, the carefully designed digital alloy period ensures the efficient transport of electrons: Existing technologies are difficult to block holes without hindering electrons. Based on the natural orbital differences between holes and electrons, this invention designs a specific digital alloy period to ensure high-speed electron passage while the vertical mobility of holes approaches zero, naturally forming a high potential barrier for holes, effectively suppressing hole leakage, and significantly improving the energy efficiency ratio of deep ultraviolet light-emitting diodes, ultraviolet lasers, and vertical structure power devices.

[0018] 3. Improved crystal quality and heat dissipation: The AlN / GaN carrier selective transport structure of this invention is prepared by a fine pulse growth mode. The atomic-level layered alternating growth helps to release the lattice mismatch stress between the epitaxial layer and the substrate, and reduces the density of through dislocations. At the same time, the ordered AlN / GaN short-period superlattice structure reduces phonon scattering compared with disordered alloys and has higher thermal conductivity, which is beneficial to the heat dissipation of high-power devices during operation and extends the device life.

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a semiconductor device based on an AlN / GaN carrier selective transport structure provided in an embodiment of the present invention; Figure 2This is a cross-sectional schematic diagram of an AlN / GaN carrier selective transport structure provided in an embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of a traditional AlGaN disordered alloy structure. Figure 4 This is a schematic diagram illustrating the temperature variation of the mobility of an AlN / GaN carrier selective transport structure provided in an embodiment of the present invention. Figure 5 This is a schematic diagram illustrating the anisotropy of an AlN / GaN carrier selective transport structure as a function of temperature, provided in an embodiment of the present invention. Figure 6 yes Figure 2 A schematic diagram of the fabrication method of the semiconductor device is shown. Figure 7 This is a schematic diagram of another semiconductor device based on an AlN / GaN carrier selective transport structure provided in an embodiment of the present invention; Figure 8 yes Figure 7 The diagram shows a method for fabricating a semiconductor device. Detailed Implementation

[0021] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of a semiconductor device based on an AlN / GaN carrier selective transport structure and its fabrication method according to the present invention.

[0022] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0023] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0024] Example 1 This embodiment provides a semiconductor device based on an AlN / GaN carrier selective transport structure, specifically an AlGaN-based diode with optimized structure, such as... Figure 1 As shown, the semiconductor device includes, from bottom to top, a sapphire substrate 101, an AlN nucleation layer 102, an n-type AlGaN layer 103, an n-type AlN / GaN hole blocking layer 104, an AlGaN multi-quantum-well active region 105, an AlGaN electron blocking layer 106, and a p-type AlGaN / GaN doped layer 107. An n-type electrode 108 is disposed on the upper surface of the n-type AlGaN layer 103 in a region not covered by the n-type AlN / GaN hole blocking layer 104. The n-type electrode 108 and the p-type AlN / GaN doped layer... N-hole blocking layers 104 are spaced apart, and n-type electrodes 108 form n-type ohmic contacts with n-type AlGaN layers 103; p-type electrodes 109 are disposed on the upper surface of p-type AlGaN / GaN doped layers 107, and p-type electrodes 109 form p-type ohmic contacts with p-type AlGaN / GaN doped layers 107; the n-type AlN / GaN hole blocking layers 104 are AlN / GaN carrier selective transport structures, formed by alternating growth of m-electron-layer AlN and n-electron-layer GaN over multiple cycles, and can be represented by the general formula (AlN...). m / (GaN) n , where m and n represent the number of atomic layers, and both m and n are less than or equal to 5.

[0025] Sapphire substrate 101 serves as the basic support material for epitaxial growth. Sapphire was chosen because of its extremely high transmittance in the deep ultraviolet band, good chemical stability, and relatively low cost, making it suitable for large-scale mass production. The AlN nucleation layer 102 has a thickness of 10-30 nm and its function is to alleviate the significant lattice and thermal mismatch between the sapphire substrate 101 and the upper nitride layer by adjusting the growth mode to reduce dislocation density. In this embodiment, the n-type AlGaN layer 103 is a 500 nm thick Al... 0.78 Ga 0.22 N acts as an electron injection layer, delivering electrons to the active region under continuous current injection.

[0026] Furthermore, the n-type AlN / GaN hole blocking layer 104 in this embodiment uses a (AlN)5 / (GaN)1 carrier selective transport structure (digital alloy). Specifically, the structure is formed by alternating growth of five-electron-layer AlN and one-electron-layer GaN for 20 cycles. Its main function is to block holes within the active region while ensuring high-efficiency injection of electrons into the active region, thereby improving the internal quantum efficiency.

[0027] It should be noted that the AlN / GaN carrier selective transport structure in this embodiment is an AlN / GaN short-period superlattice structure based on a specific atomic layer period combination. It is formed by alternating growth of nitride semiconductor materials AlN and GaN, which greatly eliminates alloy scattering in traditional AlGaN ternary disordered alloys.

[0028] Please see also Figure 2 and Figure 3 , Figure 2 This is a cross-sectional schematic diagram of an AlN / GaN carrier selective transport structure (AlN / GaN short-period superlattice structure) provided in an embodiment of the present invention. The growth direction of the superlattice structure is shown from left to right, where green represents Ga atoms, gray represents Al atoms, and red represents N atoms. Figure 3 This is a cross-sectional schematic diagram of a traditional AlGaN disordered alloy structure. From left to right, it shows the growth direction of this disordered alloy structure, which is also the carrier transport direction of the vertical structure device. The Al composition is 50%, and the Ga composition is 50%. (Comparison...) Figure 2 and Figure 3 It can be observed that the random arrangement of atoms in the disordered AlGaN alloy structure disrupts the periodic potential field of the lattice, which not only induces strong alloy scattering, causing a sharp decrease in carrier mobility, but also makes it easier to generate defects during the growth process.

[0029] While traditional AlGaN disordered alloy structures (long-period AlN / GaN superlattices) can also be represented by the general formula (AlN... m / (GaN) n This indicates that the lattice period is relatively long (generally greater than 5 nm), with m and n typically exceeding 10. The barrier layer of this structure is thick, resulting in poor vertical carrier transport efficiency.

[0030] Furthermore, this embodiment conducts a first-principles study on the AlN / GaN carrier selective transport structure based on density functional theory, density functional perturbation theory (DFPT), and electro-acoustic coupling theory. Please refer to [link to relevant documentation]. Figure 4 , Figure 4This is a schematic diagram illustrating the temperature-dependent mobility of an AlN / GaN carrier selective transport structure according to an embodiment of the present invention. (a) shows the in-plane electron mobility as a function of temperature; (b) shows the out-of-plane electron mobility as a function of temperature; (c) shows the in-plane hole mobility as a function of temperature; and (d) shows the out-of-plane hole mobility as a function of temperature. The out-of-plane direction refers to the direction along the superlattice growth axis (

[0001] crystal direction), while the in-plane direction is perpendicular to the growth direction and parallel to the heterointerface direction. The results of this embodiment are calculated using density functional theory in first-principles calculations. A systematic mobility study was conducted using the EPW tool in the quantum espresso software package. The mobility shown in the figure is calculated within the framework of electroacoustic coupling, possessing high theoretical guiding significance and experimental fabrication value.

[0031] Please see Figure 5 , Figure 5 This is a schematic diagram of the anisotropy of an AlN / GaN carrier selective transport structure as a function of temperature, provided by an embodiment of the present invention. The left figure shows the anisotropy of electron mobility as a function of temperature, and the right figure shows the anisotropy of hole mobility as a function of temperature. The formula for calculating anisotropy is |in-plane mobility - out-of-plane mobility| / (in-plane mobility + out-of-plane mobility).

[0032] pass Figure 3 and Figure 4 It can be clearly observed that the carriers in this AlN / GaN carrier selective transport structure exhibit significant differences in transport characteristics: (1) Low anisotropy and high mobility of electrons: Electrons exhibit extremely high mobility in both in-plane and out-of-plane directions. This is because the superlattice period is extremely short, and the s orbitals of the electron wave functions between adjacent potential wells can undergo strong overlapping coupling, forming a continuous electron microstrip in the conduction band direction. Electrons can perform Bloch transport in bulk materials through the microstrip without having to overcome a high potential barrier, thereby greatly improving the electron mobility in the vertical direction.

[0033] (2) This structure exhibits strong anisotropy in hole transport. Its in-plane hole mobility is superior to that of traditional disordered AlGaN alloys. Meanwhile, in the out-of-plane direction, the hole mobility of the structure represented by (AlN)5 / (GaN)1 is almost zero at all temperatures. This is mainly because the valence band apex where the hole is located is mainly composed of p orbitals, and the wave function decays extremely rapidly, resulting in almost no overlap of hole wave functions between adjacent periods. At the same time, the strong polarization electric field of AlN further exacerbates the spatial separation of wave functions, thus preventing the formation of an effective vertical microstrip and resulting in a strongly localized state, which macroscopically manifests as an extremely low out-of-plane mobility.

[0034] (3) With (AlN) m / (GaN) nAs the thickness of AlN increases, anisotropy gradually intensifies, and out-of-plane mobility decreases rapidly. For the same m+n, the higher the proportion of AlN (i.e., the larger m), the more significant the anisotropy and the lower the out-of-plane mobility. This is mainly because the valence band peak of AlN is higher than that of GaN, and holes are primarily localized within the GaN layer. Increasing the AlN thickness increases the distance between GaN layers, weakening hole wavefunction coupling, and also increases the polarization potential difference, further enhancing the hole localization effect. Thus, under the combined effect of these two factors, the out-of-plane transport capacity of holes is severely limited.

[0035] In summary, this embodiment utilizes the transport characteristics of the AlN / GaN carrier selective transport structure to effectively solve the core technical contradiction of the difficulty in simultaneously addressing the issues of "low electron vertical transport efficiency" and "difficulty in hole blocking" in wide bandgap semiconductor devices.

[0036] Furthermore, the AlGaN multi-quantum-well active region 105 in this embodiment is composed of three quantum barrier layers and two quantum well layers alternately. Specifically, the AlGaN multi-quantum-well active region 105 in this embodiment includes, from bottom to top, a first quantum barrier layer, a first quantum well layer, a second quantum barrier layer, a second quantum well layer, and a third quantum barrier layer. The first quantum barrier layer, the second quantum barrier layer, and the third quantum barrier layer are all undoped Al layers with a thickness of 10-20 nm. 0.68 Ga 0.32 N, both the first and second quantum well layers are undoped Al with a thickness of 1-5 nm. 0.58 Ga 0.42 The role of the AlGaN multi-quantum-well active region 105 is to confine charge carriers within the potential well for radiative recombination to generate photons.

[0037] In this embodiment, the AlGaN electron blocking layer 106 is an Al with a thickness of 10 nm. 0.94 Ga 0.06 The primary function of this layer is to act as an electron barrier to prevent electron leakage into the p-type doped regions (i.e., all regions doped with p-type). The p-type AlGaN / GaN doped layer 107 is a 500 nm thick Al... 0.78 Ga 0.22 N acts as a hole injection layer, delivering holes to the active region under continuous current injection.

[0038] Furthermore, in this embodiment, the n-type electrode 108 is a Ti / Al / Ni / Au metal stack structure. Preferably, the thicknesses of Ti / Al / Ni / Au are 20 nm / 100 nm / 40 nm / 100 nm, respectively, to form a good n-type ohmic contact with the n-type AlGaN layer 103 for electron injection. The p-type electrode 109 is a Ni / Au metal stack structure. Preferably, the thicknesses of Ni / Au are 20 nm / 50 nm, respectively, to form a good p-type ohmic contact with the p-type AlGaN / GaN doped layer 107 for hole injection.

[0039] It should be noted that the n-type and p-type mentioned above refer to n-type doping and p-type doping, respectively. n-type doping uses Si for doping, while p-type doping uses Mg for doping.

[0040] Traditional hole-blocking layers often degrade electron transport while blocking holes, significantly reducing device performance. This invention utilizes a short-period AlN / GaN superlattice structure to form an n-type AlN / GaN hole-blocking layer. This layer effectively blocks out-of-plane holes while maintaining excellent electron transport efficiency. The hole-blocking layer strictly prevents hole transport while simultaneously ensuring electron transport, guaranteeing efficient recombination of electrons and holes in the active region without leakage to other areas. Therefore, it greatly improves the device's internal quantum efficiency.

[0041] Example 2 Based on Example 1, this example provides a method for fabricating a semiconductor device based on an AlN / GaN carrier selective transport structure, used to fabricate the semiconductor device shown in Example 1. This fabrication method is based on MOCVD (metal-organic chemical vapor deposition) technology. The reaction source uses trimethylaluminum (TMAl), trimethylgallium (TMGa), and ammonia (NH3). The n-type doping source uses silane (SiH4), the p-type doping source uses magnesia pyrocene (Cp2Mg), and the carrier gas is hydrogen (H2) or nitrogen (N2). Figure 6 As shown, the preparation method includes: S1: Select a sapphire substrate 101 with the (0001) facet and perform pretreatment.

[0042] A sapphire substrate with the (0001) facet was selected and placed in the MOCVD reaction chamber. Hydrogen gas with a flow rate of 15 slm was introduced as a carrier gas, and the pressure in the reaction chamber was controlled at 50 Torr. Under the hydrogen atmosphere, the temperature was raised to 1050℃-1150℃ (preferably 1100℃) for high-temperature heat treatment for 10 min to remove surface oxides and adsorbed impurities, and to reconstruct surface atoms, providing a clean interface for subsequent epitaxial growth.

[0043] S2: An AlN nucleation layer 102 and an n-type AlGaN layer 103 are sequentially grown on a sapphire substrate 101.

[0044] Specifically, the pressure in the MOCVD reaction chamber was maintained at 50 Torr, and TMAl was introduced at a flow rate of 20 μmol / min and NH3 at a flow rate of 2 slm (standard L / min). First, an extremely thin AlN buffer layer of approximately 20 nm thickness was grown at a relatively low temperature of 600 °C. Then, the TMAl flow was stopped, and the temperature was raised to above 1200 °C under an NH3 atmosphere. TMAl was then introduced again at a flow rate of 40 μmol / min to grow an AlN nucleation layer 102 with a thickness of 1 μm.

[0045] Next, the temperature of the MOCVD reaction chamber was controlled at approximately 1100℃, and the pressure was maintained at 50 Torr. TMAl was introduced at a flow rate of 40 μmol / min, TMGa at a flow rate of 10 μmol / min, and NH3 at a flow rate of 2 slm. Simultaneously, diluted SiH4 was continuously introduced as an n-type dopant at a flow rate of 20 sccm (standard mL / min). By controlling the flow rate ratio of TMAl to TMGa, an Al layer with a thickness of 500 nm was grown. 0.78 Ga 0.22 N forms an n-type AlGaN layer 103.

[0046] S3: An n-type AlN / GaN hole blocking layer 104 is grown on the n-type AlGaN layer 103.

[0047] This step employs a digital alloy pulse growth mode, continuously introducing 20 sccm of SiH4 and 2 slm of NH3 into the MOCVD reaction chamber to maintain an n-type and nitrogen-rich environment. Subsequently, during GaN sublayer growth, only TMGa at a flow rate of 15 μmol / min is introduced, while TMAl is shut off, resulting in a very short growth time of 2 seconds, growing 1 mL (Monol Layer) of GaN. During AlN layer growth, the gas path is rapidly switched, TMGa is shut off, and only TMAl at a flow rate of 30 μmol / min is introduced, with the growth time controlled to be 5 times that of the GaN sublayer, growing 5 mL of AlN. This alternating growth process of GaN and AlN atomic layers is then repeated multiple times to form a superlattice barrier layer of the desired thickness, i.e., the n-type AlN / GaN hole-blocking layer 104. Preferably, this process is repeated 20 times; that is, in this embodiment, the n-type AlN / GaN hole-blocking layer 104 is formed by alternating growth of 1 atomic layer of GaN and 5 atomic layers of AlN for 20 cycles.

[0048] S4: An AlGaN multi-quantum-well active region 105 is grown on an n-type AlN / GaN hole-blocking layer 104.

[0049] The SiH4 flow was stopped, and undoped growth was carried out, i.e., alternating growth of three quantum barrier layers and two quantum well layers. Specifically, during the growth of the quantum barrier layers, the gas flow was adjusted to introduce TMAl at a flow rate of 30 μmol / min and TMGa at a flow rate of 15 μmol / min, to grow an Al layer with a thickness of 10 nm. 0.68 Ga 0.32 N-barrier layer; during quantum well layer growth, the gas flow was adjusted, appropriately reducing the Al source flow rate to 20 μmol / min and increasing the TMGa flow rate to 25 μmol / min, to grow an Al layer with a thickness of 3 nm. 0.58 Ga 0.42 N-well layer; three quantum barrier layers and two quantum well layers are alternately grown to form the AlGaN multi-quantum-well active region 105, which is used to confine charge carriers in the potential well for radiative recombination.

[0050] S5: An AlGaN electron blocking layer 106 and a p-type AlGaN / GaN doped layer 107 are sequentially grown on the AlGaN multi-quantum-well active region 105.

[0051] First, a p-type AlGaN electron blocking layer 106 was grown on the AlGaN multi-quantum-well active region 105 using MOCVD. Specifically, the temperature was maintained at 1050 °C, and Cp₂Mg was introduced as a p-type dopant at a flow rate of 200 nmol / min. The flow rate of TMAl was significantly increased to 60 μmol / min, and the flow rate of TMGa was decreased to 2 μmol / min, to grow a p-type Al with a thickness of 10 nm. 0.94 Ga 0.06 The N layer serves as an AlGaN electron blocking layer, 106.

[0052] Subsequently, a p-type AlGaN / GaN doped layer 107 was grown on the AlGaN electron blocking layer 106 using MOCVD. Specifically, Cp₂Mg was continuously introduced at a flow rate of 200 nmol / min, and the TMAl flow rate was adjusted to 40 μmol / min and the TMGa flow rate to 10 μmol / min to grow an Al₂O₃ layer with a thickness of 500 nm. 0.78 Ga 0.22 The N layer serves as a p-type AlGaN / GaN doped layer 107.

[0053] S6: Etch downwards from the upper surface of the p-type AlGaN / GaN doped layer to expose a portion of the upper surface of the n-type AlGaN layer 103, and grow an n-type electrode 108 on the n-type AlGaN layer, and grow a p-type electrode 109 on the p-type AlGaN / GaN doped layer 107.

[0054] Specifically, after the growth of the p-type AlGaN / GaN doped layer 107 is completed, all metal sources are turned off, and a high-temperature annealing treatment is performed at 750°C for 20 min in an N2 atmosphere with a flow rate of 10 slm to activate Mg acceptors and remove hydrogen passivation. The epitaxial wafer is then removed, and photolithography and ICP etching are used to etch downwards from the upper surface of the p-type AlGaN / GaN doped layer 107 to the exposed upper surface of the n-type AlGaN layer 103. Ti / Al / Ni / Au (preferably 20nm / 100nm / 40nm / 100nm thickness) is deposited on the upper surface of the exposed n-type AlGaN layer 103 as an n-type electrode 108. Subsequently, a rapid thermal annealing (RTA) treatment at 800℃-900℃ (preferably 850℃) is performed for 30-60 seconds in a nitrogen atmosphere to form a good n-type ohmic contact. Ni / Au (preferably 20nm / 50nm thickness) is deposited on the upper surface of the p-type AlGaN / GaN doped layer 107 as a p-type electrode 109, and an annealing treatment at 500℃-600℃ is performed in an oxygen-containing atmosphere to form a p-type ohmic contact, thus completing the device fabrication.

[0055] Example 3 This embodiment provides another semiconductor device based on an AlN / GaN carrier selective transport structure, specifically a p-type GaN power device based on an AlN substrate. For example... Figure 7 As shown, the semiconductor device includes, from bottom to top, an AlN substrate 201, an AlN / GaN back barrier layer 202, an AlN / GaN channel layer 203, and a p-type doped GaN barrier layer 204. The upper surface of the p-type doped GaN barrier layer 204 is further provided with an anode metal layer 205 and a cathode metal layer 206 spaced apart from each other. The anode metal layer 205 forms a p-type ohmic contact with the p-type doped GaN barrier layer 204, and the cathode metal layer 206 forms a Schottky contact with the p-type doped GaN barrier layer 204. The AlN / GaN back barrier layer 202 is formed by alternating growth of m1 atomic layers of AlN and n1 atomic layers of GaN, where m1 and n1 are both less than or equal to 5. The AlN / GaN channel layer 203 is formed by alternating growth of m2 atomic layers of AlN and n2 atomic layers of GaN, where m2 and n2 are both less than or equal to 5.

[0056] In this embodiment, the AlN substrate 201 is the basic support material for epitaxial growth. AlN is chosen because it has good epitaxial lattice matching, large band gap and good breakdown characteristics.

[0057] Furthermore, the AlN / GaN back barrier layer 202 includes a first digital alloy layer, a second digital alloy layer, a third digital alloy layer, and a fourth digital alloy layer arranged sequentially from bottom to top. The first digital alloy layer is formed by alternating growth of 5 atomic layers of AlN and 1 atomic layer of GaN, i.e., the first digital alloy layer is (AlN)5 / (GaN)1; the second digital alloy layer is formed by alternating growth of 4 atomic layers of AlN and 2 atomic layers of GaN, i.e., the second digital alloy layer is (AlN)4 / (GaN)2; the third digital alloy layer is formed by alternating growth of 3 atomic layers of AlN and 3 atomic layers of Ga, i.e., the third digital alloy layer is (AlN)3 / (GaN)3; and the fourth digital alloy layer is formed by alternating growth of 2 atomic layers of AlN and 4 atomic layers of GaN, i.e., the second digital alloy layer is (AlN)2 / (GaN)4.

[0058] Preferably, in this embodiment, the first digital alloy layer is formed by alternating growth of 5 atomic layers of AlN and 1 atomic layer of GaN for 60 cycles, that is, 5 atomic layers of AlN and 1 atomic layer of GaN constitute one cycle, and this growth is repeated 60 times; the second digital alloy layer is formed by alternating growth of 4 atomic layers of AlN and 2 atomic layers of GaN for 60 cycles; the third digital alloy layer is formed by alternating growth of 3 atomic layers of AlN and 3 atomic layers of GaN for 60 cycles; and the fourth digital alloy layer is formed by alternating growth of 2 atomic layers of AlN and 4 atomic layers of GaN for 60 cycles. The function of the AlN / GaN back barrier layer 202 is to block holes in the channel region and prevent them from leaking downwards.

[0059] In this embodiment, the AlN / GaN channel layer 203 is formed by alternating growth of one atomic layer of AlN and five atomic layers of GaN, i.e., (AlN)1 / (GaN)5 digital alloy. Specifically, it is formed by alternating growth of one atomic layer of AlN and five atomic layers of GaN for 60 cycles. The function of the AlN / GaN channel layer 203 is to form a channel for hole carriers together with the AlN / GaN back barrier layer 202.

[0060] Furthermore, in this embodiment, the p-type doped GaN barrier layer 204 is used to provide hole carriers for the channel, the anode metal layer 205 is made of Ni / Au to form a good p-type ohmic contact, and the cathode metal 206 is made of Ti / Au to form a good Schottky contact.

[0061] In traditional p-type power devices, hole carriers located in the channel layer escape into the channel region under high voltage operating conditions, extending downwards and forming additional leakage current paths. This leads to serious problems such as premature breakdown or performance degradation. The root cause is the lack of an effective carrier blocking structure in the longitudinal direction. While using a high-Al content AlGaN alloy barrier structure can suppress longitudinal transport, its randomly distributed atoms introduce strong alloy disorder scattering in the normal lateral transport direction of the carriers, resulting in performance degradation. This embodiment proposes an AlN / GaN back barrier layer using an AlN / GaN short-period superlattice back barrier structure. On the one hand, it can efficiently block longitudinal hole transport and suppress current leakage. On the other hand, the better in-plane hole mobility comes from the flat atomic surface (only AlN or GaN layer), without the scattering process caused by the randomly distributed AlN and GaN in traditional disordered alloys. This ensures the transport efficiency of hole carriers in the channel layer, thus ensuring both device reliability and excellent operating characteristics.

[0062] Example 4 This embodiment provides a method for fabricating the semiconductor device shown in Embodiment 3. This method is based on MOCVD technology, using trimethylaluminum (TMAl), trimethylgallium (TMGa), and ammonia (NH3) as the reaction source, magnesia-dicerocene (Cp2Mg) as the p-type doping source, and hydrogen (H2) or nitrogen (N2) as the carrier gas. Figure 8 As shown, the preparation method includes: S1: Select AlN single crystal substrate 201 and perform pretreatment.

[0063] A defect-free, high-quality AlN single-crystal substrate was selected and placed in the MOCVD reaction chamber. Hydrogen gas was introduced at a flow rate of 15 slm, and the pressure in the reaction chamber was controlled at 50 Torr. Under the hydrogen atmosphere, the temperature was raised to 1150℃-1200℃ for high-temperature heat treatment for 10 minutes to remove surface oxides and impurities, ensuring lattice matching and low dislocation density in the epitaxial growth.

[0064] S2: An AlN / GaN back barrier layer 202 is grown on an AlN single crystal substrate 201.

[0065] This step employs a digital alloy pulse growth mode, growing a first digital alloy layer on an AlN single crystal substrate 201, consisting of 5 atomic layers of AlN and 1 atomic layer of GaN growing alternately for 60 cycles; growing a second digital alloy layer on the first digital alloy layer, consisting of 4 atomic layers of AlN and 2 atomic layers of GaN growing alternately for 60 cycles; growing a third digital alloy layer on the second digital alloy layer, consisting of 3 atomic layers of AlN and 3 atomic layers of GaN growing alternately for 60 cycles; and growing a fourth digital alloy layer on the third digital alloy layer, consisting of 2 atomic layers of AlN and 4 atomic layers of GaN growing alternately for 60 cycles.

[0066] Specifically, MOCVD process was used, maintaining the temperature at 1100℃-1150℃, controlling the reaction chamber pressure at 50 Torr, and continuously introducing 2 slm of NH3. During GaN layer growth, only TMGa was introduced at a flow rate of 15 μmol / min (TMAl was turned off), and the growth time was extremely short, controlled at 2 seconds, to grow 1 mL of GaN. During AlN layer growth, the gas path was quickly switched, TMGa was turned off, and only TMAl was introduced at a flow rate of 30 μmol / min, and the growth time was controlled at 5 times that of the GaN sublayer, i.e., 10 seconds, to grow 5 mL of AlN. The above growth process was repeated alternately for 60 cycles to form the first digital alloy layer.

[0067] Next, maintaining the same temperature, pressure, and source flow parameters, TMGa was introduced for 4 seconds to grow 2 mL of GaN, followed by switching to TMAl and introducing it for 8 seconds to grow 4 mL of AlN. This alternating growth process was repeated for 60 cycles to form the second digital alloy layer.

[0068] Maintain the same temperature, pressure, and source flow parameters. 3 mL of GaN is grown by introducing TMGa for 6 seconds, followed by switching to TMAl and introducing TMAl for 6 seconds to grow 3 mL of AlN. This alternating growth process is repeated for 60 cycles to form the third digital alloy layer.

[0069] Maintain the same temperature, pressure, and source flow parameters. 4 mL of GaN is grown by introducing TMGa for 8 seconds, followed by switching and introducing TMAl for 4 seconds to grow 2 mL of AlN. This alternating growth process is repeated for 60 cycles to form the fourth digital alloy layer, thus forming the entire AlN / GaN back barrier layer 202.

[0070] S3: An AlN / GaN channel layer 203 is grown on the AlN / GaN back barrier layer 202.

[0071] Similarly, the same temperature, pressure, and source flow parameters were maintained. 5 mL of GaN was grown by introducing TMGa for 10 seconds, followed by switching and introducing TMAl for 2 seconds to grow 1 mL of AlN. This alternating growth process was repeated for 60 cycles to form the AlN / GaN channel layer 203.

[0072] S4: A p-type doped GaN barrier layer 204 is grown on the AlN / GaN channel layer 203.

[0073] Specifically, the growth conditions were adjusted, maintaining the temperature at 1100℃-1150℃ and controlling the pressure in the MOCVD reaction chamber at 100 Torr. TMGa gas at a flow rate of 50 μmol / min was introduced as the Ga source, ammonia gas at a flow rate of 4 slm was introduced as the N source, and Cp₂Mg gas at a flow rate of 200 nmol / min was introduced as the p-type dopant to grow a 70 nm thick p-type doped GaN barrier layer 204. After growth, a high-temperature annealing treatment of approximately 750℃ was performed in situ or ex-situ under a pure nitrogen atmosphere to activate the Mg acceptors.

[0074] S5: An anode metal layer 205 and a cathode metal layer 206 are grown on the upper surface of the p-type doped GaN barrier layer 204, spaced apart from each other.

[0075] Specifically, an ohmic contact region is defined on the surface of the p-type doped GaN barrier layer 204 using photolithography. A high work function metal layer, namely the anode metal layer 205, is deposited by electron beam evaporation, preferably Ni / Au, with thicknesses of 20-50 nm and 50-150 nm (typical values ​​are 20 nm / 50 nm). A metal lift-off process is then performed. To form an ohmic contact with low specific contact resistance, the sample is placed in a rapid thermal annealing (RTA) furnace and annealed at 500-600 °C (preferably 550 °C) for 5-10 min in an air or oxygen-nitrogen mixed atmosphere, causing Ni to oxidize to form NiO, thereby forming a good ohmic contact with the p-type doped GaN barrier layer 204.

[0076] Using photolithography again, a Schottky contact region is defined on the surface of the p-type doped GaN barrier layer 204 at a predetermined distance (e.g., 5 μm-20 μm, determined by the device design breakdown voltage) from the anode metal layer 205. A low work function metal layer is deposited using electron beam evaporation to form the Schottky barrier, i.e., the cathode metal layer 206, preferably deposited as Ti / Au (typical thicknesses of 20 nm / 100 nm). A metal lift-off process is then performed. It is important to note that the Schottky electrode is not subjected to high-temperature annealing after deposition (or only alloyed for a very short time below 300°C to improve adhesion) to ensure that the interface between the metal and the p-type doped GaN barrier layer 204 maintains ideal Schottky barrier characteristics, suppressing reverse leakage current in the device.

[0077] In summary, the semiconductor device of the present invention, by introducing a specific AlN / GaN short-period superlattice (digital alloy) structure, has the following significant advancements and beneficial effects compared to existing AlGaN disordered alloys and traditional long-period superlattice technologies: By periodically arranging AlN / GaN atomic layers, a microstrip transport mechanism is effectively induced, significantly reducing the driving voltage and solving the problem of poor conductivity in high-Al compositions. Traditional high-Al-composed AlGaN disordered alloys are severely limited by "alloy scattering," resulting in extremely low electron mobility. This invention eliminates alloy scattering through atomically ordered arrangement and utilizes the strong coupling effect of the ultrathin barrier to form a continuous electron microstrip in the conduction band direction. This enables electrons to achieve Bloch transport similar to bulk materials in the vertical direction, greatly improving vertical electron mobility. This significantly reduces the series resistance of the electron transport layer in semiconductor devices and the turn-on voltage of the devices, thereby reducing Joule heating and improving power conversion efficiency. By setting the periodic arrangement of AlN / GaN atomic layers, and utilizing the strong localization effect induced by the localized orbits of holes and the polarization electric field, effective hole blocking can be achieved. At the same time, the carefully designed digital alloy period ensures efficient electron transport. Existing technologies struggle to block holes without hindering electrons. Based on the natural orbital differences between holes and electrons, this invention designs a specific digital alloy period that ensures high-speed electron transport while the vertical mobility of holes approaches zero, naturally forming a high potential barrier for holes. This effectively suppresses hole leakage and significantly improves the energy efficiency ratio of deep ultraviolet light-emitting diodes, ultraviolet lasers, and vertical structure power devices. Improving crystal quality and heat dissipation: The AlN / GaN carrier selective transport structure of this invention is prepared by a fine pulse growth mode. The atomic-level layered alternating growth helps to release the lattice mismatch stress between the epitaxial layer and the substrate, and reduces the density of through dislocations. At the same time, the ordered AlN / GaN short-period superlattice structure reduces phonon scattering compared with disordered alloys and has higher thermal conductivity, which is beneficial to the heat dissipation of high-power devices during operation and extends the device life.

[0078] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A semiconductor device based on an AlN / GaN carrier selective transport structure, characterized in that, The structure, from bottom to top, includes a sapphire substrate (101), an AlN nucleation layer (102), an n-type AlGaN layer (103), an n-type AlN / GaN hole blocking layer (104), an AlGaN multiple quantum well active region (105), an AlGaN electron blocking layer (106), and a p-type AlGaN / GaN doped layer (107). An n-type electrode (108) is provided on the upper surface of the n-type AlGaN layer (103) in a region not covered by the n-type AlN / GaN hole blocking layer (104). The n-type electrode (108) is spaced apart from the n-type AlN / GaN hole blocking layer (104), and the n-type electrode (108) forms an n-type ohmic contact with the n-type AlGaN layer (103). A p-type electrode (109) is disposed on the upper surface of the p-type AlGaN / GaN doped layer (107), and the p-type electrode (109) forms a p-type ohmic contact with the p-type AlGaN / GaN doped layer (107). The n-type AlN / GaN hole blocking layer (104) is formed by alternating growth of m-electron-layer AlN and n-electron-layer GaN for multiple cycles, where m and n are both less than or equal to 5.

2. The semiconductor device based on the AlN / GaN carrier selective transport structure according to claim 1, characterized in that, The n-type AlN / GaN hole blocking layer (104) is formed by alternating growth of AlN with 5 electron layers and GaN with 1 electron layer for multiple cycles.

3. The semiconductor device based on the AlN / GaN carrier selective transport structure according to claim 1, characterized in that, The AlGaN multi-quantum-well active region (105) includes, from bottom to top, a first quantum barrier layer, a first quantum well layer, a second quantum barrier layer, a second quantum well layer, and a third quantum barrier layer, wherein, The first quantum barrier layer, the second quantum barrier layer, and the third quantum barrier layer are all undoped Al with a thickness of 10-20 nm. 0.68 Ga 0.32 N, where both the first and second quantum well layers are undoped Al with a thickness of 1-5 nm. 0.58 Ga 0.42 N.

4. A method for fabricating a semiconductor device based on an AlN / GaN carrier selective transport structure, characterized in that, The method for preparing the semiconductor device according to any one of claims 1 to 3 comprises: S1: Select a sapphire substrate (101) with the (0001) facet and perform pretreatment; S2: An AlN nucleation layer (102) and an n-type AlGaN layer (103) are sequentially grown on the sapphire substrate (101); S3: An n-type AlN / GaN hole blocking layer (104) is grown on the n-type AlGaN layer (103); S4: An AlGaN multi-quantum-well active region (105) is grown on the n-type AlN / GaN hole blocking layer (104); S5: An AlGaN electron blocking layer (106) and a p-type AlGaN / GaN doped layer (107) are sequentially grown on the AlGaN multi-quantum-well active region (105); S6: Etch downwards from the upper surface of the p-type AlGaN / GaN doped layer (107) to expose a portion of the upper surface of the n-type AlGaN layer (103), grow an n-type electrode (108) on the n-type AlGaN layer (103), and grow a p-type electrode (109) on the p-type AlGaN / GaN doped layer (107).

5. The preparation method according to claim 4, characterized in that, S3 includes: In the MOCVD reaction chamber, 20 sccm of SiH4 and 2 slm of NH3 were continuously introduced to maintain an n-type and nitrogen-rich environment. TMGa was introduced at a flow rate of 15 μmol / min and the time was controlled to grow 1 atomic layer of GaN. Then TMGa was turned off and TMAl was introduced at a flow rate of 30 μmol / min and the time was controlled to grow 5 atomic layers of AlN. The alternating growth process of 1 atomic layer of GaN and 5 atomic layers of AlN is repeated for multiple cycles to form the n-type AlN / GaN hole blocking layer (104).

6. A semiconductor device based on an AlN / GaN carrier selective transport structure, characterized in that, It includes, from bottom to top, an AlN substrate (201), an AlN / GaN back barrier layer (202), an AlN / GaN channel layer (203), and a p-type doped GaN barrier layer (204), wherein, The upper surface of the p-type doped GaN barrier layer (204) is further provided with an anode metal layer (205) and a cathode metal layer (206) spaced apart from each other. The anode metal layer (205) forms a p-type ohmic contact with the p-type doped GaN barrier layer (204), and the cathode metal layer (206) forms a Schottky contact with the p-type doped GaN barrier layer (204). The AlN / GaN back barrier layer (202) is formed by alternating growth of m1 atomic layers of AlN and n1 atomic layers of GaN, where m1 and n1 are both less than or equal to 5; The AlN / GaN channel layer (203) is formed by alternating growth of m2 atomic layers of AlN and n2 atomic layers of GaN, where m2 and n2 are both less than or equal to 5.

7. The semiconductor device based on the AlN / GaN carrier selective transport structure according to claim 6, characterized in that, The AlN / GaN back barrier layer (202) includes a first digital alloy layer, a second digital alloy layer, a third digital alloy layer, and a fourth digital alloy layer arranged sequentially from bottom to top, wherein, The first digital alloy layer is formed by alternating growth of 5 atomic layers of AlN and 1 atomic layer of GaN; the second digital alloy layer is formed by alternating growth of 4 atomic layers of AlN and 2 atomic layers of GaN; the third digital alloy layer is formed by alternating growth of 3 atomic layers of AlN and 3 atomic layers of GaN; and the fourth digital alloy layer is formed by alternating growth of 2 atomic layers of AlN and 4 atomic layers of GaN.

8. The semiconductor device based on the AlN / GaN carrier selective transport structure according to claim 6, characterized in that, The AlN / GaN channel layer (203) is formed by alternating growth of one atomic layer of AlN and five atomic layers of GaN.

9. A method for fabricating a semiconductor device based on an AlN / GaN carrier selective transport structure, characterized in that, The method for preparing the semiconductor device according to any one of claims 6-8 comprises: [the following is a description of the method used to prepare the semiconductor device according to any one of claims 6-8]. S1: Select an AlN single crystal substrate (201) and perform pretreatment; S2: An AlN / GaN back barrier layer (202) is grown on the AlN single crystal substrate (201); S3: Grow an AlN / GaN channel layer (203) on the AlN / GaN back barrier layer (202); S4: A p-type doped GaN barrier layer (204) is grown on the AlN / GaN channel layer (203); S5: An anode metal layer (205) and a cathode metal layer (206) spaced apart are grown on the upper surface of the p-type doped GaN barrier layer (204).

10. The preparation method according to claim 9, characterized in that, S2 includes: Using the MOCVD process, a first digital alloy layer was grown on the AlN single crystal substrate (201) consisting of 5 atomic layers of AlN and 1 atomic layer of GaN alternating for 60 cycles. A second digital alloy layer is grown on the first digital alloy layer, consisting of 4 atomic layers of AlN and 2 atomic layers of GaN grown alternately for 60 cycles. A third digital alloy layer is grown on the second digital alloy layer, consisting of alternating growth of 3 atomic layers of AlN and 3 atomic layers of GaN for 60 cycles. A fourth digital alloy layer is grown on the third digital alloy layer, which is formed by alternating growth of 2 atomic layers of AlN and 4 atomic layers of GaN for 60 cycles.

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