Semiconductor test structure and method of manufacturing the same

Abstract

Embodiments of the present application provide a semiconductor test structure and a manufacturing method thereof. The manufacturing method comprises: providing a substrate; the substrate comprises a first region and a second region; the first region and the second region have a first overlapping region; on the substrate, a first test structure located in the first overlapping region is formed; the first test structure comprises a first conductive line, a second conductive line and a first conductive channel connecting the first conductive line and the second conductive line; the first conductive line and the second conductive line are formed in a photomask bonding manner and comprise a first part and a second part partially overlapping with the first part; the first test structure is subjected to continuity detection and / or disconnection detection to obtain a detection result; the detection result indicates that a lithography deviation and a bonding deviation belong to a preset deviation range.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor test structure and its manufacturing method. Background Technology

[0002] In the semiconductor manufacturing field, photolithography is crucial for the high-precision manufacturing of semiconductor devices, and photolithography for large-size patterns faces significant challenges. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor test structure and a method for manufacturing the same.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor test structure. The method includes: providing a substrate; the substrate includes a first region and a second region; a first overlapping region exists between the first region and the second region; forming a first test structure located in the first overlapping region on the substrate; the first test structure includes a first conductive line, a second conductive line, and a first conductive channel connecting the first conductive line and the second conductive line; the first conductive line and the second conductive line are formed by photomask bonding and include a first portion and a second portion that partially overlaps with the first portion; performing connectivity detection and / or disconnection detection on the first test structure to obtain a detection result; the detection result characterizes that overlay deviation and bonding deviation are within a preset deviation range.

[0005] In some embodiments, forming a first test structure located in a first overlapping region includes: sequentially forming a first conductive line, a first conductive channel, and a second conductive line on a substrate; forming the first conductive line, or forming the second conductive line, includes: a first portion formed using a photolithographic mask of a first region and a second portion formed using a photolithographic mask of a second region; wherein the first portion and the second portion have an extending and connected first bonding region and a second bonding region; the second bonding region extends along a first direction; the first bonding region extends along a second direction; and the first direction and the second direction intersect.

[0006] In some embodiments, the first portion formed using a photolithographic mask of a first region and the second portion formed using a photolithographic mask of a second region include: forming a first material layer and a photoresist layer on a substrate; performing a first exposure on the photoresist layer of the first region to form a first pattern corresponding to the first portion in the photoresist layer of a first overlapping region; performing a second exposure on the photoresist layer of the second region to form a second pattern corresponding to the second portion in the photoresist layer of the first overlapping region where the first pattern is formed, thereby obtaining a photoresist pattern layer on the first material layer; and removing a portion of the first material layer using the photoresist pattern layer to obtain a first structural layer on the substrate; the first structural layer includes a first conductive line.

[0007] In some embodiments, the substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; a fourth overlapping region exists between the third region and the fourth region; the first overlapping region, the second overlapping region, the third overlapping region, and the fourth overlapping region all include a common region; forming a first test structure located in the first overlapping region includes: forming a first test structure located in the common region on the substrate.

[0008] In some embodiments, forming a first test structure located in a common area includes: sequentially forming a first conductive line, a first conductive channel, and a second conductive line on a substrate; forming the first conductive line, or forming the second conductive line, includes: a first portion formed using a photolithographic mask of a first region, a second portion formed using a photolithographic mask of a second region, a third portion formed using a photolithographic mask of a third region, and a fourth portion formed using a photolithographic mask of a fourth region; wherein a first bonding region is present between the first portion and the second portion; a second bonding region is present between the first portion and the third portion; a third bonding region is present between the third portion and the fourth portion; a fourth bonding region is present between the second portion and the fourth portion; the second bonding region and the fourth bonding region extend along a first direction; the first bonding region and the third bonding region extend along a second direction; and the first direction and the second direction intersect.

[0009] In some embodiments, the substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; a fourth overlapping region exists between the third region and the fourth region; a fifth overlapping region exists between the second region and the third region; both the first and third overlapping regions include a first common region; both the second and fourth overlapping regions include a second common region; the fifth overlapping region includes both the first and second common regions; forming a first test structure located in the first overlapping region includes: forming a first test structure located in the first common region on the substrate; the manufacturing method further includes: forming a second test structure located in the second common region on the substrate; the second test structure is identical to the first test structure; obtaining a detection result includes: performing connectivity detection and / or disconnection detection on the first test structure, and performing connectivity detection and / or disconnection detection on the second test structure to obtain a detection result.

[0010] Secondly, embodiments of this application provide a semiconductor test structure, which includes: a substrate; the substrate includes a first region and a second region; a first overlapping region exists between the first region and the second region; a first test structure is located on the substrate, including a first conductive line, a second conductive line, and a first conductive channel connecting the first conductive line and the second conductive line; the first conductive line and the second conductive line are formed by photomask bonding, and include a first portion and a second portion that partially overlaps with the first portion; wherein, the connectivity detection and / or disconnection detection results of the first test structure are characterized by overlay deviation and bonding deviation falling within a preset deviation range.

[0011] In some embodiments, the first conductive wire and the second conductive wire include one or more helical wires; the helical wire includes a first end located in the middle of the helical wire and a second end located at the edge of the helical wire; the first conductive channel includes one or more conductive vias; the conductive vias connect the first end of the first conductive wire and the first end of the second conductive wire, or connect the second end of the first conductive wire and the second end of the second conductive wire.

[0012] In some embodiments, the spiral wire includes a square spiral; the square spiral includes a plurality of straight extensions located between a first end and a second end and connected in sequence; the plurality of straight extensions extend alternately along a first direction and a second direction; the first direction intersects the second direction.

[0013] In some embodiments, the first part and the second part have an extended and connected first joint region and a second joint region; the second joint region extends along a first direction; the first joint region extends along a second direction; the first direction and the second direction intersect; the absolute value of the difference between the first characteristic dimension of the first conductive line of the first joint region and / or the second characteristic dimension of the first conductive line of the second joint region and the third characteristic dimension of the first conductive line of the other region is within a preset value range; the other region is the region other than the first joint region and the second joint region.

[0014] In some embodiments, the feature size of the first bonding region and / or the feature size of the second bonding region ranges from 0.25 micrometers to 0.9 micrometers; the minimum size of the first test structure along the first direction and / or the minimum size along the second direction is greater than or equal to 60 micrometers.

[0015] In some embodiments, the substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; a fourth overlapping region exists between the third region and the fourth region; the first overlapping region, the second overlapping region, the third overlapping region, and the fourth overlapping region all include a common region; a first test structure is located in the common region; or, a fifth overlapping region exists between the second region and the third region; the first overlapping region and the third overlapping region both include a first common region; the second overlapping region and the fourth overlapping region both include a second common region; the fifth overlapping region includes both the first common region and the second common region; the semiconductor test structure further includes a second test structure; the second test structure is identical to the first test structure; the first test structure is located in the first common region; the second test structure is located in the second common region.

[0016] In various embodiments of this application, a first test structure is formed in a first overlapping region between the first region and the second region by photomask bonding. A detection result is obtained by performing connectivity detection and / or disconnection detection on the first test structure. The first test structure serves as an electrical test structure, and the detection result characterizes the conduction or disconnection status of the first test structure. Furthermore, as an electrical test structure formed by photomask bonding, the detection result can also characterize whether the overlay deviation and bonding deviation of the first test structure are within a preset deviation range. Thus, the first test structure formed by photomask bonding can be used both as an electrical test structure and as a structure for monitoring overlay and bonding deviations during the photomask bonding process. In other words, the test structure used for connectivity detection and / or the test structure used for disconnection detection can be reused with a test structure used for semiconductor structures where the overlay and bonding deviations are within a preset deviation range, saving semiconductor structure area. Attached Figure Description

[0017] Figure 1 A schematic diagram of an exemplary wafer including multiple chips provided for embodiments of this application; Figure 2 A schematic diagram of the lithography mask corresponding to the maximum single exposure field of the lithography equipment provided in the embodiments of this application; Figure 3 A schematic diagram illustrating the joining of two photolithographic masks into a complete layout, as provided in an embodiment of this application; Figure 4 One of the schematic diagrams showing the assembly of four photolithographic masks into a complete layout provided in an embodiment of this application; Figure 5 A second schematic diagram illustrating the assembly of four photolithographic masks into a complete layout, as provided in an embodiment of this application; Figure 6A schematic diagram showing the assembly of six photomasks into a complete layout for an embodiment of this application; Figure 7 A schematic diagram illustrating the principle of performing connectivity and disconnection detection on the first test structure according to an embodiment of this application; Figure 8 This is a schematic diagram of the process for forming the first test structure provided in an embodiment of this application; Figures 9A to 9D A schematic diagram illustrating the formation of the first structural layer by bonding two photolithographic masks into a complete layout, as provided in an embodiment of this application; Figures 10A to 10F This is one of the schematic diagrams provided in this application for forming a first structural layer by bonding four photolithographic masks together to form a complete layout; Figure 11 A schematic diagram illustrating the formation of the first test structure by bonding two photomasks into a complete layout, as provided in an embodiment of this application; Figure 12 A schematic diagram illustrating the formation of the first test structure by bonding four photolithographic masks into a complete layout, as provided in an embodiment of this application; Figure 13 The semiconductor test structure provided in the embodiments of this application includes a schematic diagram of a plurality of first test structures. Detailed Implementation

[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0021] In chip manufacturing, photomasks serve as pattern transfer tools or master substrates, carrying pattern information and process technology information. Their function is to transfer the circuit pattern onto a substrate material, such as a silicon wafer, through exposure, thereby enabling mass production of chips. In semiconductor manufacturing, such as in advanced packaging, large-size patterns formed by photomask stitching are used to cover silicon or glass substrates in wafer-level packaging. During photomask stitching, it is crucial to ensure high alignment accuracy between adjacent photomask patterns. Significant alignment deviations between adjacent photomask patterns can lead to short circuits, open circuits, and other failures in large-size semiconductor devices etched using large-size patterns.

[0022] Due to limitations in the mechanical and thermal stability of semiconductor manufacturing processes, optical system errors in lithography equipment, and inherent characteristics (such as warpage) of large-size silicon or glass substrates (larger than the maximum size of a single exposure in a lithography machine), alignment deviations during photomask bonding are difficult to partially or completely compensate for, leading to failure issues in the resulting large-size semiconductor devices. In this article, the term "large-size" refers to a size that is ten times or more larger than the size of a "small-size" semiconductor.

[0023] Detecting the alignment accuracy and misalignment of photomask bonding is a core issue in the photomask bonding process. Therefore, this application provides a bonding semiconductor test structure and its manufacturing method. The test structure can effectively detect the alignment accuracy and misalignment of photomask bonding in semiconductor structures. For example, it can effectively detect failures in the semiconductor structure, such as short circuits and open circuits.

[0024] Figure 1 This is a schematic diagram of an exemplary wafer including multiple chips, provided for embodiments of this application.

[0025] refer to Figure 1The wafer W1 includes multiple chips 100. The size of each chip 100 is larger than the size of the maximum exposure field in a single exposure of the lithography equipment; a single exposure is insufficient to obtain the complete layout required for the large-size chip 100. In some embodiments, the chip 100 may include control chips and / or memory chips. Control chips may include, for example, a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), a Microcontroller Unit (MCU), or an Application Specific Integrated Circuit (ASIC). Memory chips may include, for example, volatile memory (e.g., Dynamic Random Access Memory (DRAM)) or non-volatile memory (e.g., NAND flash memory).

[0026] Figure 2 This is a schematic diagram of the lithography mask corresponding to the maximum exposure field of the lithography machine provided in the embodiments of this application.

[0027] refer to Figure 2 The photolithography mask corresponding to the maximum exposure field of a single exposure in a photolithography machine may include a central region PZ1 and an edge region PZ2. The central region PZ1 can be understood as the region used to form functional circuits. Functional circuits may include a variety of active devices (e.g., transistors) and passive devices (e.g., capacitors, resistors, inductors, and the like) that meet the desired structural and functional requirements of the design, as well as interconnect layers located in an insulating layer that allow the active and passive devices to be brought out. Functional circuits may include NMOS devices or PMOS devices, etc. The materials of the interconnect layers include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicides, nitrides, or any combination thereof. The materials of the insulating layer include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The edge region PZ2 can be understood as the region not used to form functional circuits. The edge region may include test structures or alignment structures. Test structures may include structures for testing the leakage current of the functional circuit or structures for testing the breakdown voltage of the functional circuit. Alignment structures may include overlay marks for overlay alignment between different layers or joint marks for joining alignment between different regions of the same layer.

[0028] Figure 3 This is a schematic diagram showing the joining of two photomasks into a complete layout, as provided in an embodiment of this application. Figure 4This is one of the schematic diagrams showing the four photomasks assembled into a complete layout according to an embodiment of this application. Figure 5 This is the second schematic diagram showing the four photolithographic masks assembled into a complete layout for an embodiment of this application. Figure 6 This is a schematic diagram showing the six photomasks provided in the embodiments of this application joined together to form a complete layout.

[0029] refer to Figures 3 to 6 Given the limited maximum exposure field of a single lithography machine, when fabricating large-size chips, such as the first structural layer (which can be understood as an interconnect layer), multiple photolithographic masks are joined together to create a continuous large-size pattern, resulting in the complete layout required for the first structural layer of the large-size chip. In some embodiments, two, three, four, or more (e.g., six) photolithographic masks can be joined together to form a complete layout for fabricating large-size chips. This complete layout can correspond to... Figure 1 The large-size chip 100 is shown.

[0030] refer to Figure 3 In some embodiments, the first lithographic mask (also referred to herein as the first region P1) and the second lithographic mask (also referred to herein as the second region P2) can be joined together to form a complete layout; the first lithographic mask and the second lithographic mask have a first overlapping region P1-2.

[0031] refer to Figure 4 In some embodiments, the first photolithography mask, the second photolithography mask, the third photolithography mask (also referred to herein as the third region P3), and the fourth photolithography mask (also referred to herein as the fourth region P4) can be joined together to form a complete layout; the first photolithography mask and the second photolithography mask have a first overlapping region P1-2, the second photolithography mask and the fourth photolithography mask have a second overlapping region P2-4, the first photolithography mask and the third photolithography mask have a third overlapping region P1-3, and the third photolithography mask and the fourth photolithography mask have a fourth overlapping region P3-4; the first photolithography mask, the second photolithography mask, the third photolithography mask, and the second photolithography mask have a common region P1-2-3-4; wherein, the first overlapping region, the second overlapping region, the third overlapping region, and the fourth overlapping region all include the common region P1-2-3-4. For example, the first lithography mask, the second lithography mask, the third lithography mask and the second lithography mask have the same size and are centrally symmetric about the common region P1-2-3-4.

[0032] refer to Figure 5In some embodiments, the first, second, third, and fourth photolithographic masks can be joined together to form a complete layout; the first and second photolithographic masks have a first overlapping region P1-2, the second and fourth photolithographic masks have a second overlapping region P2-4, the first and third photolithographic masks have a third overlapping region P1-3, and the third and fourth photolithographic masks have a fourth overlapping region P2-4; the second and third photolithographic masks have a fifth overlapping region P1-5; wherein the fifth overlapping region P1-5 includes a first common region P1-2-3 and a second common region P1-2-3, the first and third overlapping regions P1-2 and P1-3 include the first common region P1-2-3, and the second and fourth overlapping regions P2-4 and P3-4 include the second common region P2-3-4. For example, the first and fourth photolithographic masks have the same size, the second and third photolithographic masks have the same size, and the first, second, third and fourth photolithographic masks are centrally symmetrical about the fifth overlapping region P1-5.

[0033] refer to Figure 6 In some embodiments, the first, second, third, fourth, fifth (also referred to herein as the fifth region P5), and sixth (also referred to herein as the sixth region P6) photolithographic masks can be joined together to form a complete layout; details of the joining of the six photolithographic masks can be found in [reference needed]. Figure 5 The bonding details of the four photolithographic masks shown will be understood and will not be repeated here.

[0034] Figure 7 This is a schematic diagram illustrating the principle of performing connectivity and disconnection detection on the first test structure according to an embodiment of this application. Figure 7 The diagram illustrates a single layer of conductive wire in a first test structure, which includes a first portion PT1 and a second portion PT2.

[0035] In some embodiments, a first test structure formed by photomask bonding is subjected to connectivity and / or disconnection detection to obtain detection results; and based on different test results, the conduction or disconnection status of the first test structure is characterized, as well as whether the overlay deviation and bonding deviation of the first test structure are within a preset deviation range. Exemplarily, a test current is applied between the two ends of the first test structure, and the voltage between the two ends of the first test structure in response to the test current is measured; the voltage value is used to characterize the conduction or disconnection status of the first test structure, and further, it can also be used to characterize whether the overlay deviation and bonding deviation of the first test structure are within a preset deviation range.

[0036] For example, one end of the first test structure is grounded, a test current is applied to the other end of the first test structure, and the voltage at the other end of the first test structure is measured. If the voltage value is greater than or equal to a first preset value, the first test structure is open; if the voltage value is less than a second preset value, the first test structure is conductive; wherein, the first preset value is greater than the second preset value, and the second preset value is greater than the ground voltage. If the voltage value is less than the second preset value, the overlay deviation and bonding deviation of the first test structure are within the preset deviation range; if the voltage value is greater than or equal to the second preset value, the overlay deviation and bonding deviation of the first test structure exceed the preset deviation range. It should be noted that since the first test structure is formed by overlay and bonding, the larger the overlay deviation and bonding deviation of the first test structure, the larger the resistance value of the first test structure, and correspondingly, the larger the voltage value. For example, in an extreme case, the first test structure is open, and correspondingly, the voltage value is greater than or equal to the first preset value.

[0037] refer to Figure 7 The first test structure undergoes a connectivity test, which verifies the alignment accuracy of the photomask bonding. An open circuit will occur if the deviation exceeds a preset range. The first test structure also undergoes a disconnection test, which verifies the alignment accuracy of the photomask bonding. A short circuit will occur if the deviation exceeds a preset range.

[0038] refer to Figure 7 In Figure (a), with the first part PT1 and the second part PT2 properly joined, the joining portions of the first part PT1 and the second part PT2 overlap in the first joining region 301. The first joining region 301 has a characteristic dimension CDX.

[0039] refer to Figure 7 In Figure (b), in the case where there is a first offset between the first part PT1 and the second part PT2, there is a gap between the joint portions of the first part PT1 and the second part PT2, and the offset amount is... X1 is larger than the first bonding region 301, which has a characteristic size CDX, leading to a circuit open-circuit failure. Here, the first offset can be understood as an offset along the first direction (X direction). X1 and offset along the second direction (Y direction) Y1; Offset X1 exceeds the preset deviation range, offset. Y1 falls within the preset deviation range.

[0040] refer to Figure 7In Figure (c) or (d), when there is a second offset between the first part PT1 and the second part PT2, the feature dimension CD1-2 of the connection between the first part PT1 and the second part PT2 is smaller than the feature dimension CD1 of the first part PT1 or the feature dimension CD2 of the second part PT2 (for example, feature dimension CD1-2 is less than half of feature dimension CD1), leading to a failure problem of increased circuit resistance. The second offset can be understood as an offset along the first direction (X direction). X2 and offset along the second direction (Y direction) Y2; Offset X2 falls within the preset deviation range; offset amount Y2 exceeds the preset deviation range. Figure 7 Figure (c) can be understood as the first part PT1 and the second part PT2 obtained using negative photoresist (also known as negative photoresist). Figure 7 Figure (d) in the diagram can be understood as a schematic diagram of the first part PT1 and the second part PT2 obtained using positive photoresist (also known as positive photoresist).

[0041] Figure 8 This is a schematic diagram of the process for forming the first test structure provided in an embodiment of this application.

[0042] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor test structure, referring to... Figure 8 The manufacturing method includes the following steps: Step S101: Provide a substrate; the substrate includes a first region and a second region; the first region and the second region have a first overlapping region; Step S102: On the substrate, a first test structure located in the first overlapping region is formed; the first test structure includes a first conductive line, a second conductive line, and a first conductive channel connecting the first conductive line and the second conductive line; the first conductive line and the second conductive line are formed by photomask bonding and include a first portion and a second portion that partially overlaps with the first portion; Step S103: Perform connectivity and / or disconnection detection on the first test structure to obtain the detection results; the detection results indicate that the overlay deviation and the joining deviation are within the preset deviation range.

[0043] In this embodiment, a first test structure is formed in the first overlapping region between the first region and the second region by photomask bonding. A detection result is obtained by performing connectivity detection and / or disconnection detection on the first test structure. The first test structure serves as an electrical test structure, and the detection result characterizes the conduction or disconnection status of the first test structure. Furthermore, as an electrical test structure formed by photomask bonding, the detection result can also characterize whether the overlay deviation and bonding deviation of the first test structure are within a preset deviation range. Thus, the first test structure obtained by the semiconductor test structure manufacturing method can be used both as an electrical test structure and as a structure for monitoring overlay and bonding deviations during the photomask bonding process. In other words, the test structure used for connectivity detection and / or the test structure used for disconnection detection can be reused with a test structure whose overlay and bonding deviations of the semiconductor structure are within a preset deviation range, saving semiconductor structure area.

[0044] In this embodiment, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top (or bottom) of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon-germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer. Exemplarily, the substrate may be a silicon substrate or a glass substrate. In some embodiments, the type of substrate may be selected according to the actual needs of the device. The substrate may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, or silicon-on-insulator (SiGe) substrate. on Germanium on an insulator (SOI) substrate or insulator (SOI) substrate or insulator on Insulator (GOI) substrates, etc. The substrate can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as a glass substrate or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate). In some embodiments, the substrate may be retained or partially retained, or removed or partially removed, in subsequent process steps. The retention, removal, or partial removal of the substrate can be adaptively selected according to the specific requirements of the process.

[0045] In some embodiments, a first test structure obtained by photomask bonding is tested, and the test result is correlated with a preset deviation range. For example, if a connectivity test is performed on the first test structure and the test result shows an open circuit, it can indicate that the overlay deviation and / or bonding deviation of the semiconductor structure exceeds the preset deviation range; if the test result shows that the connectivity test passes, it can indicate that the overlay deviation and bonding deviation of the semiconductor structure are within the preset deviation range. Similarly, if a disconnection test is performed on the first test structure and the test result shows a short circuit, it can indicate that the overlay deviation and / or bonding deviation of the semiconductor structure exceeds the preset deviation range; if the test result shows that the disconnection test passes, it can indicate that the overlay deviation and bonding deviation of the semiconductor structure are within the preset deviation range.

[0046] In some embodiments, the preset deviation range may be associated with lithographic precision. Exemplarily, the preset deviation range may be from a few nanometers to a few micrometers. For example, the preset deviation range may be in the nanometer, tens of nanometer, hundreds of nanometer, or thousands of nanometer ranges.

[0047] In some embodiments, forming a first test structure located in a first overlapping region includes: sequentially forming a first conductive line, a first conductive channel, and a second conductive line on a substrate; forming the first conductive line, or forming the second conductive line, includes: a first portion formed using a photolithographic mask of a first region and a second portion formed using a photolithographic mask of a second region; wherein the first portion and the second portion have an extending and connected first bonding region and a second bonding region; the second bonding region extends along a first direction; the first bonding region extends along a second direction; the first direction and the second direction intersect (e.g., are orthogonal). In the embodiments of this application, the first portion formed using a photolithographic mask of the first region can reduce / avoid the offset between the central region of the first region and the first portion; the second portion formed using a photolithographic mask of the second region can reduce / avoid the offset between the central region of the second region and the second portion; the first portion and the second portion formed in the first overlapping region can better reflect the bonding deviation between the first region and the second region; and the bonding deviation between the two regions (the first region and the second region) can be reflected by forming the first test structure in only one region (the first overlapping region).

[0048] Figures 9A to 9D This is a schematic diagram illustrating the formation of the first structural layer by joining two photolithographic masks into a complete layout, as provided in an embodiment of this application. Figures 9A to 9D Figure (b) in each figure is an enlarged schematic diagram of region P102 in figure (a). For example, Figure 9A Figure (b) is Figure 9A A magnified view of region P102 in Figure (a).

[0049] refer to Figure 9A A substrate 102 is provided. The substrate 102 includes a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, etc. In some embodiments, functional circuitry can be formed in the substrate 102. The functional circuitry includes a variety of active devices (e.g., transistors) and passive devices (e.g., capacitors, resistors, inductors, and the like) that meet the desired structural and functional requirements of the design. For example, the functional circuitry may include NMOS devices or PMOS devices.

[0050] refer to Figure 9A In some embodiments, the method for manufacturing the semiconductor test structure further includes: removing a portion of the substrate 102 using the same exposure process to form a zeroth structure layer located in the substrate 102. Figure 9A (Not shown); the zeroth structural layer includes the first set of overlay marks ( Figure 9A (not shown) and the second set of overlay marks ( Figure 9A (Not shown); the first set of overlay marks is used for overlay alignment of each structural layer in the first region; the second set of overlay marks is used for overlay alignment of each structural layer in the second region. In the embodiments of this application, the division of each region of the substrate 102 can be referred to Figure 3 The division of the various regions shown is for reference only and will not be elaborated further here. Region P102 in this embodiment can be understood as… Figure 3 The public area P1-2 shown.

[0051] refer to Figures 9B to 9D In some embodiments, the first portion formed using a photolithographic mask of a first region and the second portion formed using a photolithographic mask of a second region include: forming a first material layer and a photoresist layer on the first material layer on a substrate; performing a first exposure on the photoresist layer of the first region to form a first pattern corresponding to the first portion in the photoresist layer of a first overlapping region; performing a second exposure on the photoresist layer of the second region to form a second pattern corresponding to the second portion in the photoresist layer of the first overlapping region where the first pattern is formed, thereby obtaining a photoresist pattern layer on the first material layer; and removing a portion of the first material layer using the photoresist pattern layer to obtain a first structural layer on the substrate; the first structural layer includes a first conductive line.

[0052] refer to Figure 9B In some embodiments, forming a first structural layer includes: on substrate 102 (reference numeral 102) Figure 9A On the first material layer 104 and a photoresist layer 106 located on the first material layer are formed (see reference). Figure 9B (b) Figure); Based on the first set of overlay marks, the photoresist layer 106 of the first region P1 is subjected to a first exposure, and the corresponding pattern is formed in the photoresist layer of the other regions of the first region P1 except for region P102. Figure 9B (Not shown), synchronously, a first pattern F1 is formed in a portion of the photoresist layer 106 in the region P102 of the first overlapping region P1-2, which is used to form the first test structure. The photoresist layer 106 that is first exposed is shown as the exposed photoresist layer 108 (reference). Figure 9B (Figure (b)) The exposed photoresist layer 108 is removed in the subsequent development process.

[0053] It should be noted that, in order to clearly show the graphics within region P102 used to form the first test structure, the graphics of other regions of the first region P1 excluding region P102 are omitted. In some embodiments, the central region PZ1 of the first region P1 (refer to...) Figure 2 This can form an interconnect layer that brings out active and passive devices. In some embodiments, the edge region PZ2 of the first region P1 (refer to...) Figure 2 Other areas of the removed region P102 may include alignment structures. Alignment structures may include overlay marks for overlay alignment between different layers or joint marks for joining alignment between different regions of the same layer.

[0054] refer to Figure 9C In some embodiments, forming a first structural layer includes: based on a second set of overlay marks, forming a photoresist layer 106 (reference) for the second region P2. Figure 9B A second exposure is performed to form the corresponding pattern in the photoresist layer of the other regions besides region P102 in the second region P2. Figure 9C (Not shown), synchronously, a second pattern F2 is formed in the remaining portion of the photoresist layer 106 in the region P102 of the first overlapping region P1-2 used to form the first test structure. There are two extending and connected overlapping regions between the first and second exposures, which respectively correspond to... Figure 9D The first bonding region 301 and the second bonding region 302 are shown. The second exposed photoresist layer 106 is shown as the exposed photoresist layer 108, which is removed in a subsequent development process. The pattern of other regions in the removed region P102 of the second region P2 can be understood by referring to the pattern of other regions in the removed region P102 of the first region P1, and will not be described again here.

[0055] refer to Figure 9D In some embodiments, a development process can be used to remove the exposed photoresist layer 108 (see reference). Figure 9C Figure (b) shows the photoresist pattern layer F1-2 located on the first material layer (see reference). Figure 9C(For understanding, refer to Figure (b)). Using the photoresist pattern layer F1-2, a portion of the first material layer is removed to obtain a first structural layer L1 located on the substrate. The first structural layer L1 includes a first conductive line Mx-1 of the first test structure. The first conductive line Mx-1 includes a first portion F1p and a second portion F2p, with an extending and connected first bonding region 301 and a second bonding region 302 between the first portion F1p and the second portion F2p.

[0056] In some embodiments, the same as can be used. Figures 9A to 9D A first conductive layer is formed on the first structural layer L1 in the same or similar manner as shown in the diagram; the first conductive layer includes a first conductive channel Vx-1 of the first test structure (reference). Figure 11 For example, the first conductive layer is formed in the same or similar manner as the photomask used to form the first structural layer.

[0057] In some embodiments, the same as can be used. Figures 9A to 9D A second structural layer is formed on the first conductive layer in the same or similar manner as the formation of the first structural layer shown; the second structural layer includes the second conductive line Mx of the first test structure (reference). Figure 11 For example, the second structural layer is formed in the same or similar manner as the photomask used to form the first structural layer.

[0058] Thus, the first test structure TK1 is formed by photomask bonding (reference). Figure 11 The first test structure TK1 includes a first conductive line Mx-1, a second conductive line Mx, and a first conductive channel Vx-1 connecting the first conductive line Mx-1 and the second conductive line Mx.

[0059] In some embodiments, the substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; a fourth overlapping region exists between the third region and the fourth region; the first overlapping region, the second overlapping region, the third overlapping region, and the fourth overlapping region all include a common region; forming a first test structure located in the first overlapping region includes: forming a first test structure located in the common region on the substrate. In embodiments of this application, the first test structure formed in the common region can reflect the bonding deviation between the four regions (the first region, the second region, the third region, and the fourth region) by forming the first test structure in only one region (the common region).

[0060] Figures 10A to 10F This is one of the schematic diagrams provided in this application for forming a first structural layer by connecting four photolithographic masks into a complete layout. Figures 10A to 10FFigure (b) in each figure is an enlarged schematic diagram of region P104 in figure (a). For example, Figure 10A Figure (b) is Figure 10A A magnified view of region P104 in Figure (a).

[0061] refer to Figure 10A Substrate 102 is provided. For detailed information about substrate 102, please refer to [reference needed]. Figure 9A The relevant descriptions will be understood and will not be repeated here.

[0062] refer to Figure 10A In some embodiments, the method for manufacturing the semiconductor test structure further includes: removing a portion of the substrate 102 using the same exposure process to form a zeroth structure layer located in the substrate 102. Figure 10A (Not shown); the zeroth structural layer includes the first set of overlay marks ( Figure 10A (not shown), second set of overlay marks ( Figure 10A (not shown), third set of overlay marks ( Figure 10A (not shown) and the fourth set of overlay marks ( Figure 10A (Not shown); the first set of overlay marks is used for overlay alignment of each structural layer in the first region; the second set of overlay marks is used for overlay alignment of each structural layer in the second region; the third set of overlay marks is used for overlay alignment of each structural layer in the third region; and the fourth set of overlay marks is used for overlay alignment of each structural layer in the fourth region. In the embodiments of this application, the division of each region of the substrate 102 can be referred to Figure 4 The division of the various regions shown is for reference only and will not be elaborated further here. Region P104 in this embodiment can be understood as… Figure 4 At least a portion of the public area P1-2-3-4 shown.

[0063] refer to Figures 10B to 10FIn some embodiments, forming a first test structure located in a common area includes: sequentially forming a first conductive line, a first conductive channel, and a second conductive line on a substrate; forming the first conductive line, or forming the second conductive line, includes: a first portion formed using a photolithographic mask of a first region, a second portion formed using a photolithographic mask of a second region, a third portion formed using a photolithographic mask of a third region, and a fourth portion formed using a photolithographic mask of a fourth region; wherein a first bonding region is present between the first portion and the second portion; a second bonding region is present between the first portion and the third portion; a third bonding region is present between the third portion and the fourth portion; a fourth bonding region is present between the second portion and the fourth portion; the second bonding region and the fourth bonding region extend along a first direction; the first bonding region and the third bonding region extend along a second direction; and the first direction and the second direction intersect. In this embodiment, the first portion formed using a photolithographic mask of the first region can reduce / avoid the offset between the central region of the first region and the first portion; the second portion formed using a photolithographic mask of the second region can reduce / avoid the offset between the central region of the second region and the second portion; the third portion formed using a photolithographic mask of the third region can reduce / avoid the offset between the central region of the third region and the third portion; the fourth portion formed using a photolithographic mask of the fourth region can reduce / avoid the offset between the central region of the fourth region and the fourth portion; the first, second, third, and fourth portions formed in the common area can better reflect the bonding deviation between the first, second, third, and fourth regions.

[0064] refer to Figure 10B In some embodiments, forming a first structural layer includes: on substrate 102 (reference numeral 102) Figure 10A On the first material layer 104 and a photoresist layer 106 located on the first material layer are formed (see reference). Figure 10B (b) Figure); Based on the first set of overlay marks, the photoresist layer 106 of the first region P1 is subjected to a first exposure, and the corresponding pattern is formed in the photoresist layer of the other regions of the first region P1 except for region P104. Figure 10B (Not shown), synchronously, in the public area P1-2-3-4 (reference) Figure 4 A first pattern F1 is formed in a portion of the photoresist layer 106 in region P104, which is used to form the first test structure. The first exposed photoresist layer 106 is shown as the exposed photoresist layer 108 (reference). Figure 10B (Figure (b)) The exposed photoresist layer 108 is removed in the subsequent development process.

[0065] It should be noted that, in order to clearly show the graphics within region P104 used to form the first test structure, the graphics of other regions of the first region P1 excluding region P104 are omitted. In some embodiments, the central region PZ1 of the first region P1 (refer to...) Figure 2 This can form an interconnect layer that brings out active and passive devices. In some embodiments, the edge region PZ2 of the first region P1 (refer to...) Figure 2 Other areas of the removed region P104 may include alignment structures. Alignment structures may include overlay marks for overlay alignment between different layers or engagement marks for joining alignment between different regions of the same layer.

[0066] refer to Figure 10C In some embodiments, forming a first structural layer includes: based on a second set of overlay marks, forming a photoresist layer 106 (reference) for the second region P2. Figure 10B A second exposure is performed to form the corresponding pattern in the photoresist layer of the other areas of the second region P2, excluding region P104. Figure 10C (Not shown), synchronously, in the public area P1-2-3-4 (reference) Figure 4 The second pattern F2 is formed in a portion of the photoresist layer 106 of the region P104 used to form the first test structure. There is an extended overlapping region between the first and second exposures, which corresponds to... Figure 10F The first bonding region 301 is shown. The second exposed photoresist layer 106 is shown as the exposed photoresist layer 108, which is removed in a subsequent development process. The pattern of other regions in the removed region P104 of the second region P2 can be understood by referring to the pattern of other regions in the removed region P104 of the first region P1, and will not be repeated here.

[0067] refer to Figure 10D In some embodiments, forming a first structural layer includes: based on a third set of overlay marks, forming a photoresist layer 106 (reference) in the third region P3. Figure 10C A third exposure is performed to form the corresponding pattern in the photoresist layer of the other areas of the third region P3, excluding region P104. Figure 10D (Not shown), synchronously, in the public area P1-2-3-4 (reference) Figure 4 The third pattern F3 is formed in a portion of the photoresist layer 106 within the region P104 used to form the first test structure. An extended overlapping region exists between the second and third exposures, corresponding to… Figure 10FThe second bonding region 302 is shown. The second exposed photoresist layer 106 is shown as the exposed photoresist layer 108, which is removed in a subsequent development process. The pattern of other regions in the removed region P104 of the third region P3 can be understood by referring to the pattern of other regions in the removed region P104 of the first region P1, and will not be repeated here.

[0068] refer to Figure 10E In some embodiments, forming a first structural layer includes: based on a fourth set of overlay marks, forming a photoresist layer 106 (reference) for the fourth region P4. Figure 10D A fourth exposure is performed to form the corresponding pattern in the photoresist layer of the area other than the area P104 in the fourth region P4. Figure 10E (Not shown), synchronously, in the public area P1-2-3-4 (reference) Figure 4 The fourth pattern F4 is formed in the remaining portion of the photoresist layer 106 in the region P104 used to form the first test structure. There is an extended overlapping region between the third and fourth exposures, which corresponds to... Figure 10F The third bonding region 303 shown; there is an extended overlapping region between the second exposure and the fourth exposure, which corresponds to Figure 10F The fourth bonding region 304 is shown. The second exposed photoresist layer 106 is shown as the exposed photoresist layer 108, which is removed in a subsequent development process. The pattern of other regions in the removed region P104 of the fourth region P4 can be understood by referring to the pattern of other regions in the removed region P104 of the first region P1, and will not be repeated here.

[0069] refer to Figure 10F In some embodiments, a development process can be used to remove the exposed photoresist layer 108 (see reference). Figure 10E Figure (b) shows the photoresist pattern layer located on the first material layer (see reference). Figure 9C (For understanding, refer to Figure (b)). Using a photoresist pattern layer, a portion of the first material layer is removed to obtain a first structural layer L1 located on the substrate. The first structural layer L1 includes a first conductive line Mx-1 of the first test structure. The first conductive line Mx-1 includes a first portion F1p, a second portion F2p, a third portion F3p, and a fourth portion F4p. An extended first bonding region 301 exists between the first portion F1p and the second portion F2p; an extended second bonding region 302 exists between the first portion F1p and the third portion F3p; an extended third bonding region 303 exists between the third portion F3p and the fourth portion F4p; and an extended fourth bonding region 304 exists between the second portion F2p and the fourth portion F4p.

[0070] In some embodiments, the same as can be used. Figures 10A to 10F A first conductive layer is formed on the first structural layer L1 in the same or similar manner as shown in the diagram; the first conductive layer includes a first conductive channel Vx-1 of the first test structure (reference). Figure 12 For example, the first conductive layer is formed in the same or similar manner as the photomask used to form the first structural layer.

[0071] In some embodiments, the same as can be used. Figures 10A to 10F A second structural layer is formed on the first conductive layer in the same or similar manner as the formation of the first structural layer shown; the second structural layer includes the second conductive layer Mx of the first test structure (reference). Figure 12 For example, the second structural layer is formed in the same or similar manner as the photomask used to form the first structural layer.

[0072] Thus, the first test structure TK1 is formed by photomask bonding (reference). Figure 11 The first test structure TK1 includes a first conductive line Mx-1, a second conductive line Mx, and a first conductive channel Vx-1 connecting the first conductive line Mx-1 and the second conductive line Mx.

[0073] In some embodiments, the substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; a fourth overlapping region exists between the third region and the fourth region; a fifth overlapping region exists between the second region and the third region; both the first and third overlapping regions include a first common region; both the second and fourth overlapping regions include a second common region; the fifth overlapping region includes both the first and second common regions; forming a first test structure located in the first overlapping region includes: forming a first test structure located in the first common region on the substrate; the manufacturing method further includes: forming a second test structure located in the second common region on the substrate; the second test structure is identical to the first test structure; obtaining a detection result includes: performing connectivity detection and / or disconnection detection on the first test structure, and performing connectivity detection and / or disconnection detection on the second test structure to obtain a detection result. In the embodiments of the application, the two first test structures formed in the first common region and the second common region can reflect the bonding deviation between the four regions (first region, second region, third region, and fourth region) through the formation of the first test structure by the two regions (first common region and second common region).

[0074] In this embodiment, the division of the various regions of the substrate 102 can be referred to Figure 5 The division of the various regions shown is for understanding purposes only and will not be elaborated upon here. The first overlapping region in this embodiment can be understood as… Figure 5At least a portion of the first public area P1-2-3 shown.

[0075] In this embodiment of the application, details regarding the formation of the first test structure located in the first public area can be found in [reference]. Figures 10A to 10F To understand the details of forming the first test structure shown, it is necessary to... Figures 10A to 10F The details of how the first test structure is formed by combining three lithographic masks (including the first exposure to the first region, the second exposure to the second region, and the third exposure to the combined third and fourth regions) into a complete layout are shown below. Other details are not elaborated here.

[0076] In this embodiment of the application, details regarding the formation of the second test structure located in the second public area can be found in [reference]. Figures 10A to 10F To understand the details of forming the first test structure shown, it is necessary to... Figures 10A to 10F The details of forming the second test structure by combining three lithographic masks (including the second exposure of the merged region of the first and second regions, the first exposure of the first region and the second exposure of the second region) into a complete layout are shown below. Other details are not elaborated here.

[0077] In some embodiments, connectivity and / or disconnection detection are performed on the first test structure to obtain detection results; the detection results are characterized by overlay deviation and joint deviation falling within a preset deviation range.

[0078] In some embodiments, connectivity and / or disconnection detection of the first test structure can be achieved through wafer acceptance test (WAT). The purpose of WAT is to detect the process status of each wafer product by testing the electrical parameters of specific test structures on the wafer, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer product meets the electrical specifications of the process technology platform.

[0079] For example, a connectivity test is performed on the first test structure. This connectivity test can verify the alignment accuracy of the photomask bonding. If the deviation exceeds a preset range, an open circuit will occur. For instance, by designing a chain-like resistor structure between the first conductive line Mx-1, the first conductive channel Vx-1, and the second conductive line Mx, the precise resistance value between these three layers can be measured using a four-terminal method. Based on whether this resistance value exceeds the preset deviation range, it can be accurately determined whether an open circuit has occurred in the first test structure.

[0080] For example, a disconnection test is performed on the first test structure. This disconnection test can verify the alignment accuracy of the photomask bonding. If the deviation exceeds a preset range, a short circuit will occur. For instance, by designing a structure between the first conductive line Mx-1, the first conductive channel Vx-1, and the second conductive line Mx that can form a test leakage current and breakdown voltage, the precise leakage current and breakdown voltage between these three layers can be measured. Based on whether the leakage current and breakdown voltage exceed the preset deviation range, it can be accurately determined whether a short circuit has occurred in the first test structure.

[0081] It should be noted that the details of performing connectivity and / or disconnection testing on the second test structure can be understood by referring to the details of performing connectivity and / or disconnection testing on the first test structure, and will not be repeated here.

[0082] Figure 11 This is a schematic diagram illustrating the formation of a first test structure by joining two photomasks together to form a complete layout, as provided in an embodiment of this application. Figure 11 Figure (a) is a cross-sectional schematic diagram of the first test structure. Figure 11 Figure (b) is a top view of the first conductive line of the first test structure. Figure 11 Figure (a) also illustrates the first conductive channel connected to the first conductive line. Figure 11 Figure (c) is a top view of the second conductive wire of the first test structure. Figure 11 Figure (c) also illustrates the second conductive channel connected to the second conductive line.

[0083] Secondly, embodiments of this application provide a semiconductor testing structure, with reference to... Figure 11The semiconductor test structure includes: a substrate; the substrate includes a first region and a second region; a first overlapping region exists between the first region and the second region; a first test structure TK1 is located on the substrate 102, including a first conductive line Mx-1, a second conductive line Mx, and a first conductive channel Vx-1 connecting the first conductive line Mx-1 and the second conductive line Mx; the first conductive line Mx-1 and the second conductive line Mx are formed by photomask bonding, and include a first portion F1p and a second portion F2p that partially overlaps with the first portion F1p; wherein, the connectivity detection and / or disconnection detection results of the first test structure TK1 are characterized by overlay deviation and bonding deviation falling within a preset deviation range. In this embodiment, a first test structure is formed in the first overlapping region between the first region and the second region using a photomask bonding method. A detection result is obtained by performing connectivity detection and / or disconnection detection on the first test structure. The first test structure serves as an electrical test structure, and the detection result characterizes the conduction or disconnection status of the first test structure. Furthermore, as an electrical test structure formed by photomask bonding, the detection result can also characterize whether the overlay deviation and bonding deviation of the first test structure fall within a preset deviation range. Thus, the first test structure formed by photomask bonding can be used both as an electrical test structure and as a structure for monitoring overlay and bonding deviations during the photomask bonding process. In other words, the test structure used for connectivity detection and / or the test structure used for disconnection detection can be reused with a test structure used for semiconductor structures where the overlay and bonding deviations fall within a preset deviation range, saving semiconductor structure area.

[0084] refer to Figure 11 In some embodiments, the first conductive line Mx-1 and the second conductive line Mx include one or more helical wires; the helical wire includes a first end located in the middle of the helical wire and a second end located at the edge of the helical wire; the first conductive channel Vx-1 includes one or more conductive vias; the conductive vias connect the first end of the first conductive line Mx-1 and the first end of the second conductive line Mx, or connect the second end of the first conductive line Mx-1 and the second end of the second conductive line Mx. In the embodiments of this application, the helical wire includes wires arranged at intervals (periods) along multiple directions. The wires arranged at intervals (periods) can serve as markers for photolithographic alignment in the corresponding directions. The helical wire can serve as part of the wires of the first test structure for electrical testing, and can also serve as alignment markers for forming the middle part of the first region and the middle part of the second region. In this way, the first test structure can be reused, saving the area of ​​the semiconductor structure.

[0085] For example, the first conductive wire Mx-1 includes two helical wires, namely a first helical wire 202a and a second helical wire 202b; the first conductive channel Vx-1 includes two conductive vias, namely a first conductive via 204a and a second conductive via 204b; the second conductive wire Mx includes two helical wires, namely a third helical wire 206a and a fourth helical wire 206b; the first conductive via 204a connects the first end of the first helical wire 202a and the first end of the third helical wire 206a; the second conductive via 204b connects the first end of the second helical wire 202b and the first end of the fourth helical wire 206b.

[0086] In some embodiments, during the connectivity and / or disconnection detection of the first test structure TK1, the second end of the first helical wire 202a is connected to the ground terminal. Figure 11 (Not shown), used to receive a first voltage; the third conductive through-hole 208a of the second conductive channel connected to the second end of the third helical wire 206a is used to receive a second voltage greater than the first voltage. For example, the first voltage can be a voltage greater than 0V, and the second voltage can be a voltage of 0V or less than 0V.

[0087] In some embodiments, during the connectivity and / or disconnection detection of the first test structure TK1, the second end of the second helical wire 202b is connected to the ground terminal. Figure 11 (Not shown), used to receive a third voltage; the fourth conductive through-hole 208b of the second conductive channel connected to the second end of the fourth helical wire 206b is used to receive a fourth voltage greater than the third voltage. Exemplarily, the third voltage can be a voltage greater than 0V, and the fourth voltage can be a voltage of 0V or less than 0V.

[0088] For example, during the disconnection test of the first test structure TK1, the structure formed by the first helical wire 202a, the first conductive via 204a and the third helical wire 206a can be used for either leakage current detection or breakdown voltage detection, and the structure formed by the second helical wire 202b, the second conductive via 204b and the fourth helical wire 206b can be used for the other one.

[0089] For example, during the connectivity detection of the first test structure TK1, the structure composed of the first helical wire 202a, the first conductive through hole 204a and the third helical wire 206a, as well as the structure composed of the second helical wire 202b, the second conductive through hole 204b and the fourth helical wire 206b, can all be used for resistance value detection.

[0090] In some embodiments, the spiral wire includes a circular spiral; the circular spiral includes a plurality of arcuate extensions located between a first end and a second end and connected sequentially; the shape of the arcuate extensions includes a semi-circular arc. (Reference) Figure 11 In some embodiments, the helical wire includes a square helix; the square helix includes a plurality of straight extensions located between a first end and a second end and connected in sequence; the plurality of straight extensions extend alternately along a first direction (X direction) and a second direction (Y direction); the first direction intersects (e.g., orthogonally) the second direction. Compared to a circular helix, a square helix is ​​easier to implement and align using photolithography.

[0091] refer to Figure 11 In some embodiments, a first joint region 301 and a second joint region 302 extend and connect between the first part F1p and the second part F2p; the second joint region 302 extends along a first direction; the first joint region 301 extends along a second direction; the first direction and the second direction intersect; the absolute value of the difference between the first characteristic dimension of the first conductive line of the first joint region 301 and / or the second characteristic dimension of the first conductive line of the second joint region 302 and the third characteristic dimension of the first conductive line of other regions is within a preset value range; the other regions are regions other than the first joint region and the second joint region.

[0092] In this embodiment, the preset value range can be associated with the photolithography precision. For example, the preset value range can be from a few nanometers to a few micrometers. Specifically, the preset value range can be a nanometer range, a tens of nanometer range, a hundreds of nanometer range, or a thousands of nanometer range.

[0093] refer to Figure 11 In some embodiments, the feature size of the first bonding region 301 and / or the feature size of the second bonding region 302 range from 0.25 micrometers to 0.9 micrometers; the minimum size of the first test structure TK1 along the first direction and / or the minimum size along the second direction is greater than or equal to 60 micrometers.

[0094] Figure 12 This is a schematic diagram illustrating the formation of a first test structure by connecting four photolithographic masks into a complete layout, as provided in an embodiment of this application. Figure 12 Figure (a) is a cross-sectional schematic diagram of the first test structure. Figure 12 Figure (b) is a top view of the first conductive line of the first test structure. Figure 12 Figure (a) also illustrates the first conductive channel connected to the first conductive line. Figure 12 Figure (c) is a top view of the second conductive wire of the first test structure. Figure 12 Figure (c) also illustrates the second conductive channel connected to the second conductive line.

[0095] refer to Figure 4 and Figure 12 In some embodiments, the substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; a fourth overlapping region exists between the third region and the fourth region; the first overlapping region, the second overlapping region, the third overlapping region, and the fourth overlapping region all include a common region; and the first test structure is located in the common region.

[0096] In this embodiment, the division of the various regions of the substrate 102 can be referred to Figure 4 The division of the various regions shown is for reference only and will not be elaborated further here. Region P104 in this embodiment can be understood as… Figure 4 At least a portion of the public area P1-2-3-4 shown.

[0097] In this embodiment, details of the first test structure located in the public area can be found in [reference]. Figures 10A to 10F Understanding the details of forming the first test structure as shown reveals that it is formed by bonding four photolithographic masks (including a first exposure to the first region, a second exposure to the second region, a third exposure to the third region, and a fourth exposure to the fourth region) into a complete pattern. Other details will not be elaborated here.

[0098] In some embodiments, a first engagement region 301 extending in a second direction is provided between the first portion F1p and the second portion F2p; a second engagement region 302 extending in a first direction is provided between the first portion F1p and the third portion F3p; a third engagement region 303 extending in a second direction is provided between the third portion F3p and the fourth portion F4p; and a fourth engagement region 304 extending in a first direction is provided between the second portion F2p and the fourth portion F4p.

[0099] refer to Figure 5 and Figure 12 In some embodiments, the substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; a fourth overlapping region exists between the third region and the fourth region; a fifth overlapping region exists between the second region and the third region; both the first and third overlapping regions include a first common region; both the second and fourth overlapping regions include a second common region; the fifth overlapping region includes both the first and second common regions; the semiconductor test structure further includes a second test structure; the second test structure is identical to the first test structure; the first test structure is located in the first common region; the second test structure is located in the second common region.

[0100] In this embodiment, the division of the various regions of the substrate 102 can be referred to Figure 5 The division of the various regions shown is for understanding purposes only and will not be elaborated upon here. The first overlapping region in this embodiment can be understood as… Figure 5 At least a portion of the first public area P1-2-3 shown.

[0101] In this embodiment, details of the first test structure located in the first public area can be found in [reference]. Figure 12 To understand the details of forming the first test structure shown, it is necessary to... Figure 12 After removing / masking / setting the fourth region as shown, or after merging the fourth region with the third region, details of forming the first test structure by joining three photolithographic masks (including the first exposure of the first region, the second exposure of the second region, and the third exposure of the region after merging the third and fourth regions) into a complete layout can be obtained. Other details will not be elaborated here.

[0102] In this embodiment of the application, details regarding the formation of the second test structure located in the second public area can be found in [reference]. Figure 12 To understand the details of forming the first test structure shown, it is necessary to... Figure 12 The details shown illustrate how, after removing / masking / setting redundancy in the first region, or after merging the first exposure to the first region with the second exposure to the second region, the second test structure can be formed by joining three lithographic masks (including the second exposure to the merged region of the first and second regions, the third exposure to the third region, and the fourth exposure to the fourth region) into a complete layout. Other details are not elaborated here.

[0103] Figure 13 The semiconductor test structure provided in the embodiments of this application includes a schematic diagram of a plurality of first test structures.

[0104] refer to Figure 13 For example, the semiconductor test structure includes two first test structures, namely a first test structure TK1a and a first test structure TK1b; the first test structure TK1a can be used for either connectivity detection or disconnection detection, and the first test structure TK1b can be used for the other of connectivity detection and disconnection detection.

[0105] The semiconductor test structure provided in the second aspect of this application is similar to the semiconductor test structure obtained by the manufacturing method provided in the first aspect of this application. For technical features not disclosed in detail in the second aspect of this application, please refer to the first aspect of the above-mentioned embodiments for understanding, and will not be repeated here.

[0106] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0107] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A method for manufacturing a semiconductor test structure, characterized in that, include: Provide substrate; The substrate includes a first region and a second region; There is a first overlapping area between the first region and the second region; A first test structure is formed on the substrate in the first overlapping region; the first test structure includes a first conductive line, a second conductive line, and a first conductive channel connecting the first conductive line and the second conductive line. The first conductive line and the second conductive line are formed by photomask bonding and include a first portion and a second portion that partially overlaps with the first portion; The first test structure is subjected to connectivity detection and / or disconnection detection to obtain the detection results; the detection results indicate that the overlay deviation and the joining deviation are within the preset deviation range.

2. The manufacturing method according to claim 1, characterized in that, The formation of the first test structure located in the first overlapping region includes: On the substrate, the first conductive line, the first conductive channel, and the second conductive line are formed sequentially; Forming the first conductive line, or forming the second conductive line, includes: The first portion is formed using a photolithographic mask of the first region, and the second portion is formed using a photolithographic mask of the second region; wherein the first portion and the second portion have an extending and connected first bonding region and a second bonding region; the second bonding region extends along a first direction; the first bonding region extends along a second direction; the first direction and the second direction intersect.

3. The manufacturing method according to claim 2, characterized in that, The first portion formed using the photolithographic mask of the first region and the second portion formed using the photolithographic mask of the second region include: A first material layer and a photoresist layer located on the first material layer are formed on the substrate; The photoresist layer in the first region is subjected to a first exposure, and a first pattern corresponding to the first part is formed in the photoresist layer in the first overlapping region; A second exposure is performed on the photoresist layer of the second region to form a second pattern corresponding to the second part in the photoresist layer of the first overlapping region where the first pattern is formed, thereby obtaining a photoresist pattern layer located on the first material layer. By removing a portion of the first material layer from the photoresist pattern layer, a first structural layer is obtained on the substrate; the first structural layer includes the first conductive line.

4. The manufacturing method according to claim 1, characterized in that, The substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; a fourth overlapping region exists between the third region and the fourth region; the first overlapping region, the second overlapping region, the third overlapping region, and the fourth overlapping region all include a common region; The formation of the first test structure located in the first overlapping region includes: The first test structure is formed on the substrate in the common area.

5. The manufacturing method according to claim 4, characterized in that, The formation of the first test structure located in the public area includes: On the substrate, the first conductive line, the first conductive channel, and the second conductive line are formed sequentially; Forming the first conductive line, or forming the second conductive line, includes: The image contains a first portion formed using a photolithographic mask of the first region, a second portion formed using a photolithographic mask of the second region, a third portion formed using a photolithographic mask of the third region, and a fourth portion formed using a photolithographic mask of the fourth region; wherein the first portion and the second portion have a first bonding region; the first portion and the third portion have a second bonding region; the third portion and the fourth portion have a third bonding region; the second portion and the fourth portion have a fourth bonding region; the second bonding region and the fourth bonding region extend along a first direction; the first bonding region and the third bonding region extend along a second direction; and the first direction and the second direction intersect.

6. The manufacturing method according to claim 1, characterized in that, The substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; a fourth overlapping region exists between the third region and the fourth region; a fifth overlapping region exists between the second region and the third region; the first overlapping region and the third overlapping region each include a first common region; the second overlapping region and the fourth overlapping region each include a second common region; the fifth overlapping region includes the first common region and the second common region; The formation of the first test structure located in the first overlapping region includes: The first test structure located in the first common region is formed on the substrate; The manufacturing method further includes: A second test structure is formed on the substrate, located in the second common region; the second test structure is identical to the first test structure. The obtained detection results include: The first test structure is subjected to connectivity and / or disconnection detection, and the second test structure is subjected to connectivity and / or disconnection detection to obtain the detection results.

7. A semiconductor testing structure, characterized in that, include: Substrate; the substrate includes a first region and a second region; a first overlapping region exists between the first region and the second region; A first test structure is located on the substrate and includes a first conductive line, a second conductive line, and a first conductive channel connecting the first conductive line and the second conductive line. The first conductive line and the second conductive line are formed by photomask bonding and include a first part and a second part that partially overlaps with the first part; wherein, the detection results of the connectivity detection and / or disconnection detection of the first test structure are characterized by overlay deviation and bonding deviation being within a preset deviation range.

8. The semiconductor test structure according to claim 7, characterized in that, The first conductive wire and the second conductive wire include one or more helical wires; the helical wire includes a first end located in the middle of the helical wire and a second end located at the edge of the helical wire; The first conductive channel includes one or more conductive vias; the conductive vias connect the first end of the first conductive wire and the first end of the second conductive wire, or connect the second end of the first conductive wire and the second end of the second conductive wire.

9. The semiconductor test structure according to claim 8, characterized in that, The spiral wire includes a square spiral; the square spiral includes a plurality of straight extensions located between the first end and the second end and connected in sequence; the plurality of straight extensions extend alternately along a first direction and a second direction; the first direction intersects the second direction.

10. The semiconductor test structure according to claim 7, characterized in that, The first portion and the second portion have an extending and connected first joint region and a second joint region; the second joint region extends along a first direction; the first joint region extends along a second direction; the first direction and the second direction intersect. The absolute value of the difference between the first characteristic dimension of the first conductive line in the first bonding region and / or the second characteristic dimension of the first conductive line in the second bonding region and the third characteristic dimension of the first conductive line in other regions is within a preset value range; the other regions are regions other than the first bonding region and the second bonding region.

11. The semiconductor test structure according to claim 10, characterized in that, The feature size of the first bonding region and / or the feature size of the second bonding region ranges from 0.25 micrometers to 0.9 micrometers; the minimum size of the first test structure along the first direction and / or the minimum size along the second direction is greater than or equal to 60 micrometers.

12. The semiconductor test structure according to claim 7, characterized in that, The substrate further includes a third region and a fourth region; a second overlapping region exists between the second region and the fourth region; a third overlapping region exists between the first region and the third region; and a fourth overlapping region exists between the third region and the fourth region. The first overlapping region, the second overlapping region, the third overlapping region, and the fourth overlapping region all include a common region; the first test structure is located in the common region. or, There is a fifth overlapping region between the second region and the third region; the first overlapping region and the third overlapping region both include a first common region; the second overlapping region and the fourth overlapping region both include a second common region; the fifth overlapping region includes the first common region and the second common region; the semiconductor test structure further includes a second test structure; the second test structure is the same as the first test structure; the first test structure is located in the first common region; the second test structure is located in the second common region.

Images