A processing method for suppressing self-doping at the edge of a heavily arsenic-doped silicon substrate

Abstract

The application discloses a processing method for inhibiting edge self-doping of a heavily arsenic-doped silicon substrate, and comprises the following steps: firstly, cutting and sorting a single crystal silicon ingot, and turning over; performing asymmetric chamfer processing on the edge of the cut silicon wafer; performing grinding, etching, sand blasting and cleaning processing on the silicon wafer after the chamfer processing, and then performing first back sealing layer processing; performing annealing and cleaning treatment on the silicon wafer after the first back sealing layer processing; performing edge polishing and edge removal treatment on the silicon wafer after the annealing and cleaning; performing second back sealing film processing on the silicon wafer after the edge polishing and edge removal treatment; and performing polishing and cleaning on the surface of the silicon wafer after the second back sealing film processing. Through the synergistic design of three core technologies of an asymmetric chamfer structure, double back sealing (LTO+Poly-Si) and edge polishing and edge removal, a comprehensive solution from physical isolation, chemical blocking to active adsorption is constructed, and the edge self-doping problem of the heavily arsenic-doped substrate is systematically solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor single-crystal silicon wafer substrate manufacturing, and more specifically, the present invention relates to a method for preparing heavily arsenic-doped silicon substrates to suppress epitaxial self-doping. Background Technology

[0002] Heavy arsenic-doped silicon substrates are widely used in power semiconductor devices due to their extremely low resistivity. However, during epitaxial growth, the high-temperature environment causes arsenic in the substrate to easily volatilize from the back and edge regions and diffuse into the epitaxial layer through the gas phase, resulting in a "self-doping" phenomenon. This leads to uneven resistivity distribution in the epitaxial layer, degraded device performance, and yield loss.

[0003] In existing technologies, although attempts have been made to deposit a silicon oxide layer on the back side of the substrate as an impurity barrier layer, the silicon oxide films deposited by conventional methods have poor density and limited barrier effect. In particular, the substrate edge region, due to its complex structure and large exposed area, becomes the main channel for arsenic volatilization, and traditional symmetrical chamfer designs cannot effectively suppress this phenomenon. Therefore, there is an urgent need for an innovative solution that can effectively suppress self-doping at the edges of heavily arsenic-doped silicon substrates. Summary of the Invention

[0004] To address the aforementioned problems, this application proposes a comprehensive processing method.

[0005] A processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates includes the following steps: S1: Cutting, sorting, and flipping monocrystalline silicon ingots; S2: Perform asymmetrical chamfering on the edges of the cut silicon wafers; S3: After chamfering, the silicon wafer is ground, etched, sandblasted, and cleaned, and then the first back seal layer is processed. S4: Anneal and clean the silicon wafer after the first back seal layer processing is completed; S5: Perform edge polishing and trimming on the annealed and cleaned silicon wafers; S6: Process the second back sealing film on the silicon wafer after edge polishing and edge removal; S7: Polish and clean the surface of the silicon wafer after the second back seal film has been processed.

[0006] Furthermore, the diameter of the single-crystal silicon ingot and substrate is 125mm to 200mm, the dopant is arsenic, and the resistivity is 0.002Ω·cm to 0.003Ω·cm. This range of extremely low resistivity can meet the requirements of high-performance power devices for low on-resistance, but it also brings the challenge that high-concentration arsenic dopant is easily volatilized at high temperatures. This method provides an effective solution to this specific technical problem.

[0007] Furthermore, the cutting in step S1 is diamond wire cutting with a wire diameter of 70 μm and a cutting wire tension of 12.5–15 N. The flipping involves rearranging the cut wafers by measuring their curvature to ensure that the bending radius (BOW) is within the range of 0–10 μm. By controlling the wire diameter (>60 μm), the warpage of the silicon wafer can be effectively reduced. At the same time, flipping ensures that the curvature of each LOT silicon wafer is the same. By ensuring that BOW>0, the silicon wafer is ensured to be "convex", which ensures the adhesion between the substrate and the stage during epitaxy and effectively suppresses self-doping.

[0008] Furthermore, in step S2, the asymmetric chamfer has a front chamfer width X1 of 260–300 μm and a back chamfer width X2 of 100–130 μm; the chamfer shape is R-shaped, with the angle θ1 between the X1 surface and the front plane of the substrate being 10–12°, and the angle θ2 between the X2 surface and the back plane of the substrate being 10–12°. This unique asymmetric design significantly reduces the physical gap between the back side of the substrate and the epitaxial process stage, effectively limiting the channel for arsenic vapor to escape from the back edge, and fundamentally suppressing the occurrence of self-doping from the physical structure.

[0009] Furthermore, in step S3, grinding involves grinding the chamfered silicon wafer on both sides for 60µm to eliminate cutting damage; etching is performed using a mixed solution of nitric acid and hydrofluoric acid for isotropic etching (removal amount of 20µm on both sides) to remove the damaged layer; back-side sandblasting is performed using air pressure to drive slurry; and cleaning is performed using deionized water ultrasonic cleaning. In step S3, the first back sealing layer is a SiO2 film grown by APCVD process with a thickness of 500±50nm. This SiO2 layer serves as the first back sealing barrier, which can initially cover and protect the back side of the substrate, providing a foundation for subsequent high-temperature densification processing.

[0010] Furthermore, the annealing temperature in step S4 is 500°C, the annealing time is 30 min to 90 min, and the cleaning is RCA cleaning process. Through this high-temperature annealing treatment under specific conditions, the relatively loose SiO2 film grown by APCVD can be densified, significantly improving its density and chemical stability, thereby enhancing its ability to block the diffusion of arsenic atoms.

[0011] Furthermore, in step S5, edge polishing is performed to remove edge areas that may be contaminated or rich in arsenic in the front X1 surface area. This step can accurately remove edge areas that may have been contaminated or rich in arsenic in previous processing, while eliminating sharp nucleation sites. This helps to form a clear and flat transition zone at the edge of the epitaxial layer, further avoiding abnormal epitaxial growth and self-doping caused by edge defects.

[0012] Furthermore, in step S6, the second back sealing layer is polycrystalline silicon (Poly-Si), which is grown by LPCVD process. A polycrystalline silicon (Poly-Si) film with a thickness of 800±100nm is deposited on the first SiO2 film. The deposited polycrystalline silicon layer serves as the second back sealing barrier, which can not only further physically block the volatilization of arsenic, but its polycrystalline particle interface also has an excellent "gettering" effect, which can actively adsorb and fix arsenic impurities that may penetrate the first silicon oxide layer, thus achieving dual protection of "blocking" and "adsorption".

[0013] Furthermore, the polishing described in step S7 is chemical mechanical polishing; the cleaning is performed using ultrapure water.

[0014] Furthermore, a heavily arsenic-doped silicon substrate, the substrate having asymmetric chamfered edges and a double-layer back-sealing structure, is suitable for semiconductor epitaxial processes: Beneficial effects

[0015] This invention constructs a comprehensive solution from physical isolation and chemical barrier to active adsorption through the synergistic design of three core technologies: "asymmetric chamfer structure", "double-layer back seal (LTO+Poly-Si)" and "edge polishing and removal". It systematically solves the problem of edge self-doping of heavily arsenic-doped substrates. When applied, this invention significantly reduces the self-doping concentration of the epitaxial layer, resulting in a smoother resistivity distribution. This effectively improves key performance parameters of power devices, such as breakdown voltage and frequency characteristics. The entire process is highly compatible with existing mature semiconductor manufacturing equipment and material systems, eliminating the need for expensive or special devices. This facilitates rapid deployment in large-scale production and has extremely high industrialization value and economic benefits. Attached Figure Description

[0016] The invention will now be further described with reference to the accompanying drawings; Figure 1 This is a schematic diagram of a chamfered edge structure in the prior art; Figure 2 This is a schematic diagram of the chamfered edge structure of the present invention; Figure 3 This is a schematic diagram of the substrate back seal structure of the present invention; Figure 4 This is a schematic diagram showing the bending direction of the silicon wafer before and after the flipping process of the present invention; Figure 5 The actual measured chamfered edge contour in Embodiment 1 of the present invention Figure 1 ; Figure 6 The actual measured chamfered edge contour in Embodiment 1 of the present invention Figure 2 ; Figure 7 This is a comparison diagram of the resistance distribution between Embodiment 1 and the comparative example of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of this application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0019] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0020] Example 1 Reference Figure 1 - Figure 5 This embodiment provides a method for processing a 150mm heavily doped arsenic silicon substrate.

[0021] Substrate preparation: Select heavily arsenic-doped single-crystal silicon ingots with a diameter of 150.5±0.2mm, a length of 200mm, and a resistivity of 0.002~0.003Ω·cm; process them into silicon wafers with a thickness of 725um using a wire cutting machine with a diamond wire diameter of 70um and a wire tension of 12.5N; after cutting, perform bending over (BOW) testing on the silicon wafers, and flip the silicon wafers with BOW<0um according to the test results. After processing, the BOW of all silicon wafers is within the range of 0~10um.

[0022] Asymmetric chamfering: The edges of the silicon wafer are precisely ground using a diamond grinding wheel to form an R-shaped asymmetric chamfer. Specific parameters are as follows: the chamfer width X1 on the front side is 262.9 μm, the chamfer width X2 on the back side is 123.3 μm, the angle θ1 between the X1 face and the front plane of the substrate is 11.171°, and the angle θ2 between the X2 face and the back plane of the substrate is 10.053°.

[0023] Surface pretreatment and first back seal: The chamfered silicon wafer is ground on both sides (removal amount on both sides) to 60µm to eliminate cutting damage. Then, isotropic etching (removal amount on both sides 20µm) is performed using a mixed solution of nitric acid and hydrofluoric acid to remove the damaged layer. After ultrasonic cleaning with deionized water and drying, atmospheric pressure chemical vapor deposition (APCVD) is used at 410℃, with silane (SiH4) and oxygen (O2) introduced to deposit a silicon dioxide (SiO2) layer with a thickness of 500nm on the back of the silicon wafer.

[0024] Annealing and densification: The silicon wafer with the deposited SiO2 layer is annealed at 500°C for 60 minutes in a nitrogen atmosphere. Subsequently, the silicon wafer is cleaned using a standard RCA cleaning process to ensure that the back seal layer is not affected. Specifically, RCA cleaning uses a combination of two chemical solutions (SC-1 and SC-2) with deionized water rinsing to achieve efficient removal of organic contaminants, metallic impurities, and oxide layers from the silicon wafer surface.

[0025] Chemical edge removal: The SiO2 film on the beveled edge of the X1 side of the silicon wafer, which may be contaminated or rich in arsenic, is removed using the chemical edge removal (HF) method.

[0026] Edge polishing: The edge polishing of the substrate after chemical de-edge removal is performed using an edge polishing machine, followed by cleaning.

[0027] The second back seal: Low-pressure chemical vapor deposition (LPCVD) is used to grow a 700nm thick polycrystalline silicon (Poly-Si) film on the back of the silicon wafer by introducing pure silane (SiH4) at 620℃.

[0028] Final polishing: Finally, chemical mechanical polishing (CMP) is performed on the front side of the silicon wafer to remove about 15um of silicon layer, obtaining a mirror surface with a surface roughness Ra<0.2nm. After cleaning with ultrapure water and drying with nitrogen, the finished substrate is obtained.

[0029] Example 2 This embodiment provides a method for processing a 200mm heavily doped arsenic silicon substrate.

[0030] Substrate preparation: Select a heavily arsenic-doped single crystal silicon ingot with a diameter of 200.5±0.2mm, a length of 250mm, and a resistivity of 0.002~0.025Ω·cm; process it into silicon wafers with a thickness of 825um using a wire cutting machine with a diameter of 70um and a wire tension of 15N; after cutting, perform bending over (BOW) testing on the silicon wafers, and flip the silicon wafers with BOW<0um according to the test results. After processing, the BOW of all silicon wafers should fall within 0~10um.

[0031] Asymmetric chamfering: The edges of the silicon wafer are precision ground using a diamond grinding wheel to form an R-shaped asymmetric chamfer. Specific parameters are as follows: the chamfer width X1 on the front side is 283.2 μm, the chamfer width X2 on the back side is 115.4 μm, the angle θ1 between the X1 face and the front plane of the substrate is 10.073°, and the angle θ2 between the X2 face and the back plane of the substrate is 10.569°.

[0032] Surface pretreatment and first back seal: After chamfering, the silicon wafer is ground on both sides (removal amount on both sides) to 60µm to eliminate cutting damage. Then, isotropic etching (removal amount on both sides 20µm) is performed using a mixed solution of nitric acid and hydrofluoric acid to remove the damaged layer. After ultrasonic cleaning with deionized water and drying, atmospheric pressure chemical vapor deposition (APCVD) is used at 410℃, with silane (SiH4) and oxygen (O2) introduced to deposit a silicon dioxide (SiO2) layer with a thickness of 550nm on the back of the silicon wafer.

[0033] Annealing densification: The silicon wafer with the deposited SiO2 layer is annealed in a nitrogen atmosphere at 500°C for 60 minutes. Subsequently, the silicon wafer is cleaned using a standard RCA cleaning process to ensure that the back seal layer is not affected.

[0034] Chemical edge removal: The SiO2 film on the beveled edge of the X1 side of the silicon wafer, which may be contaminated or rich in arsenic, is removed using the chemical edge removal (HF) method.

[0035] Edge polishing: The edge polishing of the substrate after chemical de-edge removal is performed using an edge polishing machine, followed by cleaning.

[0036] The second back seal: Low-pressure chemical vapor deposition (LPCVD) is used to grow a 900nm thick polycrystalline silicon (Poly-Si) film on the back of the silicon wafer by introducing pure silane (SiH4) at 620℃.

[0037] Final polishing: Finally, chemical mechanical polishing (CMP) is performed on the front side of the silicon wafer to remove about 15um of silicon layer, obtaining a mirror surface with a surface roughness Ra<0.2nm. After cleaning with ultrapure water and drying with nitrogen, the finished substrate is obtained.

[0038] Example 3 This embodiment provides a method for processing a 125mm heavily doped arsenic silicon substrate.

[0039] Substrate preparation: Select a heavily arsenic-doped single crystal silicon ingot with a diameter of 125±0.2mm, a length of 250mm, and a resistivity of 0.002~0.003Ω·cm; process it into silicon wafers with a thickness of 450um using a wire cutting machine with a diamond wire diameter of 70um and a wire tension of 12.5N; after cutting, perform bending over (BOW) testing on the silicon wafers, and flip the silicon wafers with BOW<0um according to the test results. After processing, the BOW of all silicon wafers should fall within 0~10um.

[0040] Asymmetric chamfering: The edges of the silicon wafer are precisely ground using a diamond grinding wheel to form an R-shaped asymmetric chamfer. Specific parameters are as follows: the chamfer width X1 on the front side is 292.1 μm, the chamfer width X2 on the back side is 103.7 μm, the angle θ1 between the X1 face and the front plane of the substrate is 11.894°, and the angle θ2 between the X2 face and the back plane of the substrate is 11.756°.

[0041] Surface pretreatment and first back seal: The chamfered silicon wafer is ground on both sides (removal amount on both sides) to 60µm to eliminate cutting damage. Then, isotropic etching (removal amount on both sides 20µm) is performed using a mixed solution of nitric acid and hydrofluoric acid to remove the damaged layer. After ultrasonic cleaning with deionized water and drying, atmospheric pressure chemical vapor deposition (APCVD) is used at 410℃, introducing silane (SiH4) and oxygen (O2) to deposit a silicon dioxide (SiO2) layer with a thickness of 450nm on the back of the silicon wafer.

[0042] Annealing densification: The silicon wafer with the deposited SiO2 layer is annealed in a nitrogen atmosphere at 500°C for 60 minutes. Subsequently, the silicon wafer is cleaned using a standard RCA cleaning process to ensure that the back seal layer is not affected.

[0043] Chemical edge removal: The SiO2 film on the beveled edge of the X1 side of the silicon wafer, which may be contaminated or rich in arsenic, is removed using the chemical edge removal (HF) method.

[0044] Edge polishing: The edge polishing of the substrate after chemical de-edge removal is performed using an edge polishing machine, followed by cleaning.

[0045] The second back seal: Low-pressure chemical vapor deposition (LPCVD) is used to grow a polycrystalline silicon (Poly-Si) film with a thickness of 800 nm on the back of the silicon wafer by introducing pure silane (SiH4) at 620°C.

[0046] Final polishing: Finally, chemical mechanical polishing (CMP) is performed on the front side of the silicon wafer to remove approximately 15µm of silicon layer, resulting in a mirror-like surface. The wafer is then rinsed with ultrapure water and dried with nitrogen to obtain the finished substrate.

[0047] In addition, to verify the effectiveness of the present invention, conventional processes that do not involve the three core technologies of "asymmetric chamfer structure", "double-layer back seal (LTO+Poly-Si)" and "edge polishing and trimming" were selected as comparative examples.

[0048] Standard process: Step 2 uses symmetrical chamfering, Step 5 does not perform edge polishing, and Step 6 does not perform a second back seal.

[0049] The resistivity distribution from center to edge of the epitaxial wafer obtained by conventional process and the process of the embodiment clearly shows that the resistance change from center to edge is more gradual in the embodiment and the overall resistivity is higher, indicating that the dopant introduced through self-doping extension is significantly reduced and the self-doping concentration is reduced.

[0050] Please see Figure 7 As shown, resistance tests were performed on the epitaxial wafer produced in the example. The resistivity of the test data center and a location 10 mm from the edge were compared, as shown in the table below: Table 1

[0051] from Figure 6 As shown in Table 1, the self-doping behavior of substrates of different sizes during the processing was verified. For substrates subjected to "asymmetric chamfering structure," "double-layer back sealing (LTO+Poly-Si)," and "edge polishing and removal" techniques, the overall gradient change value was obtained by measuring the resistivity at 10mm from the substrate edge and the center. The resistivity uniformity was significantly improved, with the gradient change optimized from over 30% in the original process to less than 20% in this example. Therefore, the self-doping concentration was reduced, resulting in better quality.

[0052] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

[0053] The above formulas are all derived from software simulation using a large amount of data, and are selected to be close to the actual values. The coefficients in the formulas are set by those skilled in the art based on the actual situation. The above are only preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or changes made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates, characterized in that, Includes the following steps: S1: Cutting, sorting, and flipping monocrystalline silicon ingots; S2: Perform asymmetrical chamfering on the edges of the cut silicon wafers; S3: After chamfering, the silicon wafer is ground, etched, sandblasted, and cleaned, and then the first back seal layer is processed. S4: Anneal and clean the silicon wafer after the first back seal layer processing is completed; S5: Perform edge polishing and trimming on the annealed and cleaned silicon wafers; S6: Process the second back sealing film on the silicon wafer after edge polishing and edge removal; S7: Polish and clean the surface of the silicon wafer after the second back sealing film has been processed.

2. The processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates according to claim 1, characterized in that, The diameter of the single-crystal silicon ingot and substrate is 125mm to 200mm, the dopant is arsenic, and the resistivity is 0.002Ω·cm to 0.003Ω·cm.

3. The processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates according to claim 2, characterized in that, The cutting in step S1 is diamond wire cutting with a wire diameter of 70 μm and a cutting wire tension of 12.5–15 N. The sorting is to screen out silicon wafers with a bending degree greater than 0 after cutting. The flipping is to rearrange the cut wafers by flipping them over based on the measured bending degree of the cut wafers to ensure that the bending degree (BOW) ranges from 0 to 10 μm.

4. The processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates according to claim 3, characterized in that: In step S2, the asymmetric chamfer has a front chamfer width X1 of 260–300 μm and a back chamfer width X2 of 100–130 μm. The chamfer shape is R-shaped, with the angle θ1 between the X1 surface and the front plane of the substrate being 10–12° and the angle θ2 between the X2 surface and the back plane of the substrate being 10–12°.

5. The processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates according to claim 1, characterized in that: In step S3, grinding involves grinding the chamfered silicon wafer on both sides for 60µm to eliminate cutting damage; etching is performed using a mixed solution of nitric acid and hydrofluoric acid for isotropic etching (removal amount of 20µm on both sides) to remove the damaged layer; back-side sandblasting is performed using air pressure to drive slurry; and cleaning is performed using deionized water ultrasonic cleaning. In step S3, the first back seal layer is a SiO2 film, which is grown by APCVD process and has a thickness of 500±50um.

6. The processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates according to claim 5, characterized in that: The annealing temperature in step S4 is 500℃, and the cleaning process uses RCA cleaning.

7. The processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates according to claim 6, characterized in that: In step S5, edge polishing is used to remove edge areas that may be contaminated or rich in arsenic from the front X1 surface area.

8. The processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates according to claim 7, characterized in that: In step S6, the second back seal layer is polycrystalline silicon (Poly-Si), which is grown by LPCVD process, depositing a polycrystalline silicon (Poly-Si) film with a thickness of 800±100nm on the first SiO2 film.

9. The processing method for suppressing edge self-doping of heavily arsenic-doped silicon substrates according to claim 1, characterized in that: The polishing described in step S7 is chemical mechanical polishing; the cleaning is done with ultrapure water.

10. A heavily arsenic-doped silicon substrate prepared by the processing method for suppressing edge self-doping of a heavily arsenic-doped silicon substrate according to any one of claims 1-9, characterized in that: The substrate has asymmetrical chamfered edges and a double-layer back seal structure, making it suitable for semiconductor epitaxial processes.

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