Integrated package-in antenna structure

Abstract

The present disclosure relates to integrated in-package antenna structures. A semiconductor device includes a first substrate. An electrical component is disposed on the first substrate. A board-to-board connector is disposed on the first substrate. An encapsulant is deposited on the first substrate and the electrical component to form a sub-package. The board-to-board connector remains exposed from the encapsulant. A contact pad is formed on a side surface of the sub-package. Through the contact pad, the sub-package is mounted to an antenna.

Description

Technical Field

[0001] This invention generally relates to semiconductor devices, and more particularly to semiconductor devices and methods for fabricating and using integrated in-package antenna (AiP) structures. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are used in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices are increasingly employing more advanced wireless communication technologies and protocols. Newer 5G communication chips utilize dielectric resonator antennas (DRAs) and other advanced antenna types to communicate at higher 5G frequencies. These advanced antennas are typically attached to semiconductor packages using flexible substrates, which allow the antennas to be oriented at various angles relative to the package. However, the manufacturing process using flexible substrates is expensive and complex. Therefore, there is a need for integrated AiP (Antenna-in-Package) structures. Attached Figure Description

[0004] Figures 1a-1c The illustration shows a semiconductor wafer with multiple semiconductor dies separated by sawing streets; Figures 2a-2j The diagram illustrates the formation of an integrated AiP; Figures 3a-3c Illustrated alternative embodiments; Figure 4 The diagram illustrates other features; and Figure 5a and 5b The diagram shows an electronic device with AiP. Detailed Implementation

[0005] In the following description, the invention is described with reference to the accompanying drawings in one or more embodiments, wherein the same numerals represent the same or similar elements. Although the invention has been described in accordance with the best mode for carrying out the objectives of the invention, those skilled in the art will understand that alternatives, modifications, and equivalents may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents, as supported by the following disclosure and the accompanying drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices. The terms "semiconductor die" and "die" are used interchangeably.

[0006] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves the formation of multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components (such as transistors and diodes) have the ability to control the flow of current. Passive electrical components (such as capacitors, inductors, and resistors) create the voltage and current relationship required to perform the circuit's function.

[0007] Back-end manufacturing refers to the process of dicing or dicing finished wafers into individual semiconductor dies and packaging these dies for structural support, electrical interconnection, and environmental isolation. To dice a semiconductor die, the wafer is scribed and separated along non-functional areas (called scribe blocks or scribing). The wafer is diced using a laser cutting tool or saw blade. After dicing, the individual semiconductor die is mounted onto a package substrate, which includes pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor die are then connected to contact pads within the package. Electrical connections can be achieved using conductive layers, bumps, stud bumps, conductive paste, or wire bonding. Encapsulating agents or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, and the functionality of the semiconductor device makes it usable with other system components.

[0008] Figure 1a A semiconductor wafer 100 is shown, having a bottom substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other substrate materials for structural support. Multiple semiconductor dies or components 104 are formed on the wafer 100 and separated by non-active inter-die wafer regions or saw blocks 106. The saw blocks 106 provide dicing areas to individually slice the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0009] Figure 1bA cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or passive surface 108 and an active surface 110, the active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, or other signal processing circuitry. The semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0010] A conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition processes. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 serves as contact pads for circuitry electrically connected to the active surface 110.

[0011] Conductive bump material is deposited on conductive layer 112 using processes such as evaporation, electroplating, electroless plating, ball drop, or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed to form balls or bumps 114 by heating it above its melting point. In one embodiment, the bumps 114 are formed on under-bump metallization (UBM), which has a wetting layer, a barrier layer, and an adhesive layer. The bumps 114 can also be compression bonded or thermocompressed bonded to conductive layer 112. The bumps 114 represent one type of interconnect structure that can be formed on conductive layer 112. Interconnect structures can also use bonding wires, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0012] exist Figure 1c In this process, the semiconductor wafer 100 is individually diced into individual semiconductor dies 104 by sawing blocks 106 using a saw blade or laser cutting tool 118. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies or cells (KGD / KGU) after dicing.

[0013] Figures 2a-2j The diagram illustrates the process of forming the integrated in-package antenna (AiP) 150. Figure 2a This is a partial cross-sectional view of substrate 152. Although only a single substrate 152 is shown, hundreds or thousands of substrates are typically processed on a common carrier using the same steps described herein for a single unit but performed globally. Substrate 152 can also be started as a single large substrate for multiple units that are individually cut relative to each other during or after the manufacturing process.

[0014] The substrate 152 includes one or more insulating layers 154 interleaved with one or more conductive layers 156. In one embodiment, the insulating layer 154 is a core insulating plate, wherein the conductive layers 156 are patterned on a top and bottom surface (e.g., a copper-clad laminate substrate). The conductive layers 156 also include conductive vias electrically coupled through the insulating layers 154. The substrate 152 can include any number of conductive and insulating layers interleaved with each other. A solder mask or passivation layer can be formed on either side of the substrate 152. In other embodiments, any suitable type of substrate or leadframe is used for the substrate 152.

[0015] Forming an AiP 150 begins by mounting a semiconductor die 104, discrete components 160, a board-to-board (B2B) connector 162, other discrete active or passive components, additional semiconductor dies, and any other desired components onto a substrate 152. Any number, type, and combination of semiconductor dies and other electrical components can be used to fabricate the AiP 150. In one embodiment, the semiconductor die 104 is a 5G transceiver, and the discrete components 160 form a radio frequency (RF) filter.

[0016] Solder paste is used to couple discrete component 160 and B2B connector 162 to conductive layer 156 both electrically and mechanically. Any combination of discrete active and passive components can be mounted as needed to, for example, implement radio frequency (RF) filters. B2B connector 162 is used to attach another PCB, ribbon cable, or another electrical system to AiP 150 to allow other packages to communicate with and use the functionality of semiconductor die 104. Semiconductor die 104 is connected to B2B connector 162 and discrete component 160 via conductive layer 156.

[0017] exist Figure 2b In this process, an encapsulating agent or molding compound 176 is deposited on a substrate 152, covering the top and side surfaces of the semiconductor die 104 and the discrete component 160. The encapsulating agent 176 also extends below the semiconductor die 104 and the discrete component 160 between the component and the substrate 152. In other embodiments, a separate molding underfill (MUF) is alternatively used.

[0018] Encapsulant 176 is an electrically insulating material deposited using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable coating processes. Encapsulant 176 can be a polymer composite material, such as epoxy resin, epoxy acrylate resin, or a polymer with or without fillers. Encapsulant 176 is non-conductive and, environmentally, protects semiconductor devices from external elements and contaminants.

[0019] The B2B connector 162 is held outside the encapsulant 176 by using a cap or mask that can be removed after encapsulation, or by using a mold that protects the B2B connector in a non-molding chamber. The encapsulant 176 is typically deposited, with the substrate 152 held as a larger panel, where multiple AiPs 150 are formed simultaneously. After manufacturing is complete, the substrate 152 and the larger panel of encapsulant 176 are then single-cut.

[0020] exist Figure 2c In this process, conductive material is optionally sputtered onto the AiP 150 to form a conductive shielding layer 180. The shielding layer 180 is formed using any suitable metal deposition technique (e.g., PVD, CVD, other sputtering methods, spraying, or plating). The sputtered material can be copper, steel, aluminum, gold, combinations thereof, or any other suitable conductive material. In some embodiments, the shielding layer 180 can be fabricated by sputtering on multiple layers of different materials (e.g., stainless steel-copper-stainless steel or titanium-copper).

[0021] The shielding layer 180 reduces EMI between components of the AiP 150 and other nearby electronic devices. The shielding layer 180 may optionally be connected to a ground voltage node via the conductive layer 156 to further improve EMI reduction. The shielding layer 180 can be connected to the conductive layer 156 by sputtering the shielding layer onto the exposed side surface of the substrate 152 where the conductive layer is exposed, or onto the contact pads of the conductive layer 156 on the top surface of the substrate 152. The B2B connector 162 remains outside the shielding layer 180 by sputtering the shielding layer while the B2B connector is protected by a cap or can. The shielding layer 180 is formed directly on and covers the top and side surfaces of the encapsulant 176.

[0022] Figure 2d Showing perpendicular to Figure 2c The diagram illustrates how contact pads 182 are formed on the side surface of substrate 152. Contact pads 182 are formed as conductive vias through insulating layer 154, or as a series of stacked conductive vias and conductive layers. A single cut through substrate 152 using, for example, a laser cutting tool as shown, exposes the contact pads 182 on the side surface of the substrate.

[0023] Figure 2e Showing from and Figure 2c The diagram shows an external view of the completed subpackage 181 obtained from the same angle as the cross-section, illustrating contact pads 182 formed on the side surface 184 of the substrate 152. The subpackage 181 includes the substrate 152, an encapsulated semiconductor die 104, any other desired electrical components, and a B2B connector 162.

[0024] In one embodiment, the contact pad 182 is formed as part of the conductive layer 156, for example, as one or more conductive vias and conductive layers exposed as part of a process of slicing the substrate 152. In another embodiment, the contact pad 182 is formed directly on the exposed portion of the conductive layer 156 as part of a shielding layer 180, and then chemically or laser-etched to separate the contact pad from the shielding layer. In a third embodiment, the contact pad 182 is formed separately from the conductive layer 156 and the shielding layer 180 in a separate process. Figure 2f The image shows a top-down view of the AiP 150. Contact pads on edge 184 allow the subpackage 181 to be mounted to another substrate that is vertically oriented, i.e., standing upright on edge 184.

[0025] Figure 2g The panel or sheet of antenna 200 is shown. In one embodiment, antenna 200 is a dielectric resonator antenna (DRA). DRAs are radio antennas commonly used at microwave frequencies and higher frequencies, comprising blocks of ceramic material (dielectric resonators) of various shapes mounted on a metal surface serving as a ground plane. Radio waves are introduced from transmitter circuitry into the interior of the resonator material and bounce back and forth between the resonator walls, forming standing waves. The walls of the resonator are partially transparent to radio waves, allowing radio power to radiate into space. In other embodiments, any other suitable type of antenna is used for antenna 200.

[0026] Antenna 200 is formed or mounted on substrate 202 having a structure similar to substrate 152, wherein one or more conductive layers 206 are interleaved between insulating layers 204. Any suitable type of substrate can be used for substrate 202, including those described above with respect to substrate 152. In one embodiment, a ground plane for the antenna is formed in substrate 202. Figure 2h In a manner similar to that described above where bump 114 is formed on semiconductor die 104, bump 210 is formed on substrate 202 opposite to antenna 200. In other embodiments, other types of interconnect structures are used.

[0027] exist Figure 2iIn this embodiment, the construction of AiP 150 continues by mounting subpackage 181 onto substrate 202 of antenna 200. Subpackage 181 is mounted such that substrate 152 is oriented perpendicular to substrate 202. In other embodiments, this angle can be non-perpendicular. Bumps 210 flow between conductive layer 206 of substrate 202 and contact pads 182 on surface 184 to electrically and mechanically connect substrate 152 to substrate 202. In other embodiments, other types of interconnect structures are used. Semiconductor die 104 is electrically coupled to antenna 200 via substrates 152 and 202. Figure 2j Using a laser cutting tool 212, a saw blade, or another suitable mechanism, the AiP 150 is cut through the substrate 202 and the antenna 200, and is individually cut relative to each other to complete the integrated AiP structure.

[0028] The substrate 152 is oriented perpendicular to the substrate 202, allowing the motherboard to be easily connected to the B2B connector 162 via a corresponding B2B connector directly mounted on the motherboard, while the antenna 200 remains oriented perpendicular to the motherboard. The AiP 150 is an integrated 5G in-package antenna structure that can be easily integrated into any mobile device design, connected to the mobile device's motherboard via the B2B connector 162, and provides a vertically oriented antenna for advanced 5G communication protocols as needed. Compared to existing technologies, directly and vertically mounting the substrate 152 with the semiconductor die 104 to the substrate 202 of the antenna 200 eliminates the need for a flexible substrate to orient the two parts perpendicular to each other, significantly reducing the cost and complexity of manufacturing the AiP 150.

[0029] Figures 3a-3c The diagram illustrates the formation of AiP 220, in which a metal rod 222 is used to form a side contactor to form contact pads on the side subpackage 224 instead of embedding conductive material within the substrate as in subpackage 181. Figure 3a Two AiP 220 units are shown formed back-to-back, sharing a metal rod 222 between the two units. The metal rod 222 extends across the sawn block between the units, such that after a single cut through the metal rod, a portion of the metal rod remains exposed on the side surface of the encapsulant 176 of each unit, as shown. Figure 3b As shown in the image.

[0030] Metal rod 222 is placed directly on conductive layer 156 to provide electrical connection to semiconductor die 104. Metal rod 222 may optionally be soldered to substrate 152 or attached using conductive adhesive. Shielding layer 180 may optionally be used in conjunction with metal rod 222.

[0031] Figure 3cThe AiP 220 is illustrated by attaching the subpackage 224 to the substrate 202 via metal rods 222 and solder bumps 210. The metal rods 222 serve as contact pads exposed on the side surfaces of the subpackage 224. However, the metal rods 222 are positioned on the substrate 152, rather than being embedded within or formed on the side surfaces of the substrate 152 as in the subpackage 181. In other embodiments, the contact pads on the side surfaces of the submodule extend vertically across both the substrate 152 and the encapsulant 176, rather than being contained within only one or the other.

[0032] Figure 4 AiP 230 is shown with additional features that can be used independently with any of the above embodiments. Adhesive or epoxy beads or bumps 232 are disposed between sub-package 234 and substrate 202. Epoxy resin 232 is dispensed onto substrate 202 along with bumps 210, or onto sub-package 234. In some embodiments, epoxy resin 232 may physically contact bumps 210 and even completely surround bumps 210.

[0033] Compared to solder bumps 210 that are all oriented along a single line, epoxy resin 232 stabilizes the physical connection between subpackage 234 and antenna 200 by providing physical contact points along an additional axis. Epoxy resin 232 can be added to any of the above embodiments to improve stability. In embodiments where metal rod 222 is embedded in encapsulant 176 instead of contacting pad 182 formed on the side surface of substrate 152, epoxy resin 232 is placed between substrate 152 and substrate 202, rather than as... Figure 4 The epoxy resin 232 is shown placed between the encapsulant 176 and the substrate 202. Epoxy resin 232 can be used in any of the above embodiments with or without the shielding layer 180.

[0034] Figure 4 The diagram also shows that the B2B connector 162 is positioned on the side of the substrate 152 opposite to the semiconductor die 104 and other electrical components. In other embodiments, the electrical components are mounted on both sides of the substrate 152. With or without epoxy resin 232, and with or without shielding layer 180, the B2B connector 162 on the bottom of the substrate 152 can be used with contact pads 182 or metal rods 222.

[0035] Figure 5a and 5b The illustration shows the integration of the aforementioned semiconductor package (e.g., AiP 230) into a larger electronic device 400. Figure 5aThe illustration shows a partial cross-section of an AiP 230 mounted on a printed circuit board (PCB) or other substrate 402 as part of an electronic device 400. In one embodiment, the electronic device 400 is a mobile phone, and the PCB 402 is the phone's motherboard. The AiP 230 is mounted by connecting a B2B connector 162 on PCB 152 to a corresponding B2B connector 406 on PCB 402. In some embodiments, the AiP 230 is sufficiently secured by the snap-fitting of B2B connectors 162 and 406. In other embodiments, an adhesive or other support mechanism is placed between the substrate 152 and the PCB 402. When the semiconductor die 104 and encapsulant 176 are placed on the bottom of the substrate 152, the encapsulant can physically contact the PCB 402 to physically support the AiP 230 on the PCB. The semiconductor die 104 is electrically coupled to the PCB 402 via the substrate 152 and the B2B connectors 162 and 406.

[0036] Figure 5b The illustration shows an electronic device 400, which includes a PCB 402 in which multiple semiconductor packages, including an AiP 230, are mounted on the surface of the PCB. Depending on the application, the electronic device 400 may have one or more types of semiconductor packages. The electronic device 400 may be a standalone system that uses semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device 400 may be a sub-component of a larger system. For example, the electronic device 400 may be part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. The electronic device 400 may also be a graphics card, a network interface card, or another signal processing card inserted into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor dies or electrical components.

[0037] exist Figure 5b In this PCB 402, a general substrate is provided for the structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 404 are formed on the surface of PCB 402 or within layers of PCB 402 using evaporation, electroplating, chemical plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between the semiconductor package, mounted components, and other external systems or components. Traces 404 also provide power and ground connections for the semiconductor package as needed.

[0038] In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to a PCB 402. In other embodiments, the semiconductor device may have only a first-level package, wherein the die is directly mounted to the PCB 402 mechanically and electrically.

[0039] For illustrative purposes, several types of first-level packages (including wire bond package 408 and flip chip 409) are shown on PCB 402. Additionally, several types of second-level packages (including ball grid array (BGA) 410, bump chip carrier (BCC) 407, grid array (LGA) 416, multi-chip module (MCM) 418, rectangular planar leadless package (QFN) 420, rectangular planar package 422, and embedded die-level ball grid array (eWLB) 426) are shown mounted on PCB 402 together with AiP 230. Conductive traces 404 electrically couple the various packages and components mounted on PCB 402 to AiP 230, thereby enabling the components within AiP 230 to be used for other components on the PCB.

[0040] Depending on system requirements, any combination of semiconductor packages configured with any combination of first and second level packaging styles, along with other electronic components, can be connected to PCB 402. In some embodiments, electronic device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers are able to incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs for consumers.

[0041] Although one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will understand that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: A first substrate is provided, the first substrate including a board-to-board connector mounted to the first substrate; A second substrate is provided, on which an antenna is formed; as well as The second substrate is mounted to the first substrate by solder bumps disposed between the edge of the second substrate and the surface of the second substrate.

2. The method according to claim 1, further comprising: An adhesive is disposed between the first substrate and the second substrate.

3. The method of claim 1, wherein the first substrate is oriented perpendicular to the second substrate.

4. The method according to claim 1, further comprising: A mobile device, including a motherboard, wherein the first substrate is connected to the motherboard via the board-to-board connector.

5. The method according to claim 1, further comprising: Contact pads are formed on the edge of the first substrate, wherein the second substrate is connected to the first substrate via the contact pads.

6. The method of claim 1, further comprising an electrical component disposed on a first substrate opposite to the board-to-board connector.

7. A method for manufacturing a semiconductor device, comprising: A first substrate is provided, the first substrate including a board-to-board connector mounted to the first substrate; Mount the antenna substrate onto the first substrate; as well as Solder bumps are provided between the first substrate and the antenna substrate.

8. The method of claim 7, further comprising: An adhesive is disposed between the first substrate and the antenna substrate.

9. The method of claim 7, wherein the first substrate is oriented perpendicular to the antenna substrate.

10. A semiconductor device, comprising: The first substrate includes a board-to-board connector mounted to the first substrate; as well as The antenna substrate is mounted on the first substrate.

11. The semiconductor device of claim 10, further comprising: An adhesive is disposed between the first substrate and the antenna substrate.

12. The semiconductor device of claim 10, wherein the first substrate is oriented perpendicular to the antenna substrate.

13. The semiconductor device of claim 10, further comprising: A mobile device, including a motherboard, wherein the first substrate is connected to the motherboard via the board-to-board connector.

14. The semiconductor device of claim 10, further comprising: Contact pads are formed on the side surface of the first substrate, wherein the antenna substrate is connected to the first substrate via the contact pads.

15. The semiconductor device of claim 10, further comprising contact pads disposed on the surface of the first substrate, wherein the antenna substrate is connected to the first substrate via the contact pads.

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