An integrated circuit package device having a stress relief structure
By arranging multiple bare dies side-by-side in an integrated circuit package device and sealing the gaps with bare dies, thermal stress is reduced, the stress concentration problem between the packaging material and the chip is solved, and the reliability and stability of the package are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHIHAOTONG (TIANJIN) INFORMATION TECHNOLOGY CO LTD
- Filing Date
- 2024-11-20
- Publication Date
- 2026-05-29
AI Technical Summary
During the integrated circuit packaging process, the difference in thermal expansion coefficients between the packaging material and the chip leads to stress concentration, which causes gaps between the chip and the packaging material, affecting the reliability and performance of the packaging.
An integrated circuit packaging device with a stress-reduction structure is used. Multiple bare dies are arranged side by side on a carrier board, and sealing dies are placed at the gaps to reduce thermal stress. Taking advantage of the fact that the strength of solids is greater than that of gases, the thermal stress concentration at the corners of the bare dies is reduced.
It improves the reliability and operational stability of integrated circuit packaging, reduces thermal stress at die corners, and enhances packaging stability and reliability.
Smart Images
Figure CN122121722A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor packaging technology, and in particular to an integrated circuit packaging device with a stress reduction structure. Background Technology
[0002] With the rapid development of semiconductor technology, the requirements for integrated circuit packaging are becoming increasingly stringent. During the packaging process, the difference in the coefficients of thermal expansion between the packaging material and the chip (bare die) can lead to stress concentration. Current technologies arrange multiple chips side by side; however, this arrangement generates significant stress concentration, creating gaps between the chip and the packaging material. This reduces the reliability of the integrated circuit packaging and consequently affects the performance of the chip and the integrated circuit. Summary of the Invention
[0003] In view of this, embodiments of this application provide an integrated circuit packaging device with a stress reduction structure, which facilitates the improvement of the reliability of integrated circuit packaging device packaging.
[0004] This application provides an integrated circuit packaging device with a stress-reducing structure, comprising: a carrier board; a first die disposed on the carrier board; a second die also disposed on the carrier board; the second die being disposed adjacent to the first die, and a first gap being formed between a first side surface of the second die and a first side surface of the first die; and a third die disposed on the carrier board and adjacent to the second die and the first die, and the third die blocking a first extension path of the first gap.
[0005] According to a specific implementation of this application, a second gap is formed between the second side of the second die and the first side of the third die; the integrated circuit packaging device further includes a fourth die, which is disposed on the carrier plate and blocks the first extension path of the second gap.
[0006] According to a specific implementation of an embodiment of this application, a third gap is formed between the first side of the fourth bare sheet and the second side of the third bare sheet, and a fourth gap is formed between the second side of the fourth bare sheet and the second side of the first bare sheet; wherein, the first bare sheet blocks the first extension path of the third gap, and the second bare sheet blocks the first extension path of the fourth gap.
[0007] According to a specific implementation of this application, the first, second, third, and fourth bare wafers are all rectangular parallelepipeds of equal size; the first long side of the second bare wafer is adjacent to the first short side of the first bare wafer, and the first short side of the second bare wafer is aligned with the first long side of the first bare wafer; the first long side of the second bare wafer is perpendicular to the first short side of the second bare wafer, and the first short side of the first bare wafer is perpendicular to the first long side of the first bare wafer; the first long side of the third bare wafer is adjacent to the second short side of the second bare wafer, and the first short side of the third bare wafer is aligned with the first long side of the second bare wafer. Alignment; the first long side of the third bare sheet is perpendicular to the first short side of the third bare sheet, and the first short side of the second bare sheet is perpendicular to the first long side of the second bare sheet; the first long side of the fourth bare sheet is adjacent to the second short side of the third bare sheet, and the first short side of the fourth bare sheet is aligned with the first long side of the third bare sheet; the first long side of the fourth bare sheet is perpendicular to the first short side of the fourth bare sheet, and the first short side of the third bare sheet is perpendicular to the first long side of the third bare sheet; a stress relief plate is provided in the middle area of the bare sheet arrangement area surrounded by the first bare sheet, the second bare sheet, the third bare sheet and the fourth bare sheet.
[0008] According to a specific implementation of an embodiment of this application, it further includes: a fifth bare sheet, which is disposed on the carrier plate and adjacent to the second bare sheet and the third bare sheet, and the fifth bare sheet blocks the second extension path of the second gap.
[0009] According to a specific implementation of the present application, it further includes: a sixth bare sheet, which is disposed on the carrier plate and adjacent to the first bare sheet and the fourth bare sheet, and the sixth bare sheet blocks the second extension path of the fourth gap.
[0010] According to a specific implementation of an embodiment of this application, the first short side of the fifth die and the short side of the second die have a first preset distance; the integrated circuit packaging device further includes: a first simulated die, the first simulated die being disposed on the carrier board; in the long side direction of the fifth die, the first simulated die is aligned with the fifth die; the short side of the first simulated die is aligned with the short side of the second die.
[0011] According to a specific implementation of an embodiment of this application, the second short side of the fifth die and the long side of the third die have a second preset distance; the integrated circuit device further includes: a second simulated die, the second simulated die is disposed on the carrier board and aligned with the fifth die in the length direction of the fifth die; the short side of the second simulated die is aligned with the long side of the third die.
[0012] According to a specific implementation of the present application, the method further includes: a seventh bare sheet and an eighth bare sheet, wherein the seventh bare sheet is disposed on the carrier plate and is disposed adjacent to the first bare sheet and the second bare sheet, and the seventh bare sheet blocks the second extension path of the first gap; the eighth bare sheet is disposed on the carrier plate and is disposed adjacent to the second bare sheet and the third bare sheet, and the seventh bare sheet blocks the second extension path of the third gap.
[0013] According to a specific implementation of an embodiment of this application, the carrier board is an adapter board; the first die, the second die, the third die, and the fourth die are main functional dies and are disposed on the adapter board; the integrated circuit packaging device further includes: a substrate, on which the adapter board is disposed and the substrate is electrically connected to the adapter board; and an interface die, on which the interface die is disposed and electrically connected to the substrate.
[0014] In this embodiment, the integrated circuit packaging device with a stress reduction structure has a second die and a first die disposed adjacent to each other on a carrier board, with a first gap between the first side surface of the second die and the first side surface of the first die. If only the first die and the second die are disposed on the carrier board, a large stress will be concentrated at the corner of the first die adjacent to the first gap and at the corner of the second die adjacent to the first gap. The third die is disposed adjacent to both the second die and the first die, and the third die blocks the first extension path of the first gap. Since the third die blocks the first extension path of the first gap, the large thermal stress generated at the corners of the first die and the second die near the first extension path of the first gap is reduced. Thus, the third die can reduce at least part of the thermal stress, thereby reducing the thermal stress at the corners of the first die and the second die, which facilitates the improvement of the reliability of the integrated circuit packaging device. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of the structure of an integrated circuit packaging device in the prior art; Figure 2A schematic diagram of an integrated circuit packaging device with a stress reduction structure provided in an embodiment of this application; Figure 3 A schematic diagram of an integrated circuit packaging device with a stress reduction structure provided in another embodiment of this application; Figure 4 This is a schematic diagram of an integrated circuit packaging device with a stress reduction structure provided in an embodiment of this application. Detailed Implementation
[0017] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0018] For the purposes of the background art, see [link to background art]. Figure 1 In a specific example, the integrated circuit package circuit includes a die DIE1, a die DIE2 and two IO dies. The four dies are placed side by side, forming a through channel between two adjacent dies. The presence of the channel causes stress on the die to concentrate at the corners adjacent to the channel, which in turn causes the substrate under the die to warp, resulting in unreliable packaging.
[0019] Based on this, the inventors discovered during the research process that a device can be placed in the extension direction of the channel, which can reduce stress concentration and improve the reliability of the package.
[0020] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.
[0021] See Figure 2 and Figure 3 The integrated circuit packaging device with stress reduction structure in this embodiment may include: a carrier 1, a first die 2 (DIE 1), a second die 3 (DIE2), and a third die 4 (DIE3); the first die 2 is disposed on the carrier 1; the second die 3 is also disposed on the carrier 1; the second die 3 is disposed adjacent to the first die 2, and a first gap 23 is formed between the first side surface of the second die 3 and the first side surface of the first die 2; the third die 4 is disposed on the carrier 1 and is disposed adjacent to the second die 3 and the first die 2, and the third die 4 blocks the first extension path of the first gap 23.
[0022] The carrier board 1 is a circuit board used to carry electronic components or chips. Different wiring layers can be set in the carrier board 1 for electrical connection with other components.
[0023] The first die 2, the second die 3, and the third die 4 can be dies with specific functions. A die, also known as a chip, is a tiny block of semiconductor material processed using specific techniques. It contains a large number of electronic devices to achieve a specific function. The functions of the first die 2, the second die 3, and the third die 4 can be the same or different.
[0024] Because the materials used for the die and the carrier 1 are different and have different coefficients of thermal expansion, thermal stress will be generated inside the materials when the temperature changes. If the two are packaged together, the die and / or carrier 1 will warp during the packaging process or during use, resulting in unreliable packaging and reduced die performance.
[0025] The third bare sheet 4 is sealed on the first extension path of the first gap 23. The third bare sheet 4 is a solid, while the gap between the first bare sheet 2 and the second bare sheet 3 is air. The strength of the solid is greater than that of the gas. Due to the presence of the third bare sheet 4, the thermal stress at the corners of the first extension path of the first gap 23 near the first bare sheet 2 and the second bare sheet 3 near the corners of the first extension path of the first gap 23 can be reduced.
[0026] In this embodiment, on the carrier plate 1, the second bare sheet 3 is disposed adjacent to the first bare sheet 2, and there is a first gap 23 between the first side surface of the second bare sheet 3 and the first side surface of the first bare sheet 2. If there are only the first bare sheet 2 and the second bare sheet 3 on the carrier plate 1, a large stress will be concentrated at the corner of the first bare sheet 2 adjacent to the first gap 23 and at the corner of the second bare sheet 3 adjacent to the first gap 23. In this embodiment, the third bare sheet 4 is disposed adjacent to the second bare sheet 3 and also adjacent to the first bare sheet 2, and the third bare sheet 4 blocks the first extension path of the first gap 23. Since the third bare sheet 4 blocks the first gap, On the first extension path of the first gap 23, the first die 2 near the corner of the first extension path of the first gap 23 and the second die 3 near the corner of the first extension path of the first gap 23 generate significant thermal stress. The third die blocks the first extension path of the first gap, thus the third die can offset at least part of the thermal stress, thereby reducing the thermal stress at the corner of the first extension path of the first gap 23 and the second die 3 near the corner of the first extension path of the first gap 23, which facilitates the improvement of the reliability and operational stability of the integrated circuit packaging device.
[0027] Since the third die 4 is disposed adjacent to the first die 2 and the second die 3, there will also be a gap between the third die 4 and the second die 3. Similarly, if no intervention is made, under temperature changes, large thermal stress will be generated at the corners adjacent to the gaps of the third die 4 and the second die 3. In one embodiment, there is a second gap 34 between the second side of the second die 3 and the first side of the third die 4. The integrated circuit packaging device of this embodiment also includes: a fourth die 5 (DIE 4), which is disposed on the carrier 1 and blocks the first extension path of the second gap 34.
[0028] The corners adjacent to the third die 4 and the second gap 34, as well as the corners adjacent to the second die 3 and the second gap 34, will also generate significant thermal stress. The fourth die 5 blocks the first extension path of the second gap 34, which can transmit and disperse the thermal stress, thereby reducing the thermal stress at the corners of the third die 4 and the second die 3 near the first extension path of the second gap 34. This facilitates the improvement of the reliability and operational stability of the integrated circuit packaging device.
[0029] See Figure 2 In the above embodiments, the first bare sheet 2 and the second bare sheet 3 are arranged adjacent to each other, and the third bare sheet 4 is arranged adjacent to the first bare sheet 2 and the second bare sheet 3 respectively. The fourth bare sheet 5 blocks the first extension path of the second gap 34. When reducing the thermal stress at the corners of the third bare sheet 4 and the second bare sheet 3, there is a gap between the fourth bare sheet 5 and the third bare sheet 4, and there is also a gap between the fourth bare sheet 5 and the first bare sheet 2. Similarly, if no intervention is made, under temperature changes, large thermal stress will also be generated at the corners adjacent to the gaps of the fourth bare sheet 5 and the third bare sheet 4. In order to make full use of the existing bare sheets, in one embodiment, there is a third gap 45 between the first side of the fourth bare sheet 5 and the second side of the third bare sheet 4, and there is a fourth gap 52 between the second side of the fourth bare sheet 5 and the second side of the first bare sheet 2; wherein, the first bare sheet 2 blocks the first extension path of the third gap 45, and the second bare sheet 3 blocks the first extension path of the fourth gap 52.
[0030] See Figure 3 The width of the first bare piece 2 and the width of the second bare piece 3 can be equal or unequal.
[0031] In this embodiment, the third die 4 can transmit and disperse the large thermal stress at the corner of the first extension path of the first die 2 near the first gap 23. Simultaneously, the first die 2 also blocks the extension path of the gap between the fourth die 5 and the third die 4, thus transmitting and dispersing the thermal stress at the corner of the first extension path of the third die 4 near the third gap 45 and the corner of the first extension path of the fourth die 5 near the third gap 45. The second die 3 has a similar effect in blocking the first extension path of the fourth gap 52. This embodiment can fully utilize existing dies to transmit and disperse stress as much as possible, simplifying the structure of the integrated circuit packaging device while improving its reliability and operational stability.
[0032] The first die 2, the second die 3, the third die 4, and the fourth die 5 can be the same size or different sizes. If the sizes are different, the overall shape of the distribution of the first die 2, the second die 3, the third die 4, and the fourth die 5 on the substrate is not easily symmetrical. This results in uneven stress on the carrier plate 1 from the four dies, leading to severe warping of the carrier plate 1 and large gaps between the carrier plate 1 and the first die 2, the second die 3, the third die 4, and the fourth die 5. This can cause unreliable packaging of integrated circuit devices and affect the performance of the first die 2, the second die 3, the third die 4, and the fourth die 5. To solve this problem, see [reference needed]. Figure 2 In one embodiment provided in this application, the first bare sheet 2, the second bare sheet 3, the third bare sheet 4 and the fourth bare sheet 5 are cuboids of equal size.
[0033] The first long side of the second bare sheet 3 is adjacent to the first short side of the first bare sheet 2, and the first short side of the second bare sheet 3 is aligned with the first long side of the first bare sheet 2; the first long side of the second bare sheet 3 is perpendicular to the first short side of the second bare sheet 3, and the first short side of the first bare sheet 2 is perpendicular to the first long side of the first bare sheet 2.
[0034] The first long side of the third bare sheet 4 is adjacent to the second short side of the second bare sheet 3, and the first short side of the third bare sheet 4 is aligned with the first long side of the second bare sheet 3; the first long side of the third bare sheet 4 is perpendicular to the first short side of the third bare sheet 4, and the first short side of the second bare sheet 3 is perpendicular to the first long side of the second bare sheet 3.
[0035] The first long side of the fourth bare piece 5 is adjacent to the second short side of the third bare piece 4, and the first short side of the fourth bare piece 5 is aligned with the first long side of the third bare piece 4; the first long side of the fourth bare piece 5 is perpendicular to the first short side of the fourth bare piece 5, and the first short side of the third bare piece 4 is perpendicular to the first long side of the third bare piece 4.
[0036] A stress-reducing plate 10 is provided in the middle area of the bare sheet arrangement area enclosed by the first bare sheet 2, the second bare sheet 3, the third bare sheet 4 and the fourth bare sheet 5.
[0037] The material of the stress relief plate 10 can be the same as that of the first bare sheet 2, the second bare sheet 3, the third bare sheet 4 and the fourth bare sheet 5, so as to further reduce thermal stress.
[0038] In this embodiment, the arrangement of the first die 2, the second die 3, the third die 4, and the fourth die 5 forms an annular stress reduction ring at the center of the four dies. This stress reduction ring extends outward and connects to four stress reduction channels, namely, the first gap 23, the second gap 34, the third gap 45, and the fourth gap 52. The stress reduction ring and the four gaps connected to it constitute the stress reduction zone 10, i.e., the stress reduction structure. This structure can reduce the thermal stress of the dies. The four dies are symmetrically arranged relative to the stress reduction zone, generating symmetrical stress. This improves the reliability of the integrated circuit packaging device and enables the four dies to work stably. It avoids the problem of large gaps between the dies and the carrier board 1, which could lead to unreliable packaging of the integrated circuit device and affect the performance of the first die 2, the second die 3, the third die 4, and the fourth die 5.
[0039] In some examples, the second die 3 and the third die 4 may also have concentrated thermal stress at the corner adjacent to the second gap 34. In order to reduce the concentrated thermal stress, in some examples, a fifth die 6 (IO DIE) is also included. The fifth die 6 is disposed on the carrier plate 1 and is disposed adjacent to the second die 3 and the third die 4. The fifth die 6 blocks the second extension path of the second gap 34.
[0040] The second extension path is an extension direction opposite to the first extension direction.
[0041] In this embodiment, a fifth die 6 is also provided on the carrier plate 1 to block the second extension path of the second gap 34. In this way, the thermal stress concentrated at the corner of the second extension path of the second die 3 and the third die 4 near the second gap 34 can be transferred and dispersed, thereby reducing the concentration of thermal stress and facilitating the improvement of the reliability and operational stability of the integrated circuit packaging device.
[0042] See Figure 2 To further reduce the concentrated thermal stress at the die, in some examples, a sixth die (IO DIE) 7 is also included. The sixth die 7 is disposed on the carrier plate 1 and is disposed adjacent to the first die 2 and the fourth die 5. The sixth die 7 blocks the second extension path of the fourth gap 52.
[0043] A sixth die 7 is also disposed on the carrier plate 1, which is sealed on the second extension path of the second gap 34. In this way, the heat stress concentrated at the corner of the second extension path of the second die 3 and the third die 4 near the second gap 34 can be transferred and dispersed, thereby reducing the heat stress concentration. Furthermore, the sixth die 7 and the fifth die 6 can be symmetrically distributed on both sides of the other four dies, so that the overall shape formed by the six dies is symmetrical. This can further reduce the stress on the dies and facilitate the improvement of the reliability and operational stability of the integrated circuit packaging device.
[0044] It is understood that a seventh and an eighth bare plate may also be included, distributed on the second extended path of the first slit 23 and the second extended path of the third slit 45.
[0045] To save packaging space, the size of the fifth die 6 is usually not equal to the size of the first die 2, the second die 3, the third die 4, and the fourth die 5, and is generally smaller than the above four dies. If this is the case, the area of the carrier board 1 where the short sides of the fifth die 6 and the second die 3 are opposite is prone to warping. This application provides an embodiment in which the first short side of the fifth die 6 and the short side of the second die 3 have a first preset distance.
[0046] The integrated circuit packaging device further includes: a first analog die 8, which is disposed on a carrier board 1; the first analog die 8 is aligned with the fifth die 6 along the long side; and the short side of the first analog die 8 is aligned with the short side of the second die 3.
[0047] The first simulated die, or dummy die, is a special wafer structure used to simulate the behavior of an actual chip during manufacturing, but it does not possess all the functions of a real chip. It is typically used for process monitoring and ensuring manufacturability.
[0048] In this embodiment, the first simulated die 8 is aligned with the fifth die 6 along the long side; the short side of the first simulated die 8 is aligned with the short side of the second die 3. This makes it easier to arrange the five dies arranged on the carrier board 1 in a symmetrical distribution, thereby reducing the warpage of the carrier board 1 and improving the packaging reliability of the integrated circuit packaging device.
[0049] See Figure 2 To further reduce the warpage of the carrier 1 and improve the packaging reliability of the integrated circuit packaging device, in some examples, the second short side of the fifth die 6 and the long side of the third die 4 have a second preset distance. The integrated circuit device also includes: a second analog die 9, which is disposed on the carrier 1 and aligned with the fifth die 6 along the length direction of the fifth die 6; the short side of the second analog die 9 is aligned with the long side of the third die 4.
[0050] The first analog die 8 and the second analog die 9 are disposed on both sides of the fifth die 6 and aligned with the fifth die 6 in the length direction, so that the first die 2, the second die 3, the third die 4, the fourth die 5, the fifth die 6, the first analog die 8 and the second analog die 9 are symmetrically distributed on the carrier board 1, which facilitates the reduction of the warpage of the carrier board 1 and improves the packaging reliability of the integrated circuit packaging device.
[0051] See Figure 4 It also includes: a seventh bare sheet 11 and an eighth bare sheet 12. The seventh bare sheet 11 is disposed on the carrier plate 1 and is disposed adjacent to the first bare sheet 2 and the second bare sheet 3, and the seventh bare sheet 11 blocks the second extension path of the first gap; the eighth bare sheet 12 is disposed on the carrier plate 1 and is disposed adjacent to the second bare sheet 3 and the third bare sheet 4, and the seventh bare sheet 11 blocks the second extension path of the third gap.
[0052] A simulated die can be placed on each side of the seventh die 11; a simulated die can be placed on each side of the eighth die 12, which can improve the packaging reliability of integrated circuit packaging devices.
[0053] See Figure 2 and Figure 3 In order to improve the packaging density of integrated circuit packaging devices and make reasonable use of the space, in some examples, the carrier board 1 in this embodiment is an adapter board; the first die 2, the second die 3, the third die 4 and the fourth die 5 are the main functional dies and are disposed on the adapter board.
[0054] The integrated circuit packaging device in this embodiment further includes: a substrate 13 and an interface (IO, Input / Output) die 14; an adapter plate 1 is provided on the substrate 13 and the substrate 13 is electrically connected to the adapter plate 1; the IO die 14 is disposed on the substrate 13 and the IO die 14 is electrically connected to the substrate 13.
[0055] A main function die is a die in an integrated circuit package that performs the main functions and plays a major role, such as a processor die.
[0056] IO die 14 (Input / Output Die) refers to a die that has undergone wafer dicing and testing during chip manufacturing but has not been packaged. It is specifically responsible for processor input / output functions and communication between the main functional die and external devices.
[0057] In this embodiment, the IO die 14 can be electrically connected to the main function die through the substrate 13 and the adapter board 1 to realize mutual communication between the IO die and the main function die.
[0058] In this embodiment, the main functional dies such as the first die 2, the second die 3, the third die 4, and the fourth die 5 are disposed on the adapter board, which can improve the packaging density of the integrated circuit packaging device. At the same time, the IO die 14 is disposed on the substrate 13, which can also effectively utilize the space on the substrate and improve the packaging density of the integrated circuit packaging device.
[0059] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0060] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
[0061] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. An integrated circuit package device with a stress-reducing structure, characterized in that, include: Carrier plate; A first bare die, the first bare die being disposed on the carrier plate; A second die, which is also disposed on the carrier plate; The second bare sheet is disposed adjacent to the first bare sheet, and there is a first gap between the first side surface of the second bare sheet and the first side surface of the first bare sheet; The third bare sheet is disposed on the carrier plate and is adjacent to the second bare sheet and the first bare sheet, and the third bare sheet blocks the first extension path of the first gap.
2. The integrated circuit packaging device with stress reduction structure according to claim 1, characterized in that, A second gap exists between the second side surface of the second bare sheet and the first side surface of the third bare sheet; The integrated circuit packaging device further includes a fourth die, which is disposed on the carrier plate and blocks the first extension path of the second gap.
3. The integrated circuit device according to claim 2, characterized in that, There is a third gap between the first side of the fourth bare sheet and the second side of the third bare sheet, and there is a fourth gap between the second side of the fourth bare sheet and the second side of the first bare sheet; wherein, the first bare sheet blocks the first extension path of the third gap, and the second bare sheet blocks the first extension path of the fourth gap.
4. The integrated circuit packaged device with stress reduction structure according to claim 3, characterized in that, The first, second, third, and fourth bare wafers are all rectangular parallelepipeds of equal size. The first long side of the second bare piece is adjacent to the first short side of the first bare piece, and the first short side of the second bare piece is aligned with the first long side of the first bare piece; the first long side of the second bare piece is perpendicular to the first short side of the second bare piece, and the first short side of the first bare piece is perpendicular to the first long side of the first bare piece. The first long side of the third bare sheet is adjacent to the second short side of the second bare sheet, and the first short side of the third bare sheet is aligned with the first long side of the second bare sheet; the first long side of the third bare sheet is perpendicular to the first short side of the third bare sheet, and the first short side of the second bare sheet is perpendicular to the first long side of the second bare sheet. The first long side of the fourth bare sheet is adjacent to the second short side of the third bare sheet, and the first short side of the fourth bare sheet is aligned with the first long side of the third bare sheet; the first long side of the fourth bare sheet is perpendicular to the first short side of the fourth bare sheet, and the first short side of the third bare sheet is perpendicular to the first long side of the third bare sheet. A stress-reducing plate is provided in the middle area of the bare die arrangement area surrounded by the first bare die, the second bare die, the third bare die, and the fourth bare die.
5. The integrated circuit packaged device with stress reduction structure according to claim 3, characterized in that, Also includes: The fifth bare sheet is disposed on the carrier plate and is arranged adjacent to the second bare sheet and the third bare sheet, and the fifth bare sheet blocks the second extension path of the second gap.
6. The integrated circuit package device with stress reduction structure according to claim 5, characterized in that, Also includes: The sixth bare sheet is disposed on the carrier plate and is adjacent to the first bare sheet and the fourth bare sheet, and the sixth bare sheet blocks the second extension path of the fourth gap.
7. The integrated circuit package device with stress relief structure according to claim 5, characterized in that, The first short side of the fifth bare sheet and the short side of the second bare sheet have a first preset distance; The integrated circuit packaging device further includes: a first simulated die disposed on the carrier board; the first simulated die is aligned with the fifth die along its long side. The short side of the first simulated die is aligned with the short side of the second die.
8. The integrated circuit package device with stress reduction structure according to claim 7, characterized in that, The second short side of the fifth bare sheet and the long side of the third bare sheet have a second preset distance; The integrated circuit device further includes: a second analog die, which is disposed on the carrier board and aligned with the fifth die along its length. The short side of the second simulated die is aligned with the long side of the third die.
9. The integrated circuit package device with stress reduction structure according to claim 6, characterized in that, Also includes: A seventh bare sheet and an eighth bare sheet, wherein the seventh bare sheet is disposed on the carrier plate and is disposed adjacent to the first bare sheet and the second bare sheet, and the seventh bare sheet blocks the second extension path of the first gap; The eighth bare sheet is disposed on the carrier plate and is arranged adjacent to the second bare sheet and the third bare sheet, and the seventh bare sheet blocks the second extension path of the third gap.
10. The integrated circuit package device with a stress-reducing structure according to any one of claims 2 to 4, characterized in that, The carrier plate is an adapter plate; The first die, the second die, the third die, and the fourth die are main functional dies and are disposed on the adapter board; The integrated circuit packaging device further includes: A substrate, wherein the adapter plate is disposed on the substrate, and the substrate is electrically connected to the adapter plate; An interface die is disposed on the substrate and electrically connected to the substrate.