INTEGRATED CIRCUIT PACKAGE AND METHOD

Abstract

Device comprising: an integrated circuit die (50, 50A, 50B); an encapsulation material (120) that at least partially encapsulates the integrated circuit die (50, 50A, 50B); a conductive via (116) extending through the encapsulation material (120); a redistribution structure (122) on the encapsulation material (120), wherein the redistribution structure (122) comprises: a metallization structure (126, 130, 134) that is electrically coupled to the conductive via (116) and the integrated circuit die (50, 50A, 50B); a dielectric layer (136) on the metallization structure (126, 130, 134), wherein the dielectric layer (136) has a first thickness (T1) of 10 µm to 30 µm;and a first solder metallization, under-bump metallurgy, UBM (138) comprising a first through-hole section (138A) extending through the dielectric layer (136) and a first bump section (138B) on the dielectric layer (136), wherein the first UBM (138) is physically and electrically coupled to the metallization structure (126, 130, 134), wherein the first through-hole section (138A) has a first width (W1) with a ratio of the first thickness (T1) to the first width (W1) of 1.33 to 1.66, and wherein the first bump section (138B) has a second width (W2) with a ratio of the second width (W2) to the first width (W1) in a range of 2.5 to 3.6.

Description

BACKGROUND The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a wide variety of electronic components (such as transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely attributable to the repeated reduction of the minimum size of structural elements, allowing more components to be integrated within a given area. As the demand for increasingly smaller electronic devices has grown, the need for ever smaller and more innovative packaging techniques for semiconductor dies has emerged. One example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is placed on top of a lower semiconductor package to achieve a high degree of integration and component density.PoP technology generally enables the production of semiconductor devices with improved functionality and a small footprint on a printed circuit board (PCB). US 2017 / 0365566 A1 discloses a fan-out semiconductor package. US 2014 / 0339699 A1 discloses a compound structure comprising a substrate with an embedded electrical component and an under-bump metallurgy (UBM) stack in contact with a contact surface of the electrical component embedded in the substrate. US 2012 / 0273937 A1 discloses a semiconductor device comprising a substrate with multiple contact pads. US 2017 / 0162527 A1 discloses an electronic component package with multiple components. US 2014 / 0264839 A1 describes a semiconductor package comprising contact pads, package-piercing vias, and semiconductor devices, wherein a redistribution layer is formed over an insulating material formed over the contact pads. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of this disclosure are best understood with reference to the following detailed description, when read together with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. The dimensions of the various structural elements may be enlarged or reduced as necessary for the clarity of this discussion. Fig. 1 illustrates a cross-sectional view of an integrated circuit according to some embodiments. Figs. 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 to 20 illustrate cross-sectional views of intermediate steps during a process for forming a package component according to some embodiments. Fig. 21 and Fig.Figures 22 illustrate the formation and implementation of device stacks according to some embodiments. Figure 23 illustrates a device stack according to some other embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the invention. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed. Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may also be oriented differently (rotated 90 degrees or otherwise), and the spatially relative descriptors used in this text may be interpreted accordingly. In some embodiments, under-bump metallurgies (UBMs) are formed for a redistribution structure, and external connectors are formed that physically and electrically couple the UBMs. The UBMs have vias extending through the top dielectric layer of the redistribution structure and bump sections on which the external connectors are formed. The vias have a small width and a large height-to-width ratio. Furthermore, the top dielectric layer has a large thickness. Forming the UBMs with a large height-to-width ratio allows the UBMs and the top dielectric layer of the redistribution structure to buffer mechanical stresses, thereby increasing the reliability of the redistribution structure during testing or operation. Fig. 1 illustrates a cross-sectional view of an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 is encapsulated (“packaged”) in subsequent processing to form an integrated circuit package. The integrated circuit die 50 can be: a logic die (for example, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (for example, a dynamic random-access memory (DRAM) die, a static random-access memory (SRAM) die, etc.).), an energy management die (for example, a Power Management Integrated Circuit (PMIC) die), a high frequency (HF) die, a sensor die, a micro-electro-mechanical system (MEMS) die, a signal processing die (for example, a digital signal processing (DSP) die), a front-end die (for example, analog front-end (AFE) dies), the like, or combinations thereof. The integrated circuit die 50 can be formed on a wafer, which may contain various device regions that are subsequently separated to form multiple integrated circuit dies. The integrated circuit die 50 can be processed according to suitable fabrication processes to form integrated circuits. For example, the integrated circuit die 50 contains a semiconductor substrate 52, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may also contain other semiconductor materials, such as germanium; a compound semiconductor, including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.Other substrates, such as multilayer or gradient substrates, can also be used. The semiconductor substrate 52 has an active area (for example, the area facing upwards in Fig. 1), sometimes referred to as a front, and an inactive area (for example, the area facing downwards in Fig. 1), sometimes referred to as a back. The components 54 can be formed on the front side of the semiconductor substrate 52. The components 54 can be active components (for example, transistors, diodes, etc.), capacitors, resistors, etc. An interlayer dielectric (ILD) 56 is located over the front side of the semiconductor substrate 52. The ILD 56 surrounds the components 54 and can cover them. The ILD 56 can contain one or more dielectric layers made of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Conductive connectors 58 extend through the ILD 56 to electrically and physically couple the components 54. For example, if the components 54 are transistors, the conductive connector 58 can couple the gates and source / drain regions of the transistors. The conductive connectors 58 can be made of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. An interconnect structure 60 is located above the ILD 56 and the conductive connectors 58. The interconnect structure 60 connects the components 54 to each other to form an integrated circuit. The interconnect structure 60 can be formed, for example, by metallization structures in dielectric layers on the ILD 56. The metallization structures contain metal conductors and vias formed in one or more dielectric layers.The metallization structures of the interconnect structure 60 are electrically coupled to the components 54 by the conductive connectors 58. The integrated circuit die 50 further contains pads 62, such as aluminum pads, with which external connections are made. The pads 62 are located on the active side of the integrated circuit die 50, such as in and / or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit die 50, such as on sections of the interconnect structure 60 and the pads 62. Openings extend through the passivation films 64 to the pads 62. Die connectors 66, such as conductive pillars (made, for example, of metal, such as copper), extend through the openings in the passivation films 64 and are physically and electrically coupled to the respective pads 62. The die connectors 66 can be formed, for example, by plating or the like.The die connectors 66 electrically couple the respective integrated circuits of the integrated circuit die 50. Optionally, solder regions (for example, solder beads or solder bumps) can be placed on pads 62. The solder beads can be used to perform chip probe (CP) tests on the integrated circuit die 50. CP tests can be performed on the integrated circuit die 50 to determine if it is a known good die (KGD). Thus, only integrated circuit dies 50 that are KGDs undergo subsequent processing and are encapsulated, while dies that fail the CP tests are not encapsulated. After the tests, the solder regions can be removed in subsequent processing steps. A dielectric layer 68 may (but need not) be located on the active side of the integrated circuit die 50, such as on the passivation films 64 and the die connectors 66. The dielectric layer 68 laterally encapsulates the die connectors 66 and terminates laterally with the integrated circuit die 50. Initially, the dielectric layer 68 may bury the die connectors 66 such that the top surface of the dielectric layer 68 lies above the top surfaces of the die connectors 66. In some embodiments where solder regions are arranged on the die connectors 66, the dielectric layer 68 may also bury the solder regions. Alternatively, the solder regions may be removed before the dielectric layer 68 forms. The dielectric layer 68 can be a polymer, such as PBO, polyimide, BCB, or the like; a nitride, such as silicon nitride or the like; an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like; or a combination thereof. The dielectric layer 68 can be formed, for example, by spin deposition, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectors 66 are exposed through the dielectric layer 68 during the formation of the integrated circuit die 50. In other embodiments, the die connectors 66 remain buried and are exposed during a subsequent encapsulation process of the integrated circuit die 50. Exposing the die connectors 66 can remove any solder regions that may be present on the die connectors 66. In some embodiments, the integrated circuit die 50 is a stacked device containing multiple semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device, such as a hybrid memory cube (HMC) module, a high-bandwidth memory (HBM) module, or the like, containing multiple memory dies. In such embodiments, the integrated circuit die 50 contains multiple semiconductor substrates 52 interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates 52 may (but need not) have an interconnect structure 60. Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 to 20 illustrate cross-sectional views of intermediate steps during a process for forming a first package component 100 according to some embodiments. A first package region 100A and a second package region 100B are illustrated, and one or more of the integrated circuit dies 50 are encapsulated to form an integrated circuit package in each of the package regions 100A and 100B. The integrated circuit packages can also be referred to as integrated fan-out (InFO) packages. In Fig. 2, a support substrate 102 is provided, and a release layer 104 is formed on the support substrate 102. The support substrate 102 can be a glass support substrate, a ceramic support substrate, or the like. The support substrate 102 can be a wafer, such that multiple packages can be formed simultaneously on the support substrate 102. The release layer 104 can be formed from a polymer-based material that, together with the support substrate 102, can be removed from the overlying structures formed in subsequent steps. In some embodiments, the release layer 104 is a thermally removable epoxy material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating.In other embodiments, the separating layer 104 can be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV radiation. The separating layer 104 can be applied and cured as a liquid, can be a laminate film laminated onto the support substrate 102, or the like. The top surface of the separating layer 104 can be planarized and can possess a high degree of coplanarity. In Fig. 3, a rear-side redistribution structure 106 can be formed on the separating layer 104. In the embodiment shown, the rear-side redistribution structure 106 comprises a dielectric layer 108, a metallization structure 110 (sometimes referred to as redistribution layers or redistribution lines), and a dielectric layer 112. The rear-side redistribution structure 106 is optional. In some embodiments, a dielectric layer without metallization structures is formed on the separating layer 104 instead of the rear-side redistribution structure 106. The dielectric layer 108 can be formed on the separating layer 104. The underside of the dielectric layer 108 can be in contact with the top side of the separating layer 104. In some embodiments, the dielectric layer 108 is formed from a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 108 consists of a nitride, such as silicon nitride, an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 108 can be formed by any acceptable deposition process, such as spin deposition, CVD, lamination, or a combination thereof. The metallization structure 110 can be formed on the dielectric layer 108. As an example of forming the metallization structure 110, a seed layer is formed over the dielectric layer 108. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising several sublayers made of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer can be formed, for example, by physical vapor deposition (PVD) or the like. Then, a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin deposition or the like and can be exposed to light for patterning. The structure of the photoresist corresponds to the metallization structure 110.The structuring creates openings through the photoresist to expose the nucleation layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the nucleation layer. This conductive material can be formed by plating, such as electroplating or chemical plating. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or similar. The photoresist and portions of the nucleation layer where the conductive material is not present are then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist has been removed, the exposed portions of the nucleation layer are removed, for example, by an acceptable etching process, such as wet or dry etching.The remaining sections of the nucleation layer and the conductive material form the metallization structure 110. The dielectric layer 112 is formed on the metallization structure 110 and the dielectric layer 108. In some embodiments, the dielectric layer 112 consists of a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which can be patterned using a lithographic mask. In other embodiments, the dielectric layer 112 is formed from a nitride, such as silicon nitride, an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 112 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 112 is then patterned to form openings 114 that expose sections of the metallization structure 110.The structuring can be achieved through an acceptable process, such as by exposing the dielectric layer 112 if the dielectric layer 112 is a photosensitive material, or by etching using, for example, an anisotropic etchant. If the dielectric layer 112 is a photosensitive material, it can be developed after exposure. It is understood that the backside redistribution structure 106 can contain any number of dielectric layers and metallization structures. If more dielectric layers and metallization structures are to be formed, the steps and processes described above can be repeated. The metallization structures can contain conductive conductors and conductive vias. The conductive vias can be formed during the formation of the metallization structure by forming a seed layer and a conductive material of the metallization structure in the opening of the underlying dielectric layer. The conductive vias can therefore connect and electrically couple the various conductive conductors. In Fig. 4, vias 116 can be formed in the openings 114 and extend from the uppermost dielectric layer of the backside redistribution structure 106 (for example, the dielectric layer 112). The vias 116 are optional and can be omitted. For example, the vias 116 can (but need not) be omitted in embodiments where the backside redistribution structure 106 is omitted. As an example of forming the vias 116, a seed layer is formed over the backside redistribution structure 106, for example, on the dielectric layer 112 and sections of the metallization structure 110 exposed through the openings 114. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising several sublayers made of different materials.In one specific embodiment, the seed layer comprises a titanium layer and a copper layer overlying the titanium layer. The seed layer can be formed, for example, using PVD or similar processes. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin deposition or similar processes and can be exposed for patterning. The pattern of the photoresist corresponds to conductive vias. The patterning creates openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating, or similar processes. The conductive material can comprise a metal such as copper, titanium, tungsten, aluminum, or similar materials.The photoresist and sections of the seed layer where the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed sections of the seed layer are removed, for example, by an acceptable etching process, such as wet or dry etching. The remaining sections of the seed layer and the conductive material form the vias 116. In Fig. 5, integrated circuit dies 50 are bonded to the dielectric layer 112 by an adhesive 118. A desired type and number of integrated circuit dies 50 are attached in each of the package regions 100A and 100B. In the embodiment shown, several integrated circuit dies 50 are attached side by side, including a first integrated circuit die 50A and a second integrated circuit die 50B. The first integrated circuit die 50A can be a logic device, such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a microcontroller, or the like. The second integrated circuit die 50B can be a memory device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like.In some embodiments, the integrated circuit dies 50A and 50B can be of the same type, such as SoC dies. The first integrated circuit die 50A and the second integrated circuit die 50B can be formed in processes of the same technology node, or they can be formed in processes of different technology nodes. For example, the first integrated circuit die 50A can be from a more advanced process node than the second integrated circuit die 50B. The integrated circuit dies 50A and 50B can have different sizes (for example, different heights and / or areas), or they can have the same size (for example, the same heights and / or areas).The space available for the vias 116 in package regions 100A and 100B may be limited, especially if the integrated circuit dies 50A and 50B contain devices with a large footprint, such as SoCs. The use of the rear-side redistribution structure 106 allows for an improved interconnect arrangement when package regions 100A and 100B have limited space available for the vias 116. The adhesive 118 is located on the back sides of the integrated circuit dies 50A and 50B and adheres the integrated circuit dies 50A and 50B to the backside redistribution structure 106, such as the dielectric layer 112. The adhesive 118 can be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 118 can be applied to the back sides of the integrated circuit dies 50A and 50B or can be applied over the surface of the support substrate 102. For example, the adhesive 118 can be applied to the back sides of the integrated circuit dies 50A and 50B before they are singulated to separate the integrated circuit dies 50A and 50B. In Fig. 6, an encapsulation material 120 is formed on and around the various components. After formation, the encapsulation material 120 encapsulates the vias 116 and integrated circuit dies 50A and 50B. The encapsulation material 120 can be a potting compound, an epoxy resin, or the like. The encapsulation material 120 can be applied by compression molding, injection molding, or the like and can be formed over the substrate 102 such that the vias 116 and / or the integrated circuit dies 50A and 50B are buried or covered. The encapsulation material 120 is also formed in gap regions between the integrated circuit dies 50A and 50B, if present. The encapsulation material 120 can be applied in liquid or semi-liquid form and then subsequently cured. In Fig. 7, a planarization process is performed on the encapsulation material 120 to expose the vias 116 and the die connectors 66. The planarization process can also remove material from the vias 116, the dielectric layer 68, and / or the die connectors 66 until the die connectors 66 and vias 116 are exposed. After the planarization process, the top surfaces of the vias 116, the die connectors 66, the dielectric layer 68, and the encapsulation material 120 are coplanar. The planarization process can be, for example, a chemical-mechanical polishing (CMP) process, a grinding process, or the like. In some embodiments, planarization can be omitted, for example, if the vias 116 and the die connectors 66 are already exposed. In Figures 8, 9, 10 to 11, a front-side redistribution structure 122 (see Figure 11) is formed over the encapsulation material 120, the vias 116, and the integrated circuit dies 50A and 50B. The front-side redistribution structure 122 contains dielectric layers 124, 128, 132, and 136 and metallization structures 126, 130, and 134. The metallization structures can also be referred to as redistribution layers or redistribution lines. The front-side redistribution structure 12244 is shown as an example, comprising three layers of metallization structures. More or fewer dielectric layers and metallization structures can also be formed in the front-side redistribution structure 122. If fewer dielectric layers and metallization structures are to be formed, the steps and processes discussed above can be omitted.If more dielectric layers and metallization structures are to be formed, the steps and processes discussed above can be repeated. In Fig. 8, the dielectric layer 124 is deposited on the encapsulation material 120, the vias 116, and the die connectors 66. In some embodiments, the dielectric layer 124 is formed from a photosensitive material, such as PBO, polyimide, BCB, or the like, which can be patterned using a lithography mask. The dielectric layer 124 can be formed by spin deposition, lamination, CVD, the like, or a combination thereof. The dielectric layer 124 is then patterned. The patterning creates openings that expose sections of the vias 116 and the die connectors 66. The patterning can be carried out by an acceptable process, such as by exposing the dielectric layer 124 if the dielectric layer is a photosensitive material, or by etching, for example, using an anisotropic etchant.If the dielectric layer 124 is a photosensitive material, the dielectric layer 124 can be developed after exposure. The metallization structure 126 is then formed. The metallization structure 126 contains conduction sections (also referred to as conductors) located on and extending along the main surface of the dielectric layer 124. The metallization structure 126 further contains via sections (also referred to as vias) extending through the dielectric layer 124 to physically and electrically couple the vias 116 and the integrated circuit dies 126. As an example of forming the metallization structure 126, a seed layer is formed above the dielectric layer 124 and in the openings extending through the dielectric layer 124. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising several sublayers made of different materials.In some embodiments, the seed layer comprises a titanium layer and a copper layer overlying the titanium layer. The seed layer can be formed, for example, using PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed for patterning. The structure of the photoresist corresponds to the metallization structure 126. The patterning creates openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating, or the like. The conductive material can comprise a metal such as copper, titanium, tungsten, aluminum, or the like.The combination of the conductive material and underlying sections of the nucleation layer forms the metallization structure 126. The photoresist and sections of the nucleation layer where the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed sections of the nucleation layer are removed, for example, by an acceptable etching process, such as wet or dry etching. In Fig. 9, the dielectric layer 128 is deposited on the metallization structure 126 and dielectric layer 124. The dielectric layer 128 can be formed in a similar manner to the dielectric layer 124 and can be made of a similar material to the dielectric layer 124. The metallization structure 130 is then formed. The metallization structure 130 contains conduction sections located on and extending along the main surface of the dielectric layer 128. The metallization structure 130 further contains vias extending through the dielectric layer 128 to physically and electrically couple the metallization structure 126. The metallization structure 130 can be formed in a similar manner and with a similar material as the metallization structure 126. In some embodiments, the metallization structure 130 has a different size than the metallization structure 126. For example, the conduction sections and / or vias of the metallization structure 130 can be wider or thicker than the conduction sections and / or vias of the metallization structure 126.Furthermore, the metallization structure 130 can be formed with a larger center-to-center distance than the metallization structure 126. In Fig. 10, the dielectric layer 132 is deposited on the metallization structure 130 and the dielectric layer 128. The dielectric layer 132 can be formed in a similar manner to the dielectric layer 124 and can be made from a similar material. Metallization structure 134 is then formed. Metallization structure 134 contains conduction sections located on and extending along the main surface of dielectric layer 132. Metallization structure 134 also contains vias extending through dielectric layer 132 to physically and electrically couple metallization structure 130. Metallization structure 134 can be formed in a similar manner and from a similar material as metallization structure 126. Metallization structure 134 is the top metallization structure of the front-side redistribution structure 122. Thus, all intermediate metallization structures of the front-side redistribution structure 122 (for example, metallization structures 126 and 130) are located between metallization structure 134 and the integrated circuit dies 50A and 50B.In some embodiments, the metallization structure 134 has a different size than the metallization structures 126 and 130. For example, the traces and / or vias of the metallization structure 134 may be wider or thicker than the traces and / or vias of the metallization structures 126 and 130. Furthermore, the metallization structure 134 may be formed with a larger center-to-center spacing than the metallization structure 130. In Fig. 11, the dielectric layer 136 is deposited on the metallization structure 134 and the dielectric layer 132. The dielectric layer 136 can be formed in a similar manner to the dielectric layer 124 and can be made of a similar material. The dielectric layer 136 is the uppermost dielectric layer of the front-side redistribution structure 122. Thus, all metallization structures of the front-side redistribution structure 122 (for example, the metallization structures 126, 130, and 134) are arranged between the dielectric layer 136 and the integrated circuit dies 50A and 50B. Furthermore, all intermediate dielectric layers of the front-side redistribution structure 122 (for example, the dielectric layers 124, 128, 132) are arranged between the dielectric layer 136 and the integrated circuit dies 50A and 50B. In Fig. 12, UBMs 138 are formed for external connection with the front-side redistribution structure 122. The UBMs 138 have hump sections located on and extending along the main surface of the dielectric layer 136, and have via sections extending through the dielectric layer 136 to physically and electrically couple the metallization structure 134. As a result, the UBMs 138 are electrically coupled to the vias 116 and the integrated circuit dies 50A and 50B. The UBMs 138 can be formed in one of several processes or a combination of several processes. Figures 13A to 13C illustrate a method for forming UBMs 138 according to some embodiments. The formation of a single UBM 138 is illustrated in a detailed view of a region of the first package component 100. It should be understood that some details have been omitted or enlarged for clarity. Furthermore, several UBMs 138 can be formed simultaneously. In Fig. 13A, the dielectric layer 136 is patterned to form openings 140 that expose sections of the metallization structure 134. The patterning can be carried out by an acceptable process, such as exposure of the dielectric layer 136 if the dielectric layer 136 is a photosensitive material, or by etching, for example, by anisotropic etching. If the dielectric layer 136 is a photosensitive material, it can be developed after exposure. The openings 140 have a small average width W1. In some embodiments, the width W1 is in the range of about 20 µm to about 25 µm, for example, about 25 µm. The small width W1 of the openings 140 reduces the amount of the metallization structure 134 that is contacted by the UBMs 138. Or to put it another way: The UBMs 138 touch smaller contact pads of the metallization structure 134.The amount of metallization structure 134 available for signal routing can thus be increased. The dielectric layer 136 has a large thickness, and thus the openings 140 have a large depth D1. The depth D1 is greater than the thicknesses of the interdielectric layers of the front-side redistribution structure 122. In some embodiments, the depth D1 is at least about 7 µm, for example, in the range of about 10 µm to about 30 µm, such as about 15 µm. The large thickness of the dielectric layer 136 can help to reduce the mechanical stresses acting on the metallization structures 126, 130, and 134 when the front-side redistribution structure 122 is attached to a different substrate (which will be discussed further below).In particular, because the dielectric layer 136 is the uppermost dielectric layer of the front-side redistribution structure 122, its considerable thickness allows it to buffer mechanical stresses that would otherwise act on the intermediate dielectric layers of the front-side redistribution structure 122. Cracking and delamination in the front-side redistribution structure 122 can thus be avoided. In an experiment, a depth D1 of approximately 15 µm reduced the mechanical strain stress between the dielectric layer 136 and the metallization structure 134 by about 23%, with no further cracks developing during post-processing and load tests. In Fig. 13B, a seed layer 142 is formed over the dielectric layer 136 and in the openings 140. In some embodiments, the seed layer 142 is a metal layer, which can be a single layer or a composite layer comprising several sublayers made of different materials. In some embodiments, the seed layer 142 comprises a titanium layer and a copper layer over the titanium layer. The seed layer 142 can be formed using, for example, PVD or the like. A photoresist 144 is then formed and patterned on the seed layer 142. The photoresist 144 can be formed by spin coating or the like. In some embodiments, the photoresist 144 is formed to a thickness T2 in the range of about 10 µm to about 100 µm, such as about 72 µm. The photoresist 144 can then be exposed for patterning. The structure of the photoresist 144 corresponds to that of the UBMs 138.The structuring process creates openings 146 through the photoresist 144 to expose the nucleation layer 142. After formation, the openings 140 and 146 have a combined depth D2. In some embodiments, the depth D2 is in the range of approximately 5 µm to approximately 90 µm, for example, approximately 35 µm. In Fig. 13C, a conductive material 148 is formed in the openings 146 of the photoresist 144 and on the exposed portions of the nucleated layer 142. The conductive material 148 can be formed by plating, such as electroplating or chemical plating, or the like. The conductive material 148 can comprise a metal, such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist 144 and portions of the nucleated layer 142 where the conductive material 148 is not formed are removed. The photoresist 144 can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After the photoresist 144 has been removed, exposed portions of the nucleated layer 142 are removed, such as using an acceptable etching process, such as wet or dry etching.The remaining sections of the nucleation layer 142 and the conductive material 148 form the UBMs 138. In embodiments where the UBMs 138 are formed differently, more photoresist 144 and structuring steps can be used. After formation, the vias 138A of the UBMs 138 have a thickness T1 equal to the depth D1 of the openings 140. The ratio of the thickness T1 to the width W1 can be referred to as the aspect ratio of the vias 138A of the UBMs 138. In some embodiments, the aspect ratio of the openings 140 is in the range of approximately 1.33 to approximately 1.66. In an experiment, an aspect ratio in the range of approximately 1.33 to approximately 1.66 reduced the mechanical stresses acting on the metallization structure 134 by approximately 14%. Furthermore, in some embodiments, the metallization structure 134 has a thickness T3 in the range of approximately 0.8 µm to approximately 4 µm. In some embodiments, the ratio of thickness T1 to thickness T3 is at least 6 and is, for example, in the range of approximately 3.5 to approximately 10. Furthermore, after formation, the hump sections 138B of the UBMs 138 have a thickness T2 that is greater than the thickness T1. In some embodiments, the thickness T2 is in the range of approximately 10 µm to approximately 40 µm, for example, approximately 30 µm. Such a thickness T2 can also help to reduce the mechanical stresses acting on the metallization structure 134. In an experiment, a thickness T2 of approximately 30 µm reduced the mechanical stresses acting on the metallization structure 134 by approximately 10%. The ratio of thickness T2 to thickness T1 is large. In some embodiments, the ratio of thickness T2 to thickness T1 is at least 1.5 and is, for example, in the range of approximately 1.5 to approximately 2.33. Furthermore, after formation, the via sections 138A of the UBMs 138 have the same width W1 as the openings 140. The ridge sections 138B of the UBMs 138 have a small average width W2. In some embodiments, the width W2 is at least 50 µm and, for example, ranges from about 70 µm to about 105 µm. In an experiment, a width W2 of about 82 µm reduced the mechanical stresses acting on the metallization structure 134 by about 10%. The width W2 is greater than the width W1. A small average width W2 allows the distance between adjacent UBMs 138 to be increased. The risk of solder bridging between UBMs 138 through subsequently formed conductive connectors can thus be reduced. The ratio of width W2 to width W1 is large. In some embodiments, the ratio of width W2 to width W1 is at least 2.5 and is, for example, in the range of about 2.5 to about 3.6.Furthermore, after formation, the UBMs 138 have a combined thickness TC, which is the sum of the thicknesses T1 and T2. In some embodiments, the combined thickness TC is in the range of approximately 20 µm to approximately 70 µm. The ratio of the combined thickness TC to the width W1 is large. In some embodiments, the ratio of the combined thickness TC to the width W1 is at least 0.2 and, for example, is in the range of approximately 0.2 to approximately 3.3. In an experiment, a combined thickness TC of approximately 50 µm in combination with a width W1 of approximately 15 µm reduced the mechanical stresses acting on the metallization structure 134 by approximately 15%. As noted above, the different values ​​and ratios of the UBMs 138 allow the mechanical reliability of the front redistribution structure 122 to be increased. In an experiment, the combination of the aspect ratio of the openings 140 in the range of approximately 1.33 to approximately 1.66, the ratio of thickness T1 to thickness T3 in the range of approximately 3.5 to approximately 10, and the ratio of thickness T2 to thickness T1 in the range of approximately 1.5 to approximately 2.33 allowed the UBMs 138 to withstand a thermal stress test of over 2000 times without any component failure. Fig. 14 illustrates the UBMs 138 according to some other embodiments. Several UBMs 138 are shown in a detailed view of a first region 10A and a second region 10B of the first package component 100. It is understood that some details have been omitted or enlarged for clarity. In this embodiment, the ridge sections 138B of the UBMs 138 have the same width W2 and thickness T2 in both regions 10A and 10B. Furthermore, the via sections 138A of the UBMs 138 have the same thickness T1 in both regions 10A and 10B. However, the via sections 138A of the UBMs 138 have different widths in regions 10A and 10B. For example, the via sections 138A of the UBMs 138 in the first region 10A have a first width W1A, and the via sections 138A of the UBMs 138 in the second region 10B have a second width W1B.The widths W1A and W1B differ by a significant amount. In some embodiments, the difference between the widths W1A and W1B is at least 5 µm and ranges, for example, from approximately 25 µm to approximately 45 µm. The via sections of narrower widths are located in regions subject to higher mechanical stress. For example, if the first region 10A is subject to higher mechanical stress than the second region 10B, then the width W1A is smaller than the width W1B. Fig. 15 illustrates a UBM 138 according to several other embodiments. A single UBM 138 is shown in a detailed view of a region of the first package component 100. It is understood that some details have been omitted or enlarged for clarity. Furthermore, multiple UBMs 138 can be formed simultaneously. In this embodiment, the UBMs 138 have multiple vias 138A, each having the same width W1. Each of the vias 138A for a given UBM 138 contacts an identical support pad of the metallization structure 134. The UBMs 138 can have any number of vias 138A, such as a number in the range of 2 to 4. The additional vias 138A can help to buffer mechanical stresses that would otherwise act on the intermetallization structures of the front-side redistribution structure 122.Cracking and delamination in the front redistribution structure 122 can thus be avoided. Fig. 16 illustrates a UBM 138 according to several other embodiments. A single UBM 138 is shown in a detailed view of a region of the first package component 100. It is understood that some details have been omitted or enlarged for clarity. Furthermore, several UBMs 138 can be formed simultaneously. In this embodiment, the UBMs 138 have several via sections 138A, each with a different width. For example, the UBMs 138 can have a first via section with a first width W1C and a second via section with a second width W1C. The widths W1C and W1C can differ. In some embodiments, the difference between the widths W1C and W1C is at least 5 µm and is, for example, in the range of about 25 µm to about 45 µm. Figures 17A to 17O are top views of the UBMs 138 according to the embodiments of Figures 15 and 16. The via sections 138A and the ridge sections 138B of the UBMs 138 can have several possible shapes in the top view. Furthermore, the via sections 138A and the ridge sections 138B of the UBMs 138 can have the same shapes in the top view or they can have different shapes in the top view. The via sections 138A can have circular shapes (see Figures 17A to 17E), four-sided / square shapes (see Figures 17F to 17J), and / or octagonal shapes (see Figures 17K to 17O). A single UBM 138 can contain several via sections 138A of different shapes. Likewise, the hump sections 138B can be circular shapes (see Fig. 17A, Fig. 17F and Fig. 17K), oval shapes (see Fig. 17B, Fig. 17G and Fig. 17L), octagonal shapes (see Fig. 17C, Fig. 17H and Fig. 17M), hexagonal shapes (see Fig.17D, Fig. 17I and Fig. 17N) and / or four-sided / square shapes (see Fig. 17E, Fig. 17J and Fig. 17O). Furthermore, UBMs 138 having cusp sections 138B of different shapes can be combined on the same package. In Fig. 18, conductive connectors 150 are formed on the UBMs 138. The conductive connectors 150 can be ball grid array (BGA) connectors, solder beads, metal columns, controlled collapse chip connection (C4) bumps, micro-bumps, bumps formed using electroless nickel-electroless palladium immersion gold (ENEPIG) technology, or the like. The conductive connectors 150 can contain a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 150 are formed by first forming a layer of solder by common methods such as evaporation, electroplating, printing, solder transfer, bead arrangement, or the like. After a layer of solder has been formed on the structure, remelting can be performed to bring the material into the desired bump shapes.In another embodiment, the conductive connectors comprise 150 metal columns (such as copper columns) formed by sputtering, printing, electroplating, chemical plating, CVD, or the like. The metal columns may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on the metal columns. The metal capping layer may contain nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process. Figure 19 shows a carrier substrate debonding process to separate (or debond) the carrier substrate 102 from the rear-side redistribution structure 106, for example, the dielectric layer 108. According to some embodiments, the debonding process involves projecting light, such as laser light or UV light, onto the separating layer 104, causing the separating layer 104 to decompose under the heat of the light and allowing the carrier substrate 102 to be removed. The structure is then inverted and arranged on a tape. In Fig. 20, conductive connectors 152 are formed that extend through the dielectric layer 108 to contact the metallization structure 110. Openings are formed through the dielectric layer 108 to expose sections of the metallization structure 110. The openings can be formed, for example, using laser drilling, etching, or the like. The conductive connectors 152 are formed in the openings. In some embodiments, the conductive connectors 152 comprise flux and are formed in a flux dipping process. In other embodiments, the conductive connectors 152 comprise a conductive paste, such as solder paste, silver paste, or the like, and are deposited in a printing process.In some embodiments, the conductive connectors 152 are formed in a similar manner to the conductive connectors 150 and can be formed from the same material as the conductive connectors 150. Figures 21 and 22 illustrate the formation and implementation of device stacks according to some embodiments. The device stacks are formed from the integrated circuit packages that are formed in the first package component 100. The device stacks can also be referred to as package-on-package (PoP) structures. Because the PoP structures contain InFO packages, they can also be referred to as InFO-PoP structures. In Fig. 21, second package components 200 are coupled to the first package component 100. One of the second package components 200 is coupled in each of the package regions 100A and 100B to form an IC device stack in each region of the first package component 100. The second package components 200 contain a substrate 202 and one or more stacked dies 210 (210A and 210B) coupled to the substrate 202. Although a single set of stacked dies 210 (210A and 210B) is illustrated, in other embodiments several stacked dies 210 (each of which may have one or more stacked dies) can be arranged side by side, coupled to the same area of ​​the substrate 202. The substrate 202 can be made of a semiconductor material, such as silicon, germanium, diamond, or the like. In some embodiments, composite materials, such as silicon-germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon-germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like, can also be used. Furthermore, substrate 202 can be a silicon-on-insulator (SOI) substrate.In general, an SOI substrate contains a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon-germanium, SOI, silicon-germanium on insulator (SGOI), or combinations thereof. In an alternative embodiment, substrate 202 is based on an insulating core, such as a glass fiber-reinforced resin core. An example of a core material is glass fiber resin, such as FR4. Alternatives for the core material include bismaleimide triazine (BT) resin or, alternatively, other printed circuit board (PCB) materials or films. Build-up films, such as Ajinomoto Build-up Film (ABF), or other laminates can be used for substrate 202. The substrate 202 can contain (not shown) active and passive components. A wide variety of different components, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to generate the structural and functional design requirements for the semiconductor package 300. The components can be fabricated using any suitable methods. The substrate 202 can also include (not shown) metallization layers and vias 208. The metallization layers can be formed over the active and passive components and are designed to connect the various components to create a functional circuit. The metallization layers can be formed from alternating layers of dielectric material (for example, dielectric material with a low k-value) and conductive material (for example, copper) with vias connecting the conductive material layers, and can be formed by any suitable process (such as deposition, damascening, dual damascening, or the like). In some embodiments, the substrate 202 is essentially free of active and passive components. The substrate 202 can have bonding pads 204 on a first side of the substrate 202 for coupling with the stacked dies 210, and bonding pads 206 on a second side of the substrate 202, the second side being opposite the first side of the substrate 202 for coupling with the conductive connectors 152. In some embodiments, the bonding pads 204 and 206 are formed by creating recesses in dielectric layers (not shown) on the first and second sides of the substrate 202. The recesses can be formed so that the bonding pads 204 and 206 can be embedded in the dielectric layers. In other embodiments, the recesses are omitted, since the bonding pads 204 and 206 can be formed on the dielectric layer.In some embodiments, the bonding pads 204 and 206 contain a thin nucleation layer of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bonding pads 204 and 206 can be deposited over the thin nucleation layer. The conductive material can be formed by an electrochemical plating process, a chemical plating process, CVD, atomic layer deposition (ALD), PVD, the like, or a combination thereof. In one embodiment, the conductive material of the bonding pads 204 and 206 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof. In one embodiment, the bonding pads 204 and 206 are UBMs containing three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement, can also be used to form the bonding pads 204 and 206. Any suitable materials or layers of material that can be used for the bonding pads 204 and 206 are intended to be fully included within the scope of this application. In some embodiments, the conductive vias 208 extend through the substrate 202 and couple at least one of the bonding pads 204 to at least one of the bonding pads 206. In the illustrated embodiment, the stacked dies 210 are coupled to the substrate 202 by wire bonds 212, although other connections, such as conductive bumps, can also be used. In one embodiment, the stacked dies 210 are stacked memory dies. For example, the stacked dies 210 can be memory dies, such as low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or similar memory modules. The stacked dies 210 and the wire bonds 212 can be encapsulated by a potting material 214. The potting material 214 can be applied to the stacked dies 210 and the wire bonds 212, for example, using molds. In some embodiments, the potting material 214 is a potting compound, a polymer, an epoxy, a silicon dioxide filler, the like, or a combination thereof. A curing process can be carried out to cure the potting material 214; the curing process can be thermal curing, UV curing, the like, or a combination thereof. In some embodiments, the stacked dies 210 and the wire bonds 212 are buried in the potting material 214, and after the potting material 214 has hardened, a planarization step, such as grinding, is performed to remove excess sections of the potting material 214 and to provide a substantially planar surface for the second package components 200. After the second package components 200 have been formed, they are mechanically and electrically bonded to the first package component 100 by means of the conductive connectors 152, the bonding pads 206, and the rear redistribution structure 106. In some embodiments, the stacked dies 210 can be coupled to the integrated circuit dies 50A and 50B by means of the wire bonds 212, the bonding pads 204 and 206, the conductive vias 208, the conductive connectors 152, the rear redistribution structure 106, the vias 116, and the front redistribution structure 122. In some embodiments, a solder resist is formed on the side of the substrate 202 opposite the stacked dies 210. The conductive connectors 152 can be arranged in openings in the solder resist to be electrically and mechanically coupled to conductive structural elements (for example, the bonding pads 206) in the substrate 202. The solder resist can be used to protect areas of the substrate 202 from external damage. In some embodiments, an epoxy flux is formed on the conductive connectors 152 before they are remelted, with at least part of the epoxy section of the epoxy flux remaining after the second package components 200 have been attached to the first package component 100. In some embodiments, an underfill is formed between the first package component 100 and the second package components 200, surrounding the conductive connectors 152. The underfill can reduce stresses and protect the joints created by the remelting of the conductive connectors 152. The underfill can be formed by a capillary flow process after the second package components 200 have been applied, or it can be formed by a suitable deposition process before the second package components 200 are applied. In embodiments where the epoxy flux is present, it can act as the underfill. In Fig. 22, a singulation process is performed by sawing along scribing line regions, for example, between the first package region 100A and the second package region 100B. The sawing separates the first package region 100A from the second package region 100B. The resulting singulated stack of devices originates from either the first package region 100A or the second package region 100B. In some embodiments, the singulation process is performed after the second package components 200 have been coupled to the first package component 100. In other embodiments, the singulation process is performed before the second package components 200 are coupled to the first package component 100, for example, after the carrier substrate 102 has been unbonded and the conductive connectors 152 have been formed. Each individual first package component 100 is then mounted on a package substrate 300 using the conductive connectors 150. The package substrate 300 contains a substrate core 302 and bonding pads 304 over the substrate core 302. The substrate core 302 can be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon-germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon-germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like can be used. Furthermore, the substrate core 302 can be an SOI substrate. In general, an SOI substrate contains a layer of a semiconductor material such as epitaxial silicon, germanium, silicon-germanium, SOI, SGOI, or combinations thereof.In an alternative embodiment, the substrate core 302 is based on an insulating core, such as a glass fiber-reinforced resin core. An example of a core material is glass fiber resin, such as FR4. Alternative core materials include bismaleimide triazine (BT) resin or other PCB materials or films. Build-up films, such as ABF or other laminates, can be used for the package substrate 302. The substrate core 302 can contain (not shown) active and passive components. As the average person will understand, a wide variety of different components, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to generate the structural and functional requirements for the design of the device stack. The components can be formed using any suitable methods. The substrate core 302 can also include metallization layers and vias (not shown), wherein the bonding pads 304 are physically and / or electrically coupled to the metallization layers and vias. The metallization layers can be formed over the active and passive components and are designed to connect the various components to create a functional circuit. The metallization layers can be formed from alternating layers of dielectric material (for example, a dielectric material with a low k-value) and conductive material (for example, copper), with vias connecting the conductive material layers, and can be formed by any suitable process (such as deposition, damascening, dual damascening, or the like). In some embodiments, the substrate core 302 is essentially free of active and passive components. In some embodiments, the conductive connectors 150 are remelted to attach the first package component 100 to the bonding pads 304. The conductive connectors 150 couple the package substrate 300, which contains metallization layers in the substrate core 302, electrically and / or physically to the first package component 100. In some embodiments, a solder resist 306 is formed on the substrate core 302. The conductive connectors 150 can be arranged in openings in the solder resist 306 to be electrically and mechanically coupled to the bonding pads 304. The solder resist 306 can be used to protect areas of the substrate 202 from external damage. An epoxy flux (not shown) can be formed on the conductive connectors 150 before they are remelted, with at least a portion of the epoxy flux remaining after the first package component 100 has been attached to the package substrate 300. This remaining epoxy portion can act as an underfill to reduce stress and protect the joints created by the remelting of the conductive connectors 150. In some embodiments, an underfill 308 can be formed between the first package component 100 and the package substrate 300, surrounding the conductive connectors 150. The underfill 308 can be formed by a capillary flow process after the first package component 100 has been attached, or it can be formed by a suitable deposition process before the first package component 100 is attached. In some embodiments, passive components (for example, surface-mount devices (SMDs), not illustrated) can also be attached to the first package component 100 (for example, to the UBMs 138) or to the package substrate 300 (for example, to the bonding pads 304). For example, the passive components can be bonded to the same surface of the first package component 100 or the package substrate 300 as the conductive connectors 150. The passive components can be attached to the package component 100 before the first package component 100 is mounted on the package substrate 300, or they can be attached to the package substrate 300 before or after the first package component 100 is mounted on the package substrate 300. It is understood that the first package component 100 can also be implemented in other device stacks. For example, a PoP structure is shown, but the first package component 100 can also be implemented in a Flip Chip Ball Grid Array (FCBGA) package. In such embodiments, the first package component 100 is mounted on a substrate such as the package substrate 300, but the second package component 200 is omitted. Instead, a cover or heat spreader can be attached to the first package component 100. If the second package component 200 is omitted, the rear-side redistribution structure 106 and the vias 116 can also be omitted. Other features and processes may also be included. For example, test structures may be integrated to support verification testing of the 3D packaging or 3DIC devices. These test structures may include, for instance, test pads formed in a redistribution layer or on a substrate, enabling testing of the 3D packaging or 3DIC, the use of probes and / or probing cards, and the like. Verification tests can be performed on intermediate structures as well as on the finished structure. Furthermore, the structures and methods disclosed herein may be used in conjunction with test methodologies that include intermediate verification of "known good dies" to increase production yield and reduce costs. Fig. 23 illustrates a device stack according to some other embodiments. In this embodiment, the rear-side redistribution structure 106, the vias 116, and the second package components 200 are omitted. Furthermore, the first package component 100 contains a first integrated circuit die 50A (for example, a logic device) and several second integrated circuit dies 50B (for example, memory devices). The second integrated circuit dies 50B are, in this embodiment, stacked devices, such as memory cubes, containing several semiconductor substrates 52 and an interconnect structure 60. Embodiments can realize advantages. The first package component 100 and the package substrate 300 may have mismatched coefficients of thermal expansion (CTE). The difference can be large. For example, in some embodiments, the first package component 100 may have a CTE in the range of 10 to 30 ppm, and the package substrate 300 may have a CTE in the range of 3 to 17 ppm. A large CTE difference causes mechanical stresses to be exerted on the front redistribution structure 122 during testing or operation. The increased thickness of the dielectric layer 136 allows it to buffer these mechanical stresses. Cracking and delamination in the front redistribution structure 122 can thus be avoided, and the average widths of the UBMs 138 can be reduced.By reducing the average widths of the UBMs 138, the amount of the metallization structure 134 contacted by the UBMs 138 can be reduced. The amount of the metallization structure 134 available for signal routing can thus be increased. Reducing the widths of the UBMs 138 also reduces the risk of solder bridging between the UBMs 138 via the conductive connectors 150. In one embodiment, a device comprises: an integrated circuit die; an encapsulation material that at least partially encapsulates the integrated circuit die; a conductive via extending through the encapsulation material; a redistribution structure on the encapsulation material, wherein the redistribution structure comprises: a metallization structure that is electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization structure, wherein the dielectric layer has a first thickness of 10 µm to 30 µm;and a first solder metallization (under-bump metallurgy, UBM) comprising a first through-hole section extending through the dielectric layer and a first bump section on the dielectric layer, wherein the first UBM is physically and electrically coupled to the metallization structure, wherein the first through-hole section has a first width, wherein the ratio of the first thickness to the first width is 1.33 to 1.66. In some embodiments of the device, the first hump section has a second width, wherein the ratio of the second width to the first width is at least 2.5. In some embodiments of the device, the first width is in the range of 20 µm to 25 µm. In some embodiments of the device, the second width is in the range of 70 µm to 105 µm. In some embodiments of the device, the first hump section has a second thickness, wherein the ratio of the second thickness to the first thickness is at least 1.5. In some embodiments of the device, the second thickness is in the range of 10 µm to 40 µm. In some embodiments of the device, the metallization structure has a third thickness, wherein the ratio of the first thickness to the third thickness is at least 6. In some embodiments of the device, the third thickness is in the range of 0.8 µm to 4 µm.In some embodiments of the device, the redistribution structure further comprises: a second UBM having a second via section extending through the dielectric layer and a second bump section on the dielectric layer, wherein the second UBM is physically and electrically coupled to the metallization structure, wherein the second via section has a second width, the second width being at least 5 µm larger than the first width.In some embodiments of the device, the first UBM further has a second via section extending through the dielectric layer, wherein a portion of the dielectric layer is located between the first and second via sections, and the first and second via sections of the first UBM contact the same support pad of the metallization structure. In some embodiments of the device, the second via section has the same width as the first via section. In some embodiments of the device, the second via section has a second width, wherein the second width is at least 5 µm larger than the first width.In some embodiments of the device, the first ridge section, the first via section, and the second via section of the first UBM have the same shape in a top view. In some embodiments of the device, the first ridge section of the first UBM has a first shape in a top view, and the first via section and the second via section of the first UBM have a second shape in a top view, the first shape being different from the second shape. In one embodiment, a method comprises: forming a conductive via extending from a support substrate; arranging an integrated circuit die adjacent to the conductive via; encapsulating the integrated circuit die and the conductive via with an encapsulation material; depositing a first dielectric layer on the encapsulation material; structuring first openings in the first dielectric layer that expose the integrated circuit die and the conductive via; forming a metallization structure in the first openings and along the first dielectric layer, wherein the metallization structure electrically couples the conductive via and the integrated circuit die; depositing a second dielectric layer on the metallization structure, wherein the second dielectric layer has a first thickness of 10 µm to 30 µm;Structuring a second opening in the second dielectric layer, which exposes the metallization structure, wherein the second opening has a first width, wherein the ratio of the first thickness to the first width is 1.33 to 1.66; and forming a first solder metallization (under-bump metallurgy, UBM) in the second opening and along the second dielectric layer, wherein the first UBM is physically and electrically coupled to the metallization structure. In some embodiments, the method further comprises: structuring a third opening in the second dielectric layer, which exposes the metallization structure, wherein the formation of the first UBM further comprises forming the first UBM in the third opening. In some embodiments, the method further comprises: structuring a third opening in the second dielectric layer, which exposes the metallization structure, wherein the third opening has a second width, the second width being smaller than the first width; and forming a second UBM in the third opening and along the second dielectric layer, wherein the second UBM is physically and electrically coupled to the metallization structure. In one embodiment, a method comprises: forming a conductive via extending from a support substrate; arranging an integrated circuit die adjacent to the conductive via; encapsulating the integrated circuit die and the conductive via with an encapsulation material; forming a metallization structure that electrically couples the conductive via and the integrated circuit die; depositing a dielectric layer onto the metallization structure; structuring first openings in the dielectric layer that expose a support pad of the metallization structure, each of the first openings having a different width; and forming a mask over the dielectric layer, the mask having a second opening that exposes each of the first openings.and plating with an under-bump metallurgy (UBM) in the first openings and the second opening, wherein sections of the UBM in the first openings each have a first shape in a top view, wherein a section of the UBM in the second opening has a second shape in a top view, the second shape being different from the first shape. In some embodiments of the method, the dielectric layer has a first thickness of 10 µm to 30 µm. In some embodiments of the method, the ratio of the first thickness to the width of each of the first openings is in the range of 1.33 to 1.66.

Claims

Device comprising: an integrated circuit die (50, 50A, 50B); an encapsulation material (120) that at least partially encapsulates the integrated circuit die (50, 50A, 50B); a conductive via (116) extending through the encapsulation material (120); a redistribution structure (122) on the encapsulation material (120), wherein the redistribution structure (122) comprises: a metallization structure (126, 130, 134) that is electrically coupled to the conductive via (116) and the integrated circuit die (50, 50A, 50B); a dielectric layer (136) on the metallization structure (126, 130, 134), wherein the dielectric layer (136) has a first thickness (T1) of 10 µm to 30 µm;and a first solder metallization, under-bump metallurgy, UBM (138) comprising a first through-hole section (138A) extending through the dielectric layer (136) and a first bump section (138B) on the dielectric layer (136), wherein the first UBM (138) is physically and electrically coupled to the metallization structure (126, 130, 134), wherein the first through-hole section (138A) has a first width (W1) with a ratio of the first thickness (T1) to the first width (W1) of 1.33 to 1.66, and wherein the first bump section (138B) has a second width (W2) with a ratio of the second width (W2) to the first width (W1) in a range of 2.5 to 3.

6. Device according to claim 1, wherein the first width (W1) is in the range of 20 µm to 25 µm. Device according to claim 1 or 2, wherein the second width (W2) is in the range of 70 µm to 105 µm. Device according to one of the preceding claims, wherein the first hump section (138B) has a second thickness (T2), wherein the ratio of the second thickness (T2) to the first thickness (T1) is at least 1.

5. Device according to claim 4, wherein the second thickness (T2) is in the range of 10 µm to 40 µm. Device according to claim 4 or 5, wherein the metallization structure (126, 130, 134) has a third thickness (T3), wherein the ratio of the first thickness (T1) to the third thickness (T3) is at least 6. Device according to claim 6, wherein the third thickness (T3) is in the range of 0.8 µm to 4 µm. Device according to one of the preceding claims, wherein the redistribution structure (122) further comprises: a second UBM (138) having a second via section (138A) extending through the dielectric layer (136) and a second bump section (138B) on the dielectric layer (136), wherein the second UBM (138) is physically and electrically coupled to the metallization structure (126, 130, 134), wherein the second via section (138A) has a second width (W2), wherein the second width (W2) is at least 5 µm larger than the first width (W1). Device according to one of the preceding claims, wherein the first UBM (138) further comprises a second via section (138A) extending through the dielectric layer (136), wherein a section of the dielectric layer (136) is located between the first via section (138A) and the second via section (138A), and the first via section (138A) and the second via section (138A) of the first UBM (138) contact the same support pad of the metallization structure (126, 130, 134). Device according to claim 9, wherein the second via section (138A) has the same width (W1) as the first via section (138A). Device according to claim 9, wherein the second via section (138A) has a second width (W1C), wherein the second width (W1C) is at least 5 µm larger than the first width (W1, W1D). Device according to one of the preceding claims 9 to 11, wherein the first ridge section (138B), the first via section (138A) and the second via section (138A) of the first UBM (138) have the same shape in a top view. Device according to one of the preceding claims 9 to 11, wherein the first hump section (138B) of the first UBM (138) has a first shape in a top view, and the first via section (138A) and the second via section (138A) of the first UBM (138) have a second shape in a top view, wherein the first shape is different from the second shape. A method comprising: forming a conductive via (116) extending from a support substrate (102); arranging an integrated circuit die (50, 50A, 50B) adjacent to the conductive via (116); encapsulating the integrated circuit die (50, 50A, 50B) and the conductive via (116) with an encapsulation material (120); depositing a first dielectric layer (124) on the encapsulation material (120); structuring first openings in the first dielectric layer (124) exposing the integrated circuit die (50, 50A, 50B) and the conductive via (116); forming a metallization structure (126, 130, 134) in the first openings and along the first dielectric layer (124) wherein the metallization structure (126, 130, 134) electrically couples the conductive via (116) and the integrated circuit die (50, 50A, 50B);Deposition of a second dielectric layer (136) on the metallization structure (126, 130, 134), wherein the second dielectric layer (136) has a first thickness (D1) of 10 µm to 30 µm; structuring a second opening (140) in the second dielectric layer (136) which exposes the metallization structure (126, 130, 134), wherein the second opening (140) has a first width (W1, W1C), wherein the ratio of the first thickness (D1) to the first width (W1, W1C) is 1.33 to 1.66;and forming a first solder metallization, under-bump metallurgy, UBM (138), in the second opening (140) and along the second dielectric layer (136), wherein the first UBM has a first bump section (138B) with a second width (W2) on the second dielectric layer (136) and a ratio of the second width (W2) to the first width (W1,W1C) is in a range of 2.5 to 3.6, wherein the first UBM (138) is physically and electrically coupled to the metallization structure (126, 130, 134). The method of claim 14, further comprising: structuring a third opening (140) in the second dielectric layer (136) which exposes the metallization structure (126, 130, 134), wherein the formation of the first UBM (138) further comprises forming the first UBM (138) in the third opening (140). A method according to claim 14 or 15, further comprising: structuring a third opening (140) in the second dielectric layer (136) which exposes the metallization structure (126, 130, 134), wherein the third opening (140) has a second width (W1D) wherein the second width (W1D) is smaller than the first width (W1,W1C); and forming a second UBM (138) in the third opening and along the second dielectric layer, wherein the second UBM is physically and electrically coupled to the metallization structure (126, 130, 134). A method comprising: forming a conductive via (116) extending from a support substrate (102); arranging an integrated circuit die (50, 50A, 50B) adjacent to the conductive via (116); encapsulating the integrated circuit die (50, 50A, 50B) and the conductive via (116) with an encapsulation material (120); forming a metallization structure (126, 130, 134) that electrically couples the conductive via (116) and the integrated circuit die (50, 50A, 50B); depositing a dielectric layer (136) on the metallization structure (126, 130, 134); structuring first openings (140) in the dielectric layer (136) that provide a Expose the support pad of the metallization structure (126, 130, 134), each of the first openings (140) having a different width (W1A, W1B, W1C);and forming a mask (144) over the dielectric layer (136), wherein the mask (144) has a second opening (146) that exposes each of the first openings (140); and plating a solder metallization, under-bump metallurgy, UBM (138), in the first openings (140) and the second opening (146), wherein sections of the UBM (138) in the first openings (140) each have a first shape in a top view, wherein a section of the UBM (138) in the second opening (146) has a second shape in a top view, the second shape being different from the first shape. Method according to claim 17, wherein the dielectric layer (136) has a first thickness (D1) of 10 µm to 30 µm. Method according to claim 18, wherein the ratio of the first thickness (D1) to the width (W1) of each of the first openings is in the range of 1.33 to 1.66.

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