Pixel circuit and CMOS image sensor

Abstract

The pixel circuit provided by the embodiment comprises a photodiode, a transfer gate, a floating diffusion region, a reset transistor, a charge storage element, an amplification transistor and a selection transistor; the transfer gate is coupled to a cathode of the photodiode and a gate of the amplification transistor; the floating diffusion region, a source of the reset transistor and the charge storage element are respectively coupled to a signal line connected between the transfer gate and the gate of the amplification transistor in a branch mode; and a drain of the selection transistor is coupled to a source of the amplification transistor.

Description

Technical Field

[0001] This invention relates to pixel circuits and CMOS image sensors. Background Technology

[0002] A four-transistor CMOS image sensor is known. A CMOS image sensor typically includes a photodiode and a floating diffusion region. When light shines on the photodiode, it generates a charge, which is then stored within the photodiode. This charge is subsequently transferred to the floating diffusion region through a transfer gate located between the photodiode and the floating diffusion region, which acts as a capacitor. Finally, the charge transferred to the floating diffusion region is output as a signal potential, which is used to determine the amount of light incident on the photodiode. The dynamic range of a CMOS image sensor with this configuration is limited by the amount of charge that the floating diffusion region can store.

[0003] To improve dynamic range, a method has been proposed that combines frames obtained from short exposures with frames obtained from long exposures. However, this method requires reading two frames, leading to a significant increase in power consumption. Furthermore, if the object to be imaged is moving, the time difference between the two frames may result in an image that differs from the actual image.

[0004] Typically, a reset transistor is placed between the floating diffusion region and the power supply voltage line. However, in another conventional technique, a configuration has been proposed that provides two reset transistors and an additional capacitor between them. When the first reset transistor between the floating diffusion region and the additional capacitor is turned on, the charge overflowing from the floating diffusion region is stored in the additional capacitor, thereby extending the dynamic range. However, in addition to the increased structural complexity, two readout operations are required: reading the high-gain signal from the floating diffusion region and reading the low-gain signal from the additional capacitor. This also leads to a significant increase in power consumption. Summary of the Invention

[0005] This invention provides a CMOS image sensor with wide dynamic range pixels.

[0006] The pixel circuit according to the first aspect includes: a photodiode; a transfer gate; a floating diffusion region; a reset transistor; a charge storage element; an amplifying transistor; and a selecting transistor. The transfer gate is coupled to the cathode of the photodiode and the floating diffusion region. The charge storage layer of the charge storage element is coupled to the floating diffusion region. The floating diffusion region, the source of the reset transistor, and the gate of the amplifying transistor are coupled to each other. The drain of the selecting transistor is coupled to the source of the amplifying transistor.

[0007] In the pixel circuit according to the above aspects, the charge storage element may be a MOS capacitor or a PN junction capacitor.

[0008] In the pixel circuit according to the above aspects, when the potentials of the photodiode, the floating diffusion region, and the charge storage element are reset, the potential of the floating diffusion region may be higher than the potential of the charge storage element for minority carriers.

[0009] In the pixel circuit according to the above aspects, the photodiode may have a junction capacitance, and a portion of the signal charge generated by the photodiode may be stored in the junction capacitance.

[0010] In the pixel circuit according to the above aspects, when the potentials of the photodiode, the floating diffusion region, and the charge storage element are reset, for minority carriers, the potential of the floating diffusion region may be higher than the potential of the charge storage element; for the minority carriers, the potentials of the floating diffusion region and the charge storage element may be higher than the potential of the junction capacitance.

[0011] The pixel circuit according to the above aspects may further include a signal compensation unit. The signal compensation unit may be coupled to the source of the selection transistor. When the potential applied to the floating diffusion region exceeds the reset potential of the charge storage element, the signal compensation unit can compensate the output signal into a compensation signal. The compensation signal may be obtained by subtracting the offset from the value of the output signal and then multiplying it by the gain.

[0012] The pixel circuit according to the above aspects may also include an attenuator. The attenuator may be coupled to the source of the selection transistor.

[0013] The pixel circuit according to the second aspect includes: a photodiode; a transmission gate; a floating diffusion region; a reset transistor; an amplifying transistor; and a selection transistor. The transmission gate is coupled to the cathode of the photodiode and the floating diffusion region. The transmission gate includes a first transmission gate region coupled to the cathode of the photodiode and a second transmission gate region coupled to the floating diffusion region. In the state where the transmission gate is off, the potential of the second transmission gate region is between the potential of the first transmission gate region and the potential of the floating diffusion region. The floating diffusion region, the source of the reset transistor, and the gate of the amplifying transistor are coupled to each other. The drain of the selection transistor is coupled to the source of the amplifying transistor.

[0014] In the pixel circuit according to the above aspects, the first transmission gate region and the second transmission gate region are doped with different amounts of impurities, or the transmission gate includes a first transmission gate electrode corresponding to the first transmission gate region and a second transmission gate electrode corresponding to the second transmission gate region, and the voltage applied to the first transmission gate electrode and the voltage applied to the second transmission gate electrode are different from each other.

[0015] The pixel circuit according to the above aspects may further include a signal compensation unit. The signal compensation unit may be coupled to the source of the selection transistor. When the potential applied to the floating diffusion region exceeds the reset potential of the second transmission gate region, the signal compensation unit may compensate the output signal into a compensation signal. The compensation signal may be obtained by subtracting an offset from the value of the output signal and then multiplying it by the gain.

[0016] The pixel circuit according to the above aspects may also include an attenuator. The attenuator may be coupled to the source of the selection transistor.

[0017] The CMOS image sensor according to the third aspect includes the pixel circuit according to the above aspects.

[0018] The operation method of the pixel circuit according to the fourth aspect includes: storing a charge generated by light irradiating the photodiode in a photodiode; turning on a transmission gate to transfer the charge stored in the photodiode to a floating diffusion region; storing the charge in the floating diffusion region and a charge storage element coupled to the floating diffusion region when the potential of the floating diffusion region exceeds the potential of the charge storage element due to the transfer of the charge; and amplifying the potential of the floating diffusion region and the charge storage element to output the potential as an output signal.

[0019] In the method of operating the pixel circuit according to the above aspects, when the potentials of the photodiode, the floating diffusion region, and the charge storage element are reset, the potential of the floating diffusion region may be higher than the potential of the charge storage element for minority carriers.

[0020] In the method of operating the pixel circuit according to the above aspects, storing the charge in the floating diffusion region and the charge storage element may include storing a portion of the charge in the junction capacitance of the photodiode.

[0021] In the method of operating the pixel circuit according to the above aspects, when the potentials of the photodiode, the floating diffusion region, and the charge storage element are reset, for minority carriers, the potential of the floating diffusion region may be higher than the potential of the charge storage element; for the minority carriers, the potentials of the floating diffusion region and the charge storage element may be higher than the potential of the junction capacitance.

[0022] In the method of operating the pixel circuit according to the above aspects, amplifying the potential of the floating diffusion region and the charge storage element to output the potential as an output signal may include: when the potential applied to the floating diffusion region exceeds the reset potential of the charge storage element, compensating the output signal into a compensation signal obtained by subtracting the offset from the value of the output signal and then multiplying it by the gain.

[0023] In the method of operating the pixel circuit according to the above aspects, amplifying the potential of the floating diffusion region and the charge storage element to output the potential as an output signal may include attenuating the output signal.

[0024] A method of operating a pixel circuit according to a fifth aspect includes: storing a charge generated by light irradiating the photodiode in a photodiode; turning on a transfer gate to transfer the charge stored in the photodiode to a floating diffusion region, the transfer gate including a first transfer gate region and a second transfer gate region; storing the charge in the floating diffusion region and the second transfer gate region when the potential of the floating diffusion region exceeds the potential of the second transfer gate region coupled to the floating diffusion region due to the transfer of the charge; and amplifying the potential of the floating diffusion region and the second transfer gate region to output the potential as an output signal. In a state where the transfer gate is turned off, the potential of the second transfer gate region is between the potential of the first transfer gate region and the potential of the floating diffusion region. The first transfer gate region and the second transfer gate region are doped with different amounts of impurities, or the transfer gate includes a first transfer gate electrode corresponding to the first transfer gate region and a second transfer gate electrode corresponding to the second transfer gate region, and the voltage applied to the first transfer gate electrode and the voltage applied to the second transfer gate electrode are different from each other.

[0025] The method of operating a CMOS sensor according to the sixth aspect includes a method of operating a pixel circuit according to any of the above aspects. Attached Figure Description

[0026] Figure 1 A schematic diagram of a CMOS image sensor according to a first embodiment is shown; Figure 2 A circuit diagram of a pixel circuit according to a first embodiment is shown; Figure 3 A timing diagram of the pixel circuit according to the first embodiment is shown; Figure 4 A structural diagram and a potential distribution diagram of the pixel circuit according to the first embodiment are shown; Figure 5 The time variation of the structure diagram and potential distribution diagram of the pixel circuit according to the first embodiment is shown; Figure 6 The dependence of signal charge on the voltage applied to the gate of the amplifying transistor of the pixel circuit according to the first embodiment (which is the same as the potential of the N-type layer of the floating diffusion region) is shown. Figure 7 A circuit diagram of the pixel circuit according to the first comparison example is shown; Figure 8 A structural diagram and a potential distribution diagram of the pixel circuit according to the first comparison example are shown; Figure 9 The time variation of the voltage applied to the gate of the amplifying transistor of the pixel circuit according to the first comparison example is shown (which is the same as the potential of the N-type layer of the floating diffusion region). Figure 10 A timing diagram of the pixel circuit according to the second comparison example is shown; Figure 11 A circuit diagram of the pixel circuit according to the third comparison example is shown; Figure 12 A circuit diagram of the pixel circuit according to the third comparison example is shown; Figure 13 The time variation of the structure diagram and potential distribution diagram of the pixel circuit according to the second embodiment is shown; Figure 14 The dependence of signal charge on the voltage applied to the gate of the amplifying transistor of the pixel circuit according to the second embodiment (which is the same as the potential of the N-type layer of the floating diffusion region) is shown. Figure 15 The time variation of the structure diagram and potential distribution diagram of the pixel circuit according to the third embodiment is shown; Figure 16 A circuit diagram of a pixel circuit according to a fourth embodiment is shown; Figure 17 An example of compensating the output signal of the pixel circuit according to the fourth embodiment is shown; Figure 18 A circuit diagram of a pixel circuit according to a fifth embodiment is shown.

[0027] Example The present embodiment will be explained in detail below with reference to the accompanying drawings. To make the features clearer, the drawings used in the following description may show enlarged features. The size ratios of the components may differ from the actual size ratios of the components. The materials, dimensions, etc., listed in the following description are merely examples, and the present invention is not limited thereto. As long as the effects of the present invention can be achieved, the materials and dimensions can be adjusted within an appropriate range.

[0028] (First embodiment) Figure 1 A schematic diagram of a CMOS image sensor 1 according to a first embodiment is shown. In this embodiment, the signal charge is electrons, and N-type elements are configured in a p-type silicon substrate. However, the invention is not limited to this configuration. The CMOS image sensor 1 includes a vertical scanning circuit 2, a pixel array 3, a digital processing circuit 4, and a horizontal scanning circuit 5. The vertical scanning circuit 2 selects one row of the pixel array 3 for signal reading. Pixel circuitry is integrated into the pixel array 3. Signals are read from each pixel in the pixel array 3. The digital processing circuit 4 includes an analog-to-digital converter for acquiring the difference between a zero level and a signal level (correlated double sampling) and converting the analog signal into a digital signal. The horizontal scanning circuit 5 selects one column of the pixel array 3 for signal reading.

[0029] Figure 2 A circuit diagram of a pixel circuit 10 according to a first embodiment is shown. The pixel circuit 10 includes a photodiode PD, a transmission gate Tx, a floating diffusion region FD, a reset transistor RS, a MOS capacitor DCG, an amplifying transistor AMP, and a selection transistor SL.

[0030] A photodiode (PD) generates charge through photoelectric conversion when exposed to light. For example, the anode of the photodiode (PD) is coupled to a reference potential. The cathode of the photodiode (PD) is coupled to the source of the transfer gate (Tx).

[0031] The transfer gate Tx is a transistor used to control the transfer of charge generated in the photodiode PD to the floating diffusion region FD. The source of the transfer gate Tx is coupled to the cathode of the photodiode PD. The drain of the transfer gate Tx (corresponding to the floating diffusion region FD) is coupled to the gate of the amplifying transistor AMP. For example, the gate of the transfer gate Tx is coupled to the vertical scanning circuit 2.

[0032] The floating diffusion region FD is a capacitor in a reverse-biased PN junction used to store charge. The floating diffusion region FD is coupled to the transfer gate Tx and to the signal line L1, which couples the floating diffusion region FD to the gate of the amplifying transistor AMP. By changing the potential of the floating diffusion region FD through stored charge, the signal charge is converted into a signal potential. The N-type layer of the floating diffusion region FD is coupled to the signal line L1, and the P-type layer side of the floating diffusion region FD is coupled to the reference potential.

[0033] The MOS capacitor DCG stores charge overflowing from the floating diffusion region FD. The substrate-side charge storage layer of the MOS capacitor DCG is coupled to the floating diffusion region FD. The floating diffusion region FD is coupled to the signal line L1, and the back gate of the MOS capacitor DCG is coupled to a reference potential. In the unstored charge state, for example, the potential of the charge storage layer (storage layer) under the gate of the MOS capacitor DCG is lower than the potential of the N-type layer of the floating diffusion region FD. The potentials of the storage layer of the MOS capacitor DCG and the N-type layer of the floating diffusion region FD can be arbitrarily set by changing the thickness, material, and doping level of the insulating layer between the electrodes of these capacitors. Furthermore, whether charge is stored in the MOS capacitor DCG can be selected by applying a voltage to the gate of the MOS capacitor DCG.

[0034] The reset transistor RS is branched and coupled to signal line L1, which connects the transmission gate Tx and the gate of the amplifying transistor AMP. When the on / off states of the reset transistor RS and the transmission gate Tx are switched, the potentials of the floating diffusion region and the photodiode PD are reset. The source of the reset transistor RS is coupled to signal line L1. The drain RD of the reset transistor RS is coupled to the power supply. The gate of the reset transistor RS is coupled to the reset line used to apply the reset pulse.

[0035] The amplifying transistor AMP amplifies the input signal from the input transistor to the gate. The amplifying transistor AMP, together with the select transistor SL, forms a source follower circuit. The source of the amplifying transistor AMP is coupled to the drain of the select transistor SL, and the drain of the amplifying transistor AMP is coupled to the power supply.

[0036] The selector transistor SL selects the pixel used to read the signal. The source of the selector transistor SL is coupled to the output signal line SO, and the drain of the selector transistor SL is coupled to the amplifying transistor AMP.

[0037] Figure 3 A timing diagram of the pixel circuit according to the first embodiment is shown. Figure 4 A structural diagram and a potential distribution diagram of the pixel circuit according to the first embodiment are shown. Figure 4 The state of charge stored in the floating diffusion region FD and the MOS capacitor DCG is shown.

[0038] When light shines on the photodiode PD, charge is stored in the photodiode PD. The duration of light shining on the photodiode PD is controlled by the conduction time of the electronic shutter ES and the conduction time of the transfer gate Tx.

[0039] Then, the selection transistor SL is turned on to set the pixel used for reading the signal. When the reset transistor is turned on and held in this state, the noise stored in the floating diffusion region FD is reset. Then, the reset transistor RS is turned off. At this time, the signal output from the output signal line SO is set to zero level.

[0040] Then, the selection transistor SL remains on, and the transfer gate Tx remains on. When the transistor gate Tx is on, charge is stored in the floating diffusion region FD and the MOS capacitor DCG.

[0041] Figure 5 The time variation of the structure diagram and potential distribution diagram of the pixel circuit according to the first embodiment is shown. Figure 5 (a) shows the state in which no charge is stored in the floating diffusion region FD. Figure 5 (b) shows the state of the stored charge in the floating diffusion region FD. Figure 5 (c) shows the state of charge stored in the floating diffusion region FD and the MOS capacitor DCG. As time passes, the state changes according to… Figure 5 (a) Figure 5 (b) and Figure 5 The order of (c) in the diagram changes. It should be noted that the voltage in the plotted potential distribution increases downwards. This applies to the following description.

[0042] like Figure 5 As shown in (a), the potential V of the N-type layer in the floating diffusion region FD is in the state without stored charge. FD0 The storage layer potential V higher than that of the MOS capacitor DCG DCG Therefore, charge Q1 is first stored in the floating diffusion region FD, as follows: Figure 5 As shown in (b) of the diagram.

[0043] When charge Q1 is stored in the floating diffusion region FD and the potential V of the floating diffusion region FD is... FD3 The potential V of the MOS capacitor DCG exceeds DCG At this time, charge is stored in the floating diffusion region FD and the MOS capacitor DCG. The charge stored in the floating diffusion region FD exceeding charge Q1 is called Q2. FD The charge stored in the MOS capacitor DCG is called Q2. DCG Charge Q2 FD and charge Q2 DCG The sum of these is called charge Q2.

[0044] When charge is stored in the floating diffusion region FD, the potential V FD3 A potential V is applied to the amplifying transistor AMP. FD3The signal is transferred to the output signal line SO via the amplification transistor AMP and the selection transistor SL to output the "Signal" signal. The output signal SO is coupled to the digital processing circuit 4. The digital processing circuit 4 takes the difference between the zero level and the signal level as the final output (correlated double sampling), converting the analog signal into a digital signal.

[0045] Figure 6 The signal charge is shown as the voltage applied to the gate of the amplifying transistor AMP of the pixel circuit 10 according to the first embodiment (and the potential V of the N-type layer of the floating diffusion region FD). FD3 (Same) dependency. Until the charge reaches Q1, the charge is stored only in the floating diffusion region FD. When the charge exceeds Q1, the charge is stored in the floating diffusion region FD and the MOS capacitor DCG. Therefore, the potential V FD3 The rate of change is variable. The potential V after exceeding charge Q1... FD3 The gradient is less than the potential V before reaching charge Q1. FD3 The gradient.

[0046] It should be noted that Figure 6 The result shows the effect of setting the capacitance of the MOS capacitor DCG to 6.4 fF. (As shown...) Figure 6 As shown, the charge saturation of the pixel circuit 10 according to the first embodiment is 23,000 electrons.

[0047] Because the pixel circuit 10 provided in this embodiment has a MOS capacitor DCG, it can store more charge. Due to the large amount of charge stored in the pixel circuit 10, it can still operate normally even in low-light conditions or in high-light conditions. In other words, the CMOS image sensor 1 provided in this embodiment has a wide dynamic range. In this example, the charge storage element is a MOS capacitor, but it could also be a PN junction or PNP junction capacitor.

[0048] It should be noted that the above embodiments illustrate the case where the signal charge (minority carrier) is electrons. When the signal charge (minority carrier) is holes, the voltage polarity is reversed, and with the potentials of the floating diffusion region and the MOS capacitor reset, the voltage of the charge storage layer of the MOS capacitor becomes higher than the voltage of the floating diffusion region.

[0049] Figure 7 A circuit diagram of pixel circuit 11 according to the first comparison example is shown. Figure 7 The pixel circuit 11 shown differs from the pixel circuit 10 according to the first embodiment in that the pixel circuit 11 does not have a MOS capacitor DCG. Figure 7 China and Figure 2 The same components use the same names, and detailed descriptions are omitted here.

[0050] Figure 8 A structural diagram and a potential distribution diagram of the pixel circuit 11 according to the first comparison example are shown. Figure 8 The state of charge stored in the floating diffusion region FD is shown. Figure 9 This shows the voltage applied to the gate of the amplifying transistor AMP of the pixel circuit 11 according to the first comparison example (compared to the potential V of the N-type layer of the floating diffusion region FD). FD3 (Same) time variation. The timing diagram of pixel circuit 11 according to the first comparative example is substantially the same as the timing diagram of pixel circuit 10 according to the first embodiment.

[0051] In the pixel circuit 11 according to the first comparative example, when the transfer gate Tx is turned on, charge is stored in the floating diffusion region FD. The pixel circuit 11 according to the first comparative example cannot store a charge exceeding Q1. Therefore, the potential V of the N-type layer in the floating diffusion region FD... FD3 The stored charge Q1 becomes constant. Because the effect of noise must be reduced, it is difficult to increase the capacitance of the floating diffusion region FD.

[0052] like Figure 9 As shown, the charge saturation of pixel circuit 11 according to the first comparative example is 7250 electrons. The parameters of pixel circuit 11 are the same as those of pixel circuit 10, except that it does not have a MOS capacitor DCG.

[0053] As described above, the charge saturation of pixel circuit 10 is 23,000 electrons. In other words, pixel circuit 10 has a larger charge saturation than pixel circuit 11, and has a dynamic range 10 dB wider than pixel circuit 11. Therefore, pixel circuit 10 has a significantly wider dynamic range compared to pixel circuit 11.

[0054] In the pixel circuit 10 according to the first embodiment, it has been explained that the dynamic range of the pixel 10 is extended by using a MOS capacitor DCG. The dynamic range of the pixel circuit can be extended by other methods.

[0055] Figure 10 A timing diagram of the pixel circuit according to the second comparison example is shown. Figure 10 As shown, for example, long-exposure frames can be combined with short-exposure frames to extend the dynamic range of the pixel circuitry. However, this method requires reading two frames to acquire one output signal, thus doubling the power consumption. Furthermore, if the object to be imaged is moving, a false image will be created due to the time difference between the readings of the two frames.

[0056] Figure 11A circuit diagram of the pixel circuit according to the third comparison example is shown. Figure 12 A timing diagram of a pixel circuit according to a third comparative example is shown. The pixel circuit 12 according to the third comparative example differs from the pixel circuit 11 according to the first comparative example in that pixel circuit 12 includes a second reset transistor RS2 and a capacitor C. Pixel circuit 12 can store charge in capacitor C. Whether to store charge in capacitor C can be determined by switching the on / off state of the reset transistor RS. Pixel circuit 12 switches between high-gain and low-gain signals by switching the on / off state of the reset transistor RS. Pixel circuit 12 extends the dynamic range by reading both the high-gain and low-gain signals. However, this method requires reading both the high-gain and low-gain signals, thus doubling the power consumption.

[0057] Conversely, the pixel circuit 10 according to the first embodiment can extend the dynamic range with only one analog-to-digital conversion without increasing power consumption.

[0058] (Second Embodiment) The circuit diagram, structural diagram, potential distribution diagram, and timing diagram of the pixel circuit according to the second embodiment are substantially the same as those of the pixel circuit according to the first embodiment. The difference between the pixel circuit according to the second embodiment and the pixel circuit according to the first embodiment is that a portion of the signal charge generated in the photodiode PD is stored in the junction capacitance of the photodiode PD. The MOS capacitor DCG has a potential lower than the junction capacitance of the photodiode PD, and is used to store a portion of the signal charge generated in the photodiode PD in the junction capacitance of the photodiode PD.

[0059] Figure 13 The time variation of the structure diagram and potential distribution diagram of the pixel circuit according to the second embodiment is shown. Figure 13 (a) shows the state in which no charge is stored in the floating diffusion region FD. Figure 13 (b) shows the state of the stored charge in the floating diffusion region FD. Figure 13 (c) shows the state of charge stored in the floating diffusion region FD and the MOS capacitor DCG. Figure 13 Figure (d) shows the states of charge storage in the floating diffusion region FD, the MOS capacitor DCG, and the photodiode PD. As time passes, the states change according to… Figure 13 (a) Figure 13 (b) Figure 13 (c) and Figure 13 The order of (d) in the text changes.

[0060] Figure 13 (a) Figure 13 (b) and Figure 13 (c) in the middle are respectively with Figure 5 (a) Figure 5 (b) and Figure 5 (c) is the same. For example Figure 13 As shown in (b), charge Q1 is first stored in the floating diffusion region FD. Then, as... Figure 13 As shown in (c), when the potential V of the floating diffusion region... FD3 The potential V of the MOS capacitor DCG exceeds DCG At that time, charge Q2 is stored in the floating diffusion region FD and the MOS capacitor DCG.

[0061] like Figure 13 As shown in (d), when the potential V of the floating diffusion region FD is... FD3 The potential V of the cathode of the photodiode PD exceeds PD0 At this time, charge is stored in the floating diffusion region FD, the MOS capacitor DCG, and the photodiode PD. The photodiode PD has a junction capacitance generated by the depletion layer, which can store charge corresponding to the junction capacitance. The charge stored in the floating diffusion region exceeding charge Q2 is called Q3. FD The charge stored in the MOS capacitor DCG exceeding the charge Q2 is called Q3. DCG The charge stored in the photodiode PD is called Q3. PD Charge Q3 FD Charge Q3 DCG and charge Q3 PD The sum of these is called charge Q3.

[0062] When charge is stored in the floating diffusion region FD, the potential V FD3 A potential V is applied to the amplifying transistor AMP. FD3 The signal is transferred to the output signal SO via the amplification transistor AMP and the selection transistor SL to output the "Signal" signal. The output signal SO is coupled to the digital processing circuit 4. The digital processing circuit 4 takes the difference between the zero level and the signal level as the final output (correlated double sampling), converting the analog signal into a digital signal.

[0063] Figure 14 The signal charge is shown as the voltage applied to the gate of the amplifying transistor AMP of the pixel circuit according to the second embodiment (and the potential V of the N-type layer of the floating diffusion region FD). FD3 (Same) dependency. Until the charge reaches Q1, the charge is only stored in the floating diffusion region FD. When the charge exceeds Q1, the charge is stored in the floating diffusion region FD and the MOS capacitor DCG, with potential V. FD3 The rate of change changes. The potential V after exceeding charge Q1... FD3 The gradient is less than the potential V before reaching charge Q1.FD3 The gradient. When the charge exceeds Q2, the charge is stored in the floating diffusion region FD, the MOS capacitor DCG, and the photodiode PD, therefore the potential V... FD3 The rate of change further changes. The potential V after the charge exceeds Q2... FD3 The gradient is less than the potential V FD3 The gradient from charge Q1 to charge Q2.

[0064] It should be noted that Figure 14 The results are shown when the capacitance of the MOS capacitor DCG is set to 6.4 fF. Figure 14 In the floating diffusion region, when the potential V of the N-type layer... FD3 When the voltage is set to 0.5 V or higher and the charge is also stored in the photodiode PD, the charge saturation of the pixel circuit according to the second embodiment is 132,000 electrons. The charge saturation of the pixel circuit according to the second embodiment is greater than that of the pixel circuit 10 according to the first embodiment and the pixel circuit 11 according to the first comparative example. The dynamic range of the pixel circuit according to the second embodiment is 25 dB wider than that of the pixel circuit 11 according to the first comparative example.

[0065] As described above, the pixel circuit according to the second embodiment provides an effect similar to that of the pixel circuit according to the first embodiment, and can extend the dynamic range.

[0066] (Third embodiment) Figure 15 A structural diagram and a time-varying potential distribution diagram of a pixel circuit according to a third embodiment are shown. The pixel circuit according to the third embodiment has the same structure as the pixel circuit 11 according to the first comparative example. However, the pixel circuit according to the third embodiment and Figure 8 The difference in the structural diagram of the pixel circuit 11 shown is that a stepped potential is provided under the transmission gate Tx, and a region Tx_1 with a shallow potential is provided near the photodiode PD, while a region Tx_2 with a deep potential is provided near the floating diffusion region FD. When the transmission gate Tx is off, the potential of region Tx_2 is between the potential of region Tx_1 and the potential of the floating diffusion region FD. N-type impurities can be doped into region Tx_2 to deepen its potential. Alternatively, the electrodes of the transmission gate Tx are separated, and different voltages can be applied to the electrodes corresponding to region Tx_1 and region Tx_2, respectively.

[0067] Figure 15 (a) shows the state in the floating diffusion region where no charge is stored. Figure 15 (b) shows the state of the stored charge in the floating diffusion region FD. Figure 15(c) shows the state of charge storage in the floating diffusion region FD and region Tx_2. When a large amount of signal charge is generated and the potential of the floating diffusion region exceeds the potential of the second transmission gate region, the pixel circuit according to this application can store more charge using the capacitance of region Tx_2. Compared to the first embodiment, the pixel circuit according to the third embodiment does not require the provision of a MOS capacitor DCG, thus simplifying the arrangement of pixel elements. Since the number of elements coupled to the floating diffusion region FD is not increased, and the capacitance of the floating diffusion region FD is not increased, noise is suppressed when the stored charge is small. The signal charge dependence of the floating diffusion region FD is similar to... Figure 6 The timing diagram of the pixel circuit is similar to... Figure 3 .

[0068] (Fourth embodiment) Figure 16 A circuit diagram of a pixel circuit 13 according to a fourth embodiment is shown. The pixel circuit 13 according to the fourth embodiment differs from the pixel circuit 10 according to the first embodiment in that the pixel circuit 13 further includes a signal compensation unit 20. The structural diagram, potential distribution diagram, and timing diagram of the pixel circuit according to the fourth embodiment are substantially the same as those of the pixel circuit according to the first embodiment.

[0069] For example, signal compensation unit 20 is coupled to output signal line SO. Signal compensation unit 20 can be part of digital processing circuit 4. When a potential V is applied to the floating diffusion region FD... FD3 When the reset potential of the MOS capacitor DCG is exceeded, the signal compensation unit 20 will output a compensation signal. The reset potential of the MOS capacitor DCG is the storage layer potential of the MOS capacitor DCG in the state where the MOS capacitor DCG does not store charge.

[0070] Figure 17 An example of compensating the output signal of the pixel circuit 13 according to the fourth embodiment is shown. Figure 6 and Figure 14 As shown, the output signal of the pixel circuit may be nonlinear. The signal compensation unit 20 converts the nonlinear output signal into a compensated linear signal. When a potential V is applied to the floating diffusion region FD... FD3 When the potential exceeds the reset potential of the MOS capacitor DCG, the output signal from the pixel circuit becomes nonlinear. Therefore, preferably, the signal compensation unit 20 can compensate for the signal when the potential exceeds the reset potential.

[0071] For example, the signal compensation unit 20 includes a memory and a processing unit. The memory stores the position of the pixel circuit 13 in the pixel array 3, the amount of charge stored in the pixel circuit 13, and the output voltage from the pixel circuit 13. The processing unit performs calculations based on the data stored in the memory to obtain a linear compensation signal. For example, the processing unit calculates the product of the output signal minus the offset and then multiplying it by the gain. Figure 16 In this diagram, 'a' and 'a' represent offsets, and 'b' and 'b' represent gains. Due to variations in each pixel, the offset and gain of each pixel differ from those of other pixels. Furthermore, the offset and gain vary depending on the amount of charge stored in the pixel circuitry. Therefore, the offset value of the gain for each pixel circuitry is initially set. Figure 15 In this diagram, for simplicity, the signal compensation unit 20 is shown coupled to one output signal line SO. However, the signal compensation unit can be an integrated signal compensation unit disposed outside the pixel array and coupled to all output signal lines SO. The integrated signal compensation unit may include a memory storing preliminary settings for offset and gain for each pixel circuit; and an operation unit for reading signals from the compensation signal based on the pixel circuit, as well as the preliminary settings for offset and gain.

[0072] As described above, the pixel circuit according to the fourth embodiment provides effects similar to those of the pixel circuit according to the first embodiment, and can extend the dynamic range. Furthermore, the pixel circuit according to the fourth embodiment can output a compensated linear signal.

[0073] (Fifth Embodiment) Figure 18 A circuit diagram of a pixel circuit 14 according to a fifth embodiment is shown. The pixel circuit 14 according to the fifth embodiment differs from the pixel circuit 10 according to the first embodiment in that it includes an attenuator 30. The structure diagram, potential distribution diagram, and timing diagram of the pixel circuit according to the fifth embodiment are similar to those of the pixel circuit according to the first embodiment.

[0074] For example, attenuator 30 is coupled to the output signal line SO. Attenuator 30 is positioned between the output signal line SO and the analog-to-digital converter (ADC) of the digital processing circuit 4. Attenuator 30 can be part of the digital processing circuit 4. Attenuator 30 attenuates the voltage amplitude of the output signal from the output signal line SO. When the charge saturation of the pixel circuit increases, the voltage amplitude output by the pixel circuit may exceed the input range of the ADC of the digital processing circuit 4. Attenuator 30 attenuates the voltage amplitude input to the ADC. Although Figure 17The attenuator 30 is shown coupled to one output signal line SO for simplicity, but the attenuator could be an integrated attenuator positioned outside the pixel array and coupled to all output signal lines SO. The integrated attenuator can attenuate the voltage amplitude output from each output signal line SO so as not to exceed the input range of the analog-to-digital converter.

[0075] As described above, the pixel circuit according to the fifth embodiment provides effects similar to those of the pixel circuit according to the first embodiment, and can extend the dynamic range. Even if the voltage amplitude of the output signal becomes too high, the pixel circuit according to the fifth embodiment can still appropriately perform analog-to-digital conversion.

[0076] The signal compensation unit 20 according to the fourth embodiment and the attenuator 30 according to the fifth embodiment can be used together.

[0077] Embodiments of the invention have been explained in detail with reference to the accompanying drawings, but the configurations and combinations of each embodiment are merely examples. Additions, omissions, substitutions, and other changes to the configurations can be made without departing from the spirit of the invention. For example, the feature components in the embodiments can be used in combination.

[0078] name 1: CMOS image sensor 2: Vertical scanning circuit 3: Pixel array 4: Digital processing circuit 5: Horizontal scanning circuit 10 to 14: Pixel Circuits 20: Signal compensation unit 30: Attenuator AMP: Amplifying Transistor DCG: MOS capacitor FD: Floating diffusion region L1: Signal line PD: Photodiode RD: Drain RS: Reset transistor RS2: Second reset transistor SO: Output signal line SL: Select Transistor Tx: Transfer gate

Claims

1. A pixel circuit, characterized in that, include: Photodiode; Transmission gate; Floating diffusion zone; Reset transistor; Charge storage element; Amplifying transistors; Select transistors, The transmission gate is coupled to the cathode of the photodiode and the floating diffusion region. The charge storage layer of the charge storage element is coupled to the floating diffusion region. The floating diffusion region, the source of the reset transistor, and the gate of the amplifying transistor are coupled to each other. The drain of the selection transistor is coupled to the source of the amplification transistor.

2. The pixel circuit according to claim 1, characterized in that, The charge storage element is a MOS capacitor or a PN junction capacitor.

3. The pixel circuit according to claim 1, characterized in that, With the potentials of the photodiode, the floating diffusion region, and the charge storage element reset, the potential of the floating diffusion region is higher than the potential of the charge storage element for minority carriers.

4. The pixel circuit according to claim 1, characterized in that, The photodiode has a junction capacitance. A portion of the signal charge generated in the photodiode is stored in the junction capacitance.

5. The pixel circuit according to claim 3, characterized in that, When the potentials of the photodiode, the floating diffusion region, and the charge storage element are reset, for minority carriers, the potential of the floating diffusion region is higher than the potential of the charge storage element. For the minority carriers, the potential of the floating diffusion region and the potential of the charge storage element are higher than the potential of the junction capacitance.

6. The pixel circuit according to claim 1, characterized in that, It also includes a signal compensation unit. The signal compensation unit is coupled to the source of the selection transistor. When the potential applied to the floating diffusion region exceeds the reset potential of the charge storage element, the signal compensation unit will output a compensation signal. The compensation signal is obtained by subtracting the offset from the value of the output signal and then multiplying it by the gain.

7. The pixel circuit according to claim 1, characterized in that, It also includes attenuators, The attenuator is coupled to the source of the selected transistor.

8. A pixel circuit, characterized in that, include: Photodiode; Transmission gate; Floating diffusion zone; Reset transistor; Amplifying transistors; Select transistors, The transmission gate is coupled to the cathode of the photodiode and the floating diffusion region. The transmission gate includes a first transmission gate region coupled to the cathode of the photodiode and a second transmission gate region coupled to the floating diffusion region. When the transmission gate is turned off, the potential of the second transmission gate region is between the potential of the first transmission gate region and the potential of the floating diffusion region. The floating diffusion region, the source of the reset transistor, and the gate of the amplifying transistor are coupled to each other. The drain of the selection transistor is coupled to the source of the amplification transistor.

9. The pixel circuit according to claim 8, characterized in that, The first transmission gate region and the second transmission gate region are doped with different amounts of impurities, or the transmission gate includes a first transmission gate electrode corresponding to the first transmission gate region and a second transmission gate electrode corresponding to the second transmission gate region, and the voltage applied to the first transmission gate electrode and the voltage applied to the second transmission gate electrode are different from each other.

10. The pixel circuit according to claim 8, characterized in that, It also includes a signal compensation unit. The signal compensation unit is coupled to the source of the selection transistor. When the potential applied to the floating diffusion region exceeds the reset potential of the second transmission gate region, the signal compensation unit will output a compensation signal. The compensation signal is obtained by subtracting the offset from the value of the output signal and then multiplying it by the gain.

11. The pixel circuit according to claim 8, characterized in that, It also includes attenuators, The attenuator is coupled to the source of the selected transistor.

12. A CMOS image sensor, characterized in that, Includes the pixel circuit according to any one of claims 1 to 11.

13. A method for operating a pixel circuit, characterized in that, include: The photodiode stores the charge generated by the light illuminating it; The transmission gate is turned on to transfer the charge stored in the photodiode to the floating diffusion region; When the potential of the floating diffusion region exceeds the potential of the charge storage element through the transfer of the charge, the charge is stored in the floating diffusion region and the charge storage element coupled to the floating diffusion region; The potential of the floating diffusion region and the charge storage element is amplified to output the potential as an output signal.

14. The method according to claim 13, characterized in that, With the potentials of the photodiode, the floating diffusion region, and the charge storage element reset, the potential of the floating diffusion region is higher than the potential of the charge storage element for minority carriers.

15. The method according to claim 13, characterized in that, Storing the charge in the floating diffusion region and the charge storage element includes storing a portion of the charge in the junction capacitance of the photodiode.

16. The method according to claim 15, characterized in that, When the potentials of the photodiode, the floating diffusion region, and the charge storage element are reset, for minority carriers, the potential of the floating diffusion region is higher than the potential of the charge storage element. For the minority carriers, the potential of the floating diffusion region and the potential of the charge storage element are higher than the potential of the junction capacitance.

17. The method according to claim 13, characterized in that, Amplifying the potential of the floating diffusion region and the charge storage element to output the potential as an output signal includes: when the potential applied to the floating diffusion region exceeds the reset potential of the charge storage element, compensating the output signal into a compensation signal obtained by subtracting the offset from the value of the output signal and then multiplying it by the gain.

18. The method according to claim 13, characterized in that, Amplifying the potential of the floating diffusion region and the charge storage element to output the potential as an output signal includes attenuating the output signal.

19. A method for operating a pixel circuit, characterized in that, include: The photodiode stores the charge generated by the light illuminating it; The transfer gate is turned off to transfer the charge stored in the photodiode to the floating diffusion region, the transfer gate including a first transfer gate region and a second transfer gate region; When the potential of the floating diffusion region exceeds the potential of the second transmission gate region coupled to the floating diffusion region due to the transfer of charge, the charge is stored in the floating diffusion region and the second transmission gate region. The potential of the floating diffusion region and the second transmission gate region is amplified to output the potential as an output signal. When the transmission gate is turned off, the potential of the second transmission gate region is between the potential of the first transmission gate region and the potential of the floating diffusion region. The first transmission gate region and the second transmission gate region are doped with different amounts of impurities, or the transmission gate includes a first transmission gate electrode corresponding to the first transmission gate region and a second transmission gate electrode corresponding to the second transmission gate region, and the voltage applied to the first transmission gate electrode and the voltage applied to the second transmission gate electrode are different from each other.

20. A method for operating a CMOS sensor, characterized in that, Including a method of operating a pixel circuit according to any one of claims 13 to 19.

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