Stacked semiconductor device with semiconductor dies of variable size

Abstract

A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die and an additional semiconductor component coupled with a logic die. A dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and the dielectric peripheral material outside a second footprint of the second semiconductor die and a third footprint of the additional semiconductor component such that the gap fill material at least partially encloses the second semiconductor die and the additional semiconductor component.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor device assemblies, and more specifically to a stacked semiconductor device having semiconductor dies of variable size. Background Technology

[0002] Microelectronic devices generally have a die (i.e., a chip) containing an integrated circuit system with a high density of extremely small components. Typically, a die contains an array of extremely small bonding pads electrically coupled to the integrated circuit system. These bonding pads are external electrical contacts through which voltage, signals, etc., are transmitted to and from the integrated circuit system. After the die is formed, it is “encapsulated” to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power supply lines, signal lines, and ground lines. A typical process for encapsulating a die involves electrically coupling the bonding pads on the die to lead, ball pads, or other types of electrical terminal arrays, and encapsulating the die to protect it from environmental factors such as moisture, particles, static electricity, and physical shock. Attached Figure Description

[0003] Figure 1A A simplified schematic cross-sectional view illustrating a semiconductor device assembly according to an embodiment of the present technology.

[0004] Figure 1B A simplified schematic plan view illustrating a wafer-level semiconductor device assembly according to an embodiment of the present technology.

[0005] Figure 2A A simplified schematic cross-sectional view illustrating a semiconductor device assembly according to an embodiment of the present technology.

[0006] Figure 2B A simplified schematic plan view illustrating a wafer-level semiconductor device assembly according to an embodiment of the present technology.

[0007] Figures 3 to 11 A simplified schematic perspective view and cross-sectional view illustrating a series of steps for manufacturing a semiconductor device assembly according to an embodiment of the present technology.

[0008] Figure 12 This diagram illustrates a system comprising a semiconductor device assembly configured according to an embodiment of the present technology.

[0009] Figure 13 A method for manufacturing a semiconductor device assembly according to embodiments of the present technology is described. Detailed Implementation

[0010] Semiconductor device packages are used to implement multiple semiconductor dies into a single, monolithic structure that provides functionality for an electronic device. For example, multiple semiconductor dies can be stacked on top of each other to implement additional circuitry within the package without increasing its footprint. As semiconductor devices are designed for increasingly complex applications, the semiconductor dies implemented within the package may become larger and more complex, increasing the likelihood of such dies exhibiting defects that reduce yield.

[0011] Typically, semiconductor devices are packaged at the wafer level to enable the simultaneous assembly of multiple semiconductor devices. For example, individual semiconductor dies or stacks of semiconductor dies (e.g., memory dies) can be attached to different semiconductor dies (e.g., logic dies) within a wafer. When a defective die is detected within the wafer, dummy semiconductor components that do not contain functional circuitry can be coupled to the defective die, while functional semiconductor dies can be coupled to other functional semiconductor dies within the wafer. In this way, continuity can be maintained across the wafer without wasting functional semiconductor dies within the package that would be rendered inoperable due to defects in one or more of the semiconductor dies within it. However, this process still wastes assembly processes and dummy components on inoperable devices, which is increasingly likely to occur with low-yield semiconductor dies.

[0012] Furthermore, previous assembly techniques that stack dies of similar size on top of each other may not be feasible for semiconductor device packages designed for some complex applications. For example, memory dies or memory die stacks may be stacked onto logic dies of similar size. When implementing large logic dies that are much larger than the memory dies stacked on them, stacking only single memory dies or single memory die stacks onto logic dies can be wasteful of space and result in a lack of continuity across the package. Therefore, additional assembly techniques can improve some semiconductor device packages, especially implementations that utilize low-yield dies or semiconductor device packages containing dies of different sizes stacked on top of each other.

[0013] This technology provides a stacked semiconductor device with variable-sized semiconductor dies. Semiconductor devices can be fabricated at the wafer level by reconstructing a wafer from a monolithically sized “known good die.” For example, a logic die can be monolithically sized from a logic wafer and tested to determine its operability. Once determined to be operable, the logic die can be attached to a carrier wafer and surrounded by a gap-filling material (e.g., dielectric material or oxide). In this way, the logic dies within the reconstructed wafer can be determined to be functional before attaching additional semiconductor dies, thus improving yield. A stack of semiconductor dies and additional semiconductor components can be coupled to each of the logic dies within the reconstructed wafer. In one aspect, the additional semiconductor components can be an additional stack of semiconductor dies lacking a functional circuitry or a dummy semiconductor component. The functionality of the additional semiconductor die stack or additional semiconductor component can be similarly tested before coupling to the logic dies. Additional gap-filling material can be disposed around the semiconductor die stack and additional semiconductor components. Individual logic dies can then be monolithically sized between the gap-filling material and the additional gap-filling material to monolithically sized a single semiconductor device. The semiconductor device may have a peripheral portion formed by gap-filling material and additional gap-filling material, the peripheral portion extending along the sidewall of the semiconductor die.

[0014] Figure 1A A simplified schematic cross-sectional view illustrating a semiconductor device assembly 100 according to an embodiment of the present technology is provided. The semiconductor device assembly 100 includes a semiconductor die 102 and one or more semiconductor dies 104 (e.g., a semiconductor die stack) and one or more semiconductor dies 106 (e.g., a semiconductor die stack) assembled onto the semiconductor die 102. Semiconductor dies 104 may be assembled onto the semiconductor die 102 at a first lateral position, and semiconductor dies 106 may be assembled onto the semiconductor die 102 at a second lateral position different from the first lateral position. In one aspect, the semiconductor die 102 may include a logic die implementing a processor, central processing unit (CPU), graphics processing unit (GPU), interface (IF) controller, or the like. Semiconductor dies 104 and 106 may implement memory dies storing data to be operated by the logic dies. In some cases, the memory die may act as main memory or dedicated memory accessible by the logic die. Semiconductor dies 104 and 106 can implement the same type of memory or different types of memory. For example, semiconductor die 104 may contain dynamic random access memory (DRAM), semiconductor die 106 may contain static random access memory (SRAM), and additional semiconductor dies may contain NAND memory.

[0015] Semiconductor dies 104 and 106 are electrically and mechanically coupled to semiconductor die 102. For example, interconnects (e.g., copper-copper (Cu-Cu) interconnects) may be formed (e.g., by hybrid bonding) between contacts 108 at semiconductor die 102 and contacts 110 at semiconductor die 104. Similarly, contacts 112 at semiconductor die 102 and contacts 114 at semiconductor die 106 may form interconnects that electrically and mechanically couple semiconductor dies 102 and 106. Contacts 108 and 112 may be coupled to functional circuitry (e.g., transistors, diodes, resistors, and other components) on the front side of semiconductor die 102 via connection circuitry (e.g., traces, lines, vias, and through-silicon vias (TSVs)). Contacts 110 and 114 may similarly be coupled to functional circuitry at semiconductor dies 104 and 106 via connection circuitry. Therefore, interconnects can electrically couple the circuitry at the stack of semiconductor dies 104 and 106 to the circuitry at semiconductor die 102. The dielectric material (e.g., dielectric blocks) at semiconductor dies 104 and 106 can further bond with the dielectric material at semiconductor die 102 to mechanically couple the components. The dielectric material may comprise silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or the like.

[0016] Semiconductor die 102 may further include dummy pads 116, implemented similarly to contacts 108 and 112, but decoupled from the functional circuitry at semiconductor die 102. In this way, dummy pads 116 cannot be used to electrically couple additional components (e.g., contacts 108 and 112) to semiconductor die 102. Instead, dummy pads 116 can be used to mechanically bond components to semiconductor die 102 and increase the uniformity of the bonding surface across semiconductor die 102. Dummy pads 116 may be implemented at locations lacking contacts (for example, outside the occupied area of ​​semiconductor die 104 or semiconductor die 106) with a similar spacing to contacts 108 and 112. Dummy pads may similarly be implemented on the gap filler material 118 surrounding semiconductor die 102.

[0017] Semiconductor die 102 may be assembled (e.g., by adhesive or dielectric material) onto a carrier substrate 120 for reconstructing semiconductor die 102 and other semiconductor dies into a wafer. For example, semiconductor die 102 and other semiconductor dies may be attached to carrier substrate 120 (e.g., by chip-to-wafer bonding), and gap filler material 118 may be disposed around semiconductor die 102 and other semiconductor dies to form a reconstructed wafer. In some cases, semiconductor die 102 may be attached to carrier substrate 120 via a fusion bonding process. Gap filler material 118 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, etc. In some cases, gap filler material 118 is an oxide. In some cases, gap filler material 118 may be at least partially disposed above the distal surface of semiconductor die 102 opposite to carrier substrate 120. By referencing reference point 122 at semiconductor die 102 and reference point 124 at carrier substrate 120, semiconductor die 102 can be attached to carrier substrate 120 at the appropriate location. The surface of semiconductor die 102 is exposed due to the thinning process at gap filler material 118. Once gap filler material 118 is applied, semiconductor dies 104 and 106 can be attached to the reconstructed wafer at semiconductor die 102.

[0018] A gap filler material 126, similar to gap filler material 118, may be disposed around semiconductor dies 104 and 106. In one aspect, gap filler material 126 may be different from gap filler material 118. Either gap filler material 118 or gap filler material 126 may be selected to achieve maximum heat dissipation of semiconductor die 102. Gap filler material 126 may be disposed outside the occupied area of ​​semiconductor dies 104 and 106 above semiconductor die 102 and gap filler material 118. In some cases, gap filler material 126 may be disposed above the distal surfaces of semiconductor dies 104 and 106 opposite to the carrier substrate 120.

[0019] A cover 128 may be disposed over semiconductor dies 104 and 106. The cover 128 may contain dummy semiconductor material lacking functional circuitry. In some cases, the cover may improve heat dissipation of the assembly 100. The cover 128 may be attached to the gap filler 126, semiconductor die 104, or semiconductor die 106 by an adhesive or dielectric material (e.g., a dielectric block). For example, the dielectric material may be disposed over the gap filler 126 and coupled to the dielectric material disposed over the cover 128. In one aspect, the cover 128 may be used to increase the thickness of the semiconductor device assembly 100 to meet design specifications or improve the mechanical strength of the semiconductor device assembly 100.

[0020] Although described with reference to a specific configuration, the stacked semiconductor device assembly may contain different... Figure 1A The configuration shown is illustrated. Stacked semiconductor device assemblies may comprise varying numbers of semiconductor die stacks, varying numbers of semiconductor dies within each stack, and so on. In some cases, the semiconductor device assembly may comprise 3, 4, 5, 6, 8, 10, 20, or any number of semiconductor die stacks. In some embodiments, each semiconductor die stack may comprise 3, 4, 5, 6, 8, 10, 12, or any number of semiconductor dies. In other aspects, one or more of the semiconductor die stacks may be replaced by a single semiconductor die.

[0021] As discussed above, semiconductor device assembly 100 can be monolithically derived from multiple semiconductor device assemblies assembled through a wafer-level process. Figure 1B A simplified schematic plan view illustrating a wafer-level semiconductor device assembly 150 according to an embodiment of the present technology. In this aspect, after semiconductor die 104 and semiconductor die 106 are coupled to semiconductor die 102 and in Figure 1A Before the gap filler material 126 is disposed around semiconductor dies 104 and 106, the semiconductor device assembly 150 is described. In addition to semiconductor dies 104 and 106, additional semiconductor dies are attached to semiconductor die 102. Semiconductor dies 104 or 106 may have a length or width different from that of semiconductor die 102. Each of the semiconductor dies may have a smaller occupied area than that of semiconductor die 102. In this way, multiple semiconductor dies can be attached to semiconductor die 102 within the occupied area of ​​semiconductor die 102.

[0022] Additional semiconductor die 102' may be positioned adjacent to semiconductor die 102. Semiconductor dies 104', 106', and any additional semiconductor dies may be disposed at semiconductor die 102'. Generally, components referenced by prime numbers may be separate examples of similar components referenced by the same element symbol. For example, semiconductor die 102' may be implemented similarly to semiconductor die 102. Although Figure 1BThe description specifies only one additional semiconductor die 102', but the wafer-level semiconductor device assembly 150 may contain any number of semiconductor dies. In this way, any number of semiconductor devices can be assembled on a single reconstructed wafer. Semiconductor dies 102 and 102' (and any number of other semiconductor dies not shown) can be used to form a reconstructed wafer by depositing a gap-filling material 118 outside the occupied area of ​​semiconductor dies 102 and 102'. Although not shown, the gap-filling material 118 may be disposed on a carrier substrate to which semiconductor dies 102 and 102' are attached.

[0023] Figure 2A A simplified schematic cross-sectional view illustrating a semiconductor device assembly 200 according to an embodiment of the present technology is provided. Generally, the semiconductor device assembly 200 may be similar to... Figure 1A The semiconductor device assembly 200 is implemented as described herein, but wherein the semiconductor die 106 is replaced with a dummy semiconductor assembly 206. The dummy semiconductor assembly 206 can be used to implement a wider range of memory devices using a single integration process to meet different customer memory requirements. For example, if a customer only needs half the memory that can be implemented in the maximum memory configuration, a similar integration process for the maximum memory configuration can be used to meet this requirement, but half of the memory components are replaced with the dummy semiconductor assembly 206. The semiconductor device assembly 200 includes a semiconductor die 202 (e.g., a logic die) and a semiconductor die 204 electrically and mechanically coupled to the semiconductor die 202.

[0024] A dummy semiconductor component 206 is mechanically attached to a semiconductor die 202 adjacent to a semiconductor die 204. The circuitry at the dummy semiconductor component 206 and the semiconductor die 202 is electrically disconnected. For example, the dummy semiconductor component 206 may lack the functional or connection circuitry capable of implementing an interconnect between the dummy semiconductor component 206 and the semiconductor die 202. The dummy semiconductor component 206 may have the same height as the semiconductor die 204 (e.g., along the stacked dimension of the semiconductor dies in the semiconductor die 204). The dummy semiconductor component 206 may have a footprint suitable for being exposed within at least a portion of the footprint of the semiconductor die 202, beyond the footprint of the semiconductor die 204. In this way, the dummy semiconductor component 206 can fill any empty space on the surface of the semiconductor die 202.

[0025] The dummy semiconductor component 206 can be coupled to the semiconductor die 202 via an adhesive or dielectric material (e.g., a dielectric block). In some cases, a dummy pad 208 may be disposed within the area occupied by the dummy semiconductor component 206 at the semiconductor die 202. The dummy pad 208 may be disconnected from the functional circuitry at the semiconductor die 202. Although not shown, the dummy semiconductor component 206 may include a dummy pad corresponding to the dummy pad 208, which may be coupled to the dummy pad 208 to mechanically couple the dummy semiconductor component 206 and the semiconductor die 202.

[0026] The dummy semiconductor component 206 can improve the thermal regulation of the semiconductor device assembly 200. For example, the dummy semiconductor component 206 may comprise a semiconductor material, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. The semiconductor material may have a higher thermal conductivity than the gap-fill material that would otherwise be placed at the location of the dummy semiconductor component 206. Therefore, heat can be dissipated more easily from the semiconductor die 202 outside the semiconductor device assembly 200.

[0027] The dummy semiconductor component 206 can also improve package consistency. For example, the dummy semiconductor component 206 may have material properties similar to those of the bare semiconductor die 204. Therefore, assembly processes performed across the semiconductor device assembly 200 can similarly affect different parts of the semiconductor device assembly. For example, depressions created by chemical mechanical planarization (CMP) or back-side grinding may be limited.

[0028] Figure 2B A simplified schematic plan view illustrating a wafer-level semiconductor device assembly 250 according to an embodiment of the present technology. Figure 2A Semiconductor device assembly 200 can be monolithically derived from semiconductor device assembly 250. In this aspect, semiconductor device assembly 250 is described after semiconductor die 204 and dummy semiconductor component 206 are coupled to semiconductor die 202 and before gap filler material is disposed around semiconductor die 204 and dummy semiconductor component 206. In addition to semiconductor die 204, additional semiconductor dies are attached to semiconductor die 202. Furthermore, one or more additional dummy semiconductor components may be attached to semiconductor die 202. As discussed above, dummy semiconductor component 206 (and additional dummy semiconductor components) may have a footprint suitable for exposure within the footprint of semiconductor die 202 outside of semiconductor die 204 (and the additional semiconductor die stack).

[0029] Additional semiconductor die 202' may be positioned adjacent to semiconductor die 202. Semiconductor die 204' and any additional semiconductor dies, as well as dummy semiconductor assembly 206' and any additional dummy semiconductor assembly, may be attached to additional semiconductor die 202'. Although Figure 2BThe description specifies only one additional semiconductor die 202', but the wafer-level semiconductor device assembly 250 may contain any number of semiconductor dies. In this way, any number of semiconductor devices can be assembled on a single reconstructed wafer. Semiconductor dies 202 and 202' (and any number of other semiconductor dies not shown) can be used to form a reconstructed wafer by depositing gap-fill material outside the occupied area of ​​semiconductor dies 202 and 202'. The reconstructed wafer can then be sawn to monolithize individual semiconductor devices.

[0030] This disclosure now turns to a series of steps for manufacturing a semiconductor device assembly according to embodiments of the present technology. Specifically, Figures 3 to 11 Simplified schematic perspective and cross-sectional views illustrate a series of steps for manufacturing a semiconductor device assembly according to embodiments of the present technology. For ease of description, the steps are described with respect to specific embodiments. However, the steps may be performed with respect to… Figures 3 to 11 The steps described are for manufacturing a semiconductor device assembly according to other embodiments.

[0031] from Figure 3 Beginning in stage 300, semiconductor die 302' (e.g., Figure 1A Examples of semiconductor die 102), semiconductor die 302'' and any additional semiconductor dies (collectively referred to as semiconductor die 302) are attached to a wafer-level carrier substrate 304 (e.g., Figure 1A (A non-monolithic example of a carrier substrate 120). Semiconductor dies 302 can be attached to the carrier substrate 304 at different lateral locations (e.g., based on reference points) by adhesive or by dielectric bonding. Semiconductor dies 302 can be selected from multiple semiconductor dies diced from a wafer. In this aspect, semiconductor dies 302 may have low yield. Therefore, some semiconductor dies diced from a wafer may be inoperable, and their inclusion in a semiconductor device assembly may waste space and assembly resources. To reduce this waste, semiconductor dies 302 can be selected based on their quality (e.g., whether the die is operable or not). The quality of semiconductor dies 302 can be determined by probing a test pad coupled to a functional circuit system at semiconductor die 302. If the probing results in the expected outcome, then semiconductor die 302 can be determined to be operable. If operable, then semiconductor die 302 is determined to be a "known good die" and can be included in the assembly. Therefore, by including only operable dies in the semiconductor device assembly, the overall yield of the process can be improved.

[0032] Then turn to Figure 4In stage 400, the semiconductor die 302 is at least partially surrounded by a gap-filling material 402 (e.g., a dielectric material or oxide filler) to form a reconstructed wafer. In some cases, the semiconductor die 302 may be thinned to expose contacts (e.g., TSV 404) at the distal end of the semiconductor die 302 opposite the carrier substrate 304. In some aspects, the semiconductor die 302 can be thinned by back-side grinding. However, in some cases, back-side grinding can result in suboptimal surface roughness, scratches, or chipping of the die edges. In another aspect, the semiconductor die 302 can be thinned by CMP. However, in some such cases, the CMP process can trap slurry between some adjacent semiconductor dies 302, which can reduce the strength of the assembly. In yet another aspect, the semiconductor die 302 can be thinned by dry etching. In some cases, dry etching can result in the removal of at least some of the dielectric material (not shown) surrounding the TSV 404, which can lead to mechanical or electrical failure or propagation of the TSV 404. In other cases, selective dry etching can prevent the removal of the dielectric material surrounding the TSV 404. Generally, any technique can be used to thin the semiconductor die 302 and expose the TSV 404.

[0033] The contacts can be coupled to the functional circuitry at the semiconductor die 302 via a connection circuitry system. To form a protective coating over the distal end of the semiconductor die 302, a dielectric material layer, such as silicon oxide, silicon nitride, silicon carbide, or silicon carbonitride, can be disposed over the distal end of the semiconductor die 302. The dielectric material layer may extend over the TSV 404 exposed at the distal end of the semiconductor die 302.

[0034] The gap filler material 402 may be disposed outside the occupied area of ​​the semiconductor die 302 at the carrier substrate 304. The gap filler material 402 may extend along the side of the semiconductor die 302 between the side attached to the carrier substrate 304 and the opposite side. In this aspect, the gap filler material 402 may fill the gaps between the semiconductor dies 302. As illustrated, the gap filler material 402 is also disposed over the distal end of the semiconductor die 302. The gap filler material 402 may be disposed by any suitable method (e.g., using chemical vapor deposition, physical vapor deposition, application, oxidation, spin coating and / or other suitable techniques). Once the gap filler material 402 is deposited, the gap filler material 402 and the semiconductor die 302 can form a reconstructed wafer of a “known good die” to which additional assembly processes can be performed. This process is significantly different from other assembly processes that use non-monomeric functional wafers to support the semiconductor die 302.

[0035] Then turn to Figure 5In stage 500, the gap filler 402 is thinned and a dielectric material layer 502 and contacts 504 are disposed at the distal end of the semiconductor die 302 and the gap filler 402. The gap filler 402 at the distal end opposite the carrier substrate 304 can be thinned by any suitable method (e.g., back-side grinding, CMP, etching, or the like). In some cases, the gap filler 402 may be thinned until the semiconductor die 302 is exposed. In other cases, at least a portion of the gap filler 402 may remain above the distal end of the semiconductor die 302 opposite the carrier substrate 304. Generally, only the gap filler 402 or the gap filler 402 and the semiconductor die 302 may form a planar surface on which additional material can be disposed.

[0036] As described, a dielectric material layer 502 is disposed over the gap filler material 402. The dielectric material layer 502 may be a dielectric block comprising silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or the like. The dielectric material 502 (and, in the case where the gap filler material is disposed above the semiconductor die 302, the gap filler material 402) may be etched to expose a TSV 404 at the distal end of the semiconductor die 302. A contact 504 may then be disposed in an opening etched to expose the TSV 404 to achieve electrical contact with a functional circuit system at the semiconductor die 302. The contact 504 may be implemented by disposing a conductive material within the opening. In some cases, a copper damascene process may be used to implement the contact.

[0037] In some embodiments, the dielectric material layer 502 may be similarly etched at locations not containing the TSV 404. For example, an opening may be created at a location not containing the TSV 404, outside the occupied area of ​​the semiconductor die 302 but above the space fill material 402. A conductive material may be disposed at the opening to implement a dummy pad 506 disconnected from the functional circuitry at the semiconductor die 302. In one aspect, the dummy pad 506 may be positioned to maintain a similar spacing between the contact 504 and the dummy pad 506 across the surface. In this way, the dummy pad 506 may reduce recesses caused by planarization or other assembly processes at the surfaces where the contact 504 and the dummy pad 506 are disposed. In yet another aspect, the dummy pad 506 may be used to mechanically couple additional components to the semiconductor die 302 or the space fill material 402.

[0038] Then turn to Figure 6In stage 600, a semiconductor wafer stack 602 is provided. The semiconductor wafer stack 602 is bonded to a carrier wafer 604 to enable the semiconductor wafers to withstand processing. A semiconductor wafer 606 is bonded to the carrier wafer 604. TSVs or other contacts coupled to functional circuitry within the semiconductor wafer 606 may be exposed at the semiconductor wafer 606, and contact pads may be disposed thereon. A second semiconductor wafer 608 may be electrically and mechanically coupled to the first semiconductor wafer 606 at the contact pads via wafer-to-wafer bonding (e.g., hybrid bonding) (e.g., face-to-back configuration). The semiconductor wafer stack 602 may then be processed and diced to monolithically stack individual semiconductor dies.

[0039] For example, the semiconductor wafer stack 602 can be bonded to a back-grinding tape and the semiconductor wafer 608 can be thinned by any suitable method (e.g., back-grinding, CMP, or the like). After thinning, the back-grinding tape can be removed from the semiconductor wafer stack 602, and the semiconductor wafer stack 602 can be attached to a dicing tape. Once attached to the dicing tape, the semiconductor wafer stack 602 can be diced into multiple semiconductor die stacks.

[0040] Although only two semiconductor wafers are described, additional semiconductor wafers can be attached to the semiconductor wafer stack 602 via a similar process as described with respect to semiconductor wafers 606 and 608. In this way, semiconductor die stacks with different numbers of semiconductor dies can be assembled.

[0041] Then turn to Figure 7 In stage 700, semiconductor dies 702', semiconductor dies 702'', and any other number of semiconductor dies (collectively referred to as semiconductor die stack 702) are assembled onto the reconstructed wafer of semiconductor die 704. Semiconductor dies 702 can be obtained from... Figure 6 The semiconductor wafer stack 602 is single-chipped. The reconstructed wafer of the semiconductor bare die 704 can correspond to the... Figure 5 The reconstructed wafer, formed in stage 500 as described herein and supported by a carrier substrate 304, is a semiconductor die. The semiconductor die 702 can (e.g., via...) Figure 5 The dielectric material layer 502 and contacts 504 described herein are mechanically and electrically coupled to the reconstructed wafer of the semiconductor die 704. For example, multiple semiconductor dies 702 may be coupled to a single semiconductor die at different lateral locations. The semiconductor die 702 may be formed by chip-to-wafer bonding (e.g., hybrid bonding).

[0042] In some cases, from Figure 6The semiconductor dies 702, which are monolithically represented by the semiconductor wafer stack 602, can be tested before being included in a semiconductor device assembly. Semiconductor dies 702 can be selected based on quality. For example, the operability of each of the semiconductor dies 702 can be determined by probing, and once a semiconductor die 702 is determined to be operable, it can be coupled to the reconstructed wafer of semiconductor die 704. In this way, the semiconductor dies 702 coupled to the reconstructed wafer of semiconductor die 704 can be a "known good cube" (or a stack determined to be operable), which can improve yield.

[0043] In some cases, one or more of the semiconductor dies 702 can be replaced by dummy semiconductor components, such as regarding Figure 2A and 2B As discussed above, in this aspect, a dummy semiconductor component can be coupled to the reconstructed wafer of semiconductor die 704 via a process similar to that described for semiconductor die 702. However, since the dummy semiconductor component is not electrically coupled to the reconstructed wafer of semiconductor die 704, the dummy semiconductor component can be coupled via a dummy pad or dielectric material instead of contacts coupled to the functional circuitry system at the reconstructed wafer of semiconductor die 704.

[0044] Then turn to Figure 8 In stage 800, the semiconductor die 702 is at least partially surrounded by a gap-filling material 802 (e.g., a dielectric material or oxide filler). Figure 3 As discussed herein, a stack of multiple semiconductor dies (e.g., semiconductor die 702' and semiconductor die 702'') may be attached to a single semiconductor die (e.g., semiconductor die 302'). For example, semiconductor die 702' may include contacts 804 coupled to a functional circuit system at semiconductor die 702' via a connection circuit system, and contacts 804 may be coupled to contacts 504 at semiconductor die 302' to form an interconnect coupling the functional circuit system at semiconductor die 702' to semiconductor die 302'. Furthermore, a dielectric layer at semiconductor die 702' may be mechanically coupled to a dielectric layer 502 at semiconductor die 302'. In some cases, semiconductor dies 702 and 302 may be mechanically coupled via a dummy pad 506. Similar operations can be performed to couple semiconductor die 702'' to semiconductor die 302', and to couple other sets of semiconductor dies (e.g., semiconductor die 702''' and semiconductor die 702'''') to additional semiconductor dies (e.g., semiconductor die 302'') in the reconstructed wafer of semiconductor die 704.

[0045] Interval filler material 802 (e.g., dielectric material, oxide filler, or the like) may be disposed outside the occupied area of ​​semiconductor die 702 at semiconductor die 302 and interval filler material 402. In some cases, interval filler material 802 may be disposed over the distal end of semiconductor die 702 opposite to carrier substrate 304. Thus, a portion of interval filler material 802 may at least partially surround the distal end of semiconductor die 702. In some cases, interval filler material 802 may be disposed over the distal end of semiconductor die 702, and interval filler material 802 may be thinned until no interval filler material 802 or a small portion of interval filler material 802 remains over the distal end of semiconductor die 702.

[0046] As described, a cap 806 is positioned over the semiconductor die 702. For example, the cap 806 may be attached to the gap filler 802 or the distal end of the semiconductor die 702 opposite the carrier substrate 304 by an adhesive or by a dielectric material (e.g., a dielectric block). The cap 806 may comprise a semiconductor material, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. The cap 806 may improve the mechanical strength of the assembly or increase the thickness of the assembly to meet the design requirements of a semiconductor device assembly.

[0047] Generally speaking, Figure 7 and 8 This describes a technique for attaching semiconductor die 702 to semiconductor die 302 via a chip-to-wafer process. Alternatively, semiconductor die 702 can be attached to semiconductor die 302 via a wafer-to-wafer process. For example, see [link to documentation]. Figure 9 In stage 900, the semiconductor die 702 can be coupled to the carrier substrate 902 and filled with gap-filling material 802 to form a reconstructed wafer. The semiconductor die 702 can be positioned corresponding to the semiconductor die to which it is attached (e.g., Figure 5 The semiconductor die 302 is coupled to the carrier substrate 902 at a lateral position. For example, semiconductor dies 702' and 702'' may be disposed on the first semiconductor die to which they are attached (e.g., Figure 5 The semiconductor die 702'' is located at a lateral position within the occupied area of ​​the semiconductor die 302', and the semiconductor die 702''' and the semiconductor die 702'''' can be disposed on the second semiconductor die to which it is attached (e.g., Figure 5 The semiconductor die 702 is located at a lateral position within the occupied area of ​​the semiconductor die 302''. The semiconductor die 702 can be selected as a "known good cube" before being attached to the carrier substrate 902, thus improving yield. The semiconductor die 702 can be attached to the carrier substrate 902 by adhesive or dielectric material.

[0048] Interval filler material 802 may be disposed outside the occupied area of ​​semiconductor die 702 at carrier substrate 902 to form a reconstructed wafer. In some cases, interval filler material 802 may be disposed over the distal end of semiconductor die 702 opposite to carrier substrate 902. Cap 806 may be disposed over semiconductor die 702 and interval filler material 802 to increase the thickness of the assembly or to increase the mechanical strength of the assembly. Upon assembly, semiconductor die 702 and interval filler material 802 can form a continuous wafer-like structure, where wafer-level processes such as wafer-to-wafer bonding can be performed.

[0049] Then turn to Figure 10 In stage 1000, the reconstructed wafer formed from semiconductor die 702 and gap filler material 802 is coupled to the reconstructed wafer formed from semiconductor die 302 and gap filler material 402. For example, semiconductor die 702 can be coupled to it in... Figure 9 In stage 900, the carrier substrate 902 to which the semiconductor die 702 is attached is separated, and the contact 804 can be disposed at the exposed surface. Next, semiconductor die 702 and semiconductor die 302 can be coupled via wafer-to-wafer bonding (e.g., hybrid bonding). For example, semiconductor die 702' and semiconductor die 702'' can be coupled to semiconductor die 302' (e.g., electrically and mechanically) via contact 804 and contact 504. Semiconductor die 702''' and semiconductor die 702'''' can similarly be attached to semiconductor die 302''.

[0050] In this regard, coupling semiconductor die 702 to semiconductor die 302 via chip-to-wafer and wafer-to-wafer processes can result in similar assemblies. In some cases, wafer-to-wafer processes may have advantages over chip-to-wafer processes. For example, wafer-to-wafer processes may have higher yields. Furthermore, interconnects formed via wafer-to-wafer processes can have better alignment. However, generally, once semiconductor die 702 and semiconductor die 302 are coupled via chip-to-wafer or wafer-to-wafer processes, the assemblies can be monolithically assembled and packaged into individual devices.

[0051] Although each of the semiconductor dies 302 is described as being related to Figure 8 and 10The semiconductor dies 702 are coupled in some embodiments, but one or more of the semiconductor dies 702 may be coupled to a dummy semiconductor component lacking functional circuitry. In some cases, the dummy semiconductor component may replace one or more of the semiconductor dies 702. In other cases, the dummy semiconductor component may be used to fill space and provide thermal regulation between the semiconductor dies 702. Generally, the dummy semiconductor component may be coupled to the semiconductor die 302 via a process similar to that described for semiconductor die 702, but no electrical interconnect is formed between the dummy semiconductor component and the semiconductor die 302.

[0052] Then turn to Figure 11 In stage 1100, the assemblies are monolithized and packaged into a single semiconductor device. For example, in... Figure 8 Stage 800 or Figure 10 The assembly of stage 1000 can be sawn at the gap filler material 402, gap filler material 802, and cap 806 between semiconductor dies 302. As described, the semiconductor device including semiconductor dies 302', semiconductor dies 702', and semiconductor dies 702'' is monolithically assembled and packaged. By sawing through the gap filler material 402 and gap filler material 802, the gap filler material 402 and gap filler material 802 form peripheral portions along the sidewalls of semiconductor dies 302' and semiconductor dies 702, respectively. Contact 1102 is disposed at and coupled to the circuit system at semiconductor die 302' to provide external connectivity to semiconductor dies 302' and semiconductor dies 702.

[0053] Semiconductor die 302' is attached to package-grade substrate 1104 (e.g., printed circuit board (PCB), semiconductor substrate, or the like). Interconnects 1106 (e.g., solder, conductive pillars, or the like) may be formed between contacts 1102 on the bottom surface of semiconductor die 302' and contacts (not shown) on package-grade substrate 1104 to enable the transmission of electrical signals between semiconductor die 302' (or semiconductor die 702) and package-grade substrate 1104. Package-grade substrate 1104 may further include package-grade contact pads (not shown) that provide external connectivity (e.g., power, ground, and input / output (I / O) signals) to semiconductor die 302' and semiconductor die 702 (e.g., power, ground, and I / O signals) via solder balls 1108 or other connection structures. Traces, lines, vias, and other electrical connection structures in package-grade substrate 1104 may electrically connect the package-grade contact pads to contact pads on the upper surface of package-grade substrate 1104.

[0054] An underfill material 1110 (e.g., capillary underfill) may be provided between the semiconductor die 302' and the package-grade substrate 1104 to provide electrical insulation to the interconnect 1106 and structurally support the device. The semiconductor die 302', semiconductor die 702, and package-grade substrate 1104 may be at least partially encapsulated by an encapsulating material 1112 (e.g., a molding resin compound or the like) to prevent electrical contact therewith and to provide mechanical strength and protection to the assembly.

[0055] Although the semiconductor device assembly has been described and depicted in the foregoing exemplary embodiments as having a specific configuration including semiconductor dies, in other embodiments, the assembly may have different configurations of semiconductor dies. For example, the semiconductor device assembly described in any of the foregoing examples may be implemented using (for example) vertical semiconductor dies, multiple semiconductor dies, or a single semiconductor die (with appropriate modifications).

[0056] According to one aspect of this disclosure, in Figures 1A to 11 The semiconductor device described in the assembly may be a memory die, such as a DRAM die, a NAND memory die, a NOR memory die, a magnetic random access memory (MRAM) die, a phase-change memory (PCM) die, a ferroelectric random access memory (FeRAM) die, an SRAM die, or the like. In embodiments in which multiple dies are disposed in a single assembly, the semiconductor device may comprise the same type of memory dies (e.g., both are NAND, both are DRAM, etc.) or different types of memory dies (e.g., one is DRAM and one is NAND, etc.). According to another aspect of this disclosure, the semiconductor dies of the assemblies described above may be logic dies (e.g., controller dies, processor dies, etc.), or a mixture of logic dies and memory dies (e.g., a memory controller die and memory dies controlled by it).

[0057] The above text is about Figures 1A to 11 Any of the described semiconductor devices and semiconductor device assemblies can be incorporated into any of a multitude of larger and / or more complex systems, a representative example of which is... Figure 12 The system 1200 is shown schematically in the image. (Example) Figures 1A to 11The semiconductor dies provided can communicate with one or more devices within system 1200 using one or more standard protocols. For example, the memory can communicate using the High Bandwidth Memory (HBM) protocol. Alternatively, the memory can communicate using any other suitable protocol. System 1200 may include a semiconductor device assembly 1202 (e.g., a discrete semiconductor device), a power supply 1204, a driver 1206, a processor 1208, and / or other subsystems or components 1210. Semiconductor device assembly 1202 may include components related to those described above. Figures 1A to 11 The described semiconductor device assemblies are characterized by generally similar features. The resulting system 1200 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 1200 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. Components of system 1200 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 1200 may also include remote devices and any of a wide variety of computer-readable media.

[0058] Figure 13 A method 1300 for manufacturing a semiconductor device assembly according to an embodiment of the present technology is described. Although described with a particular configuration, one or more operations of method 1300 may be omitted, repeated, or rearranged. Furthermore, method 1300 may include... Figure 13 Other operations not described herein, for example, those detailed in one or more other methods described herein.

[0059] At 1302, a carrier wafer is provided. The carrier wafer may contain semiconductor material. The carrier wafer may have sufficient thickness to support the assembly during processing.

[0060] At 1304, a plurality of first semiconductor dies (e.g., logic dies) are placed at corresponding locations on the carrier wafer. For example, the plurality of first dies may be selected as "known good dies" and assembled to different locations on the carrier wafer. The first dies may be attached to the carrier wafer by adhesive or dielectric material.

[0061] At 1306, a gap-filling material is disposed over a carrier wafer and at least partially surrounds a plurality of first dies to form a first reconstructed wafer. The gap-filling material may comprise a dielectric material or an oxide filler. In some cases, the gap-filling material comprises silicon oxide. The gap-filling material may be disposed outside the occupied area of ​​the first dies and extend along the edges of the first dies. In some cases, the gap-filling material may be disposed over the distal ends of the first dies opposite the carrier wafer. By filling the spaces between the first dies, the reconstructed wafer can be formed from the first dies that have been determined to be operable.

[0062] At 1308, the corresponding group of second semiconductor dies and corresponding additional semiconductor components are coupled to each corresponding logic die among a plurality of logic dies. In one aspect, the second semiconductor die includes a memory die (e.g., a DRAM die or an SRAM die). The additional semiconductor component may include components implemented using semiconductor materials. For example, the additional semiconductor component may include a semiconductor die, such as a memory die. In some cases, the second semiconductor die and the additional semiconductor component may include the same or different types of memory dies. For example, the second semiconductor die may include a DRAM die, and the additional semiconductor component may include an SRAM die. In some cases, the additional semiconductor component may include a dummy semiconductor component lacking a functional circuit system. In this way, the dummy semiconductor component may fill space or improve thermal regulation rather than increase the functionality of the device.

[0063] The corresponding set of second semiconductor dies and corresponding additional semiconductor components can be coupled to the first die via a chip-to-wafer or wafer-to-wafer process. For example, using chip-to-wafer processing, the corresponding set of second semiconductor dies and corresponding additional semiconductor components can be individually attached to the wafer of the first die. Alternatively, using wafer-to-wafer processing, the corresponding set of second semiconductor dies and corresponding additional semiconductor components can be formed as reconstructed wafers, which are coupled to the reconstructed wafer formed from the first die. For example, the corresponding set of second semiconductor dies and corresponding additional semiconductor components can be attached to a second carrier wafer and surrounded by a gap-filling material. The carrier wafer can then be removed, and the reconstructed wafer can be attached to the reconstructed wafer of the first die.

[0064] At 1310, additional gap filler material is disposed outside each respective group of second semiconductor dies and each respective additional semiconductor component. When forming an assembly via a chip-to-wafer process, the additional gap filler material may be disposed on the logic die or on the gap filler material disposed at 1306. Alternatively, when forming an assembly via a wafer-to-wafer process, the additional gap filler material may be disposed at the second carrier wafer when reconstructing the wafer from the second semiconductor dies and additional semiconductor components. The additional gap filler material may be exposed outside the occupied area of ​​the respective group of second semiconductor dies and each respective additional semiconductor component. In some cases, the additional gap filler material may be disposed at the distal end of one or more of the second semiconductor dies or additional semiconductor components.

[0065] At 1312, the assembly can be sawed through the gap filler material and additional gap filler material to monolithize each corresponding first die. In this way, a single semiconductor device comprising a first die, a second semiconductor die, and additional semiconductor components can be monolithized. The single device can then be packaged and transported.

[0066] The foregoing describes specific details of several embodiments of semiconductor devices and associated systems and methods. Depending on the context in which the term "substrate" is used, it may refer to a wafer-level substrate or a monolithically prepared die-level substrate. Furthermore, unless the context otherwise indicates, conventional semiconductor manufacturing techniques can be used to form the structures disclosed herein. Examples of techniques for depositing materials include chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, examples of techniques for removing materials include plasma etching, wet etching, CMP, or other suitable techniques.

[0067] The technologies disclosed herein relate to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include, in particular, logic devices, memory devices, and diodes. Furthermore, the term "semiconductor device" may refer to a finished device or an assembly or other structure at various processing stages prior to becoming a finished device. Depending on the context in which the term "substrate" is used, it may refer to a structure supporting electronic components (e.g., a die), such as a PCB or wafer-level substrate, a die-level substrate, or another die for die stacking or three-dimensional integration (3DI) applications.

[0068] The devices discussed herein (including memory devices) can be formed on a semiconductor substrate or die (e.g., silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0069] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functions may also be physically located in various locations, including portions distributed such that the functions are implemented in different physical locations.

[0070] As used herein, the word "or," as included in the claims and as used in a list of items (for example, a list of items beginning with phrases such as "at least one of..." or "one or more of..."), indicates an inclusive list such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0071] As used herein, the terms “vertical,” “horizontal,” “up,” “down,” “above,” and “below” can refer to the relative orientation or position of a feature in a semiconductor device given the orientation shown in the figures. For example, “up” or “topmost” can refer to a feature positioned closer to the top of the page than another feature. However, such terms should be interpreted broadly to include semiconductor devices with other orientations (e.g., inverted or tilted orientations), where top / bottom, above / below, above / below, up / down, and left / right can be interchanged depending on the orientation.

[0072] As should be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details are set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details described herein. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the present technology. Generally, it should be understood that various other devices, systems, and methods, in addition to the specific embodiments disclosed herein, may also be within the scope of the present technology.

Claims

1. A semiconductor device assembly comprising: A first semiconductor die having a first side and a second side; A dielectric peripheral material is disposed against the sidewall of the first semiconductor die and extends beyond the first occupied area of ​​the first semiconductor die between the first side and the second side; One or more second semiconductor dies are electrically and mechanically coupled to the first semiconductor die at a first position on the second side; An additional semiconductor component is mechanically coupled to the first semiconductor die at a second location on the second side, different from the first location; and A gap-filling material is disposed above the first semiconductor die and above the dielectric peripheral material, outside the second occupied area of ​​the one or more second semiconductor dies and the third occupied area of ​​the additional semiconductor assembly, the gap-filling material at least partially surrounding the one or more second semiconductor dies and the additional semiconductor assembly.

2. The semiconductor device assembly of claim 1, wherein the additional semiconductor component comprises one or more third semiconductor dies.

3. The semiconductor device assembly according to claim 2, wherein: The one or more second semiconductor dies include memory dies of the first type; and The one or more third semiconductor dies include memory dies of a second type, which are different from the first type.

4. The semiconductor device assembly of claim 1, wherein the additional semiconductor component includes a dummy semiconductor component lacking a functional circuit system.

5. The semiconductor device assembly of claim 4, wherein the first semiconductor die includes a dummy conductive pad electrically disconnected from the circuitry at the first side of the first semiconductor die, the dummy conductive pad being disposed at the second location on the second side within the third occupied area of ​​the additional semiconductor assembly.

6. The semiconductor device assembly of claim 1, wherein: The one or more second semiconductor dies comprise a stack of second semiconductor dies having a first height along the dimension of the second semiconductor dies in the stack; and The additional semiconductor component has a second height along the dimension, the second height being equal to the first height.

7. The semiconductor device assembly of claim 1, further comprising one or more dummy conductive pads disconnected from the circuitry at the first side of the first semiconductor die, the one or more dummy conductive pads being disposed at the second side of the first semiconductor die or at the dielectric peripheral material outside the second occupied area of ​​the one or more second semiconductor dies and the third occupied area of ​​the additional semiconductor assembly.

8. A method for manufacturing a semiconductor device assembly, comprising: Provide carrier chips; Multiple first semiconductor dies are placed at corresponding positions on the carrier wafer; A gap-filling material is placed above the carrier wafer and at least partially surrounds the plurality of first semiconductor dies; For each of the plurality of logic dies, a corresponding first group of one or more semiconductor dies and a corresponding additional semiconductor component are coupled to the corresponding first semiconductor die in the plurality of first semiconductor dies. The corresponding first group of one or more semiconductor dies are disposed at a corresponding first position of the corresponding first semiconductor die, and the corresponding additional semiconductor component is disposed at a corresponding second position of the corresponding first semiconductor die that is different from the corresponding first position. Additional gap filler material is placed above each corresponding first semiconductor die and above the gap filler material, outside each corresponding first group of one or more semiconductor dies and each corresponding additional semiconductor assembly; and The gap filler material and the additional gap filler material between each corresponding first semiconductor die are sawed through to monolithize each corresponding semiconductor die.

9. The method of claim 8, further comprising: A wafer comprising the plurality of first semiconductor dies is provided; The plurality of first semiconductor dies are cut from the wafer of the semiconductor die; The plurality of first semiconductor dies are probed to determine the quality of the plurality of first semiconductor dies; and Determining that the plurality of first semiconductor dies are operable, wherein placing the plurality of first semiconductor dies at corresponding positions on the carrier wafer is in response to determining that the plurality of first semiconductor dies are operable.

10. The method of claim 8, further comprising: The gap-filling material is placed above the distal ends of the plurality of first semiconductor dies opposite to the carrier wafer; A portion of the gap filler material is removed to expose a corresponding contact at the distal end of each of the plurality of first semiconductor dies, the corresponding contact being coupled to a corresponding circuit system at the corresponding first semiconductor die; and For each of the plurality of first semiconductor dies, the corresponding first group of one or more semiconductor dies is coupled to the corresponding first semiconductor die at the corresponding contact.

11. The method of claim 8, further comprising placing one or more corresponding dummy contacts at the distal end of the gap filling material opposite to the carrier wafer or at the distal end of a corresponding first semiconductor die among the plurality of first semiconductor dies opposite to the carrier wafer, wherein the one or more corresponding dummy contacts are disconnected from the corresponding circuit system at the corresponding first semiconductor die.

12. The method of claim 8, further comprising: Separate the carrier wafer from the plurality of first semiconductor dies; and For each of the plurality of first semiconductor dies, a corresponding contact is disposed at the corresponding first semiconductor die, and the corresponding contact is coupled to a corresponding circuit system at the corresponding first semiconductor die.

13. The method of claim 8, wherein the corresponding additional semiconductor component includes a corresponding dummy semiconductor component lacking a functional circuit system.

14. The method of claim 8, wherein the respective additional semiconductor component comprises a respective second group of one or more semiconductor dies.

15. The method of claim 14, wherein: The corresponding first group of one or more semiconductor dies includes memory dies of a first type; and The corresponding second group of one or more semiconductor dies includes a second type of memory die that is different from the first type.

16. A method for manufacturing a semiconductor device assembly, comprising: Provide the first carrier chip; Multiple first semiconductor dies are placed at corresponding first positions on the first carrier wafer; A gap-filling material is placed above the first carrier wafer and at least partially surrounds the plurality of first semiconductor dies to form a first reconstructed wafer; Provide a second carrier chip; One or more second semiconductor dies and additional semiconductor components are disposed at corresponding second positions on the second carrier wafer, wherein the corresponding second positions on the second carrier wafer correspond to the corresponding first positions on the first carrier wafer; Additional gap-filling material is placed over the second carrier wafer and at least partially surrounds the corresponding group of one or more second semiconductor dies and the additional semiconductor components to create a second reconstructed wafer; Separate the second carrier wafer from the corresponding group of one or more second semiconductor dies, the additional semiconductor components, and the additional gap filler material; In response to separating the second carrier wafer from the corresponding group of one or more second semiconductor dies and the additional semiconductor components and the additional gap filler material, the second reconstructed wafer and the first reconstructed wafer are coupled such that each of the corresponding group of one or more second semiconductor dies and the additional semiconductor components is coupled to a corresponding first semiconductor die of the plurality of first semiconductor dies; and The gap filler material and the additional gap filler material between each corresponding first semiconductor die are sawed through to monolithize each corresponding first semiconductor die.

17. The method of claim 16, wherein the additional semiconductor component comprises a dummy semiconductor component lacking a functional circuit system.

18. The method of claim 16, wherein the additional semiconductor component comprises one or more third semiconductor dies.

19. The method of claim 18, wherein: The one or more second semiconductor dies include memory dies of the first type; and The one or more second semiconductor dies include memory dies of a second type that are different from the first type.

20. The method of claim 17, further comprising placing one or more corresponding dummy contacts at the distal end of the gap filler material opposite to the carrier wafer or at the distal end of a corresponding first semiconductor die among the plurality of first semiconductor dies opposite to the carrier wafer, wherein the one or more corresponding dummy contacts are disconnected from the corresponding circuitry at the corresponding first semiconductor die.

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