Monolithic rgb micro-led array

Abstract

A light emitting diode (LED) pixel array and a method of manufacturing the same. A semiconductor wafer template includes a continuous stack of a lower n-GaN layer, a lower MQW layer, a lower p-GaN layer, an upper n-GaN layer, and a dielectric layer. A plurality of openings are formed through the dielectric layer, extending to the upper n-GaN layer. A plurality of mesas are formed by forming, within each opening, a mesa n-GaN layer, a mesa MQW layer over each mesa n-GaN layer, and a mesa p-GaN layer over each mesa MQW layer. The mesa n-GaN layer, the mesa MQW layer, and the mesa p-GaN layer of each mesa form a respective mesa LED. The lower n-GaN layer, the lower MQW layer, and the lower p-GaN layer form a lower LED.

Description

Priority Statement

[0001] This application claims the priority of U.S. Provisional Application Serial No. 63 / 596,174, filed November 3, 2023, and U.S. Patent Application Serial No. 18 / 924,840, filed October 23, 2024, each of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates generally to the manufacture of light-emitting diodes (LEDs), and more specifically to the manufacture of monolithic red micro-LED / green micro-LED / blue micro-LED pixel arrays. Background Technology

[0003] III-nitride LEDs grown at the micrometer scale are called micro-LEDs, or simply micro-LEDs, micro-LEDs, or μLEDs. Typically, μLEDs have a diameter of 50 micrometers or less. μLEDs are expected to provide the foundation for next-generation displays and visible light communication (VLC) applications. Compared to organic light-emitting diodes (OLEDs) and liquid crystal displays (LCDs), III-nitride μLEDs exhibit several unique characteristics for display applications. Unlike LCDs, III-nitride micro-displays using μLEDs are self-emitting. Monochrome displays using μLEDs typically exhibit high resolution, high efficiency, and high contrast. OLEDs typically operate at current densities several orders of magnitude lower than semiconductor LEDs to maintain a reasonable lifetime. Therefore, the brightness of OLEDs is lower than that of III-nitride μLEDs. Furthermore, compared to OLEDs, III-nitride μLEDs inherently exhibit longer operating lifetimes and chemical robustness. Therefore, it is anticipated that in the near future, III-nitride μLEDs may potentially replace LCDs and OLEDs in a wide range of applications, such as smartphones, for high-resolution and high-brightness displays. Attached Figure Description

[0004] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals may describe similar parts in different views. To facilitate identification of any particular element or action being discussed, one or more of the highest-ranking digits in the reference numerals indicate the drawing number in which that element was first introduced. Some non-limiting examples are shown in the figures below:

[0005] Figure 1 The operation of an example method for manufacturing an LED pixel array is shown according to some examples.

[0006] Figure 2 A cross-sectional view of a first example semiconductor wafer template is shown, based on some examples.

[0007] Figure 3 The following are examples of methods for obtaining semiconductor wafer templates. Figure 1 The example operation of the method is a suboperation.

[0008] Figure 4 The following is illustrated, according to some examples, after the first LED pixel array manufacturing operation. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0009] Figure 5 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0010] Figure 6 Four different orientations of surfaces formed by a hexagonal crystal structure are shown, based on some examples.

[0011] Figure 7 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0012] Figure 8 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0013] Figure 9 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0014] Figure 10 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0015] Figure 11 The following are examples of LED pixel array manufacturing operations. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0016] Figure 12 The diagram illustrates, according to some examples, the subsequent LED pixel array manufacturing operations used to form the first example LED pixel structure. Figure 2 A cross-sectional view of a semiconductor wafer template.

[0017] Figure 13 The following are examples of the basis. Figure 12 A top view of the LED pixel structure. Detailed Implementation

[0018] Examples of this disclosure provide monolithic red-green-blue (RGB) LED pixels, LED pixel arrays, and methods for manufacturing the same. In some examples, the LED pixel structure (e.g., a micro-LED pixel structure) can be fabricated using a semiconductor wafer template to include a first multiple quantum well (MQW) layer and one or more mesa formed above the lower MQW layer. The lower MQW layer can be configured as part of an LED to emit a single color of light, such as blue light, or the LED can be configured to be tunable between two colors of light, such as a tunable blue LED / green LED. Each mesa provides additional LEDs, such as red LEDs or tunable red / green LEDs. The LED pixel structure can be formed using wafer-level epitaxial and etching techniques to create an array of LED pixel structures.

[0019] Therefore, some of the examples described herein attempt to address one or more technical problems in the fabrication of micro-LEDs. By using epitaxial growth to fabricate monolithic multicolor micro-LED arrays at the wafer level, some examples can avoid the need to stack and bond multiple wafers. Additionally, some examples can avoid damage to the sidewalls of micro-LEDs typically caused by etching in conventional micro-LED fabrication methods, potentially improving LED performance.

[0020] As used herein, the “color” of an LED, multi-quantum-well stack, or other light-emitting component can refer to the dominant or center wavelength of the light emitted by the component. The wavelength of light emitted by a given LED can be controlled using various techniques, such as controlling the size of the LED, and / or the structure, material composition, and / or size of the multi-quantum-well stack of the LED.

[0021] Some examples described herein can utilize tunable multicolor LEDs, such as red / green or blue / green LEDs. Tunable multicolor LEDs can be fabricated using various techniques: for example, blue-green light emission from a blue LED / green LED or red-green light emission from a red LED / green LED can be achieved by utilizing a blue shift phenomenon caused by band-filling and piezoelectric shielding effects. In examples using group III nitride LEDs, this blue shift phenomenon is unavoidable but can be reduced by optimizing the LED epitaxial structure. For example, more quantum well (QW) layers can be grown to reduce the carrier density between each QW, V-shaped pits can be formed on the MQW surface to increase the uniformity of current injection into each QW, and / or the strain on the MQW can be reduced to decrease the piezoelectric field. However, the tunable LEDs described herein can utilize the blue shift phenomenon to modulate the wavelength of the emitted light by modulating the current injection, such that an increase in the injection current shifts the light wavelength toward a shorter (bluer) wavelength.

[0022] As used herein, terms such as “above,” “below,” “upper,” “lower,” and other terms referring to relatively vertical positions are intended to denote the relative positions of various features with respect to a reference frame in which a surface perpendicular to the substrate surface used in semiconductor fabrication (e.g., a crystal substrate surface) defines an upward direction. It will be understood that portions of the fabricated semiconductor device remote from the substrate surface are referred to as “above” those portions closer to the substrate surface, even though the semiconductor device may be fabricated in contact with the substrate surface in any orientation relative to the Earth’s gravitational field or any other reference frame, and even though the semiconductor device may be used in any orientation after fabrication.

[0023] Other technical features and / or benefits will be readily apparent to those skilled in the art from the accompanying drawings, description and claims.

[0024] Figure 1 An example method 100 for manufacturing an LED pixel array is shown. Although the example method 100 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not substantially affect the functionality of method 100. In other examples, different components of the example apparatus or system implementing method 100 may perform their functions substantially simultaneously or in a specific order.

[0025] Refer to the example LED pixel structure (for example, see below) Figure 12 The example method 100 is described in connection with the fabrication of the pixel structure 1200. It will be understood that in other examples, method 100 may be performed to fabricate devices with structures or properties different from the example pixels and pixel arrays described herein. In some examples, the operation of method 100 may be performed at the wafer level to form a micro-LED pixel array, such that thousands or millions of LED pixel structures are simultaneously formed within the wafer. Wafer-level deposition techniques such as metal-organic chemical vapor deposition (MOCVD) may be used to perform epitaxial or overgrowth operations and other deposition operations, and selective etching operations may be performed using photolithography combined with wafer-level or at least multi-pixel-level wet or dry etching. In some examples, the semiconductor materials used in method 100 include p-type gallium nitride and n-type gallium nitride (p-GaN and n-GaN) materials, and wet etching may be used only in etching operations contacting the p-GaN material or MQW stack to prevent damage to the p-GaN structure caused by dry etching.

[0026] The following reference is provided. Figures 2 to 12The example method 100 is described by way of example LED pixel array fabrication operations performed on the first example semiconductor wafer template 200. It will be understood that in other examples, method 100 may be performed using operations different from the example operations and structures shown and described.

[0027] According to some examples, method 100 includes obtaining a semiconductor wafer template at operation 102. See below. Figure 2 This describes an example semiconductor wafer template. In some examples, operation 102 includes a sequence of sub-operations for fabricating the semiconductor wafer template 200, as described below. Figure 3 describe.

[0028] Figure 2 A cross-sectional view of a first example semiconductor wafer template 200 is shown. In some examples, the semiconductor wafer template 200 is obtained in a prefabricated form as a laminated structure of continuously stacked layers: a lower n-GaN layer 206, a lower MQW layer 208, a lower p-GaN layer 210, and a dielectric layer 214. In some examples, the semiconductor wafer template 200 is constructed using the following reference... Figure 3 The sequence of one or more sub-operations of the described operation 102 is formed (or further formed).

[0029] Figure 3 An example of a sub-operation of operation 102 of method 100 is shown. Although Figure 3 The flowchart depicts a specific sequence of operations, but this sequence may be changed without departing from the scope of this disclosure. For example, some of the operations depicted may be performed in parallel or in a different order that does not substantially affect the functionality of the routine. In other examples, different components of an example apparatus or system implementing the routine may perform their functions substantially simultaneously or in a specific order.

[0030] According to some examples, operation 102 includes growing a lower n-GaN layer 206 on a substrate at sub-operation 302. In some examples, the substrate is a substrate layer 202 suitable for semiconductor growth. In some examples, the substrate also includes a buffer, such as an undoped gallium nitride layer (shown as a u-GaN buffer layer 204), grown above the substrate layer 202.

[0031] According to some examples, operation 102 includes growing a lower MQW layer 208 on the lower n-GaN layer 206 at sub-operation 304. In some examples, the lower MQW layer 208 is a multi-quantum well stack optimized or configured to emit a single specific color of light, such as a blue MQW layer configured to emit blue light. In some examples, the lower MQW layer 208 is a tunable multi-quantum well stack configured to be tunable between the emission of two colors of light, such as a blue MQW layer / green MQW layer configured to be tunable between blue and green light.

[0032] According to some examples, operation 102 includes growing a lower p-GaN layer 210 above the lower MQW layer 208 at sub-operation 306. When stimulated by an electrical signal delivered via a p-contact formed on the lower p-GaN layer 210 and an n-contact formed on the lower n-GaN layer 206, the lower p-GaN layer 210, the lower MQW layer 208, and the lower n-GaN layer 206 together form a first LED, such as a blue LED or a tunable blue-green LED, as shown below. Figure 12 As described.

[0033] According to some examples, operation 102 may optionally include cleaning the upper surface of the lower p-GaN layer 210 at sub-operation 308. In some cases, growing an n-GaN layer (e.g., upper n-GaN layer 212) over the lower p-GaN layer 210 may be challenging. If the semiconductor wafer template 200 is formed in the same growth chamber used for operation 106, it may be necessary to perform surface cleaning of the top surface of the lower p-GaN layer 210 before further n-type semiconductor overgrowth over the lower p-GaN layer 210. Surface cleaning removes magnesium and / or other p-type surface dopants used during p-GaN growth that pose a risk of contaminating subsequent n-GaN layers (e.g., upper n-GaN layer 212), resulting in a vertical doping gradient from p-type to n-type doping within the n-GaN layer as magnesium is depleted during the n-type growth process (e.g., sub-operation 312 described below). In some examples, operation 308 can be omitted; depending on the technology used for wafer fabrication, the tunnel junction 216 can be formed between the lower p-GaN layer 210 and the upper n-GaN layer 212 without performing wafer surface cleaning operation 308.

[0034] According to some examples, operation 102 includes forming a tunnel junction 216 above the lower p-GaN layer 210 at sub-operation 310. In some examples, the tunnel junction 216 is a heavily doped positive-negative (PN) junction. The thickness of the tunnel junction 216 can be approximately 10 nanometers (nm). Heavy doping results in a broken bandgap, where the conduction band electronic states on the n-side (in this case, the upper n-GaN layer 212 described below) are more or less aligned with the valence band hole states on the p-side (in this case, the lower p-GaN layer 210). In some examples, the tunnel junction 216 can be formed from germanium, gallium arsenide, and / or silicon materials.

[0035] According to some examples, operation 102 includes forming an upper n-GaN layer 212 over the tunnel junction 216 at sub-operation 312. In some examples, operations 310 and 312 can be combined into a single operation, wherein n-GaN is grown over the lower p-GaN layer 210 to form the tunnel junction 216.

[0036] According to some examples, operation 102 includes forming a dielectric layer 214 above the upper n-GaN layer 212 at sub-operation 314. The dielectric layer 214 can be formed of a suitable dielectric material such as an oxide like SiO2.

[0037] According to some examples, method 100 includes forming an opening 402 through dielectric layer 214 at operation 104 (e.g. Figure 4 (As depicted). In some examples, the aperture 402 is formed by selective etching using photolithography.

[0038] Figure 4 A cross-sectional view of the semiconductor wafer template 200 after operation 104 is shown. The opening 402 can be formed by etching (e.g., wet etching) through the dielectric layer 214 to the upper n-GaN layer 212. In some examples, such as the one shown, two openings 402 can be formed at operation 104 to form two mesa, as described below. However, it will be understood that the techniques described herein can be adapted, with appropriate modifications, to LED pixel structures comprising one mesa or two or more mesa.

[0039] According to some examples, method 100 includes growing a mesa n-GaN layer 504 in each aperture 402 at operation 106. In some examples, the mesa n-GaN layer 504 can be formed by selective MOCVD overgrowth.

[0040] Figure 5 A cross-sectional view of the semiconductor wafer template 200 after operation 106 is shown. In the example shown, two mesa n-GaN layers 504 are grown on... Figure 4In the two openings 402 shown, each mesa n-GaN layer 504 forms the base of the mesa 502 within the opening 402, and each mesa n-GaN layer 504 functionally serves as an extension of the upper n-GaN layer 212. The sidewalls of the mesa 502 can be formed as a semi-polar surface of the GaN material used to form the mesa n-GaN layer 504, as shown below. Figure 6 As described.

[0041] Figure 6 Four different orientations of the surface formed by the hexagonal crystal structure 602 of GaN material are shown. The hexagonal crystal structure 602 shown represents GaN and its various related ternary compounds such as indium gallium nitride (InGaN) and aluminum gallium nitride (AlGaN), all of which can be referred to herein as GaN materials.

[0042] The hexagonal crystal structure 602 of the GaN material defines several surface orientations that can be formed through the material. A polar (c-plane) surface 604 (also called the (0001) surface) defines a horizontal plane orientation perpendicular to the c-vector 612. A semi-polar surface 606 (also called the (10-11) surface) defines an oblique plane orientation in which the plane intersects the top centerline of the hexagonal crystal structure 602 and one of the two bottom edges of the hexagonal crystal structure 602 parallel to the top centerline. A non-polar (m-plane) surface 608 (also called the (10-10) surface) defines a vertical plane orientation coplanar with one of the six sides of the hexagonal crystal structure 602. A non-polar (a-plane) surface 610 (also called the (11-20) surface) defines another vertical plane orientation extending from two non-adjacent top vertices of the hexagonal crystal structure 602 and parallel to the c-vector 612 that contacts the two corresponding bottom vertices. The radial direction of the hexagonal crystal structure 602 is specified by vectors a1 614, a2 616, and a3 618.

[0043] therefore, Figures 5 to 12 The sidewalls of the mesa 502 shown can be formed to extend obliquely from the top of the mesa at an angle defined by the semi-polar surface 606 of the hexagonal crystal structure 602 of the mesa n-GaN layer 504. Specifically, the semi-polar surface 606 forms a 62° angle with the horizontal plane (e.g., the upper surface of the upper n-GaN layer 212). Therefore, in some examples, the sidewalls of the mesa 502 can be inclined at a 62° angle.

[0044] According to some examples, method 100 includes growing a mesa MQW layer 702 on top of each mesa n-GaN layer 504 at operation 108 (in Figure 7 (As depicted in the image). In some examples, the mesa MQW layer 702 can be formed via selective MOCVD overgrowth.

[0045] Figure 7 A cross-sectional view of the semiconductor wafer template 200 after operation 108 is shown. Mesa MQW layers 702 form the middle portion of each mesa 502. The sidewalls of each mesa 502 may continue to be aligned with the semi-polar surface 606 of the material of the mesa MQW layer 702, for example, at a 62° angle to the surface of the upper n-GaN layer 212.

[0046] In some examples, each of the two or more mesa MQW layers 702 is configured to emit the same color, forming either a red LED or a tunable red / green LED. In other examples, the two or more mesa MQW layers 702 are configured differently: for example, one mesa MQW layer 702 may be configured to form a red LED, while another mesa MQW layer 702 may be configured to form a green LED.

[0047] According to some examples, method 100 includes growing a mesa p-GaN layer 802 on top of each mesa MQW layer 702 at operation 110. In some examples, the mesa p-GaN layer 802 can be formed by selective MOCVD overgrowth.

[0048] Figure 8 A cross-sectional view of the semiconductor wafer template 200 after operation 110 is shown. Mesa p-GaN layers 802 form the middle portion of each mesa 502. The sidewalls of each mesa 502 may continue to be aligned with the semi-polar surface 606 of the GaN material of the mesa p-GaN layer 802, for example, at a 62° angle to the surface of the upper n-GaN layer 212.

[0049] According to some examples, method 100 includes forming electrical contacts above each mesa p-GaN layer 802 at operation 112. The electrical contacts are p-type electrical contacts.

[0050] Figure 9 A cross-sectional view of the semiconductor wafer template 200 after operation 112 is shown. The p-type electrical contact is shown as p-contact 902. In some examples, p-contact 902 may be formed from a suitable conductive material for forming electrical contacts on p-GaN material, such as gold, gold alloys, or transparent conductive oxides such as indium tin oxide (ITO).

[0051] According to some examples, method 100 includes removing a portion of dielectric layer 214 at operation 114 to expose a portion of the upper n-GaN layer 212. In some examples, this portion of dielectric layer 214 can be removed by selective etching using photolithography (e.g., wet etching).

[0052] Figure 10A cross-sectional view of the semiconductor wafer template 200 after operation 114 is shown. The dielectric layer 214 between the two mesa 502 has been removed to provide a first exposed portion 1002 of the upper n-GaN layer 212. The dielectric layer 214 to the right of the second mesa 502 has been removed to provide a second exposed portion 1004 of the upper n-GaN layer 212.

[0053] In some examples, in the first iteration of operation 114, only the first exposed portion 1002 is removed. This is followed by the deposition of the electrical contact 1204 at operation 118 (see below). Figure 12 (Description) During the second iteration of operation 114, the electrical contact 1204 is masked (e.g., photolithographic masking) to selectively remove the second exposed portion 1004.

[0054] According to some examples, method 100 includes etching at operation 116 through a portion of dielectric layer 214, a portion of upper n-GaN layer 212, and a portion of lower MQW layer 208 to expose a portion of lower n-GaN layer 206. As in operations 104 and 114, wet etching may be used to prevent damage to the exposed layers. In some examples, dry etching may be used instead of wet etching, or in addition to wet etching, to maintain straight edges of the etched openings and the dimensions of the openings in the layers beneath them.

[0055] Figure 11 A cross-sectional view of the semiconductor wafer template 200 after operation 116 is shown. Wet etching can be used to etch through the portion located on the right side of the figure, passing through the dielectric layer 214, the upper n-GaN layer 212, and the lower MQW layer 208, exposing the exposed portion 1102 of the lower n-GaN layer 206.

[0056] As described above, in some examples, operation 116 is performed only at electrical contact 1204 (see below). Figure 12 (Description) This is performed after the first exposed portion 1002 of the upper n-GaN layer 212 has been deposited and masked to protect the electrical contact 1204 from damage from the etching step of operation 116.

[0057] According to some examples, method 100 includes forming an electrical contact 1204 on the exposed upper n-GaN layer 212 (e.g., on a first exposed portion 1002 of the upper n-GaN layer 212) at operation 118.

[0058] According to some examples, method 100 includes forming an n-contact 1202 on an exposed portion (e.g., exposed portion 1102) of the lower n-GaN layer 206 at operation 120. The n-contact 1202 is an n-type electrical contact.

[0059] Figure 12 The following are shown after operations 118 and 120. Figure 2 A cross-sectional view of the semiconductor wafer template. n-contact 1202 has been deposited on the exposed portion 1102 of the lower n-GaN layer 206. Electrical contact 1204 has been deposited on the first exposed portion 1002 of the upper n-GaN layer 212.

[0060] In the final pixel structure 1200, the mesa p-GaN layer 802 and mesa MQW layer 702 of each mesa LED form a corresponding mesa LED 1206 with the upper n-GaN layer 212. The mesa LED 1206 is excited by an electrical contact 1204 (used as an n-type electrical contact) and a p-contact 902 on the mesa. The lower n-GaN layer 206 and lower MQW layer 208 form a lower LED 1208 with the lower p-GaN layer 210. The lower LED 1208 is excited by an electrical contact 1204 (used as a p-type electrical contact) and an n-contact 1202 formed on the lower n-GaN layer 206. Therefore, in some examples, the electrical contact 1204 is configured to serve as an n-type electrical contact for each mesa LED 1206 and a p-type electrical contact for the lower LED 1208.

[0061] In some examples, both the n-contact 1202 and the electrical contact 1204 can be formed from a suitable conductive material, such as aluminum or an aluminum-containing compound or alloy, for forming electrical contacts on the n-GaN material.

[0062] Figure 13 It shows including Figure 12 A top view of an LED pixel array of 1200 tiles. Figure 12 The cross-sectional view can be considered as passing through Figure 13 The view of section line AA shown.

[0063] In the example LED pixel array layout shown, each mesa 502 has six sidewalls defining a generally hexagonal shape for each mesa 502. Each mesa p-GaN layer 802, mesa MQW layer 702, and mesa n-GaN layer 504 is hexagonal. The mesa 502 are arranged to form a honeycomb or hexagonal grid layout. Therefore, a pair of mesa 502 can be considered as forming a single pixel structure 1200, as shown by the dashed outline.

[0064] What will be understood is... Figure 13 The layout shown may constitute only a small part of the entire LED pixel array, which in some examples may include hundreds, thousands or millions of pixel structures 1200.

[0065] In some examples, different top-view shapes can be used for mesa 502, and / or mesa 502 can be laid out in different patterns. However, the hexagonal crystal structure 602 of the mesa p-GaN layer 802, the mesa MQW layer 702, and the mesa n-GaN layer 504 can facilitate the formation of mesa 502 with a hexagonal shape, such as... Figure 13 As shown in the figure.

[0066] In some examples, the various structures shown and described herein have dimensions configured to form microLED pixels. In a first example, the lower n-GaN layer 206 has a thickness approximately between several hundred nanometers (nm) and several (e.g., less than ten) micrometers (µm). The lower MQW layer 208 has a thickness approximately between 10 nm and several hundred nm. The lower p-GaN layer 210 has a thickness approximately between 50 nm and several hundred nm. The mesa height depends on the total thickness of the MOCVD overgrowth, and therefore ranges approximately from 100 nm to several (e.g., < 10) micrometers. The mesa width and pixel pitch can be selected based on the desired pixels per inch (PPI) specification of the pixel array; in various examples, the mesa width can range from tens of nm to hundreds of micrometers.

[0067] in conclusion

[0068] This article describes LED pixel arrays and their manufacturing methods with reference to various examples.

[0069] Example 1 is a method for fabricating a light-emitting diode (LED) pixel array from a semiconductor wafer template, the semiconductor wafer template comprising a continuously stacked lower n-type gallium nitride (n-GaN) layer, a lower multiple quantum well (MQW) layer, a lower p-type gallium nitride (p-GaN) layer, an upper n-GaN layer, and a dielectric layer, the method comprising: forming a plurality of openings through the dielectric layer and extending to the upper n-GaN layer; and forming a plurality of mesas by forming the following layers in each opening: a mesas n-GaN layer; a mesas MQW layer above each mesas n-GaN layer; and a mesas p-GaN layer above each mesas MQW layer, such that: the mesas n-GaN layer, the mesas MQW layer, and the mesas p-GaN layer of each mesas form a corresponding mesas LED; and the lower n-GaN layer, the lower MQW layer, and the lower p-GaN layer form a lower LED.

[0070] In Example 2, the subject matter of Example 1 includes: removing a portion of the dielectric layer to expose a portion of the upper n-GaN layer; and forming electrical contacts on the exposed portion of the upper n-GaN layer, wherein the electrical contacts are configured to serve as: an n-type electrical contact for a mesa LED; and a p-type electrical contact for a lower LED.

[0071] In Example 3, the subject of Example 2 includes, wherein: the electrical contact portion contains aluminum.

[0072] In Example 4, the subject matter of Examples 1 to 3 includes: etching through a dielectric layer, an upper n-GaN layer, and a lower MQW layer to expose a portion of the lower n-GaN layer; and forming an n-type electrical contact on the exposed portion of the lower n-GaN layer.

[0073] In Example 5, the subject of Example 4 includes, wherein: the n-type electrical contact comprises aluminum.

[0074] In Example 6, the subject matter of Examples 1 to 5 includes: forming p-type electrical contacts on the mesa p-GaN layer of each mesa.

[0075] In Example 7, the subject of Example 6 includes, wherein: the p-type electrical contact comprises a transparent conductive oxide.

[0076] In Example 8, the subject matter of Examples 1 to 7 includes: forming a p-type electrical contact on the mesa p-GaN layer of each mesa; masking the p-type electrical contact; removing a portion of the dielectric layer to expose a portion of the upper n-GaN layer; forming an electrical contact on the exposed portion of the upper n-GaN layer; etching through the dielectric layer, the upper n-GaN layer, and the lower MQW layer to expose a portion of the lower n-GaN layer; and forming an n-type electrical contact on the exposed portion of the lower n-GaN layer, wherein the electrical contact is configured to serve as: an n-type electrical contact for the mesa LED; and a p-type electrical contact for the lower LED.

[0077] In Example 9, the subject matter of Examples 1 to 8 includes, wherein: each mesa has sidewalls formed at an angle defined by the semi-polar surface of the crystal structure of the mesa n-GaN layer, the mesa MQW layer and the mesa p-GaN layer.

[0078] In Example 10, the subject of Examples 1 through 9 includes, where: the lower LED is a blue LED.

[0079] In Example 11, the subject of Example 10 includes the following: each tabletop LED is a tunable red LED / green LED.

[0080] In Example 12, the subject matter of Examples 10 to 11 includes: the tabletop LED includes at least one red LED and at least one green LED.

[0081] In Example 13, the subject matter of Examples 1 to 12 includes: the lower LED is a tunable blue LED / green LED; and each tabletop LED is a red LED.

[0082] In Example 14, the subject matter of Examples 1 to 13 includes, wherein: the semiconductor wafer template further includes a continuously stacked substrate layer and an undoped gallium nitride (u-GaN) layer below the lower n-GaN layer.

[0083] In Example 15, the subject of Example 14 includes forming a semiconductor wafer template by means of the following steps: epitaxially forming a u-GaN layer on a substrate layer; epitaxially forming a lower n-GaN layer on the u-GaN layer; epitaxially forming a lower MQW layer above the lower n-GaN layer; epitaxially forming a lower p-GaN layer above the lower MQW layer; cleaning the upper surface of the lower p-GaN layer to remove p-type dopants; forming a tunnel junction above the lower p-GaN layer; epitaxially forming an upper n-GaN layer above the tunnel junction; and epitaxially forming a dielectric layer above the upper n-GaN layer.

[0084] In Example 16, the subject matter of Examples 1 to 15 includes, wherein: each tabletop has six sidewalls defining the approximate hexagonal shape of each tabletop.

[0085] Example 17 is a pixel array formed according to the method of Example 1.

[0086] Example 18 is a light-emitting diode (LED) pixel array comprising multiple LED pixel structures, each LED pixel structure comprising: a lower LED comprising a lower n-GaN layer, a lower MQW layer and a lower p-GaN layer stacked sequentially; and multiple mesas formed above the lower p-GaN layer, each mesas defining a corresponding mesas LED comprising a mesas n-GaN layer, a mesas MQW layer and a mesas p-GaN layer.

[0087] In Example 19, the subject of Example 18 includes the following: the lower LED is a tunable blue LED / green LED; and each tabletop LED is a red LED.

[0088] In Example 20, the subject matter of Examples 18 and 19 includes: the lower LED is a blue LED; and each tabletop LED is a tunable red / green LED.

[0089] Example 21 is at least one machine-readable medium including instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any one of Examples 1 to 20.

[0090] Example 22 is an apparatus that includes means for implementing any one of Examples 1 to 20.

[0091] Example 23 is a system for implementing any one of Examples 1 through 20.

[0092] Example 24 is a method for implementing any one of Examples 1 through 20.

[0093] Other technical features and / or benefits will be readily apparent to those skilled in the art from the accompanying drawings, descriptions and claims herein.

Claims

1. A method for fabricating a light-emitting diode (LED) pixel array from a semiconductor wafer template, the semiconductor wafer template comprising a continuously stacked lower n-type gallium nitride (n-GaN) layer, a lower multiple quantum well (MQW) layer, a lower p-type gallium nitride (p-GaN) layer, an upper n-GaN layer, and a dielectric layer, the method comprising: Multiple openings are formed that penetrate the dielectric layer and extend to the upper n-GaN layer; as well as Multiple platform surfaces are formed by creating the following layers within each opening: Mesa n-GaN layer; Mesa MQW layer above each mesa n-GaN layer; as well as Above each mesa MQW layer is a mesa p-GaN layer. Make: The mesa n-GaN layer, the mesa MQW layer and the mesa p-GaN layer of each mesa form a corresponding mesa LED; as well as The lower n-GaN layer, the lower MQW layer, and the lower p-GaN layer form the lower LED.

2. The method according to claim 1, further comprising: Remove a portion of the dielectric layer to expose a portion of the upper n-GaN layer; as well as An electrical contact is formed on the exposed portion of the upper n-GaN layer. The electrical contact portion is configured to serve as: n-type electrical contacts for the LED on the tabletop; as well as p-type electrical contact for the lower LED.

3. The method according to claim 2, wherein: The electrical contact portion contains aluminum.

4. The method according to claim 1, further comprising: Etching through the dielectric layer, the upper n-GaN layer, and the lower MQW layer to expose a portion of the lower n-GaN layer; as well as An n-type electrical contact is formed on the exposed portion of the lower n-GaN layer.

5. The method according to claim 4, wherein: The n-type electrical contact comprises aluminum.

6. The method according to claim 1, further comprising: A p-type electrical contact is formed on the p-GaN layer of each mesa.

7. The method according to claim 6, wherein: The p-type electrical contact comprises a transparent conductive oxide.

8. The method according to claim 1, further comprising: A p-type electrical contact is formed on the p-GaN layer of each mesa; The p-type electrical contact portion is shielded; Remove a portion of the dielectric layer to expose a portion of the upper n-GaN layer; An electrical contact is formed on the exposed portion of the upper n-GaN layer; Etching through the dielectric layer, the upper n-GaN layer, and the lower MQW layer to expose a portion of the lower n-GaN layer; as well as An n-type electrical contact is formed on the exposed portion of the lower n-GaN layer. The electrical contact portion is configured to serve as: n-type electrical contacts for the LED on the tabletop; as well as p-type electrical contact for the lower LED.

9. The method according to claim 1, wherein: Each mesa has sidewalls formed at an angle defined by the semi-polar surfaces of the crystal structures of the mesa n-GaN layer, the mesa MQW layer, and the mesa p-GaN layer.

10. The method according to claim 1, wherein: The lower LED is a blue LED.

11. The method of claim 10, wherein: Each tabletop LED is a tunable red / green LED.

12. The method according to claim 10, wherein: The tabletop LED includes at least one red LED and at least one green LED.

13. The method according to claim 1, wherein: The lower LED is a tunable blue / green LED; and Each LED on the tabletop is a red LED.

14. The method according to claim 1, wherein: The semiconductor wafer template also includes a continuously stacked substrate layer and an undoped gallium nitride (u-GaN) layer below the lower n-GaN layer.

15. The method of claim 14, further comprising forming the semiconductor wafer template by the following step: The u-GaN layer is epitaxially formed on the substrate layer; The lower n-GaN layer is epitaxially formed on the u-GaN layer; The lower MQW layer is epitaxially formed above the lower n-GaN layer; The lower p-GaN layer is epitaxially formed above the lower MQW layer; Clean the upper surface of the lower p-GaN layer to remove p-type dopant; A tunnel junction is formed above the lower p-GaN layer; The upper n-GaN layer is epitaxially formed above the tunnel junction; and The dielectric layer is epitaxially formed above the upper n-GaN layer.

16. The method according to claim 1, wherein: Each countertop has six sidewalls, defining the approximate hexagonal shape of each countertop.

17. A pixel array formed by the method according to claim 1.

18. A light-emitting diode (LED) pixel array, comprising a plurality of LED pixel structures, each LED pixel structure comprising: The lower LED comprises a continuously stacked lower n-GaN layer, a lower MQW layer, and a lower p-GaN layer; as well as Multiple mesa are formed above the lower p-GaN layer, each mesa defining a corresponding mesa LED, the mesa LED including a mesa n-GaN layer, a mesa MQW layer and a mesa p-GaN layer.

19. The pixel array according to claim 18, wherein: The lower LED is a tunable blue / green LED; and Each LED on the tabletop is a red LED.

20. The pixel array according to claim 18, wherein: The lower LED is a blue LED; as well as Each tabletop LED is a tunable red / green LED.

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