Multi-channel bioelectric signal transmission methods, equipment and storage media

Abstract

This application discloses a multi-channel bioelectric signal transmission method, device, and storage medium. The device includes: an analog front-end module comprising multiple analog front-end units, each analog front-end unit including multiple acquisition channels for acquiring bioelectric signals and performing analog-to-digital conversion, transmitting the converted data stream to a data transmission module; and a data transmission module connected to the analog front-end module via a four-data-line serial peripheral interface for receiving the data stream and transmitting the received data stream to a remote host via a wireless ultra-wideband module; wherein the data transmission module has multiple switchable operating modes. This application provides a bioelectric signal transmission device that integrates multiple operating modes suitable for various scenarios, reduces system power consumption, and realizes multi-channel acquisition and wireless transmission of bioelectric signals.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and more specifically, to a method, device, and storage medium for multi-channel bioelectric signal transmission. Background Technology

[0002] Bioelectrical signals, as important physiological parameters reflecting the state of life activities, carry rich physiological and pathological information and are widely used in various fields such as clinical diagnosis, health monitoring, human-computer interaction, and neuroscience and engineering research. Common bioelectrical signals include electrocardiograms (ECG), electroencephalograms (EEG), and electromyograms (EMG). As a key interface connecting the human physiological state with digital medical systems, the performance of bioelectrical signal acquisition systems directly affects the accuracy and reliability of subsequent signal processing, feature extraction, and disease identification. Therefore, developing high-precision, low-power, portable, and intelligent bioelectrical signal acquisition systems has become an important research direction in the field of biomedical engineering.

[0003] Traditional bioelectrical signal acquisition uses rigid electrodes and wired methods, which restricts the subject's freedom of movement. To address this issue, wireless bioelectrical signal acquisition and transmission devices have been proposed. Wireless data acquisition does not affect the subject's freedom of movement and can effectively eliminate motion artifacts caused by cable swaying. However, existing wireless bioelectrical signal acquisition and transmission devices not only have limited data transmission capacity but also consume a lot of power. Summary of the Invention

[0004] This application provides a method, apparatus, device, and storage medium for transmitting multi-channel bioelectric signals, in order to at least solve the technical problems of difficulty in multi-channel acquisition of bioelectric signals and high power consumption in related technologies.

[0005] According to one aspect of the embodiments of this application, a multi-channel bioelectric signal transmission device is provided, comprising: The analog front-end module includes multiple analog front-end units, each of which includes multiple acquisition channels for acquiring bioelectric signals and performing analog-to-digital conversion, and then transmitting the converted data stream to the data transmission module. The data transmission module is connected to the analog front-end module via a four-data-line serial peripheral interface, and is used to receive data streams and transmit the received data streams to the remote host via the wireless ultra-wideband module. The data transmission module has multiple switchable operating modes.

[0006] In one implementation, acquiring bioelectrical signals and performing analog-to-digital conversion includes: Each acquisition channel of the analog front-end unit uses a voltage-controlled oscillator to convert the bioelectric signal into an oscillating clock signal with a continuously varying frequency; The counter is driven by the oscillating clock signal to perform analog-to-digital signal conversion, and the converted data stream is obtained.

[0007] In one embodiment, the analog front-end module includes eight analog front-end units, each of which includes 128 channels.

[0008] In one implementation, transmitting the converted data stream to a data transmission module includes: Each analog front-end unit synchronously acquires bioelectric signals from 128 channels, performs analog-to-digital conversion on the signals from each channel, and generates 16-bit digital sample values. The 16-bit digital sample values ​​from 128 channels are combined in channel order to form a valid data block of 64 words; Add a 1-word header to the beginning of the valid data block to form a 65-word data transmission packet; At the beginning of each sampling period, the data transmission packet is transmitted from the analog front-end unit to the data transmission module via a four-data-line serial peripheral interface.

[0009] In one embodiment, the data transmission module includes an interrupt unit, an access control unit, and a preset buffer; When the amount of data in the receive first-in-first-out queue of the four-data-line serial peripheral interface reaches a threshold, the interrupt unit activates the first access control unit to write the data stream from the receive first-in-first-out queue into the buffer, and activates the second access control unit to write the data stream from the buffer into the output interface. The buffer includes multiple sub-regions, and provides a target address for the first access control unit and a source address for the second access control unit based on the interrupt unit.

[0010] In one implementation, providing a target address to the first access control unit and a source address to the second access control unit based on the interrupt unit includes: Assign address parameters to the buffer, including the starting address, address depth, and accumulation threshold; Based on the sum of the starting address and n times the address depth, calculate the target address of the nth data transmission of the simulated front-end unit, where n is greater than or equal to 0 and less than or equal to the cumulative threshold. When the number of transmissions reaches the accumulation threshold, the address pointer is reset to the starting address, and the accumulation process restarts. When reading data from the buffer, the calculated target address is used as the source address.

[0011] In one embodiment, the data transmission module includes a power-off mode, a deep sleep mode, and an activation mode; The operating mode is switched based on a preset hardware button.

[0012] In one implementation, in the activation mode, the data transmission module operates at a preset first system clock or a preset second system clock, wherein the frequency of the first system clock is greater than the frequency of the second system clock. In the deep sleep mode, the data transmission module operates at a preset third system clock; the second system clock frequency is greater than the third system clock frequency. In the shutdown mode, the system clock remains off.

[0013] According to another aspect of the embodiments of this application, a multi-channel bioelectric signal transmission method is provided, comprising: The analog front-end module collects bioelectric signals and performs analog-to-digital conversion, then transmits the converted data stream to the data transmission module. The simulation front-end module includes multiple simulation front-end units, and each simulation front-end unit includes multiple acquisition channels; Based on the data transmission module being connected to the analog front-end module via a four-data-line serial peripheral interface, the data stream is received and transmitted to the remote host via the wireless ultra-wideband module. The data transmission module has multiple switchable operating modes.

[0014] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, and the computer program is configured to execute the above-described multi-channel bioelectric signal transmission method when it is run.

[0015] The technical solutions provided in this application embodiment may include the following beneficial effects: This application provides a multi-channel bioelectric signal transmission device, including an analog front-end module and a data transmission module. The analog front-end module includes multiple analog front-end units, and each analog front-end unit includes multiple acquisition channels, which can realize high-throughput data acquisition.

[0016] The data transmission module is connected to the analog front-end module via QSPI (Quad Serial Peripheral Interface) to receive data streams and transmit them to a remote host via a wireless ultra-wideband module. This enables automatic transmission of high-speed data streams. The solution in this embodiment supports wireless transmission, improving user convenience, and integrates multiple working modes suitable for various scenarios, significantly reducing system power consumption. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a structural diagram of a multi-channel bioelectric signal transmission device according to an embodiment of this application; Figure 2 This is a schematic diagram of a simulated front-end module data transmission and integration method according to an embodiment of this application; Figure 3 This is a schematic diagram of the working mode of a data transmission module according to an embodiment of this application; Figure 4 This is a schematic diagram of a data format stored in a buffer according to an embodiment of this application; Figure 5 This is a schematic diagram of the control logic of an interrupt unit according to an embodiment of this application; Figure 6 This is a schematic diagram of a multi-channel bioelectric signal transmission method according to an embodiment of this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0019] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0020] Existing solutions can only provide data transmission at the level of hundreds of channels and have relatively high power consumption, which limits the application scenarios of the device and makes it difficult to apply to application scenarios with higher spatial resolution and more precise motion unit resolution.

[0021] Based on this, this application proposes a wireless bioelectric signal transmission device supporting 1024 channels. It includes eight analog front-end circuits, each AFE (Analog Front-End Unit) containing 128 channels, collectively forming a total of 1024 acquisition channels. The maximum sampling rate of the acquisition channels is 32 kHz, and the sampled data is output in 16-bit quantization.

[0022] In addition, this application embodiment also includes a data transmission module, which uses a RISC-V (Reduced Instruction Set Computing) core-based SoC (System-on-a-Chip) as the data transmission module. It connects to eight analog front-ends via a QSPI interface, responsible for the automatic transmission of high-speed data streams. The transmission module supports a maximum data rate of 524.288 Mbps. This transmission module integrates three operating modes suitable for various scenarios and can switch the system clock as needed. Its power consumption in low-power mode is 15.58 uW. The output of the transmission module is connected to an ultra-wideband module for wireless transmission. This transmission device has been verified through a 40nm CMOS (Complementary Metal-Oxide-Semiconductor) tape-out process, with a chip area of ​​2.97mm x 1.98mm.

[0023] The multi-channel bioelectric signal transmission device according to embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0024] This application proposes a wireless bioelectric signal transmission device supporting 1024 channels. The analog front-end and transmission module are connected at the board level. The transmission module is responsible for the system's logic control and high-speed data transmission. Wireless transmission is achieved using a radio frequency method based on ultra-wideband technology, providing a maximum data rate of up to 1.8 Gbps.

[0025] The analog front-end module includes multiple analog front-end units, each of which includes multiple acquisition channels for acquiring bioelectrical signals and performing analog-to-digital conversion, then transmitting the converted data stream to the data transmission module.

[0026] In one embodiment, the analog front-end module includes eight analog front-end units, each with 128 channels. It is understood that those skilled in the art can set the number of analog front-end units and channels according to their needs, and this application does not impose specific limitations. For example, the analog front-end module may have six analog front-end units, each with 64 channels, etc.

[0027] The analog front-end module is used to acquire bioelectrical signals and perform analog-to-digital conversion. The input end is connected to bioelectrical signal acquisition devices such as electrocardiogram, electroencephalogram, and electromyogram. Each acquisition channel of the analog front-end unit uses a voltage-controlled oscillator to convert the bioelectrical signal into an oscillating clock signal with a continuously changing frequency. Based on the oscillating clock signal, the counter is driven to perform analog-to-digital signal conversion to obtain the converted data stream.

[0028] Specifically, each channel uses a VCO (Voltage-Controlled Oscillator) to convert the potential signal into a continuously varying frequency oscillation clock signal. This clock signal drives a counter circuit, which calculates the potential value based on the frequency, thus achieving analog-to-digital signal conversion. The channel supports a maximum sampling rate of 32 kHz and 16-bit quantization. The 16-bit resolution supports 65,536 discrete quantization levels, making it ideal for high-precision signal acquisition.

[0029] Furthermore, the converted data stream is transmitted to the data transmission module, including the synchronous acquisition of 128 channels of bioelectric signals by each analog front-end unit, the analog-to-digital conversion of the bioelectric signals of each channel to generate 16-bit digital sample values; the 16-bit digital sample values ​​of the 128 channels are combined in channel order to form a 64-word effective data block; a 1-word header is added at the beginning of the effective data block to form a 65-word data transmission packet; at the beginning of each sampling period, the data transmission packet is transmitted from the analog front-end unit to the data transmission module through the QSPI interface.

[0030] In the embodiments of this application, 16-bit data from 128 channels constitutes a 64-word data block for each transmission. To distinguish each data transmission, a one-word header is added at the beginning of each data block to indicate the transmission sequence. Within each sampling period, the acquired data is transmitted from the analog front-end module to the data transmission module via a four-data-line serial peripheral interface. The data structure dictates that each transmission requires the transmission of 65 words of data to the RX FIFO (Receive First-In-First-Out Queue) of the four-data-line serial peripheral interface module.

[0031] like Figure 2 As shown, this diagram illustrates the data transmission and integration method in a 128-channel analog front-end module, including the complete transmission process from analog bioelectrical signal acquisition and multi-channel data packaging to single-channel data reconstruction. The "32kHz sampling rate, 16-bit quantization accuracy" label on the left, along with a sine wave sampling diagram, clearly defines the key parameters for signal acquisition. The dashed box in the middle shows the data organization; the transmitted data packets are arranged in channel order, containing multiple channel data groups from channel 1 to channel 128. The right side shows the final extraction of "channel 1 data," and the processing result is visually presented using a voltage-sampling index relationship diagram, demonstrating the entire process of signal transmission and reconstruction from analog form to digital form in a multi-channel acquisition system.

[0032] The analog front-end provided in this application supports 1024-channel acquisition. Combined with 16-bit resolution and a 32kHz sampling rate, it can accurately capture signal details while avoiding the influence of quantization noise on weak signals. This configuration, while ensuring signal fidelity, meets the real-time requirements of multi-channel high-precision bioelectrical signal acquisition, and is particularly suitable for the accurate acquisition and processing of weak bioelectrical signals such as electrocardiograms and electroencephalograms.

[0033] The device in this application also includes a data transmission module, which is connected to the analog front-end module via a four-data-line serial peripheral interface, for receiving data streams and transmitting the received data streams to a remote host via a wireless ultra-wideband module; wherein, the data transmission module has multiple switchable working modes.

[0034] In one implementation, this solution uses a RISC-V core-based SoC as the data transmission module. Through custom design, it realizes the transmission of data streams from multiple analog front-ends. The automatic data transmission process of the transmission module runs independently without the intervention of the CPU (central processing unit).

[0035] The transmission module is used to integrate and transmit data from up to 8 analog front-end units. It is based on a 32-bit RISC-V architecture and integrates comprehensive peripheral resources as well as an ultra-wideband wireless transmission mode, which fully meets the wireless transmission requirements of the acquisition module.

[0036] In one implementation, the data transmission module includes an interrupt unit, an access control unit, and a preset buffer. When the amount of data in the receive-first-out queue of the four-data-line serial peripheral interface of the analog front end reaches a threshold, the interrupt unit activates the first access control unit to write the data stream from the receive-first-out queue into the buffer, and activates the second access control unit to write the data stream from the buffer into the output interface. The buffer includes multiple sub-regions, with the interrupt unit providing a target address for the first access control unit and a source address for the second access control unit.

[0037] To achieve flow control for high-throughput data streams and balance the difference between the four-data-line serial peripheral interface rate and the bus write rate, a data relay method using an SRAM (Static Random Access Memory) buffer was designed, which flexibly divides a 64kB SRAM buffer into eight sub-regions.

[0038] In the RX FIFO of the four-data-line serial peripheral interface of the analog front end, the interface will be triggered when 65 words are reached, and the data will be moved from the analog front end to the transmission module. After receiving the data packet, the transmission module will buffer it.

[0039] Therefore, when the data volume in the RX FIFO of the four-data-line serial peripheral interface of the analog front-end reaches 65 words (the total capacity of the RX FIFO is 128 words), the first access control unit is triggered to buffer the data into SRAM. The transmission module integrates an interrupt unit to provide the target address to the first access control unit and the source address to the second access control unit, allocating SRAM space for data from the eight analog front-ends. In this configuration, the first access control unit is used to transfer data from the RX FIFO of the analog front-end to SRAM, while the second access control unit is used to transfer data from SRAM to the output interface.

[0040] In one implementation, the interrupt unit provides a target address for the first access control unit and a source address for the second access control unit.

[0041] Specifically, address parameters are allocated to the buffer, including the starting address, address depth, and accumulation threshold. Based on the sum of the starting address and n times the address depth, the target address for the nth data transmission of the simulated front-end unit is calculated, where n is greater than or equal to 0 and less than or equal to the accumulation threshold. When the number of transmissions reaches the accumulation threshold, the address pointer is reset to the starting address, and the accumulation process restarts.

[0042] First, the starting address is specified as the target address for the first data transmission operation. In other words, the target address for the first transmission is the starting address.

[0043] Secondly, specify the address depth; the sum of the starting address and the address depth will be used as the target address for the second transfer. To ensure sufficient storage capacity for each data transfer, the address depth parameter must be set to at least 65 words.

[0044] For the third and subsequent transmissions, the accumulation is performed in a similar manner. Finally, an accumulation threshold T is specified; when the accumulated count is reached, the system returns to the starting address to restart the accumulation process.

[0045] Taking the nth data transmission of the i-th simulated front-end unit as an example, the formula for calculating the target address is as follows: DstAddri = HAddri +n×Depthi, (0 ≤ ni ≤ Ti) Where DstAddri represents the target address of the i-th analog front-end unit, HAddri represents the starting address of the i-th analog front-end unit, Depthi represents the address depth of the i-th analog front-end unit, and the number of transmissions n is counted starting from 0. For the first transmission, n equals 0, for the second transmission, n equals 1, and so on.

[0046] Furthermore, when reading data from the buffer, the calculated target address is used as the source address. When reading data from SRAM, the formula for calculating the source address is similar to that for the target address: SrcAddri = HAddri + n×Depthi, (0 ≤ ni ≤ Ti) Where SrcAddri represents the source address of the i-th analog front-end unit.

[0047] The data format stored in SRAM is as follows: Figure 4 As shown, each AFE (e.g., AFE 1, AFE 7, AFE 8) is allocated to an independent SRAM partition, and the partition's starting address (e.g., 0xF0F0_A001, 0xF0F0_A002, etc.) is configured via registers. Within each partition, data is stored in transmission order. The first transmission contains a 1-word header (e.g., the 0x0000_0002 identifier sequence) and 16-bit data from 128 channels, forming a 65-word data packet. The partition depth is dynamically configurable, but must accommodate at least one complete data packet (65 words), with any extra space used for buffer management.

[0048] By configuring the starting address, depth, and accumulation threshold, independent storage spaces are partitioned in SRAM, supporting parallel caching and cyclic writing of multi-channel data streams. The interrupt unit maintains the address parameters and transmission count of each analog front-end, and calculates the target address and source address corresponding to the current transmission in real time, ensuring accurate synchronization of read and write addresses and efficient reuse of buffers in high-throughput data stream scenarios.

[0049] like Figure 5 As shown, eight QSPI interfaces receive data from the analog front-end and write it to independent partitions of SRAM via DMA1 (First Access Control Unit). Each partition is identified by a 3-bit address and associated with a counter A to record the number of writes. During reading, DMA2 (Second Access Control Unit) retrieves data from the corresponding SRAM partition based on the address identifier stored in the RX FIFO and tracks the read progress via counter B. Eight counters C compare the difference between counters A and B in real time to monitor for data overwrite risks, ultimately achieving efficient and reliable transmission of multiple data streams from input to output.

[0050] Specifically, a write operation to SRAM simultaneously writes a 3-bit identifier to an RXFIFO with a depth of 255. Each time a 3-bit identifier is written, the corresponding counter A increments by 1, indicating the address of the written data and recording the number of writes from that AFE. Similarly, when reading data from SRAM, the RX FIFO is read simultaneously. Eight counters B are used to record the number of reads, identifying the address of the read data and recording the number of read operations. Counter C calculates the difference between counters A and B. When the difference exceeds a preset upper limit, it indicates that the SRAM data corresponding to that AFE has been overwritten by new data before being read. At this time, an overwrite alarm interrupt is automatically sent to the CPU, thereby realizing real-time buffer status monitoring and data integrity protection during multi-channel data stream transmission.

[0051] In one implementation, the data transmission module includes a power-off mode, a deep sleep mode, and an activation mode, and the working mode is switched based on a preset hardware button.

[0052] Specifically, in active mode, the data transmission module operates on either a preset first system clock or a preset second system clock, where the first system clock frequency is higher than the second system clock frequency. For example, in active mode, there are two selectable system clocks: 24 MHz and 72 MHz. In active mode, the system operates normally and data transmission is enabled. The 24 MHz system clock can be used for sampling rates of 4 kHz and 8 kHz, while the 72 MHz system clock can be used for sampling rates of 16 kHz and 32 kHz.

[0053] In deep sleep mode, the data transmission module operates on a preset third system clock; the second system clock frequency is higher than the third system clock frequency. For example, in deep sleep mode, the system clock operates at 32 kHz, and only basic modules such as the programmable interval timer, watchdog timer, and general-purpose input / output are active.

[0054] In shutdown mode, the system clock remains off.

[0055] The system can switch directly between three operating modes via a hardware button and flexibly set the corresponding system clock through a configuration register. At the hardware level, the power-off mode, deep sleep mode, and active mode can be switched via a button. At the software level, the 24MHz or 72MHz clock can be dynamically selected in active mode through register configuration. This hardware and software collaborative control mechanism enables the system to quickly and accurately adjust the operating mode and clock according to real-time performance requirements and power consumption constraints.

[0056] like Figure 3As shown, dynamic power consumption control is achieved through "active mode," "sleep mode," and "shutdown mode." In active mode, the system can select a 24MHz (low data rate) or 72MHz (high data rate) clock to provide clock signals for the RISC-V, AHB / APB bus, and peripherals, while employing a watchdog timer and a programmable interval timer to ensure system stability. In sleep mode, the system switches to a 32kHz low-frequency clock, maintaining only basic peripherals and timer functions to reduce power consumption. In shutdown mode, only the watchdog timer and programmable interval timer are retained, while all other clocks are turned off, achieving the lowest power consumption state. This design significantly reduces system power consumption through a configurable clock strategy.

[0057] The multi-channel data acquisition and transmission device provided in this application integrates three operating states: power-off mode, deep sleep mode, and active mode. The active mode, combined with selectable 24MHz and 72MHz system clock frequencies, achieves adaptive coverage for diverse transmission scenarios. In active mode, the system dynamically switches between high and low frequency clocks to balance performance and power consumption. When there is no transmission task, it enters deep sleep or power-off state, minimizing power consumption. While meeting the requirements for high-channel-count and high-sampling-rate bioelectrical signal acquisition, it significantly reduces device power consumption.

[0058] To facilitate understanding of the device provided in the embodiments of this application, the following description is provided in conjunction with the accompanying drawings. Figure 1 Further description.

[0059] like Figure 1 As shown in the figure, this diagram illustrates the complete hardware architecture of a multi-channel bioelectrical signal acquisition and wireless transmission system based on the RISC-V architecture. The left side shows the AFE (Automatic External Wire), each containing 128 channels. Each AFE integrates a VCO-ADC (Voltage-Controlled Oscillator-Analog-Digital Converter) and connects to the transmission device on the right via a QSPI interface.

[0060] The right-side transmission device is based on a RISC-V processor and connects to eight QSPI controllers, IPUs (interrupt handling units), two-level DMA (DMA1 / DMA2), SRAM buffers, and ClkGen / RstGen (clock and reset management modules) via AHB (Advanced High Performance Bus). It also expands peripheral interfaces via APB (Peripheral Bus). The system integrates a UWB (Ultra-Wideband) physical layer and transceivers to achieve wireless data transmission, forming a low-power data transmission platform from multi-channel signal acquisition and on-chip buffer processing to wireless transmission.

[0061] This application proposes a bioelectric signal transmission device capable of supporting 1024 channels and a maximum sampling rate of 32 kHz, with a maximum data rate of 524.288 Mbps and a power consumption of 15.58 uW in low-power mode. Furthermore, the transmission device can flexibly adjust the number of sampling channels, sampling rate, and system clock according to different operating scenarios to achieve a balance between performance and power consumption. This transmission device has been verified through 40nm CMOS tape-out process.

[0062] According to another aspect of the embodiments of this application, a method for transmitting multi-channel bioelectric signals in order to implement the above-described multi-channel bioelectric signal transmission device is also provided. For example... Figure 6 As shown, the method includes: S1 acquires bioelectric signals based on the analog front-end module and performs analog-to-digital conversion, then transmits the converted data stream to the data transmission module. The analog front-end module includes multiple analog front-end units, and each analog front-end unit includes multiple acquisition channels.

[0063] S2 sets the working mode of the data transmission module, which has multiple switchable working modes.

[0064] The S3 data transmission module is connected to the analog front-end module via a four-data-line serial peripheral interface to receive data streams.

[0065] S4 transmits the received data stream to the remote host via the wireless ultra-wideband module.

[0066] It should be noted that the multi-channel bioelectric signal transmission device provided in the above embodiments is only illustrated by the division of the above functional modules when executing the multi-channel bioelectric signal transmission method. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the multi-channel bioelectric signal transmission device and the multi-channel bioelectric signal transmission method embodiments provided in the above embodiments belong to the same concept, and the implementation process is detailed in the device embodiments, which will not be repeated here.

[0067] According to another aspect of the present application, a computer-readable storage medium corresponding to the multi-channel bioelectric signal transmission method provided in the foregoing embodiments is also provided, wherein a computer program (i.e., a program product) is stored thereon, and when the computer program is run by a processor, it executes the multi-channel bioelectric signal transmission method provided in any of the foregoing embodiments.

[0068] It should be noted that examples of computer-readable storage media may also include, but are not limited to, PRAM (phase-change memory), SRAM (static random access memory), DRAM (dynamic random access memory), other types of RAM (random access memory), ROM (read-only memory), EEPROM (electrically erasable programmable read-only memory), flash memory, or other optical and magnetic storage media, which will not be elaborated here.

[0069] The computer-readable storage medium provided in the above embodiments of this application and the multi-channel bioelectric signal transmission method provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the applications stored therein.

[0070] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A multi-channel bioelectric signal transmission device, characterized in that, include: The analog front-end module includes multiple analog front-end units, each of which includes multiple acquisition channels for acquiring bioelectric signals and performing analog-to-digital conversion, and then transmitting the converted data stream to the data transmission module. The data transmission module is connected to the analog front-end module via a four-data-line serial peripheral interface, and is used to receive data streams and transmit the received data streams to the remote host via the wireless ultra-wideband module. The data transmission module has multiple switchable operating modes.

2. The device according to claim 1, characterized in that, Acquiring bioelectrical signals and performing analog-to-digital conversion, including: Each acquisition channel of the analog front-end unit uses a voltage-controlled oscillator to convert the bioelectric signal into an oscillating clock signal with a continuously varying frequency; The counter is driven by the oscillating clock signal to perform analog-to-digital signal conversion, and the converted data stream is obtained.

3. The device according to claim 1, characterized in that, The analog front-end module includes 8 analog front-end units, and each analog front-end unit includes 128 channels.

4. The device according to claim 3, characterized in that, The converted data stream is transmitted to the data transmission module, including: Each analog front-end unit synchronously acquires bioelectric signals from 128 channels, performs analog-to-digital conversion on the signals from each channel, and generates 16-bit digital sample values. The 16-bit digital sample values ​​from 128 channels are combined in channel order to form a valid data block of 64 words; Add a 1-word header to the beginning of the valid data block to form a 65-word data transmission packet; At the beginning of each sampling period, the data transmission packet is transmitted from the analog front-end unit to the data transmission module via a four-data-line serial peripheral interface.

5. The device according to claim 1, characterized in that, The data transmission module includes an interrupt unit, an access control unit, and a preset buffer. When the amount of data in the receive first-in-first-out queue of the four-data-line serial peripheral interface reaches a threshold, the interrupt unit activates the first access control unit to write the data stream from the receive first-in-first-out queue into the buffer, and activates the second access control unit to write the data stream from the buffer into the output interface. The buffer includes multiple sub-regions, and provides a target address for the first access control unit and a source address for the second access control unit based on the interrupt unit.

6. The device according to claim 5, characterized in that, Based on the interrupt unit, the first access control unit is provided with a target address, and the second access control unit is provided with a source address, including: Assign address parameters to the buffer, including the starting address, address depth, and accumulation threshold; Based on the sum of the starting address and n times the address depth, calculate the target address of the nth data transmission of the simulated front-end unit, where n is greater than or equal to 0 and less than or equal to the cumulative threshold. When the number of transmissions reaches the accumulation threshold, the address pointer is reset to the starting address, and the accumulation process restarts. When reading data from the buffer, the calculated target address is used as the source address.

7. The device according to claim 1, characterized in that, The data transmission module includes a power-off mode, a deep sleep mode, and an activation mode; The operating mode is switched based on a preset hardware button.

8. The device according to claim 7, characterized in that, In the activation mode, the data transmission module operates at a preset first system clock or a preset second system clock, wherein the frequency of the first system clock is greater than the frequency of the second system clock. In the deep sleep mode, the data transmission module operates at a preset third system clock; The second system clock frequency is greater than the third system clock frequency; In the shutdown mode, the system clock remains off.

9. A method for transmitting multi-channel bioelectric signals, characterized in that, include: The analog front-end module collects bioelectric signals and performs analog-to-digital conversion, then transmits the converted data stream to the data transmission module. The simulation front-end module includes multiple simulation front-end units, and each simulation front-end unit includes multiple acquisition channels; Based on the data transmission module being connected to the analog front-end module via a four-data-line serial peripheral interface, the data stream is received and transmitted to the remote host via the wireless ultra-wideband module. The data transmission module has multiple switchable operating modes.

10. A computer-readable medium, characterized in that, It stores computer-readable instructions, which are executed by a processor to implement a multi-channel bioelectric signal transmission method as described in claim 9.

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