Bonding apparatus and method for manufacturing semiconductor device

Abstract

The exposure apparatus includes a stage (140), a measuring device (144), and a control device (10). During the exposure process of the substrate, the control device (10) calculates a first correction factor corresponding to the positional deviation of the magnification component in a first direction and a second correction factor corresponding to the positional deviation of the magnification component in a second direction, based on the measurement results of at least three alignment marks. When a first setting is applied, the control device (10) uses the first correction factor to correct the positional deviation of the magnification component in the first direction and uses a third correction factor based on the first correction factor to correct the positional deviation of the magnification component in the second direction. When a second setting is applied, the control device (10) uses a fourth correction factor based on the second correction factor to correct the positional deviation of the magnification component in the first direction and uses the second correction factor to correct the positional deviation of the magnification component in the second direction.

Description

[0001] This invention is a divisional application of the following application, the original application information of which is as follows: Application date: July 8, 2022 Application Number: 202210805100.6 Invention Title: Method for Manufacturing an Exposure Apparatus, a Bonding Apparatus, and a Semiconductor Device This application claims priority based on prior Japanese Patent Application No. 2021-204292, filed on December 16, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to a method for manufacturing an exposure apparatus, a bonding apparatus, and a semiconductor device. Background Technology

[0003] Three-dimensional stacking technology is known for stacking semiconductor circuit substrates in three dimensions. Summary of the Invention

[0004] The purpose of this invention is to improve the yield of semiconductor devices.

[0005] The exposure apparatus of the technical solution exposes a substrate using illumination light via a projection optics system. The exposure apparatus includes a stage, a measuring device, and a control device. The stage holds the substrate. The measuring device measures at least three alignment marks on the substrate. The control device moves the stage based on the measurement results of the measuring device, controlling the exposure position of the substrate. During the substrate exposure process, based on the measurement results of the at least three alignment marks, the control device calculates a first correction coefficient corresponding to the positional deviation of the magnification component in a first direction and a second correction coefficient corresponding to the positional deviation of the magnification component in a second direction intersecting the first direction. When a first setting is applied, the control device uses the first correction coefficient to correct the positional deviation of the magnification component in the first direction and uses a third correction coefficient based on the first correction coefficient to correct the positional deviation of the magnification component in the second direction. When a second setting is applied, the control device uses a fourth correction coefficient based on the second correction coefficient to correct the positional deviation of the magnification component in the first direction and uses the second correction coefficient to correct the positional deviation of the magnification component in the second direction.

[0006] Based on the above structure, the yield of semiconductor devices can be improved. Attached Figure Description

[0007] Figure 1 It is a schematic diagram showing an outline of the manufacturing process of a semiconductor device.

[0008] Figure 2 This is a schematic diagram illustrating an example of overlap deviation components that may occur during the manufacturing process of a semiconductor device.

[0009] Figure 3 This is a schematic diagram illustrating an example of the configuration of alignment marks used in the manufacturing process of a semiconductor device.

[0010] Figure 4 This is a table illustrating an example of the correction performance of overlap deviation components within the wafer surface of the exposure and bonding apparatus used in the semiconductor device manufacturing process.

[0011] Figure 5 This is a block diagram illustrating an example of the structure of the exposure apparatus according to the first embodiment.

[0012] Figure 6 This is a flowchart illustrating an example of the exposure process of the exposure apparatus according to the first embodiment.

[0013] Figure 7 This is a table showing an example of the exposure formula used in the exposure apparatus of the first embodiment.

[0014] Figure 8 This is a schematic diagram illustrating an example of the change in wafer magnification overlap deviation when a normal alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment.

[0015] Figure 9 This is a schematic diagram illustrating an example of the change in wafer magnification overlap deviation when a normal alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment.

[0016] Figure 10 This is a schematic diagram illustrating an example of the change in wafer magnification overlap deviation when X-weighted mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment.

[0017] Figure 11 This is a schematic diagram illustrating an example of the change in wafer magnification overlap deviation when Y-weighted mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment.

[0018] Figure 12 This is a schematic diagram illustrating an example of the variation in wafer orthogonality overlap deviation when a normal alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment.

[0019] Figure 13 This is a schematic diagram illustrating an example of the variation in wafer orthogonality overlap deviation when a normal alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment.

[0020] Figure 14 This is a schematic diagram illustrating an example of the change in wafer orthogonality overlap deviation in the case where alignment correction using the X-weighted mode is used in the manufacturing process of the semiconductor device according to the first embodiment.

[0021] Figure 15 This is a schematic diagram illustrating an example of the change in wafer orthogonality overlap deviation in the case where alignment correction using the Y-weighted mode is used in the manufacturing process of the semiconductor device according to the first embodiment.

[0022] Figure 16 This is a block diagram illustrating an example of the structure of the semiconductor manufacturing system according to the second embodiment.

[0023] Figure 17 This is a block diagram illustrating an example of the structure of the coupling device according to the second embodiment.

[0024] Figure 18 This is a block diagram illustrating an example of the structure of the server according to the second embodiment.

[0025] Figure 19 This is a schematic diagram showing an outline of the joining process of the joining device in the second embodiment.

[0026] Figure 20 This is a flowchart illustrating an example of a process related to wafer magnification correction in the bonding process of the bonding apparatus of the second embodiment.

[0027] Figure 21 This is a flowchart illustrating an example of a process related to wafer magnification correction in the bonding process of a bonding apparatus according to a modified embodiment of the second embodiment.

[0028] Figure 22 This is a flowchart illustrating an example of a manufacturing method for a correction of the overlap deviation used in the coupling device of the third embodiment.

[0029] Figure 23 This is a flowchart illustrating an example of the joining process of the joining device according to the third embodiment.

[0030] Figure 24 This is a schematic diagram illustrating an example of multiple wafers used in the fabrication of a correction for the overlap deviation used in the bonding apparatus of the third embodiment.

[0031] Figure 25 This is a graph illustrating an example of the change in the amount of miscalculation in displacement measurement before and after the fabrication of a correction formula for the overlap deviation in the joining process of the joining device of the third embodiment.

[0032] Figure 26This is a block diagram illustrating an example of the structure of the storage device according to the fourth embodiment.

[0033] Figure 27 This is a circuit diagram illustrating an example of the circuit structure of the memory cell array of the memory device according to the fourth embodiment.

[0034] Figure 28 This is a perspective view showing an example of the construction of the storage device according to the fourth embodiment.

[0035] Figure 29 This is a top view showing an example of the planar layout of the storage cell array of the storage device according to the fourth embodiment.

[0036] Figure 30 This is a cross-sectional view showing an example of the cross-sectional structure of the storage cell array of the storage device according to the fourth embodiment.

[0037] Figure 31 This is an example of the cross-sectional structure of the storage column of the storage device according to the fourth embodiment, along... Figure 30 A cross-sectional view of the XXXI-XXXI line.

[0038] Figure 32 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the fourth embodiment. Detailed Implementation

[0039] Hereinafter, embodiments will be described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for embodying the inventive concept. The drawings are schematic or conceptual. The dimensions and scales of the drawings are not necessarily identical to reality. Structural details are appropriately omitted. The shading added to the drawings is not necessarily related to the material or properties of the constituent elements. In this specification, constituent elements having substantially the same function and structure are given the same reference numerals. Numbers and other reference numerals attached to reference numerals are referenced by the same reference numerals and are used to distinguish similar elements from each other.

[0040] The semiconductor device described in this specification is formed by bonding two semiconductor circuit substrates on which semiconductor circuits are formed respectively, and then separating the bonded semiconductor circuit substrates according to each chip.

[0041] Hereinafter, the semiconductor circuit substrate is referred to as a "wafer". The process of bonding two wafers is referred to as a "bonding process". The apparatus for performing the bonding process is referred to as a "bonding apparatus". The wafer positioned on the upper side during the bonding process is referred to as the "upper wafer UW". The wafer positioned on the lower side during the bonding process is referred to as the "lower wafer LW". The group of the two wafers after bonding, namely the upper wafer UW and the lower wafer LW, is referred to as the "bonded wafer BW". In this specification, the X and Y directions are intersecting directions that are parallel to the surface of the wafer. The Z direction is a direction that intersects with the X and Y directions respectively and is a plumb line relative to the surface of the wafer. The "surface of the wafer" is the side on which the semiconductor circuit is formed through the preceding process described later. The "back side of the wafer" is the side opposite to the surface of the wafer. The terms "upper" and "lower" in this specification are defined based on the direction along the Z direction.

[0042] <An Overview of Semiconductor Device Manufacturing Methods> Figure 1 This is a schematic diagram illustrating an outline of a semiconductor device manufacturing process. See below for reference. Figure 1 The general process flow of the semiconductor device manufacturing method described in this specification is explained.

[0043] First, wafers are assigned to batches (“batch allocation”). These batches are, for example, classified into batches containing upper wafers (UW) and batches containing lower wafers (LW). Then, front-end processes are performed on the batches containing upper wafers (UW) and the batches containing lower wafers (LW) respectively, forming semiconductor circuits on the upper wafers (UW) and the lower wafers (LW). The front-end processes include a combination of “exposure processing”, “overlay measurement”, and “processing”.

[0044] Exposure processing is, for example, a process of transferring the pattern of a mask onto a wafer coated with resist by irradiating it with light that has passed through the mask. The area where the mask pattern is transferred in one exposure corresponds to "one exposure". In exposure processing, the exposures of one exposure are staggered and repeated. That is, exposure processing is performed in a step-and-repeat manner. In exposure processing, the configuration and shape of each exposure are corrected based on the measurement results of alignment marks (described later), and the overlap position with the pattern formed on the substrate on the wafer is adjusted (aligned). The configuration (layout) of multiple exposures on the upper wafer (UW) and the configuration (layout) of multiple exposures on the lower wafer (LW) are set to be the same. Hereinafter, the apparatus for performing exposure processing will be referred to as an "exposure apparatus".

[0045] Exposure OL measurement is the process of measuring the overlap deviation between the pattern formed by the exposure process and the pattern on the substrate used for the exposure process. The overlap deviation measurement results obtained by exposure OL measurement are used for rework determination of the exposure process, calculation of overlap deviation correction values ​​for subsequent batches, etc. Processing is the process of processing (e.g., etching) the wafer using a mask formed by the exposure process. Once processing is complete, the mask used is removed, and the next process is performed.

[0046] If the preceding process is completed, a bonding process is performed. In the bonding process, the bonding apparatus positions the surfaces of the upper wafer (UW) and the lower wafer (LW) facing each other. Furthermore, the bonding process adjusts (aligns) the overlapping positions of the patterns formed on the surface of the upper wafer (UW) and the patterns formed on the surface of the lower wafer (LW). Then, the bonding apparatus joins the surfaces of the upper wafer (UW) and the lower wafer (LW) together to form a bonded wafer (BW).

[0047] For the bonded wafers (BW) formed through the bonding process, an overlay (OL) measurement is performed. The overlay (OL) measurement is a process that measures the overlap deviation between the patterns formed on the surface of the upper wafer (UW) and the patterns formed on the surface of the lower wafer (LW). The measurement results of the overlap deviation obtained through the overlay (OL) measurement are used to calculate the correction value for the overlap deviation applied to subsequent batch exposure processes, etc.

[0048] The amount of overlap deviation generated in exposure processing or bonding processing can be represented by a combination of various components. Figure 2 This is a schematic diagram illustrating an example of overlap deviation components that may occur during the manufacturing process of a semiconductor device. Figure 2 Examples are given for the formulas corresponding to each coincidence deviation component and the shape changes after a single irradiation based on these formulas. For example... Figure 2 As shown, the coincidence deviation components include, for example, (A) offset component, (B) magnification component, (C) rhombus (orthogonality) component, (D) eccentric magnification component, (E) trapezoidal component, (F) fan-shaped component, (G) C-shaped magnification component, (H) folding component, (I) off-center C-shaped component, and (J) flow-shaped component. Figure 2 The overlap deviation components of (A) to (J) also include components in the X and Y directions.

[0049] The following lists and Figure 2 The numerical expressions corresponding to each component of (A) to (J). Furthermore, in the following numerical expressions, "x" and "y" correspond to the coordinates in the X direction (X coordinate) and Y direction (Y coordinate), respectively. "dx" and "dy" are the overlap deviations in the X and Y directions, respectively. "K1" to "K20" are the coefficients of each overlap deviation component.

[0050] (A) The offset (displacement) component in the X direction is "dx=K1". The offset (displacement) component in the Y direction is "dy=K2".

[0051] (B) The magnification component in the X direction is "dx = K3·x". The magnification component in the Y direction is "dy = K4·y".

[0052] (C) The rhombus (orthogonality) component in the X direction is "dx=K5·y". The rhombus (orthogonality) component in the Y direction is "dy=K6·x".

[0053] (D) The eccentricity component in the X direction is "dx = K7·x". 2 The eccentricity factor in the Y direction is "dy = K8·y". 2 ".

[0054] (E) The trapezoidal component in the X direction is "dx = K9·x·y". The trapezoidal component in the Y direction is "dy = K10·x·y".

[0055] (F) The sector component in the X direction is "dx=K11·y 2 The sector component in the Y direction is "dy = K12·x". 2 ".

[0056] The C-magnification component in the (G)X direction is "dx=K13·x". 3 The C-factor component in the Y direction is "dy = K14·y". 3 ".

[0057] The folding component in the (H)X direction is "dx = K15·x". 2 The folding component in the Y direction is dy = K16·x·y. 2 ".

[0058] (I) The C-shaped component in the X direction is "dx=K17·x·y 2 The C-shaped component in the Y direction is "dy = K18·x". 2 ·y”.

[0059] (J) The flow formation component in the X direction is "dx=K19·y 3 The flow formation component in the Y direction is "dy = K20·x". 3 ".

[0060] In addition, Figure 2The example illustrates the overlap deviation component of the irradiation unit, but the overlap deviation component generated within the wafer plane can also be represented by the same overlap deviation component as the irradiation unit. Hereinafter, the overlap deviation of the magnification component generated within the wafer plane will also be referred to as "wafer magnification." The overlap deviation of the orthogonality component generated within the wafer plane will also be referred to as "wafer orthogonality." The exposure apparatus and bonding apparatus utilize the measurement results of alignment marks formed on the wafer during alignment at the overlap position.

[0061] Figure 3 This is a schematic diagram illustrating an example of the configuration of alignment marks used in the manufacturing process of a semiconductor device. Figure 3 (A) illustrates the position of the alignment mark AM measured during exposure processing. Figure 3 (B) illustrates the position of the alignment mark AM on the upper wafer UW, measured during the bonding process. Figure 3 (C) illustrates the position of the alignment mark AM of the lower wafer LW as measured during the bonding process.

[0062] like Figure 3 As shown in (A), the exposure apparatus can measure alignment marks AM at multiple points (at least three) disposed on the wafer during the exposure process. Furthermore, by performing a function approximation of the measurement results of the alignment marks AM at multiple points in an orthogonal coordinate system, the exposure apparatus can calculate correction values ​​for overlap deviation components, such as shift components, magnification components, and orthogonality components, in both the X and Y directions. In addition, the exposure apparatus can correct the overlap deviation components of the irradiated unit and the in-plane overlap deviation components of the wafer separately. In this way, the exposure apparatus can correct complex overlap deviation components.

[0063] like Figure 3 As shown in (B) and (C), during the bonding process, the bonding apparatus measures alignment marks AM_C, AM_L, and AM_R at at least three points respectively disposed on the upper wafer UW and the lower wafer LW. Alignment mark AM_C is disposed near the center of the wafer. The bonding apparatus uses the measurement results of alignment mark AM_C for aligning the shifting components of the wafer. Alignment marks AM_L and AM_R are disposed on one side and the other side of the outer periphery of the wafer, respectively. The bonding apparatus uses the measurement results of alignment marks AM_L and AM_R for aligning the rotational components of the wafer.

[0064] In this way, the bonding apparatus can use alignment marks AM_C, AM_L, and AM_R at at least three points to calculate correction values ​​for simple coincidence deviation components (displacement and rotation components) within the wafer plane. Furthermore, the bonding apparatus can measure the alignment marks AM of the upper wafer UW and the lower wafer LW in parallel. For example, the alignment marks AM_C of the upper wafer UW and the lower wafer LW are offset from each other in opposite directions from the wafer center to allow for simultaneous measurement under the constraint of the AM alignment mark configuration.

[0065] Figure 4 This table is an example of how the correction performance of overlap deviation components within the wafer surface is demonstrated by the exposure and bonding equipment used in the semiconductor device manufacturing process. For example... Figure 4 As shown, both the exposure apparatus and the bonding apparatus can correct the displacement component. Both the exposure apparatus and the bonding apparatus can correct the common wafer magnification in the X and Y directions (XY common magnification component). The method for correcting the XY common magnification component of the bonding apparatus will be described later. Wafer magnification that differs in the X and Y directions (XY difference magnification component) can be corrected in the exposure apparatus. On the other hand, the XY difference magnification component is difficult to correct in the bonding apparatus. Both the exposure apparatus and the bonding apparatus can correct the rotation component. Rotation components that differ in the X and Y directions (orthogonality component) can be corrected in the exposure apparatus. On the other hand, the orthogonality component is difficult to correct in the bonding apparatus. Randomly generated overlap deviation components within the wafer plane (random component) can be corrected in the exposure apparatus at the irradiation unit level. On the other hand, the random component is difficult to correct in the bonding apparatus.

[0066] [1] First Embodiment The first embodiment relates to an exposure apparatus capable of modifying alignment correction settings in a specific process preceding the next wafer LW (Layer Wafer) to correspond with the design of the semiconductor device. Hereinafter, details of the exposure apparatus 1 of the first embodiment will be described.

[0067] [1-1] Structure of Exposure Device 1 Figure 5 This is a block diagram illustrating an example of the structure of the exposure apparatus 1 according to the first embodiment. For example... Figure 5 As shown, the exposure apparatus 1 includes, for example, a control device 10, a storage device 11, a transport device 12, a communication device 13, and an exposure unit 14.

[0068] The control device 10 is a computer or similar device that controls the overall operation of the exposure apparatus 1. The control device 10 controls the storage device 11, the transport device 12, the communication device 13, and the exposure unit 14 respectively. Although not shown in the figure, the control device 10 includes a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory). The CPU is a processor that executes various programs for controlling the apparatus. ROM is a non-volatile storage medium that stores the control programs for the apparatus. RAM is a volatile storage medium used as the working area of ​​the CPU.

[0069] Storage device 11 is a storage medium used for storing data or programs, etc. Storage device 11 stores, for example, exposure recipe 110 and correction value information 111. Exposure recipe 110 is a table recording the settings for exposure processing. Exposure recipe 110 includes information such as the shape and layout of the irradiation, exposure amount, focus setting, and alignment setting. Exposure recipe 110 can be prepared for each processing step or batch. Correction value information 111 is a log recording the correction values ​​(i.e., alignment results) for the overlap deviation used during exposure processing.

[0070] The transport device 12 is a device having a transport arm capable of transporting wafers, a transfer section for temporarily holding multiple wafers, etc. For example, the transport device 12 transports wafers (WF) received from an external coating and developing apparatus to the exposure unit 14. Furthermore, after exposure processing, the transport device 12 transports wafers (WF) received from the exposure unit 14 to the outside of the exposure apparatus 1. Additionally, the "coating and developing apparatus" is a device that performs pre-processing and post-processing of the exposure process. Pre-processing of the exposure process includes coating the wafer with a resist material (photosensitive material). Post-processing of the exposure process includes developing the pattern already exposed on the wafer. Furthermore, multiple semiconductor manufacturing apparatuses can be used as devices for the pre-processing and post-processing of the exposure process.

[0071] The communication device 13 is a communication interface that can be connected to a network. The exposure device 1 can operate based on operations performed by a terminal on the network, or it can enable a server on the network to store the exposure formula 110 and correction value information 111.

[0072] Exposure unit 14 is a collection of structures used in the exposure process. Exposure unit 14 includes, for example, a wafer stage 140, a tracing stage 141, a light source 142, a projection optics system 143, and a camera 144. Wafer stage 140 functions to hold the wafer facet (WF). Tracing stage 141 functions to hold the tracing mask (RT). The stage positions of wafer stage 140 and tracing stage 141 can be controlled based on the control of control device 10. Light source 142 illuminates the tracing mask (RT) with generated light. Projection optics system 143 converges the light transmitted through tracing mask (RT) onto the surface of wafer facet (WF). Camera 144 is a photographic mechanism used for measuring alignment marks (AM).

[0073] [1-2] Manufacturing methods for semiconductor devices Hereinafter, as a method for manufacturing a semiconductor device according to the first embodiment, an example of a specific process using the exposure apparatus 1 will be described. That is, a semiconductor device is manufactured using the exposure method (exposure process) of the first embodiment described below.

[0074] [1-2-1] Exposure Processing Figure 6 This is a flowchart illustrating an example of the exposure process of the exposure apparatus 1 according to the first embodiment. Hereinafter, refer to... Figure 6 The exposure process of exposure device 1 is explained.

[0075] If the coating and developing apparatus notifies that the wafer pretreatment is complete, the exposure apparatus 1 begins the exposure process (start).

[0076] First, the exposure apparatus 1 loads the wafer (S100). The wafer loaded from the coating and developing apparatus is held by the wafer stage 140.

[0077] Next, the exposure apparatus 1 confirms the exposure formula 110 (S101). As a result, the control device 10 determines the processing conditions to be applied to the loaded wafer.

[0078] Next, the exposure apparatus 1 measures the alignment marks AM (S102). Specifically, the camera 144 photographs a plurality of alignment marks AM disposed at predetermined positions on the wafer.

[0079] Next, the exposure apparatus 1 performs alignment correction processing (S103). Specifically, the control device 10 calculates correction values ​​for the irradiation configuration and irradiation shape of the wafer exposure based on the photographic results of multiple alignment marks AM.

[0080] Next, the exposure apparatus 1 executes the exposure sequence (S104). Specifically, the control device 10 controls the light source 142, the wafer stage 140 and the marker stage 141 based on the correction value calculated in S103, and illuminates the wafer with light that has passed through the mask in a distributed and repetitive manner.

[0081] Next, the exposure apparatus 1 updates the correction value information 111 (S105). That is, in S105, the correction value calculated in S103 is associated with the processed wafer and recorded in the correction value information 111.

[0082] Next, the exposure apparatus 1 unloads the wafer (S106). The unloaded wafer is then transferred to the coating and developing apparatus. The coating and developing apparatus performs heat treatment, development, and cleaning on the exposed wafer. As a result, a pattern is formed on the wafer.

[0083] If the wafer is unloaded, the exposure apparatus 1 ends the exposure process (end).

[0084] [1-2-2] Specific examples of exposed formulas Figure 7 This is a table showing an example of the exposure formula 110 used in the exposure apparatus 1 of the first embodiment. For example... Figure 7 As shown, the exposure recipe 110 associates and stores settings, selected branches, and process categories. Settings for the exposure recipe 110 include, for example, "alignment correction," "wafer magnification correction," "wafer magnification correction ratio (MagX / MagY)," "wafer rotation correction," and "wafer rotation correction ratio (RotX / RotY)."

[0085] The alignment correction settings include three options: "Normal (Mode)", "X-Focus (Mode)", and "Y-Focus (Mode)". Normal mode applies approximately 100% correction to the overlap deviation components in both the X and Y directions during exposure processing. X-Focus mode prioritizes correcting the overlap deviation components in the X direction during exposure processing. Specifically, X-Focus mode applies approximately 100% correction to the X-direction overlap deviation components for the alignment result. On the other hand, X-Focus mode applies a correction to the Y-direction overlap deviation components based on a percentage of the correction value relative to the X-direction. Y-Focus mode prioritizes correcting the Y-direction overlap deviation components during exposure processing. Specifically, Y-Focus mode applies approximately 100% correction to the Y-direction overlap deviation components for the alignment result. On the other hand, Y-Focus mode applies a correction to the X-direction overlap deviation components based on a percentage of the correction value relative to the Y-direction.

[0086] The wafer magnification correction setting has two options: "Off" and "On". When the wafer magnification correction setting is "Off", the exposure apparatus 1 applies the normal mode conditions to the calculation of the wafer magnification correction value during exposure processing. When the wafer magnification correction setting is "On", the exposure apparatus 1 applies either the X-weighted mode or the Y-weighted mode conditions to the calculation of the wafer magnification correction value during exposure processing. Furthermore, when the wafer magnification correction setting is "On", the wafer magnification correction ratio is set with reference. The wafer magnification correction ratio setting represents the ratio (MagX / MagY) of the wafer magnification correction value in the X direction (MagX) to the wafer magnification correction value in the Y direction (MagY) during alignment correction. The wafer magnification correction ratio is set, for example, in the range of 0.5 to 2.0. When MagX / MagY = 1, the exposure apparatus 1 sets the exposure apparatus reference MagX:MagY to 1:1.

[0087] The wafer rotation correction setting has two options: "Off" and "On". When the wafer rotation correction setting is "Off", the exposure apparatus 1 applies the normal mode conditions to the calculation of the correction value for the wafer rotation component during exposure processing. When the wafer rotation correction setting is "On", the exposure apparatus 1 applies either the X-weighted mode or the Y-weighted mode conditions to the calculation of the correction value for the wafer rotation component during exposure processing. Furthermore, when the wafer rotation correction setting is "On", the wafer rotation correction ratio is set. The wafer rotation correction ratio represents the ratio (RotX / RotY) of the correction value for wafer orthogonality in the X direction (RotX) to the correction value for wafer orthogonality in the Y direction (RotY) during alignment correction. The wafer rotation correction ratio is set, for example, in the range of 0.5 to 2.0. When RotX / RotY = 1, the exposure apparatus 1 sets the exposure apparatus reference RotX:RotY to 1:1.

[0088] Process categories are parameters assigned to processing steps for each exposure apparatus. Process categories include, for example, Group 1 and Group 2. Processing steps in Group 1 are assigned to, for example, the first half of the exposure process in the preceding process. Processing steps in Group 2 are assigned to, for example, the exposure process in the preceding process used to form the wiring layer near the wafer surface. For Group 1, a normal mode is used, for example, as an alignment correction setting. For Group 2, a Y-weighting mode is used, for example, as an alignment correction setting. Furthermore, in Group 2, for example, wafer magnification correction is set to "on," the wafer magnification correction ratio is set to "1," and wafer rotation correction is set to "off." Thus, when using either the X-weighting mode or the Y-weighting mode, only at least one of the wafer magnification correction and wafer rotation correction needs to be used. The user can change the alignment correction parameters, such as the X-weighting mode or the Y-weighting mode, for each processing step or batch by editing the exposure recipe 110.

[0089] [1-2-3] Specific examples of alignment correction processing The following uses Figures 8-15 A specific example of alignment correction processing is explained. Figures 8-15 The illumination shape of the upper wafer (UW) in the preceding process, the illumination shape of the lower wafer (LW) before and after exposure in the preceding process, the alignment correction in the bonding process, and the overlap state of the bonded wafer (BW) after bonding are simplified and shown separately. Furthermore, the illustrated illumination shapes illustrate the shapes of multiple illumination groups arranged within the wafer plane, schematically showing the effects of fluctuations in wafer magnification or wafer orthogonality within the wafer plane. Hereinafter, the alignment correction process will be explained with regard to wafer magnification and wafer orthogonality; however, in actual exposure processes, the alignment result can be reflected in both the overlap deviation component of the illumination unit (illumination component) and the overlap deviation component within the wafer plane (wafer component).

[0090] Figure 8 This is a schematic diagram illustrating an example of the change in wafer magnification overlap deviation when a normal alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment.

[0091] like Figure 8As shown, in this example, the XY ratio of the wafer magnification of the lower wafer LW is the same as the XY ratio of the wafer magnification of the substrate shape of the upper wafer UW. In this example, since the alignment correction setting is in normal mode, the irradiation shape, which has been corrected by applying wafer composition correction through exposure processing, is corrected to be approximately the same as the substrate shape. Therefore, in the exposure processing of the lower wafer LW, the generation of wafer magnification overlap deviation is suppressed. Furthermore, the XY ratio of the wafer magnification of the lower wafer LW after exposure processing is the same as the XY ratio of the wafer magnification of the upper wafer UW. Then, the bonding apparatus performs bonding processing on the lower wafer LW by applying XY common wafer magnification correction. In this example, since the XY ratios of the wafer magnification of the upper wafer UW and the lower wafer LW are the same during bonding processing, the overlap deviation of the wafer magnification of the upper wafer UW and the lower wafer LW of the bonding wafer BW is suppressed.

[0092] Figure 9 This is a schematic diagram illustrating an example of the change in wafer magnification overlap deviation when a conventional alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. Figure 9 As shown, in this example, the XY ratio of the wafer magnification of the lower wafer (LW) differs from the XY ratio of the wafer magnification of the substrate shape of the upper wafer (UW). In this example, since the alignment correction setting is in normal mode, the irradiation shape, which has undergone wafer composition correction through exposure processing, is corrected to be approximately the same as the substrate shape. Therefore, the generation of wafer magnification overlap deviation during the exposure processing of the lower wafer (LW) is suppressed. Furthermore, the XY ratio of the wafer magnification of the lower wafer (LW) after exposure processing differs from the XY ratio of the upper wafer (UW). Then, the bonding apparatus performs bonding processing on the lower wafer (LW) by applying a common XY wafer magnification correction. In this example, the XY ratios of the wafer magnification of the upper wafer (UW) and the lower wafer (LW) are different during bonding processing, and the bonding apparatus cannot correct the XY difference in wafer magnification, so the overlap deviation of the wafer magnification between the upper wafer (UW) and the lower wafer (LW) of the bonded wafer (BW) remains.

[0093] Figure 10 This is a schematic diagram illustrating an example of the change in wafer magnification overlap deviation when X-weighted mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. Figure 10As shown, the XY ratio of the wafer magnification of the lower wafer (LW) in this example is different from that of the upper wafer (UW). In this example, since the alignment correction setting is X-emphasis mode, the wafer magnification setting applied to the wafer composition correction during the exposure process is the same as the XY ratio of the wafer magnification of the upper wafer (UW), and only the X-direction suppresses the overlap deviation with the substrate shape. Therefore, in the exposure process of the lower wafer (LW), the generation of wafer magnification overlap deviation in the X direction is suppressed; on the other hand, the wafer magnification overlap deviation in the Y direction remains. Then, the bonding apparatus performs the bonding process for the lower wafer (LW) by applying the XY common wafer magnification correction. In this example, since the XY ratio of the wafer magnification of the upper wafer (UW) and the lower wafer (LW) is the same during the bonding process, the overlap deviation of the wafer magnification of the upper wafer (UW) and the lower wafer (LW) of the bonded wafer (BW) is suppressed.

[0094] Figure 11 This is a schematic diagram illustrating an example of the change in wafer magnification overlap deviation when Y-preferred mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. Figure 11 As shown, the XY ratio of the wafer magnification of the lower wafer (LW) in this example is different from that of the upper wafer (UW). In this example, since the alignment correction is set to Y-priority mode, the wafer magnification applied to the wafer composition correction during exposure processing is the same as the XY ratio of the wafer magnification of the upper wafer (UW), and it is set to suppress the overlap deviation with the substrate shape only in the Y direction. Therefore, in the exposure processing of the lower wafer (LW), the generation of wafer magnification overlap deviation in the Y direction is suppressed; on the other hand, the wafer magnification overlap deviation in the X direction remains. Then, the bonding apparatus performs the bonding process by applying a common XY wafer magnification correction to the lower wafer (LW). In this example, since the XY ratio of the wafer magnification of the upper wafer (UW) and the lower wafer (LW) is the same during the bonding process, the overlap deviation of the wafer magnification of the upper wafer (UW) and the lower wafer (LW) of the bonding wafer (BW) is suppressed.

[0095] Figure 12 This is a schematic diagram illustrating an example of the change in wafer orthogonality overlap deviation when a conventional alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. Figure 12As shown, in this example, the XY ratio of the wafer orthogonality of the lower wafer LW is the same as the XY ratio of the wafer orthogonality of the substrate shape of the upper wafer UW. In this example, since the alignment correction setting is in normal mode, the irradiation shape, which has been corrected by applying wafer composition correction through exposure processing, is corrected to be approximately the same as the substrate shape. Therefore, during the exposure processing of the lower wafer LW, the generation of wafer orthogonality overlap deviation is suppressed. Furthermore, the XY ratio of the wafer orthogonality of the lower wafer LW after exposure processing is the same as the XY ratio of the wafer orthogonality of the upper wafer UW. Then, the bonding apparatus performs bonding processing by applying XY common wafer orthogonality correction (i.e., rotation correction) to the lower wafer LW. In this example, since the XY ratio of the wafer orthogonality of the upper wafer UW and the lower wafer LW is the same during bonding processing, the overlap deviation of the wafer orthogonality of the upper wafer UW and the lower wafer LW of the bonding wafer BW is suppressed.

[0096] Figure 13 This is a schematic diagram illustrating an example of the change in wafer orthogonality overlap deviation when a conventional alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. Figure 13 As shown, the XY ratio of the wafer orthogonality of the lower wafer (LW) in this example differs from the XY ratio of the wafer orthogonality of the substrate shape of the upper wafer (UW). In this example, since the alignment correction setting is in normal mode, the irradiation shape, which has undergone wafer composition correction through exposure processing, is corrected to be approximately the same as the substrate shape. Therefore, during the exposure processing of the lower wafer (LW), the generation of wafer orthogonality overlap deviation is suppressed. Furthermore, the XY ratio of the wafer orthogonality of the lower wafer (LW) after exposure processing differs from the XY ratio of the wafer orthogonality of the upper wafer (UW). Then, the bonding apparatus performs the bonding process by applying a common XY wafer orthogonality correction (i.e., rotation correction) to the lower wafer (LW). In this example, the XY ratios of the wafer orthogonality of the upper wafer UW and the lower wafer LW are different during the bonding process. The bonding device cannot correct the XY difference in wafer orthogonality, so the overlap deviation of the wafer orthogonality of the upper wafer UW and the lower wafer LW of the bonded wafer BW remains.

[0097] Figure 14 This is a schematic diagram illustrating an example of the change in wafer orthogonality overlap deviation when X-weighted mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. Figure 14As shown, the XY ratio of the wafer orthogonality of the lower wafer (LW) in this example is different from that of the upper wafer (UW). In this example, since the alignment correction setting is in X-priority mode, the wafer orthogonality setting applied to the wafer composition correction during the exposure process is the same as the XY ratio of the wafer orthogonality of the upper wafer (UW), and only the X-direction suppresses the overlap deviation with the substrate shape. Therefore, in the exposure process of the lower wafer (LW), the generation of wafer orthogonality overlap deviation in the X direction is suppressed; on the other hand, the overlap deviation of wafer orthogonality in the Y direction remains. Then, the bonding apparatus performs the bonding process by applying a common XY wafer orthogonality correction (i.e., rotation correction) to the lower wafer (LW). In this example, since the XY ratio of the wafer orthogonality of the upper wafer UW and the lower wafer LW is the same during the bonding process, the overlap deviation of the wafer orthogonality between the upper wafer UW and the lower wafer LW of the bonding wafer BW is suppressed.

[0098] Figure 15 This is a schematic diagram illustrating an example of the change in wafer orthogonality overlap deviation when Y-weighted mode alignment correction is used in the manufacturing process of the semiconductor device according to the first embodiment. Figure 15 As shown, the XY ratio of the wafer orthogonality of the lower wafer (LW) in this example is different from that of the upper wafer (UW). In this example, since the alignment correction setting is Y-emphasis mode, the wafer orthogonality applied to the wafer composition correction during the exposure process has the same XY ratio as that of the upper wafer (UW), and is set to suppress the overlap deviation with the substrate shape only in the Y direction. Therefore, in the exposure process of the lower wafer (LW), the generation of overlap deviation of wafer orthogonality in the Y direction is suppressed, while the overlap deviation of wafer orthogonality in the X direction remains. Then, the bonding apparatus performs the bonding process by applying a common XY wafer orthogonality correction (i.e., rotation correction) to the lower wafer (LW). In this example, since the XY ratio of the wafer orthogonality of the upper wafer UW and the lower wafer LW is the same during the bonding process, the overlap deviation of the wafer orthogonality between the upper wafer UW and the lower wafer LW of the bonding wafer BW is suppressed.

[0099] [1-3] Effects of the first embodiment The exposure apparatus 1 according to the first embodiment described above can improve the yield of semiconductor devices. Hereinafter, the effects of the exposure apparatus 1 according to the first embodiment will be explained in detail.

[0100] A known bonding apparatus can only correct for the overlap deviation of wafer magnification and rotational composition between the upper wafer UW and the lower wafer LW using the same value in both the X-direction and Y-direction compositions. For a bonded wafer BW formed by such a bonding apparatus, if the XY difference in wafer magnification between the upper wafer UW and the lower wafer LW fluctuates between wafers, then using... Figure 9As explained, overlap deviations between the upper wafer (UW) and the lower wafer (LW) may remain. Similarly, when the XY differences in the wafer orthogonality of the upper wafer (UW) and the lower wafer (LW) fluctuate between wafers, if using... Figure 13 As explained, there may be residual overlap deviation between the upper wafer (UW) and the lower wafer (LW).

[0101] As a method to improve the overlap deviation in the bonding process, it is possible to adjust the wafer ratio and wafer orthogonality XY difference in the bonding surface pattern of the lower wafer (LW) to match the upper wafer (UW). This can suppress the overlap deviation between the lower wafer (LW) and the upper wafer (UW) during the bonding process. However, even when adjusting the bonding surface pattern of the lower wafer (LW) to match the upper wafer (UW), if using... Figure 10 , Figure 11 , Figure 13 and Figure 14 As explained, there are residual discrepancies in the overlap between the pattern on the mating surface and the pattern on its base.

[0102] On the other hand, the permissible range of overlap deviation between the bonding surface pattern and the substrate pattern can be narrow in one direction (X) and wide in the other (Y). That is, prioritizing the correction of overlap deviation between the upper wafer (UW) and the lower wafer (LW), even if the overlap deviation between the bonding surface pattern and the substrate pattern at the lower wafer (LW) worsens, the overlap deviation in one of the X and Y directions may still have a small impact on the yield.

[0103] Therefore, the exposure apparatus 1 of the first embodiment has the function of determining the wafer magnification correction value in the other direction based on the wafer magnification correction value in one of the wafer magnification correction values ​​in the X and Y directions obtained by measuring the alignment mark AM during the exposure process.

[0104] Specifically, when using the X-focus mode, the exposure apparatus 1 can match the wafer magnification correction value in the X direction of the lower wafer LW to the substrate, and determine the wafer magnification correction value in the Y direction based on the wafer magnification correction ratio. When using the X-focus mode, the exposure apparatus 1 can match the wafer orthogonality correction value in the X direction of the lower wafer LW to the substrate, and determine the wafer orthogonality correction value in the Y direction based on the wafer rotation correction ratio. Furthermore, when using the Y-focus mode, the exposure apparatus 1 can match the wafer magnification correction value in the Y direction of the lower wafer LW to the substrate, and determine the wafer magnification correction value in the X direction based on the wafer magnification correction ratio. When using the Y-focus mode, the exposure apparatus 1 can match the wafer orthogonality correction value in the X direction of the lower wafer LW to the substrate, and determine the wafer magnification correction value in the Y direction based on the wafer magnification correction ratio.

[0105] Furthermore, for the exposure apparatus 1 of the first embodiment, the alignment correction setting can be differentiated according to the tendency of the range of allowable overlap deviations in the X and Y directions in each processing step. Specifically, when the range of allowable overlap deviations is only wide in the Y direction, it is preferable to use the X-focus mode as the alignment correction setting. When the range of allowable overlap deviations is only wide in the X direction, it is preferable to use the Y-focus mode as the alignment correction setting. When the range of allowable overlap deviations is strict in both the X and Y directions, it is preferable to use the normal mode that matches the overlap deviation components in the X and Y directions to the substrate as the alignment correction setting.

[0106] As described above, by using an X-weighted mode or a Y-weighted mode, the exposure apparatus 1 of the first embodiment can suppress overlap deviations in directions with a large permissible range of overlap deviations, even though the overlap deviation in these directions can increase. In other words, by appropriately tolerating overlap deviations in processes and directions with a large permissible range of overlap deviations, the exposure apparatus 1 of the first embodiment can suppress overlap deviations in processes and directions with a small permissible range of overlap deviations, thereby improving the yield of the semiconductor device.

[0107] [2] Second Embodiment The second embodiment relates to a semiconductor manufacturing system that corrects the wafer ratio of the lower wafer LW in a bonding process based on the exposure results of the lower wafer LW and the upper wafer UW. Hereinafter, details of the semiconductor manufacturing system PS of the second embodiment will be described.

[0108] [2-1] Structure [2-1-1] Structure of a semiconductor manufacturing system PS Figure 16 This is a block diagram illustrating an example of the structure of the semiconductor manufacturing system PS according to the second embodiment. For example... Figure 16 As shown, a semiconductor manufacturing system PS includes, for example, an exposure apparatus 1, a bonding apparatus 2, and a server 3. The exposure apparatus 1, the bonding apparatus 2, and the server 3 are configured to communicate via a network NW. The network NW can use either wired or wireless communication.

[0109] [2-1-2] Structure of the coupling device 2 Figure 17 This is a block diagram illustrating an example of the structure of the coupling device 2 according to the second embodiment. For example... Figure 17 As shown, the joining device 2 includes, for example, a control device 20, a conveying device 21, a communication device 22, and a joining unit 23.

[0110] The control device 20 is a computer or similar device that controls the overall operation of the bonding device 2. The control device 20 controls the conveying device 21, the communication device, and the bonding unit 23 respectively. The control device 20 is not shown in the figure, but like the exposure device 1, it has a CPU, ROM, RAM, etc.

[0111] The transport device 21 includes a transport arm capable of transporting wafers and a transfer section for temporarily mounting multiple wafers. For example, the transport device 21 transports the upper wafer UW and lower wafer LW received from the pre-processing unit of the bonding process to the bonding unit 23. Furthermore, after the bonding process, the transport device 21 transports the bonding wafer BW received from the bonding unit 23 to the outside of the bonding device 2. The transport device 21 may also have a mechanism for reversing the wafer's orientation.

[0112] The communication device 22 is a communication interface capable of connecting to the network NW. The connection device 2 can operate based on the control of the terminal on the network NW, or it can enable the server 3 on the network NW to store the operation log, or it can calculate the correction value of the overlap deviation based on the information stored in the server 3.

[0113] The bonding unit 23 is a collection of structures used in the bonding process. The bonding unit 23 includes, for example, a lower stage 230, a stress device 231, a camera 232, an upper stage 233, a pressing pin 234, and a camera 235. The lower stage 230 functions to hold the lower wafer (LW). The lower stage 230 includes, for example, a wafer chuck that holds the wafer by vacuum suction. The stress device 231 functions to apply stress to the lower stage 230, thereby deforming the lower wafer (LW) via the lower stage 230. The scaling of the lower wafer (LW) held on the lower stage 230 varies according to the amount of deformation of the lower stage 230 caused by the stress device 231. The camera 232 is disposed on the lower stage 230 side and is a photographic mechanism used for measuring the alignment mark AM on the upper wafer (UW). The upper stage 233 functions to hold the upper wafer (UW). The upper stage 233 includes, for example, a wafer chuck that holds the wafer by vacuum suction. The pressing pin 234 is driven vertically under the control of the control device 20, and is capable of pressing a pin held at the center of the upper wafer UW on the upper stage 233. The camera 235, disposed on the upper stage 233 side, is a photographic mechanism used for measuring the alignment mark AM on the lower wafer LW. The bonding device 2 may also have a vacuum pump used for vacuum adsorption on the lower stage 230 and the upper stage 233.

[0114] Furthermore, the lower stage 230 and the upper stage 233 are configured to allow the lower wafer LW held on the lower stage 230 and the upper wafer UW held on the upper stage 233 to be arranged opposite each other. That is, the upper stage 233 can be arranged above the lower stage 230. In other words, the lower stage 230 and the upper stage 233 can be arranged opposite each other. During the bonding process, the upper surface of the upper wafer UW is the back surface of the upper wafer UW and is held by the upper stage 233 of the bonding device 2. During the bonding process, the lower surface of the upper wafer UW is the surface surface of the upper wafer UW and corresponds to the bonding surface. The upper surface of the lower wafer LW is the surface surface of the lower wafer LW and corresponds to the bonding surface. The lower surface of the lower wafer LW is the back surface of the lower wafer LW and is held by the lower stage 230 of the bonding device 2. The bonding device 2 can adjust the displacement component and rotation component of the overlap deviation by adjusting the relative position of the lower stage 230 and the upper stage 233. Furthermore, the bonding device 2 can deform the lower stage 230 by the stress device 231, and adjust the common XY wafer ratio of the lower wafer LW held on the lower stage 230 after deformation.

[0115] Furthermore, the aforementioned "pre-treatment apparatus for bonding processing" is an apparatus that modifies and hydrophilizes the bonding surfaces of the upper wafer UW and the lower wafer LW respectively before the bonding process of the bonding apparatus 2. In short, the pre-treatment apparatus first performs plasma treatment on the surfaces of the upper wafer UW and the lower wafer LW respectively, modifying their surfaces. During plasma treatment, oxygen ions or nitrogen ions are generated based on oxygen or nitrogen gas as the treatment gas under a specified reduced pressure gas environment, and the generated oxygen ions or nitrogen ions are irradiated onto the bonding surfaces of each wafer. Then, the pre-treatment apparatus supplies pure water to the surfaces of the upper wafer UW and the lower wafer LW respectively. As a result, hydroxyl groups are attached to the surfaces of the upper wafer UW and the lower wafer LW respectively, making the surfaces hydrophilic. In the bonding process, the upper wafer UW and the lower wafer LW with such modified and hydrophilic bonding surfaces are used. The bonding apparatus 2 can also be combined with the pre-treatment apparatus to form a bonding system.

[0116] [2-1-3] Structure of Server 3 Figure 18 This is a block diagram illustrating an example of the structure of server 3 in the second embodiment. For example... Figure 18 As shown, server 3 includes, for example, a CPU 30, a ROM 31, a RAM 32, a storage device 33, and a communication device 34. The CPU 30 is a processor that executes various programs controlling server 3. The ROM 31 is a non-volatile storage device that stores the control programs for server 3. The RAM 32 is a volatile storage device used as the working area of ​​the CPU 30. The storage device 33 is a non-volatile storage medium capable of storing information received from the exposure device 1 or the bonding device 2, etc. The communication device 34 is a communication interface capable of connecting to a network NW.

[0117] [2-2] Manufacturing method of semiconductor device Hereinafter, as a method for manufacturing a semiconductor device according to the second embodiment, an example of a specific process using the bonding device 2 will be described. That is, the semiconductor device is manufactured using the bonding method (bonding process) of the second embodiment described below. Furthermore, in the following description, the alignment of the shift component is referred to as "shift alignment," and the alignment of the rotation component is referred to as "rotation alignment." That is, alignment correction (or simply "alignment") includes shift alignment and rotation alignment. In this specification, "shift alignment" and "rotation alignment" each include measuring at least one associated alignment mark AM and calculating an alignment correction value based on the measurement result of the alignment mark AM.

[0118] [2-2-1] Overview of the jointing process Figure 19 This is a schematic diagram showing an overview of the joining process of the joining device 2 according to the second embodiment. In the joining process, Figure 19 (1) to (8) represent the states of the joining unit 23 during the joining process, respectively. Hereinafter, refer to... Figure 19 The general process of the bonding treatment is explained.

[0119] Figure 19 (1) indicates the state of the joining unit 23 before the joining process.

[0120] If the control device 20 initiates the bonding process, it controls the stress device 241 based on a correction value for the common wafer magnification in both the X and Y directions. Figure 19 As shown in (2), the lower stage 230 is deformed.

[0121] Next, the control device 20 causes the conveyor 21 to convey the lower wafer LW to the lower stage 230 and the upper wafer UW to the upper stage 233. Then, as... Figure 19 As shown in (3), the control device 20 holds the lower wafer LW on the lower stage 230 and holds the upper wafer UW on the upper stage 233. In addition, the surfaces of the upper wafer UW and the lower wafer LW transported by the bonding device 2 are modified and hydrophilized by the pretreatment device for bonding.

[0122] Next, the control device 20 performs rotational alignment. Specifically, first, the control device 20, as... Figure 19As shown in (4), the positions of the lower stage 230 and the upper stage 233 are controlled. The optical axis of the camera 232 of the lower stage 230 is aligned with the alignment mark AM_L of the upper wafer UW, and the optical axis of the camera 235 of the upper stage 233 is aligned with the alignment mark AM_L of the lower wafer LW. Next, the control device 20 uses the camera 232 to measure the alignment mark AM_L of the upper wafer UW and uses the camera 235 to measure the alignment mark AM_L of the lower wafer LW.

[0123] Next, the control device 20, as Figure 19 As shown in (5), the positions of the lower stage 230 and the upper stage 233 are controlled. The optical axis of the camera 232 of the lower stage 230 is aligned with the alignment mark AM_R of the upper wafer UW, and the optical axis of the camera 235 of the upper stage 233 is aligned with the alignment mark AM_R of the lower wafer LW. Next, the control device 20 uses the camera 232 to measure the alignment mark AM_R of the upper wafer UW and uses the camera 235 to measure the alignment mark AM_R of the lower wafer LW. Then, the control device 20, based on the... Figure 19 The measurement results of the alignment marks AM_L and AM_R of cameras 232 and 235 obtained by processing (4) and (5) are used to calculate the correction amount of the coincidence deviation of the rotation component.

[0124] Next, the control device 20 performs camera origin alignment. Specifically, the control device 20, as follows: Figure 19 As shown in (6), the positions of the lower stage 230 and the upper stage 233 are controlled, and the common target 236 is inserted between the optical axis of the camera 232 of the lower stage 230 and the optical axis of the camera 235 of the upper stage 233. Then, the control device 20 aligns the origins of the cameras 232 and 235 based on the measurement results of the common target 236 of each of the cameras 232 and 235.

[0125] Next, the control device 20 performs the shift alignment. Specifically, first, the control device 20, as follows: Figure 19 As shown in (7), the positions of the lower stage 230 and the upper stage 233 are controlled. The optical axis of the camera 232 of the lower stage 230 is aligned with the position of the alignment mark AM_C on the upper wafer UW, and the optical axis of the camera 235 of the upper stage 233 is aligned with the position of the alignment mark AM_C on the lower wafer LW. Next, the control device 20 uses the camera 232 to measure the alignment mark AM_C on the upper wafer UW and uses the camera 235 to measure the alignment mark AM_C on the lower wafer LW. Then, based on the measurement results of the alignment marks AM_C on the lower wafer LW and the upper wafer UW respectively, the control device 20 calculates the correction value of the overlap deviation of the shift component.

[0126] Next, the control device 20, as Figure 19As shown in (8), the bonding process is performed. Specifically, firstly, the control device 20 performs horizontal alignment based on the correction values ​​calculated by rotational alignment and shift alignment, as well as the correction result of the camera origin, and adjusts the relative positions of the lower stage 230 and the upper stage 233. Furthermore, the control device 20 moves the position of the upper stage 233 closer to the lower stage 230, adjusting the gap between the upper wafer UW and the lower wafer LW. Then, the control device 20 lowers the pressing pin 244 to press down the center of the upper wafer UW, so that the surface of the upper wafer UW and the surface of the lower wafer LW come into contact.

[0127] Then, the control device 20 releases the holding of the upper wafer UW by the upper stage 233 sequentially from the inside to the outside. The upper wafer UW then falls onto the lower wafer LW, and the surfaces of the upper wafer UW and lower wafer LW bond. Specifically, van der Waals forces (intermolecular forces) are generated between the bonding surfaces of the modified upper wafer UW and the modified lower wafer LW, bonding the contact portions of the upper wafer UW and lower wafer LW. Furthermore, due to the hydrophilization of the bonding surfaces of the upper wafer UW and lower wafer LW, hydrogen bonds (intermolecular forces) are formed between the hydrophilic groups at the contact portions of the upper wafer UW and lower wafer LW, further strengthening the bond between the contact portions of the upper wafer UW and lower wafer LW.

[0128] [2-2-2] Methods for correcting wafer magnification Figure 20 This is a flowchart illustrating an example of a process related to wafer magnification correction in the bonding process of the bonding apparatus 2 according to the second embodiment. Hereinafter, refer to... Figure 20 The wafer ratio correction method of the second embodiment will be described.

[0129] First, the pre-processing steps for both the upper wafer (UW) and lower wafer (LW) are performed. Specifically, the exposure process for the upper wafer (UW) is performed (S210). Correction value information 111a, which includes the wafer magnification correction value used in the exposure process of S210, is saved to the server 3 (S211). Similarly, the exposure process for the lower wafer (LW) is performed (S220). Correction value information 111b, which includes the wafer magnification correction value used in the exposure process of S220, is saved to the server 3 (S221).

[0130] If the preprocessing steps for both the upper wafer (UW) and the lower wafer (LW) are completed (S230), the server 3 calculates the wafer ratio correction value during the bonding process based on the correction value information 111a and 111b stored in S211 and S221 respectively (S231). Specifically, in S231, the difference between the processed wafer ratio value (alignment correction value + overlap correction value) of the upper wafer (UW) and the processed wafer ratio value (alignment correction value + overlap correction value) of the lower wafer (LW) is calculated. The server 3 then feeds back the calculation result of S231 to the bonding apparatus 2. Furthermore, in this specification, the "alignment correction value" is a correction value for the overlap deviation calculated based on the measurement results of the alignment mark AM. The "overlap correction value" is, for example, a correction value calculated based on the exposure OL measurement results during high-level process control performed in large-scale batch processing.

[0131] Then, the bonding device 2 performs the bonding process using the wafer magnification correction value calculated in S231. That is, the bonding device 2 determines the wafer magnification correction value in the bonding process based on the alignment results of the exposure processes of the upper wafer UW and the lower wafer LW in the previous process. In other words, in the bonding process, the bonding device 2 controls the stress device 231 based on the difference in the alignment results of the exposure processes of the upper wafer UW and the lower wafer LW in the previous process, causing the lower stage 230 to deform ( Figure 19 (2)). Other actions and uses in the joint process. Figure 19 The actions described are the same.

[0132] Furthermore, the above description illustrates the case where server 3 is used to determine the wafer magnification correction value during the bonding process, but it is not limited to this. Exposure apparatus 1 or bonding apparatus 2 may also calculate the wafer magnification correction value during the bonding process. In this case, information regarding the wafer magnification correction value is exchanged between exposure apparatus 1 and bonding apparatus 2.

[0133] [2-3] Effects of the second embodiment If used Figure 3 As explained, the bonding device 2 sometimes has fewer measurement points for the alignment mark AM compared to the exposure device 1. Furthermore, the bonding device 2 sometimes lacks a unit for measuring the wafer magnification (i.e., the wafer size) during alignment measurements.

[0134] Therefore, for the semiconductor manufacturing system PS of the second embodiment, the exposure apparatus 1 feeds forward information about the wafer size (correction value information 111) obtained through alignment measurement to the bonding apparatus 2. Furthermore, the bonding apparatus 2 uses a correction value for the wafer magnification based on the correction value information 111 from the feedforward correction value in the bonding process. As a result, the bonding apparatus 2 of the second embodiment can suppress the generation of wafer magnification overlap deviations in the bonding process, thereby improving the yield of the semiconductor device.

[0135] [2-4] Variations of the second embodiment The size of a wafer held (e.g., by vacuum adsorption) on a stage, i.e., the wafer magnification, tends to vary depending on the film (film stress) on the wafer surface. That is, there is a correlation between wafer warpage and wafer magnification. Therefore, in a variation of the second embodiment, the warpage of the upper wafer UW and the lower wafer LW is measured in a preceding process, and a correction value for the wafer magnification during the bonding process is determined based on the warpage amount.

[0136] Figure 21 This is a flowchart illustrating an example of a step related to wafer magnification correction in the bonding process of the bonding apparatus 2 in a modified embodiment of the second embodiment. Hereinafter, refer to... Figure 21 The method for correcting the wafer magnification in the modified example of the second embodiment will be described.

[0137] First, the pre-processing steps for both the upper wafer (UW) and the lower wafer (LW) are performed. Specifically, the exposure process for the upper wafer (UW) is performed (S210). Then, the warpage of the upper wafer (UW) is measured (S240), and the measurement result of S240 is saved as wafer warpage information to the server 3 (S241). Similarly, the exposure process for the lower wafer (LW) is performed (S220). Then, the warpage of the lower wafer (LW) is measured (S250), and the measurement result of S250 is saved as wafer warpage information to the server 3 (S251). Furthermore, the timing for performing the processes S240 and S250 is preferably such that the film stress (i.e., the amount of wafer warpage) on the surface of the upper wafer (UW) and the lower wafer (LW) is at the same timing as before the bonding process is performed.

[0138] Next, if the preprocessing steps for both the upper wafer (UW) and the lower wafer (LW) are completed (S230), the server 3 calculates a correction value for the wafer ratio during the bonding process based on the wafer warpage information stored in S241 and S251 (S260). In S260, the server 3 uses a formula relating wafer warpage to wafer ratio in calculating the correction value. This formula can be calculated based on measurements of the warpage and wafer ratio of multiple wafers, or it can be calculated based on simulation results. Furthermore, the server 3 feeds the calculation results from S260 forward to the bonding apparatus 2.

[0139] Then, the bonding device 2 performs the bonding process using the wafer ratio correction value calculated in S261. That is, the bonding device 2 determines the wafer ratio correction value in the bonding process based on the warpage amounts of the upper wafer UW and the lower wafer LW in the previous process. More specifically, in the bonding process, the bonding device 2 controls the stress device 231 based on the difference in warpage amounts of the upper wafer UW and the lower wafer LW in the previous process, causing the lower stage 230 to deform ( Figure 19(2)). Other actions and uses in the joint process. Figure 19 The actions described are the same.

[0140] The semiconductor device manufacturing method described above for the modified example of the second embodiment is similar to that of the second embodiment, and can suppress the generation of overlap deviation in the bonding process, thereby improving the yield of the semiconductor device.

[0141] [3] Third embodiment The third embodiment relates to a semiconductor manufacturing system PS that corrects alignment miscalculations of shift components in the bonding process corresponding to the wafer ratios of the lower wafer (LW) and the upper wafer (UW). Hereinafter, details of the semiconductor manufacturing system PS according to the third embodiment will be described.

[0142] [3-1] Manufacturing method of semiconductor device Hereinafter, as a method for manufacturing a semiconductor device according to the third embodiment, an example of a specific process using a semiconductor manufacturing system PS will be described. That is, a semiconductor device is manufactured using the bonding method (bonding process) of the third embodiment described below.

[0143] [3-1-1] Modified manufacturing method Figure 22 This is a flowchart illustrating an example of a manufacturing method for correcting the overlap deviation used in the coupling device 2 of the third embodiment. Hereinafter, refer to... Figure 22 The method for manufacturing the correction formula for the overlap deviation of the third embodiment will be described.

[0144] First, prepare the upper wafer (UW) and lower wafer (LW) with their magnification changed in a specified process (S300). The magnification conditions are two or more, preferably prepared under as many conditions as possible. The specified process corresponds, for example, to the exposure processing of the wiring layers near the surfaces of the upper wafer (UW) and lower wafer (LW).

[0145] Next, the alignment marks AM of the upper wafer UW and the lower wafer LW are measured at multiple measurement points using the bonding device 2 (S301). The bonding device 2 utilizes wafer magnification correction using the stress device 231 during the measurement of the alignment marks AM. That is, the lower wafer LW is in a state with corrected wafer magnification during the measurement of the alignment marks AM. The alignment measurement results are then saved, for example, to the server 3.

[0146] Next, server 3 calculates the change in measurement coordinates for each measurement point based on the multiple wafer magnification settings prepared in S300 and the alignment measurement results in S301 (S302).

[0147] Next, server 3 establishes a correlation with the wafer magnification, and generates a relationship between the measurement coordinates and the change in measurement coordinates for both the upper wafer (UW) and the lower wafer (LW) (S303). This relationship (modified form) is calculated, for example, by approximating the calculation result of S302 using a function in an orthogonal coordinate system. The modified form for the lower wafer (LW) is correlated with the correction value of the magnification component used in the exposure process of the lower wafer (LW), representing the relationship between the measurement coordinates of the alignment mark AM of the lower wafer (LW) and the measurement error between these measurement coordinates and the center position of the lower wafer (LW). The modified form for the upper wafer (UW) is correlated with the correction value of the magnification component used in the exposure process of the upper wafer (UW), representing the relationship between the measurement coordinates of the alignment mark AM of the upper wafer (UW) and the measurement error between these measurement coordinates and the center position of the upper wafer (UW). The relationship between the measurement coordinates and the change in measurement coordinates for each wafer magnification of the upper wafer (UW) and the lower wafer (LW) can be saved to server 3 or transmitted to bonding device 2.

[0148] [3-1-2] Joining treatment Figure 23 This is a flowchart illustrating an example of the joining process of the joining device 2 in the third embodiment. Hereinafter, refer to... Figure 23 The process of the joining procedure of the joining device 2 in the third embodiment will be described.

[0149] If the pre-processing unit of the bonding process notifies the wafer that the pre-processing is complete, the bonding unit 2 begins the bonding process (start).

[0150] First, the bonding device 2 obtains correction value information 111 for both the upper wafer UW and the lower wafer LW (S310). The bonding device 2 can obtain the correction value information 111 from either the server 3 or the exposure device 1.

[0151] Next, the joining device 2 deforms the lower stage 230 based on the correction value information 111 (S311). The processing in S317 is the same as that described in the second embodiment. Figure 19 The treatment of (2) is the same.

[0152] Next, the bonding device 2 loads the upper wafer UW and the lower wafer LW (S312). The process of S312 is the same as that described in the second embodiment. Figure 19 The treatment of (3) is the same.

[0153] Next, the coupling device 2 performs rotational alignment (S313). The process of S313 is the same as that described in the second embodiment. Figure 19 The treatments for (4) and (5) are the same.

[0154] Next, the joining device 2 performs the origin alignment process for cameras 242 and 245 (S314). The process in S314 is the same as described in the second embodiment. Figure 19 The treatment of (6) is the same.

[0155] Next, the coupling device 2 performs a shift alignment (S315). The process of S315 is the same as that described in the second embodiment. Figure 19 The treatment of (7) is the same.

[0156] Next, the bonding device 2 corrects the shift alignment correction amount using the formula created in S303 (S316). Specifically, the control device 20 obtains the respective correction values ​​for the wafer ratio of the upper wafer UW and the wafer ratio of the lower wafer LW from the correction value information 111. Furthermore, the control device 20 calculates the miscalculation amount of the shift alignment measurement result of the upper wafer UW by substituting the measurement coordinates of the alignment mark AM_C of the upper wafer UW into the formula created in S303 corresponding to the wafer ratio of the upper wafer UW. Similarly, the control device 20 calculates the miscalculation amount of the shift alignment measurement result of the lower wafer LW by substituting the measurement coordinates of the alignment mark AM_C of the lower wafer LW into the formula created in S303 corresponding to the wafer ratio of the lower wafer LW. Then, the control device 20 considers the miscalculation amount of the measurement results of the shift alignment of the upper wafer UW and the lower wafer LW respectively, and calculates the correction amount of the shift alignment in the bonding process. Furthermore, "miscalculation amount of the measurement results of the shift alignment" refers to the deviation between the coordinates of the wafer center obtained from the measurement results of the shift alignment and the actual position of the wafer center. When the position of the wafer center is inferred from the measurement results of the alignment mark AM_C, the "miscalculation of the measurement results" may occur depending on the interval between the measured coordinates of the alignment mark AM_C and the position of the wafer center, and the size of the wafer magnification.

[0157] In other words, the control device 20 adjusts the relative positions of the first and second wafers based on the measurement results of the alignment mark AM_C of the lower wafer LW, the measurement results of the alignment mark AM_C of the upper wafer UW, the correction form associated with the lower wafer LW, and the correction form associated with the upper wafer UW. Specifically, the control device 10 can adjust the relative positions of the first and second wafers based on the measurement results of the alignment mark AM_C of the lower wafer LW plus the measurement error calculated using the correction form associated with the lower wafer LW, and the measurement results of the alignment mark AM_C of the upper wafer UW plus the measurement error calculated using the correction form associated with the upper wafer UW. Alternatively, the processes in S315 and S316 can be combined.

[0158] Next, the bonding device 2 bonds the upper wafer UW to the lower wafer LW (S317). The process in S317 is the same as that described in the second embodiment. Figure 19 The treatment of (8) is the same.

[0159] Next, the bonding device 2 unloads the bonding wafer BW (S318).

[0160] If the bonding wafer BW is unloaded, the bonding device 2 ends the bonding process (end).

[0161] Furthermore, in S316, if the wafer magnification value obtained from the correction value information 111 is inconsistent with the wafer magnification associated with the relationship generated in S303, the control device 20 can use a relationship generated with a closer wafer magnification. Additionally, when generating the correction value, the control device 20 can generate a relationship based on multiple relationships to predict the miscalculation amount of the wafer magnification and the measurement result of the shift alignment, and use this relationship in S316.

[0162] [3-1-3] Specific examples Figure 24 This is a schematic diagram illustrating an example of multiple wafers used in the fabrication of a correction scheme for the overlap deviation used by the bonding device 2 of the third embodiment. Figure 24 Examples of wafers W1 to W5 subjected to exposure processing with varying wafer magnification are shown. The wafer magnifications for wafers W1, W2, W3, W4, and W5 are set to -2ppm, -1ppm, 0ppm, +1ppm, and +2ppm, respectively. As illustrated, the size of multiple irradiations within the wafer plane changes with the wafer magnification. Since wafers W1 to W5 use the same mask to form their patterns, alignment marks AM are positioned at the same coordinates. However, due to the different wafer magnifications of wafers W1 to W5, the actual positions of the alignment marks AM on the wafers deviate from the corresponding wafer magnification. Specifically, the smaller the wafer magnification, the closer the alignment marks AM are to the center; the larger the wafer magnification, the closer the alignment marks AM are to the outer periphery.

[0163] Figure 25 This is a graph illustrating an example of the change in the miscalculation amount of the measurement results of the displacement alignment before and after the fabrication of the correction formula for the overlap deviation in the joining process of the joining device 2 of the third embodiment. Figure 25 This represents the relationship between the wafer X-coordinate and the displacement measurement error corresponding to the measurement results of wafers W1 to W5. Server 3 obtains the modified fabrication method described in [3-1-1]. Figure 25The measurement results are as shown in (A). The larger the wafer magnification, the steeper the slope of the miscalculation of the shift measurement before correction. Furthermore, in this example, server 3 calculates the correction form for the miscalculation of the shift alignment measurement results at wafer magnifications of -2ppm, -1ppm, 0ppm, +1ppm, and +2ppm, respectively. The results are as follows... Figure 25 As shown in (B), the slope of the corrected shift measurement miscalculation is smaller than that before the correction. That is, shift measurement miscalculation can be suppressed regardless of the wafer's X-coordinate position.

[0164] [3-2] Effects of the third embodiment During the shift alignment, the bonding device 2 calculates the shift amount within the wafer surface based on the measurement result of the alignment mark AM_C at one point. However, if the wafer magnification changes, the measurement result of the alignment mark AM_C obtained by the bonding device 2 may sometimes deviate from the coordinates of the alignment mark AM_C referenced by the exposure device 1 (measurement miscalculation). That is, the alignment measurement result may change due to wafer magnification fluctuations, resulting in an overlap deviation between the upper wafer UW and the lower wafer LW during the bonding process.

[0165] Therefore, in the third embodiment, the exposure apparatus 1 sends the processing results of the previous exposure apparatus 1 (including wafer magnification correction value information 111) to the bonding apparatus 2. Furthermore, the bonding apparatus 2 corrects for measurement miscalculations in the wafer magnification caused by the wafer magnification based on the wafer magnification processing results received from the exposure apparatus 1. That is, the bonding apparatus 2 in the third embodiment predicts and corrects the positional deviation of the measurement coordinates based on the wafer magnifications of the upper wafer UW and the lower wafer LW.

[0166] As a result, the bonding apparatus 2 of the third embodiment can mitigate the positional deviation from the device reference caused by the wafer magnification. Therefore, the semiconductor device manufacturing method of the third embodiment can suppress the generation of overlap deviation during the bonding process and improve the yield of the semiconductor device.

[0167] [3-3] Variations of the third embodiment In the third embodiment, a case of correcting measurement errors based on wafer magnification is illustrated, but it is not limited to this. The bonding apparatus 2 can also correct the wafer measurement error based on wafer warpage information. As explained in the second embodiment, the wafer warpage has a correlation with the wafer magnification. Therefore, the bonding apparatus 2 can estimate the correction amount of the wafer magnification based on the wafer warpage. Thus, by utilizing the wafer magnification based on the wafer warpage information of the upper wafer UW and the lower wafer LW respectively, the bonding apparatus 2 can use the relationship generated in S303 to correct the measurement error. In addition, relationships between the wafer warpage and the measurement error can be generated separately for the upper wafer UW and the lower wafer LW. Furthermore, the bonding apparatus 1 can also use both the wafer warpage and the correction value information 111 containing the wafer magnification when selecting the relationship to use. In the third embodiment, the generation of the relationship for the upper wafer UW, which is less prone to measurement errors, can also be omitted. In this case, both the process of forming the relational expression corresponding to the upper wafer UW and the process of correcting measurement miscalculations are omitted.

[0168] [4] Fourth embodiment The fourth embodiment relates to a specific example of a semiconductor device that can be applied to the manufacturing methods of the semiconductor devices described in the first to third embodiments. Hereinafter, a storage device 4, which is a NAND flash memory, will be described as a specific example of a semiconductor device.

[0169] [4-1] Structure [4-1-1] Structure of storage device 4 Figure 26 This is a block diagram illustrating an example of the structure of the storage device 4 according to the fourth embodiment. For example... Figure 26 As shown, the storage device 4 includes, for example, a memory interface (memory I / F) 40, a sequencer 41, a memory cell array 42, a driver module 43, a line decoder module 44, and a sense amplifier module 45.

[0170] Memory I / F 40 is a hardware interface that connects to an external memory controller. Memory I / F 40 performs communication conforming to the interface specifications between storage device 4 and the memory controller. Memory I / F 40, for example, supports the NAND interface specification.

[0171] The sequencer 41 is a control circuit that controls the overall operation of the storage device 4. Based on the commands received via the memory I / F 40, the sequencer 41 controls the drive module 43, the line decoder module 44, and the sense amplifier module 45 to perform read, write, and delete operations.

[0172] The memory cell array 42 is a storage circuit comprising a collection of multiple memory cells. The memory cell array 42 includes multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). Blocks BLK are used, for example, as units for data deletion. Furthermore, the memory cell array 42 includes multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. Each memory cell is identified based on the address of the identified word line WL and the address of the identified bit line BL.

[0173] The driver module 43 is a driver circuit that generates the voltages used in read, write, and delete operations. The driver module 43 is connected to the row decoder module 44 via multiple signal lines. The driver module 43 can change the voltage applied to each of the multiple signal lines based on the page address received via the memory I / F 40.

[0174] The row decoder module 44 is a decoder that decodes the row address received via the memory I / F 40. Based on the decoding result, the row decoder module 44 selects one block BLK. Furthermore, the row decoder module 44 transmits voltages applied to multiple signal lines to multiple wirings (word lines WL, etc.) located on the selected block BLK.

[0175] The sensing amplifier module 45 is a sensing circuit that senses the data read from the selected block BLK based on the voltage of the bit line BL during the read operation.

[0176] The sensing amplifier module 45 sends the read data to the memory controller via the memory I / F 40. Furthermore, during a write operation, the sensing amplifier module 45 can apply a voltage corresponding to the data written to the memory cell to each bit line BL.

[0177] [4-1-2] Circuit structure of memory cell array 42 Figure 27 This is a circuit diagram illustrating an example of the circuit structure of the memory cell array 42 of the memory device 4 in the fourth embodiment. Figure 27 This shows one block BLK out of the multiple block BLKs contained in the storage cell array 42. For example... Figure 27 As shown, block BLK includes, for example, string units SU0 to SU3.

[0178] Each string cell (SU) comprises multiple NAND strings (NS). Each NAND string (NS) is associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Different column addresses are assigned to each bit line BL0 to BLm. Each bit line BL is shared by NAND strings (NS) that are assigned the same column address across multiple blocks (BLK). Each NAND string (NS) includes, for example, memory cell transistors MT0 to MT7 and select transistors STD and STS.

[0179] Each memory cell transistor MT includes a control gate and a charge storage layer, storing data non-volatilely. Memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of memory cell transistors MT0 to MT7 are respectively connected to word lines WL0 to WL7. Word lines WL0 to WL7 are configured for each block BLK. A collection of multiple memory cell transistors MT connected to a common word line WL in the same string cell SU is, for example, called a "cell unit CU".

[0180] With each memory cell transistor MT storing 1 bit of data, the cell unit CU stores "1 page of data". The cell unit CU can have a storage capacity of more than two pages of data, corresponding to the number of bits of data stored in the memory cell transistor MT.

[0181] Selector transistors STD and STS are used to select the serial cell SU. The drain of selector transistor STD is connected to the associated bit line BL. The source of selector transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MT7. The gates of the selector transistors STD included in the serial cells SU0 to SU3 are connected to the select gate lines SGD0 to SGD3 respectively. The drain of selector transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selector transistor STS is connected to the source line SL. The gate of selector transistor STS is connected to the select gate line SGS. The source line SL is shared by multiple blocks BLK, for example.

[0182] [4-1-3] Structure of storage device 4 Hereinafter, an example of the construction of the memory device 4 according to the fourth embodiment will be described. In addition, in the fourth embodiment, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate used in the formation of the memory device 4.

[0183] Figure 28 This is a perspective view showing an example of the construction of the storage device 4 according to the fourth embodiment. For example... Figure 28 As shown, the storage device 4 includes a memory chip MC and a CMOS chip CC. The lower surface of the memory chip MC corresponds to the surface of the lower wafer LW. The upper surface of the CMOS chip CC corresponds to the surface of the upper wafer UW. The memory chip MC includes, for example, a storage region MR, lead-out regions HR1 and HR2, and a pad region PR1. The CMOS chip CC includes, for example, a sense amplifier region SR, a peripheral circuit region PER1, transmission regions XR1 and XR2, and a pad region PR2.

[0184] The memory region MR includes a memory cell array 42. Lead-out regions HR1 and HR2 include wiring used in the connection between the stacked wiring disposed on the memory chip MC and the row decoder module 44 disposed on the CMOS chip CC. Pad region PR1 includes pads for connecting the memory device 4 to the memory controller. Lead-out regions HR1 and HR2 sandwich the memory region MR in the X direction. Pad region PR1 is adjacent to the memory region MR and lead-out regions HR1 and HR2 in the Y direction.

[0185] The sensing amplifier area SR includes a sensing amplifier module 45. The peripheral circuit area PERI includes a sequencer 41, a driver module 43, etc. The transmission areas XR1 and XR2 include a line decoder module 44. The pad area PR2 includes a memory I / F 40.

[0186] The sense amplifier region SR and the peripheral circuit region PERI are arranged adjacent to each other in the Y direction and overlap with the memory region MR. The transmission regions XR1 and XR2 sandwich the sense amplifier region SR and the peripheral circuit region PERI in the X direction and overlap with the lead-out regions HR1 and HR2, respectively. The pad region PR2 overlaps with the pad region PR1 of the memory chip MC.

[0187] The memory chip MC has multiple bonding pads BP at the bottom of each of the memory region MR, lead-out regions HR1 and HR2, and pad region PR1. The bonding pads BP of the memory region MR are connected to the associated bit lines BL. The bonding pads BP of the lead-out regions HR are connected to the associated wiring (e.g., word lines WL) in the stacked wiring of the memory region MR. The bonding pads BP of the pad region PR1 are connected to pads (not shown) on the upper surface of the memory chip MC. The pads on the upper surface of the memory chip MC are used, for example, for the connection between the memory device 4 and the memory controller.

[0188] The CMOS chip CC has multiple bonding pads BP on the upper part of the sense amplifier region SR, the peripheral circuit region PERI, the transmission regions XR1 and XR2, and the pad region PR2. The bonding pads BP of the sense amplifier region SR overlap with the bonding pads BP of the memory region MR. The bonding pads BP of the transmission regions XR1 and XR2 overlap with the bonding pads BP of the lead-out regions HR1 and HR2, respectively. The bonding pads BP of the pad region PR1 overlap with the bonding pads BP of the pad region PR2.

[0189] The storage device 4 has a structure in which the lower surface of a memory chip MC and the upper surface of a CMOS chip CC are bonded. Two bonding pads BP, which are opposite each other between the memory chip MC and the CMOS chip CC, are electrically connected by bonding among a plurality of bonding pads BP disposed on the storage device 4. Thus, the circuitry within the memory chip MC and the circuitry within the CMOS chip CC are electrically connected via the bonding pads BP. The group of two bonding pads BP opposite each other between the memory chip MC and the CMOS chip CC can be either boundary-bounded or integrated.

[0190] (Planar layout of storage cell array 42) Figure 29 This is a top view showing an example of the planar layout of the storage cell array 42 of the storage device 4 in relation to the fourth embodiment. Figure 29 This shows a region in the storage area MR that includes one block BLK. For example... Figure 29 As shown, storage device 4 includes, for example, multiple slots (SLT), multiple slots (SHE), multiple storage cylinders (MP), multiple bit lines (BL), and multiple contacts (CV). In the storage region (MR), the planar layout described below is repeatedly configured in the Y direction.

[0191] Each slit SLT has, for example, a structure with embedded insulating components. Each slit SLT insulates the wiring adjacent to it (e.g., word lines WL0-WL7 and select gate lines SGD and SGS). Each slit SLT has a portion extending along the X direction, traversing the memory region MR and the lead-out regions HR1 and HR2 along the X direction. Multiple slit SLTs are arranged in the Y direction. The regions defined by the slit SLTs correspond to the block BLK.

[0192] Each slit SHE has, for example, a structure with embedded insulating components. Each slit SHE insulates the wiring (at least the gate line SGD) adjacent to that slit SLT. Each slit SHE has a portion extending along the X direction, traversing the memory region MR. Multiple slit SHEs are arranged in the Y direction. In this example, three slit SHEs are arranged between adjacent slit SLTs. The multiple regions divided by the slit SLTs and SHEs correspond to the string cells SU0 to SU3, respectively.

[0193] Each memory column (MP) functions as a NAND string (NS). Multiple memory columns (MPs) are arranged in an alternating pattern of 19 columns in the region between two adjacent slots (SLTs). Furthermore, counting from the top of the paper, the memory columns (MPs) in the 5th, 10th, and 15th columns each overlap with one slot (SHE).

[0194] Each bit line BL has a portion extending along the Y direction, traversing the area where multiple blocks BLK are located. Multiple bit lines BL are arranged in the X direction. Each bit line BL is configured such that each string cell SU overlaps with at least one memory column MP. In this example, two bit lines BL overlap with each memory column MP.

[0195] Each contact CV is positioned between one of the multiple bit lines BL that overlap with the memory cylinder MP and the memory cylinder MP. The contact CV electrically connects the memory cylinder MP and the bit line BL. The contact CV between the memory cylinder MP and the bit line BL that overlap with the slit SHE is omitted.

[0196] (Cross-sectional structure of memory cell array 42) Figure 30 This is a cross-sectional view showing an example of the cross-sectional structure of the storage cell array 42 of the storage device 4 in the fourth embodiment. Figure 30 A cross-section along the Y direction is shown within the storage region MR, including the storage column MP and the slot SLT. Additionally, Figure 30 In this context, the Z-direction refers to the bottom of the paper, but... Figure 30 In the instructions, the top edge of the paper is referred to as "the upper part," and the bottom edge as "the lower part." For example... Figure 30 As shown, the storage device 4 includes, for example, insulating layers 50-57, conductive layers 60-66, and contacts V1 and V2.

[0197] An insulating layer 50 is disposed, for example, at the bottom layer of a memory chip MC. A conductive layer 60 is disposed above the insulating layer 50. An insulating layer 51 is disposed above the conductive layer 60. Conductive layers 61 and insulating layers 52 are alternately disposed above the insulating layer 51. An insulating layer 53 is disposed above the top conductive layer 61. Conductive layers 62 and insulating layers 54 are alternately disposed above the insulating layer 53. An insulating layer 55 is disposed above the top conductive layer 62.

[0198] Conductor layers 63 and insulating layers 56 are alternately disposed above insulating layer 55. Insulating layer 57 is disposed above the uppermost conductive layer 63. Conductor layer 64 is disposed above insulating layer 57. Contact V1 is disposed above conductive layer 64. Conductor layer 65 is disposed above contact V1. Contact V2 is disposed above conductive layer 65. Conductor layer 66 is disposed above contact V2. Hereinafter, the wiring layers with conductive layers 64, 65 and 66 will be referred to as "M0", "M1" and "M2" respectively.

[0199] Conductor layers 60, 61, 62, and 63 are respectively formed, for example, as plates that expand along the XY plane. Conductor layer 64 is formed, for example, as a line extending in the Y direction.

[0200] Conductor layers 60, 61, and 63 are used as source line SL, select gate line SGS, and select gate line SGD, respectively. Multiple conductor layers 62, starting from conductor layer 60, are used sequentially as word lines WL0 to WL7. Conductor layer 64 is used as bit line BL. Contacts V1 and V2 are columnar. Conductor layers 64 and 65 are connected via contact V1. Conductor layers 65 and 66 are connected via contact V2. Conductor layer 65 is, for example, formed as a linear wiring extending in the X direction. Conductor layer 66 contacts the interface of the memory chip MC, serving as bonding pad BP. Conductor layer 66 contains, for example, copper.

[0201] The slit SLT has a plate-like portion extending along the XZ plane, dividing the insulating layers 51-56 and the conductive layers 61-63. Each memory pillar MP extends along the Z direction, penetrating the insulating layers 51-56 and the conductive layers 61-63. Each memory pillar MP includes, for example, a core component 70, a semiconductor layer 71, and a laminated film 72. The core component 70 is an insulator extending along the Z direction. The semiconductor layer 71 covers the core component 70. The lower portion of the semiconductor layer 71 contacts the conductive layer 60. The laminated film 72 covers the side surface of the semiconductor layer 71. A contact CV is provided on the semiconductor layer 71. The conductive layer 64 contacts the contact CV.

[0202] Additionally, in the illustrated area, a contact CV corresponding to one of the two memory pillars MP is shown. Memory pillars MP not connected to contact CV in this area are connected to contact CV in an area not shown. The portion of the memory pillar MP intersecting with the multiple conductive layers 61 functions as a select transistor STS. The portion of the memory pillar MP intersecting with the conductive layer 62 functions as a memory cell transistor MT. The portion of the memory pillar MP intersecting with the multiple conductive layers 63 functions as a select transistor STD.

[0203] (Cross-sectional structure of storage column MP) Figure 31 This is an example of the cross-sectional structure of the storage column MP of the storage device 4 in the fourth embodiment, along... Figure 30 A cross-sectional view of the XXXI-XXXI line. Figure 31 A cross-section is shown, including the storage pillar MP and the conductive layer 62, and parallel to the conductive layer 60. (See diagram.) Figure 31 As shown, the laminated membrane 72 includes, for example, a tunnel insulating membrane 73, an insulating membrane 74, and a block insulating membrane 75.

[0204] The core component 70 is disposed, for example, at the center of the memory column MP. A semiconductor layer 71 surrounds the sides of the core component 70. A tunnel insulating film 73 surrounds the sides of the semiconductor layer 71. An insulating film 74 surrounds the sides of the tunnel insulating film 73. A bulk insulating film 75 surrounds the sides of the insulating film 74. A conductive layer 62 surrounds the sides of the bulk insulating film 75. The semiconductor layer 71 serves as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors STD and STS. The tunnel insulating film 73 and the bulk insulating film 75 each contain, for example, silicon oxide. The insulating film 74 serves as the charge accumulation layer for the memory cell transistor MT and contains, for example, silicon nitride. Thus, each memory column MP functions as a NAND string NS.

[0205] (Cross-sectional view of storage device 4) Figure 32 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device 4 according to the fourth embodiment. Figure 32 A cross-section including the memory region (MR) and the sense amplifier region (SR) is shown, that is, a cross-section including the memory chip (MC) and the CMOS chip (CC). Figure 32 As shown, the storage device 4 includes a semiconductor substrate 80, conductive layers GC and 81-84, and contacts CS and C0-C3 in the sensing amplifier region SR.

[0206] The semiconductor substrate 80 is a substrate used in the formation of the CMOS chip CC. The semiconductor substrate 80 includes multiple well regions (not shown). A transistor TR is formed, for example, in each of the multiple well regions. The multiple well regions are separated, for example, by STI (Shallow Trench Isolation). A conductive layer GC is disposed on the semiconductor substrate 80 via a gate insulating film. The conductive layer GC within the sense amplifier region SR is used as the gate electrode of the transistor TR included in the sense amplifier module 45. A contact C0 is disposed on the conductive layer GC. Corresponding to the source and drain of the transistor TR, two contacts CS are disposed on the semiconductor substrate 80.

[0207] Conductive layers 81 are provided above contact CS and contact C0 respectively. Contact C1 is provided above conductive layer 81. Conductive layer 82 is provided above contact C1. Conductive layers 81 and 82 are electrically connected via contact C1. Contact C2 is provided above conductive layer 82. Conductive layer 83 is provided above contact C2. Conductive layers 82 and 83 are electrically connected via contact C2. Contact C3 is provided above conductive layer 83. Conductive layer 84 is provided above contact C3. Conductive layers 83 and 84 are electrically connected via contact C3. Hereinafter, the wiring layers with conductive layers 81 to 84 will be referred to as "D0", "D1", "D2", and "D3" respectively.

[0208] The conductive layer 84 contacts the interface of the CMOS chip CC and serves as a bonding pad BP. The conductive layer 84 in the sense amplifier region SR is bonded to the conductive layer 66 (i.e., the bonding pad BP of the memory chip MC) in the oppositely configured memory region MR. Furthermore, each conductive layer 84 in the sense amplifier region SR is electrically connected to a bit line BL. The conductive layer 84 contains, for example, copper.

[0209] In storage device 4, the wiring layer D3 of the CMOS chip CC and the wiring layer M2 of the memory chip MC are adjacent to each other by bonding with the memory chip MC and the CMOS chip CC. The semiconductor substrate 80 corresponds to the back side of the upper wafer UW, and the wiring layer D3 corresponds to the surface side of the upper wafer UW. The insulating layer 50 corresponds to the back side of the lower wafer LW, and the wiring layer M2 corresponds to the surface side of the lower wafer LW. The semiconductor substrate used in the formation of the memory chip MC is removed during processes such as the formation of bonding pads after the bonding process.

[0210] [4-2] Effects of the fourth embodiment As explained above, the storage device 4 includes, for example, a memory chip MC and a CMOS chip CC. The memory chip MC includes a structure in which memory cells are stacked in three dimensions, and the CMOS chip CC includes other control circuits, etc. In the memory chip MC and CMOS chip CC, the wafer ratio fluctuation tends to increase between wafers. Specifically, since the memory chip MC has a layered memory cell array 42, the wafer warpage fluctuation can increase, and the wafer ratio fluctuation can increase. On the other hand, the irradiation configuration of the CMOS chip CC is close to an ideal grid based on the exposure apparatus. Therefore, when performing the bonding process, it is preferable to assign the wafer on which the memory chip MC is formed to the lower wafer LW, which can correct the wafer ratio, and to assign the wafer on which the CMOS chip CC is formed to the upper wafer UW. Thus, the first to third embodiments can respectively improve the yield of the storage device 4.

[0211] Furthermore, for wiring layers near the bonding surface in the preceding processes of the memory chip MC, the range of overlap deviation in the process of wiring layer M1 is small. In wiring layer M1, for example, a conductive layer 65 extending in the X direction is formed. And, the contacts V2 connected to wiring layer M1 are formed in a manner that overlaps with the conductive layer 65. That is, the overlap in the formation process of contact V2 has a margin in the X direction, but no margin in the Y direction.

[0212] Therefore, in the exposure process used to form the contact V2 in this example, it is preferable to use the Y-priority mode. In this way, during the manufacture of the storage device 4, by using the exposure apparatus 1 of the first embodiment, the influence of the XY difference in wafer magnification can be suppressed, and the yield of the semiconductor device can be improved.

[0213] [5] Other In this embodiment, the flowchart used in the description of the actions is merely one example. The order of the processes described using the flowchart can be changed within a possible range, additional processes can be added, and some processes can be omitted. In the above embodiment, the case of applying alignment correction to the lower wafer LW mounted (held) on the lower stage 230 for bonding is illustrated, but it is not limited to this. Alignment correction in the bonding process can also be applied to the upper wafer UW mounted (held) on the upper stage 233, or to both the upper wafer UW held on the upper stage 233 and the lower wafer LW held on the lower stage 230. In this specification, an MPU (Micro Processing Unit), ASIC (Application Specific Integrated Circuit), or FPGA (Field-Programmable Gate Array) can be used instead of a CPU. Furthermore, the processes described in the embodiment can also be implemented by dedicated hardware. The processes described in the embodiment may include a mixture of software-executed processes and hardware-executed processes, or only one of them.

[0214] In this specification, "connection" refers to an electrical connection, excluding the possibility of other components being sandwiched in between. An "electrical connection" can also include an insulator, as long as it can operate in the same way as the electrically connected structure. "Columnar" refers to a structure disposed within a hole formed during the manufacturing process. "Top view" corresponds, for example, to viewing an object in a direction perpendicular to the surface of the semiconductor substrate 80. "Region" can be considered as a structure contained within the semiconductor substrate 80 of the CMOS chip CC. For example, when the semiconductor substrate 80 is defined as including a memory region MR, the memory region MR is associated with the region above the semiconductor substrate 80. The bonding pad BP can also be referred to as "bonding metal." The camera 144 of the exposure apparatus 1 can be separately configured as an optical system (microscope) and a light-receiving sensor. Cameras 144, 232, and 235 can each be referred to as "measuring devices" as long as they can measure the alignment mark AM. In this specification, "overlap deviation" can also be referred to as "position deviation."

[0215] The structures described in the fourth embodiment are merely illustrative, and the structure of the storage device 4 is not limited to these. The circuit structure, planar layout, and cross-sectional structure of the storage device 4 can be appropriately modified according to the design of the storage device 4. For example, in the fourth embodiment, a case is illustrated where a memory chip MC is disposed on top of a CMOS chip CC, but a CMOS chip CC can also be disposed on top of a memory chip MC. A case is illustrated where a memory chip MC is assigned to a lower wafer LW and a CMOS chip CC is assigned to an upper wafer UW, but a case is also illustrated where a memory chip MC is assigned to an upper wafer UW and a CMOS chip CC is assigned to a lower wafer LW. When applying the manufacturing method described in the first to third embodiments, it is preferable to assign wafers with large fluctuations in inter-wafer ratio to the lower wafer LW. This can suppress overlap deviations during the bonding process, thus suppressing the generation of defects caused by overlap deviations.

[0216] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: Based on the first information about the first substrate and the second information about the second substrate, a correction value for the positional deviation of the magnification component when the first substrate and the second substrate are bonded together is calculated. Based on the above correction value, the first unit is deformed, and the deformed first unit retains the first substrate. The second unit, which is opposite to the first unit, retains the second substrate. The first and second units are used to arrange the first substrate and the second substrate facing each other, so that the first substrate and the second substrate are bonded together.

2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein, The first information mentioned above is a correction value for the magnification component calculated based on the results of measuring at least three alignment marks on the first substrate during the exposure process of the first substrate. The second information mentioned above is a correction value for the magnification component calculated based on the results obtained from measuring at least three alignment marks on the second substrate during the exposure process of the second substrate.

3. The method for manufacturing a semiconductor device as claimed in claim 1, wherein, The first piece of information mentioned above is information indicating the amount of warpage of the first substrate; The second piece of information mentioned above is information indicating the amount of warpage of the second substrate.

4. A coupling device comprising: The first unit is capable of holding the first substrate; The second unit, which is opposite to the first unit, is able to hold the second substrate. The first measuring device measures the first alignment mark of the first substrate; The second measuring device measures the second alignment mark on the second substrate. as well as The control device performs the engagement process; In the bonding process, the control device adjusts the relative positions of the first and second units based on the measurement results of the first alignment mark, the measurement results of the second alignment mark, and the first modification form associated with the first substrate, and then bonds the first substrate to the second substrate.

5. The coupling device as claimed in claim 4, wherein, The first revision form mentioned above is associated with the correction value of the magnification component used in the exposure process of the first substrate, indicating the relationship between the measurement coordinates of the first alignment mark and the measurement error for the center position of the first substrate. The control device adjusts the relative positions of the first unit and the second unit based on the measurement result of the first alignment mark plus the measurement error calculated using the first revision.

6. The coupling device as claimed in claim 4, wherein, The first revision form mentioned above is associated with the warpage of the first substrate, indicating the relationship between the measurement coordinates of the first alignment mark and the measurement error for the center position of the first substrate. The control device adjusts the relative positions of the first unit and the second unit based on the measurement result of the first alignment mark plus the measurement error calculated using the first revision.

7. The coupling device according to any one of claims 4 to 6, wherein, In the bonding process, the control device adjusts the relative positions of the first and second units based on the second modification form associated with the second substrate.

8. The coupling device as claimed in claim 7, wherein, The aforementioned second revision is associated with the correction value of the magnification component used in the exposure process of the aforementioned second substrate, indicating the relationship between the measurement coordinates of the aforementioned second alignment mark and the measurement error for the center position of the aforementioned second substrate. The control device adjusts the relative positions of the first unit and the second unit based on the measurement results of the second alignment mark plus the measurement error calculated using the second revision.

9. The coupling device as claimed in claim 7, wherein, The aforementioned second revision is correlated with the warpage of the aforementioned second substrate, indicating the relationship between the measurement coordinates of the aforementioned second alignment mark and the measurement error for the center position of the aforementioned second substrate. The control device adjusts the relative positions of the first unit and the second unit based on the measurement results of the second alignment mark plus the measurement error calculated using the second revision.

10. A method for manufacturing a semiconductor device, comprising the steps of bonding a first substrate and a second substrate together, wherein the semiconductor device is formed by bonding a first substrate and a second substrate together. The first unit is kept in place with the aforementioned first substrate; The second unit, which is opposite to the first unit, retains the second substrate. Measure the first alignment mark of the first substrate mentioned above; Measure the second alignment mark of the second substrate mentioned above; Based on the measurement results of the first alignment mark, the measurement results of the second alignment mark, and the first revision form associated with the first substrate, the relative positions of the first stage and the second stage are adjusted, and the first substrate and the second substrate are then joined.

11. The method of manufacturing a semiconductor device as claimed in claim 10, wherein, The first revision form mentioned above is associated with the correction value of the magnification component used in the exposure process of the first substrate, indicating the relationship between the measurement coordinates of the first alignment mark and the measurement error for the center position of the first substrate. The adjustment of the relative positions of the first and second units mentioned above is based on the measurement results of the first alignment mark mentioned above plus the measurement error calculated using the first revision method mentioned above.

12. The method of manufacturing a semiconductor device as claimed in claim 10, wherein, The first revision form mentioned above is associated with the warpage of the first substrate, indicating the relationship between the measurement coordinates of the first alignment mark and the measurement error for the center position of the first substrate. In adjusting the relative positions of the first and second units, the value is obtained by adding the measurement result of the first alignment mark to the measurement error calculated using the first revision method.

13. The method for manufacturing a semiconductor device according to any one of claims 10 to 12, wherein, The adjustment of the relative positions of the first and second units mentioned above is based on the second revision form associated with the second substrate mentioned above.

14. The method of manufacturing a semiconductor device as claimed in claim 13, wherein, The aforementioned second revision is associated with the correction value of the magnification component used in the exposure process of the aforementioned second substrate, indicating the relationship between the measurement coordinates of the aforementioned second alignment mark and the measurement error for the center position of the aforementioned second substrate. In adjusting the relative positions of the first and second units, the value is obtained by adding the measurement result of the second alignment mark to the measurement error calculated using the second revision method.

15. The method of manufacturing a semiconductor device as claimed in claim 13, wherein, The aforementioned second revision is correlated with the warpage of the aforementioned second substrate, indicating the relationship between the measurement coordinates of the aforementioned second alignment mark and the measurement error for the center position of the aforementioned second substrate. In adjusting the relative positions of the first and second units, the value is obtained by adding the measurement result of the second alignment mark to the measurement error calculated using the second revision method.

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