A high-speed, high-linearity voltage-time converter circuit

Abstract

This invention proposes a high-speed, high-linearity voltage-to-time converter circuit, comprising a sampling switch, a sampling capacitor, a comparator, and a current source. Existing voltage-to-time converters charge or discharge the sampled capacitor using the current source. After charging or discharging to the threshold voltage across the comparator, the comparator output inverts, thus converting two different voltage signals into a time difference signal with the comparator output inverted. This invention, building upon this, performs sampling and charging separately on both sides of the capacitor and utilizes a non-overlapping clock to control sampling, charging, and reset, overcoming the influence of different initial voltages on the sampling capacitor on the charging current, further improving the linearity of the voltage-to-time domain conversion.

Description

Technical Field

[0001] This invention is a high-speed, high-linearity voltage-time converter circuit, belonging to the field of analog integrated circuit technology. Background Technology

[0002] Most signals in nature exist in analog form, such as sound, temperature, and pressure. To perceive these analog quantities more accurately, people need to use corresponding electronic devices for measurement. Analog-to-digital converters (ADCs), as the core of these electronic devices, can convert continuous analog signals into discrete digital signals. Therefore, various types of ADCs are being researched extensively. With the continuous reduction in CMOS process dimensions and chip power supplies, the design of traditional voltage-domain ADCs faces voltage challenges, particularly limiting the dynamic range of the input signal. This, in turn, affects the accuracy of signal conversion and the signal-to-noise ratio. Time-domain ADCs have proven to alleviate the limitations of power supply voltage under this trend, converting voltage-domain signals to the time domain for quantization. This achieves higher sampling rates and better energy efficiency, making them a research hotspot in next-generation wireless communication and other application fields.

[0003] Among them, the basic architecture of time-domain based ADC is as follows: Figure 1 As shown, it comprises two parts: a voltage-to-time converter (VTC) and a time-to-digital converter (TDC). The VTC acts as a sample-and-hold circuit, converting the analog input voltage into a time-domain signal; the TDC is responsible for further converting the time-domain signal into a digital signal. Although TDCs have improved in speed and energy efficiency due to technological advancements, most time-domain ADCs are limited in resolution due to factors such as VTC nonlinearity. Therefore, to avoid limiting the overall performance of the time-domain ADC, it is necessary to analyze the VTC performance and optimize its structure. Existing optimization schemes include... Figure 2 As shown in the diagram, the circuit includes a sampling capacitor, a switch, a charging current source, a voltage comparator, and an output buffer.

[0004] Sampling accuracy determines the upper limit of the overall architecture's resolution; therefore, CMOS sampling switches or bootstrap switches are often used to achieve the required high sampling accuracy. The charging current source is one of the key factors determining linearity. To reduce the impact of capacitor plate voltage changes on the charging current during charging, a cascode current source structure with two layers of PMOS stacked is often used, which has proven effective in practice. Therefore, this invention further improves the circuit structure based on existing solutions and adds timing optimizations to overcome the influence of the sampling voltage magnitude on the initial charging state and improve the effect of voltage changes on linear conversion during charging. This significantly improves the linearity and speed of the voltage-time converter. To further reduce power consumption, an inverter is used as a voltage comparator. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by proposing a high-speed, high-linearity voltage-to-time converter circuit. Through simple circuit improvements and timing optimizations, it completes the sampling, reset, charging, and voltage comparison processes more efficiently under different clock phases. While improving linearity and speed, it also reduces power consumption and hardware overhead to a certain extent, and can be widely used in time-domain based ADCs.

[0006] The technical solution to achieve the objective of this invention is:

[0007] A high-speed, high-linearity voltage-to-time converter circuit, characterized in that it comprises:

[0008] The voltage comparator uses an inverter structure with an enable signal to convert the voltage signal into a rising edge signal under the control of clock Φ3.

[0009] One end of the first switch Φ1 is connected to the input signal V. in (V) ip The other end is connected to the sampling capacitor C. S The upper plate of the first electrode is connected to the input terminal of the comparator COMP; one end of the second switch Φ2 is grounded, and the other end is connected to the auxiliary capacitor C. A The upper electrode plate; one end of the fourth switch Φ4 is grounded, and the other end is connected to the auxiliary capacitor C. A The upper electrode plate; one end of the fifth switch Φ5 is connected to a constant current source I. dc One end is connected to an auxiliary capacitor C. A Upper electrode plate; constant current source I dc The other end is connected to the power supply; auxiliary capacitor C A The upper plate is connected to the sampling capacitor C s The lower electrode plate is grounded;

[0010] The output of comparator COMP is connected to the input of buffer BUFFER; the output of buffer BUFFER will then provide the required rising edge signal.

[0011] A high-speed, high-linearity voltage-time converter circuit is described in the following brief description of its operation steps.

[0012] Sampling stage: Under the control of a non-overlapping clock, the input signal is sampled through the first switch Φ1 and onto the sampling capacitor C. S The upper electrode plate and the lower electrode plate are grounded through the second switch Φ2.

[0013] First reset phase: This phase occurs after sampling ends and before the comparator begins comparison, and the sampling capacitor C is reset. S The lower electrode and auxiliary capacitor C A The upper electrode plate is reset via the fourth switch Φ4.

[0014] Charging and Comparison Phase: The charging phase occurs after sampling. Under the control of timing Φ5, switch Φ5 is closed, and the sampling capacitor C is charged. S The lower electrode and auxiliary capacitor C A The upper plate is charged, causing the sampling capacitor C to... S The voltage on the upper plate increases as the voltage on the lower plate increases. The comparison phase occurs after the first reset phase ends, and the comparator COMP is activated under the control of the enable signal Φ3. When the voltage on the upper plate of the sampling capacitor exceeds the inversion threshold of the comparator, the comparator output inverts, and the required rising edge signal can be obtained after passing through the buffer.

[0015] The second reset phase: During the low-level phase of timing Φ3, the comparator output will be permanently reset to a low level "0". Attached Figure Description

[0016] Figure 1 A schematic diagram of the overall time-domain analog-to-digital converter.

[0017] Figure 2 This is a schematic diagram of an existing voltage-time conversion circuit.

[0018] Figure 3 This is a schematic diagram of the circuit structure of the present invention.

[0019] Figure 4 This is a schematic diagram of the comparator in the circuit of the present invention.

[0020] Figure 5 This is a timing diagram of the circuit of the present invention.

[0021] Figure 6 This is a schematic diagram of the linear operation of the present invention.

[0022] Figure 7 This is a schematic diagram of the equivalent capacitance of the circuit at node A in this invention. Detailed Implementation

[0023] To make the objectives and technical advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0024] like Figure 3The diagram shown illustrates the circuit structure of this invention, a high-speed, high-linearity voltage-to-time converter circuit. Taking its application in a time-domain ADC as an example, it is often used in pairs. The sampled voltage is in differential form, and its function is to convert the differential input voltage signal ΔV into a time difference signal Δt, which is then fed to the next-stage time-to-digital converter (TDC) circuit for quantization in the time domain. The voltage change process of the upper plate of the sampling capacitor is as follows... Figure 6 As shown. For a pair of differential input voltages V ip and V in , Figure 3 The circuit structures shown need to be used in pairs, and the circuit connections must be identical.

[0025] First, sampling is performed under the control of non-overlapping clocks Φ1 and Φ2. Ideally, the two sampling capacitors C... S The lower plates are ground voltage, and the upper plates are two differential input voltages V. ip and V in However, MOS transistors used as switches experience channel charge injection during turn-on and turn-off, causing a slight fluctuation in the voltage across the upper and lower plates of the sampling capacitor. Furthermore, the effect of channel charge injection varies depending on the magnitude of the sampled voltage, contributing to the nonlinearity in voltage-time conversion. To address this issue, this invention incorporates a first-stage reset after sampling, using clock Φ4 to reset the sampling capacitor C. S The voltage of the lower plate is grounded again, and the upper plate is forced to return to the sampling voltage V. ip and V in .

[0026] Secondly, under the control of clock Φ5, a constant current source I is used. dc The capacitor is charged. Considering the following practical problems, and to avoid the influence of the initial charging state on the charging process, this invention improves the existing circuit structure by modifying the sampling capacitor C. S The upper plate serves as the sampling plate, and the lower plate serves as the plate being charged. Before each effective charging begins, the lower plate is reset to a fixed ground voltage. This ensures that the voltage at the start of each charging cycle is ground voltage. Compared to traditional circuit structures, the initial charging voltage is always the differential voltage obtained from the sampling, which significantly improves the linearity of charging. Furthermore, considering the parasitic capacitance at each node connected to the upper plate of the sampling capacitor, and the fact that the capacitance value changes with the voltage across the upper plate, this can be equivalent to the sampling capacitor C. S And a parasitic capacitance C with a variable capacitance. p Series connection is one of the reasons for the nonlinearity in voltage-time conversion. To address this issue, this invention cleverly connects a fixed auxiliary capacitor C to the lower plate of the sampling capacitor.A This improves the overall linearity to some extent. The equivalent circuit of node A is as follows: Figure 7 As shown; considering that the charging current takes a certain amount of time to establish, this invention starts the current establishment while performing the first stage reset of the lower plate of the sampling capacitor. This does not affect the reset and also improves the overall speed of the voltage-time converter.

[0027] The first stage of reset is complete, and effective charging begins immediately, with sampling capacitor C. S Lower plate (auxiliary capacitor C) A The voltage at the upper plate (node ​​A) rises linearly from ground voltage. The voltage at the upper plate also rises linearly with the voltage at the lower plate by a certain coefficient. After time t, the voltage at the upper plate reaches the inversion threshold V of the comparator COMP (node ​​B). th The output of comparator COMP is inverted, i.e., "0" becomes "1".

[0028] Due to the sampling capacitor C S Initial voltage of the upper plate (V) ip V in If the values ​​are different, then the upper plate reaches the threshold V of the comparator COMP. th The timing is also different, so a pair of differential input voltages (ΔV=V) can be used. ip -V in This is converted into a pair of rising edge signals with a time difference (Δt = t1 - t2). It is important to note that the comparator threshold voltage must be selected to be greater than the sampling voltage to ensure that the comparator only reverses after a certain charging time. Figure 3 The circuit structure diagram shown is as follows: Figure 7 The equivalent diagram shown illustrates the following relationship between the voltage change at node A and the charging current:

[0029] (1)

[0030] Among them, I charge Let V be the charging current, t be the charging time, and ΔV. A This represents the magnitude of the voltage change at node A.

[0031] The relationship between the voltage changes at node A and node B is as follows:

[0032] (2)

[0033] Wherein, △V B This represents the magnitude of the voltage change at node B.

[0034] Considering that voltage-time converters are often used in pairs, we define that during the sampling phase, the voltage obtained from one of the samples is V. ipThe voltage obtained from another sampling is V in Therefore, during the charging process, the relationship between different sampling voltages and the charging time is as follows:

[0035] (3)

[0036] (4)

[0037] Where t1 is the sampled input voltage V in The time required for the capacitor to start charging and for the voltage to rise to the comparator COMP threshold voltage; t2 is the time required for the sampled input voltage V. ip The time required for the capacitor to rise from the start of charging to the comparator COMP threshold voltage; V TH This is the threshold voltage of the comparator COMP.

[0038] Therefore, the voltage difference (V) of the voltage-time converter ip -V in The relationship between t1 and the time difference (t1-t2) is as follows:

[0039] (5)

[0040] in, , is the proportionality coefficient, and also the theoretical value of linearity.

[0041] As can be seen from the above formula, compared with the existing technical solution (C) A =0), by adding a large fixed capacitor C at node A. A This can reduce the variable parasitic capacitance C during the voltage-to-time conversion process. p The effect on linearity k.

Claims

1. A high-speed, high-linearity voltage-to-time converter circuit, characterized in that, include: Sampling and charging core circuit, voltage comparator; The sampling charging core circuit has one end of the first switch Φ1 connected to the input signal V. in (V) ip The other end is connected to the sampling capacitor C. S The upper plate of the first electrode is connected to the input terminal of the comparator COMP; one end of the second switch Φ2 is grounded, and the other end is connected to the auxiliary capacitor C. A The upper electrode plate; one end of the fourth switch Φ4 is grounded, and the other end is connected to the auxiliary capacitor C. A The upper electrode plate; one end of the fifth switch Φ5 is connected to a constant current source I. dc One end is connected to an auxiliary capacitor C. A Upper electrode plate; constant current source I dc The other end is connected to the power supply; auxiliary capacitor C A The upper plate is connected to the sampling capacitor C s The lower electrode plate is grounded; The output of comparator COMP is connected to the input of buffer BUFFER; the output of buffer BUFFER will then provide the required rising edge signal.

2. The circuit according to claim 1, characterized in that, The voltage comparator circuit has its input terminal connected to one end of the first switch Φ1 and the sampling capacitor C. S The upper plate of the circuit is connected to the upper plate; the output is connected to the input of the buffer. The voltage comparator includes a PMOS transistor M. P1 M P2 M P3 NMOS transistor M N1 M N2 M N3 Among them, PMOS transistor M P1 The gate terminal is connected to the NMOS transistor M N1 The gate terminal is the input terminal IN of the voltage comparator, the source terminal is connected to the power supply, and the drain terminal is connected to the NMOS transistor M. N1 The drain terminal of the PMOS transistor M P2 The drain terminal of the PMOS transistor M P3 The gate terminal of the NMOS transistor M N3 The gate terminal of the NMOS transistor; N1 The source terminal is connected to the NMOS transistor M. N2 The drain terminal of the NMOS transistor M; N2 The gate terminal is connected to the PMOS transistor M P2 The gate terminal and clock control signal Φ3 are connected, and the source terminal is grounded; PMOS transistor M P2 The source terminal is connected to the power supply; PMOS transistor M P3 The source terminal is connected to the power supply, and the drain terminal is connected to the NMOS transistor M. N3 The drain terminal of the voltage comparator, the output terminal OUT; the NMOS transistor M N3 The source end is grounded.

Images