A memory management unit verification method, device, apparatus and storage medium
By dividing the execution logic of the MMU into application, control, and resource layers and communicating them through standardized interfaces, the problem caused by logical coupling in the MMU verification model is solved, and a more efficient and reliable verification process is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI SUIYUAN TECH CO LTD
- Filing Date
- 2026-05-06
- Publication Date
- 2026-06-02
AI Technical Summary
In existing technologies, the verification model of the Memory Management Unit (MMU) leads to an increase in the number of lines of verification code due to logical coupling, which affects readability, maintainability and reusability, and hinders verification efficiency and quality.
The execution logic of the MMU is divided into application layer module, control layer module and resource layer module, and they communicate through standardized interfaces to achieve logical decoupling, reduce the amount of verification code and improve maintainability and reusability.
This improves the maintainability and reusability of the MMU verification model, reduces development time, and ensures the accuracy and efficiency of the verification results.
Smart Images
Figure CN122132187A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for verifying a memory management unit. Background Technology
[0002] Currently, with the rapid development of fields such as artificial intelligence and high-performance computing, the design structure of the Memory Management Unit (MMU), as a core intellectual property module that ensures the correctness and efficiency of processor system memory, has become extremely complex.
[0003] When verifying the design structure of an MMU, existing technologies typically couple all the execution logic of the MMU into a large verification model, which leads to a sharp increase in the number of lines of verification code. This results in poor readability, maintainability, and reusability of the verification model, and any minor functional adjustment may cause unpredictable errors, greatly hindering the verification efficiency and quality of the MMU. Summary of the Invention
[0004] This invention provides a method, apparatus, device, and storage medium for verifying a memory management unit (MMU), which can improve the maintainability and reusability of the target MMU verification model, reduce the development time of the target MMU verification environment, and improve the verification efficiency of the target MMU while ensuring the accuracy of the verification results.
[0005] According to one aspect of the present invention, a method for verifying a memory management unit is provided, comprising: After detecting that a verification request has been triggered in the application layer module of the target MMU, the verification request is transmitted to the control layer module through the application layer module calling the standardized interface; The control layer module executes the control logic corresponding to the verification request and converts the execution result of the control logic into a call request for each functional interface in the standardized interface. The standardized interface routes each call request to the corresponding logic function in the resource layer module, and the resource layer module calls the standardized interface to feed back the execution results of each logic function to the control layer module. The control layer module generates the target verification result corresponding to the target MMU based on the execution results of each logic function, and calls the standardized interface to feed the target verification result back to the application layer module.
[0006] According to another aspect of the present invention, a memory management unit verification apparatus is provided, comprising: The request triggering module is used to transmit the verification request to the control layer module by calling a standardized interface through the application layer module after detecting that a verification request has been triggered in the application layer module of the target MMU. The control logic execution module is used to execute the control logic corresponding to the verification request through the control layer module, and convert the control logic execution result into a call request for each functional interface in the standardized interface; The function routing module is used to route each call request to the corresponding logical function in the resource layer module through a standardized interface, and to feed back the execution results of each logical function to the control layer module through the standardized interface called by the resource layer module. The verification result generation module is used to generate the target verification result corresponding to the target MMU through the control layer module based on the execution results of each logic function, and call the standardized interface to feed back the target verification result to the application layer module.
[0007] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the memory management unit verification method according to any embodiment of the present invention.
[0008] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the memory management unit verification method according to any embodiment of the present invention.
[0009] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the memory management unit verification method according to any embodiment of the present invention.
[0010] The technical solution provided by this invention, by detecting a verification request triggered in the application layer module of the target MMU, the application layer module calls a standardized interface to transmit the verification request to the control layer module, the control layer module executes the control logic corresponding to the verification request, converts the execution result of the control logic into a call request to each functional interface in the standardized interface, the standardized interface routes each call request to the corresponding logic function in the resource layer module, the resource layer module calls the standardized interface to feed back the execution result of each logic function to the control layer module, and the control layer module generates the target verification result corresponding to the target MMU based on the execution result of each logic function, and calls the standardized interface to feed back the target verification result to the application layer module, can achieve decoupling between the execution logic of the target MMU, improve the maintainability and reusability of the target MMU verification model, reduce the development time of the target MMU verification environment, and improve the verification efficiency of the target MMU while ensuring the accuracy of the verification result.
[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a flowchart of a memory management unit verification method provided according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating a scenario applicable to a memory management unit verification method provided in an embodiment of the present invention; Figure 3 This is a flowchart of another memory management unit verification method provided according to an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating a scenario applicable to another memory management unit verification method provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a memory management unit verification device according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device that implements the memory management unit verification method of this invention. Detailed Implementation
[0014] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0015] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0016] Figure 1 This is a flowchart illustrating a memory management unit (MMU) verification method according to an embodiment of the present invention. This embodiment is applicable to verifying the execution logic of the MMU. The method can be executed by a memory management unit verification device, which can be implemented in hardware and / or software and configured in an electronic device, such as... Figure 1 As shown, the method includes: Step 110: After detecting that a verification request has been triggered in the application layer module of the target MMU, the verification request is transmitted to the control layer module through the standardized interface called by the application layer module.
[0017] In this embodiment, to address the problem in existing technologies where coupling all the execution logic of the MMU into a single massive verification model leads to a dramatic increase in the number of lines of verification code, a verification method is proposed that manages the execution logic of the MMU under test (i.e., the target MMU) in a hierarchical manner. Specifically, the execution logic of the target MMU can be divided into application layer modules, control layer modules, and resource layer modules, thereby obtaining the verification model corresponding to the target MMU.
[0018] The application layer module receives verification requests corresponding to the target MMU and constructs a verification scenario based on the verification requests. The control layer module schedules specific verification tasks according to the verification requests and transmits status data related to the verification tasks. The resource layer module encapsulates the underlying physical resources corresponding to the target MMU, such as driver modules for read (RD) channels and write (WR) channels.
[0019] In this embodiment, the application layer module, control layer module, and resource layer module can communicate through a pre-built standardized interface. This standardized interface covers the core operations required for the target MMU verification process, such as querying resource status, triggering address comparison instructions, and triggering page fault exceptions.
[0020] The advantages of this setup are twofold: First, compared to existing technologies that couple all the execution logic of the target MMU into a single massive verification model, layered management of the target MMU's execution logic decouples the verification logic from the control logic, reducing the amount of verification code in the target MMU. Modifications to any layer module do not affect other layers, thereby improving the maintainability and verification efficiency of the target MMU verification model. Second, by constructing standardized interfaces for decoupling communication, each layer module can be transformed into a pluggable service module. That is, the control layer module can drive the resource layer module by calling the standardized interface, rather than directly manipulating its internal variables. As long as the interface specifications are met, the resource layer module or the control layer module can be replaced or upgraded individually, greatly improving the reusability of the target MMU verification model.
[0021] Specifically, Figure 2 This can be a schematic diagram illustrating a scenario applicable to the memory management unit verification method in this embodiment, such as... Figure 2 As shown, the verification engineer can trigger a verification request through the application layer module of the target MMU. After receiving the verification request, the application layer module can call the standardized interface to transmit the verification request to the control layer module.
[0022] Step 120: Execute the control logic corresponding to the verification request through the control layer module, and convert the execution result of the control logic into a call request for each functional interface in the standardized interface.
[0023] In this embodiment, the standardized interface can integrate multiple functional interfaces, such as a resource query interface and a reliability control interface. Optionally, such as... Figure 2 As shown, after receiving the verification request, the control layer module can schedule specific verification tasks according to the verification request, transform the status data related to the verification tasks, and generate call requests for each functional interface in the standardized interface based on the transformation results.
[0024] Step 130: Route each call request to the corresponding logic function in the resource layer module through the standardized interface, and feed back the execution results of each logic function to the control layer module through the standardized interface called by the resource layer module.
[0025] In this step, such as Figure 2 As shown, the standardized interface can route each call request to a specific logical function (such as a write operation function or a read operation function) in the resource layer module. The resource layer module can execute the logical function through its internally integrated driver unit. For example, it can transmit the drive signal corresponding to the logical function to the target MMU, obtain the execution result fed back by the target MMU for the drive signal, and then feed back the execution result to the control layer module through the standardized interface.
[0026] Step 140: The control layer module generates the target verification result corresponding to the target MMU based on the execution results of each logic function, and calls the standardized interface to feed back the target verification result to the application layer module.
[0027] In this step, optional, such as Figure 2 As shown, the control layer module can generate the target verification result corresponding to the target MMU based on the execution result of the logic function and the verification task corresponding to the target MMU, and call the standardized interface to feed back the target verification result to the application layer module.
[0028] The technical solution provided by this invention, by detecting a verification request triggered in the application layer module of the target MMU, the application layer module calls a standardized interface to transmit the verification request to the control layer module, the control layer module executes the control logic corresponding to the verification request, converts the execution result of the control logic into a call request to each functional interface in the standardized interface, the standardized interface routes each call request to the corresponding logic function in the resource layer module, the resource layer module calls the standardized interface to feed back the execution result of each logic function to the control layer module, and the control layer module generates the target verification result corresponding to the target MMU based on the execution result of each logic function, and calls the standardized interface to feed back the target verification result to the application layer module, can achieve decoupling between the execution logic of the target MMU, improve the maintainability and reusability of the target MMU verification model, reduce the development time of the target MMU verification environment, and improve the verification efficiency of the target MMU while ensuring the accuracy of the verification result.
[0029] Figure 3 A flowchart of another memory management unit verification method provided in an embodiment of the present invention is shown below. Figure 3 As shown, the method includes: Step 310: After detecting that a verification request has been triggered in the application layer module of the target MMU, the verification request is transmitted to the control layer module through the application layer module calling the standardized interface.
[0030] Specifically, Figure 4 This can be a schematic diagram illustrating a scenario applicable to the memory management unit verification method in this embodiment, such as... Figure 4 As shown, verification engineers can trigger verification requests through application layer modules, which can then initiate corresponding verification scenarios. These verification scenarios can describe the functions or boundary information of the target MMU to be verified (e.g., "verifying the page table traversal process when the Translation Lookaside Buffer (TLB) is missing"), but do not include the specific control logic or signal timing information of the target MMU.
[0031] In this step, such as Figure 4 As shown, the application layer module can call a standardized interface to transmit verification requests to the control layer module, thereby decoupling the verification logic from the control logic.
[0032] Step 320: Arbitrate the priority of the verification request through the control layer module, and determine the execution order of the verification request based on the arbitration result.
[0033] In this step, such as Figure 4 As shown, after receiving a verification request, the control layer module can arbitrate the priority of the verification request based on the current resource usage and multiple pending request types to determine the execution order of the verification request.
[0034] Step 330: The control layer module executes the control logic corresponding to the verification request according to the execution order and the state data of the target MMU verification model.
[0035] In this step, such as Figure 4 As shown, the control layer module can also transform the current state data based on the current state data of the target MMU verification model and the execution order of the verification request, and determine the atomic operations required to complete the verification request.
[0036] Step 340: The control layer module converts the execution result of the control logic into a call request for each functional interface in the standardized interface.
[0037] In this step, such as Figure 4As shown, the control layer module can convert the above atomic operations into calls to various functional interfaces in the standardized interface, such as calling the query interface query() to query resources, and calling the performance metric (reliability, availability, serviceability) control interface ras_control() to control reliability, availability, and serviceability.
[0038] Step 350: Using the routing component in the standardized interface, route each call request to the corresponding logical function in the resource layer module.
[0039] Step 360: If the logic function is a read operation function, the drive signal corresponding to the read data is generated through the read channel unit in the resource layer module, and the drive signal is transmitted to the target MMU; if the logic function is a write operation function, the drive signal corresponding to the write data is generated through the write channel unit in the resource layer module, and the drive signal is transmitted to the target MMU.
[0040] In this embodiment, taking the logical function as the read operation function or the write operation function as an example, such as... Figure 4 As shown, if the logic function is a read operation function, a read transaction timing signal conforming to the bus protocol is generated through the RD channel unit in the resource layer module, and this signal is transmitted to the target MMU; if the logic function is a write operation function, a write transaction timing signal conforming to the bus protocol is generated through the WR channel unit in the resource layer module, and this signal is transmitted to the target MMU.
[0041] Step 370: Obtain the response signal of the target MMU to the drive signal feedback through the resource layer module, and call the standardized interface to feed the response signal back to the control layer module.
[0042] In this step, such as Figure 4 As shown, after receiving the aforementioned drive signal, the target MMU can perform calculations and processing according to its internal execution logic, and feed back a response signal to the resource layer module through the physical interface. Optionally, the response signal may include an operation completion flag, an error signal, etc.
[0043] In this embodiment, calling the standardized interface to feed back the response signal to the control layer module includes: encapsulating the response signal into response data according to the preset interface data format through the resource layer module, and calling the standardized interface to feed back the response data to the control layer module.
[0044] Step 380: The control layer module generates the target verification result corresponding to the target MMU based on the response signal, and calls the standardized interface to feed back the target verification result to the application layer module.
[0045] In one specific embodiment, the control layer module can update the state data of the target MMU verification model based on the encapsulated response data, and generate the target verification result corresponding to the target MMU based on the response data. After calling the standardized interface to feed back the target verification result to the application layer module, the module further includes: comparing the target verification result with the preset standard result through the application layer module, and determining the coverage data of the target MMU under different verification metrics.
[0046] In this step, such as Figure 4 As shown, after receiving the response data, the control layer module can update the state of the target MMU verification model based on the response data (e.g., update the TLB content model, etc.). Simultaneously, the control layer module can also feed back the target verification result (e.g., verification successful, verification failed, verification exception, etc.) to the application layer module through a standardized interface.
[0047] The application layer module can compare the target verification results with the preset standard results, perform assertion checks on the verification code of the target MMU based on the target verification results, and determine the coverage data of the target MMU under different verification metrics based on the target verification results.
[0048] The technical solution provided by this invention, through the following steps, achieves decoupling between the execution logic of the target MMU: after detecting a verification request triggered in the application layer module of the target MMU, the application layer module calls a standardized interface to transmit the verification request to the control layer module; the control layer module arbitrates the priority of the verification request; and, based on the execution order and the state data of the target MMU verification model, executes the control logic corresponding to the verification request. The control logic execution result is then converted into a call request to each functional interface in the standardized interface. The routing component in the standardized interface routes each call request to the corresponding logic function in the resource layer module. The resource layer module obtains the response signal from the target MMU in response to the drive signal feedback, calls the standardized interface to feed the response signal back to the control layer module, and the control layer module generates the target verification result corresponding to the target MMU based on the response signal and calls the standardized interface to feed the target verification result back to the application layer module. This technical approach improves the maintainability and reusability of the target MMU verification model, reduces the development time of the target MMU verification environment, and enhances the verification efficiency of the target MMU while ensuring the accuracy of the verification results.
[0049] Based on the above implementation methods, in order to better explain the technical solution of this embodiment, taking the target MMU verification scenario "a TLB miss occurs during virtual address translation, requiring page table traversal" as an example, the memory management unit verification method may include the following steps: Step 1: The application layer module initializes the control layer module and the resource layer module, sets the state machine of the control layer module to the initial state, adds several preset entries to the TLB model of the resource layer module, and removes the entry corresponding to the target virtual address vaddr_test during this verification process to construct a TLB missing instance. Step 2: The application layer module calls the standardized interface start_translation() to transmit the verification request to the control layer module; after receiving the request, the arbitration logic submodule of the control layer module places it in the pending queue and at the same time switches the state machine from the "idle" state to the "TLB lookup" state. Step 3: When the state machine is in the "TLB lookup" state, it calls the query interface query_tlb() in the standardized interface. Step 4: The standardized interface routes the call request to the TLB query unit in the resource layer module. After receiving the call request, the TLB query unit searches for the target virtual address vaddr_test in the TLB model maintained internally. Since it was not found during initialization, the unit then returns a "missing" response signal and the associated page table base address information to the control layer module through the standardized interface. Step 5: The state machine of the control layer module jumps to the "page table traversal" state according to the "missing" response signal. It calculates the physical address of each level of page table entry based on the page table base address and virtual address, and sequentially calls the read_physical_mem() function interface in the standardized interface to initiate a memory read transaction to obtain the page table entry. Step 6: The physical memory read / write unit in the resource layer module converts the physical address paddr into a read transaction timing signal that conforms to the bus protocol, drives the signal to the storage interface of the target MMU, obtains the response signal of the target MMU, encapsulates the response signal into response data, and returns it to the control layer module through a standardized interface. Step 7: After collecting page table entries from all levels, the control layer module performs permission checks and address synthesis. The state machine transitions to the "Update TLB" state and calls the write_tlb(vaddr, paddr, attributes) function interface. The resource layer module's TLB writing unit performs this operation to update its internal model. The state machine then returns to the "Idle" state and returns the final physical address paddr_final of this address translation and a "successful" execution result to the application layer module through the standardized interface. Step 8: After receiving the final execution result, the application layer module compares the returned physical address paddr_final with the expected value and asserts that the two are consistent. At the same time, it collects the coverage data of the target MMU under functions such as "TLB missing handling" and "multi-level page table traversal".
[0050] The above implementation methods can reduce the amount of verification code for the target MMU and improve the verification efficiency of the target MMU.
[0051] Figure 5 This is a schematic diagram of the structure of a memory management unit verification device provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the device includes: a request triggering module 510, a control logic execution module 520, a function routing module 530, and a verification result generation module 540.
[0052] The request triggering module 510 is used to transmit the verification request to the control layer module by calling a standardized interface through the application layer module after detecting that a verification request has been triggered in the application layer module of the target MMU. The control logic execution module 520 is used to execute the control logic corresponding to the verification request through the control layer module, and convert the control logic execution result into a call request for each functional interface in the standardized interface; The function routing module 530 is used to route each call request to the corresponding logical function in the resource layer module through a standardized interface, and to feed back the execution results of each logical function to the control layer module through the standardized interface called by the resource layer module. The verification result generation module 540 is used to generate the target verification result corresponding to the target MMU through the control layer module based on the execution results of each logic function, and call the standardized interface to feed back the target verification result to the application layer module.
[0053] The technical solution provided by this invention, by detecting a verification request triggered in the application layer module of the target MMU, the application layer module calls a standardized interface to transmit the verification request to the control layer module, the control layer module executes the control logic corresponding to the verification request, converts the execution result of the control logic into a call request to each functional interface in the standardized interface, the standardized interface routes each call request to the corresponding logic function in the resource layer module, the resource layer module calls the standardized interface to feed back the execution result of each logic function to the control layer module, and the control layer module generates the target verification result corresponding to the target MMU based on the execution result of each logic function, and calls the standardized interface to feed back the target verification result to the application layer module, can achieve decoupling between the execution logic of the target MMU, improve the maintainability and reusability of the target MMU verification model, reduce the development time of the target MMU verification environment, and improve the verification efficiency of the target MMU while ensuring the accuracy of the verification result.
[0054] Based on the above embodiments, the control logic execution module 520 includes: The arbitration unit is used to arbitrate the priority of the verification request through the control layer module, and determine the execution order of the verification request according to the arbitration result; the control layer module executes the control logic corresponding to the verification request according to the execution order and the state data of the target MMU verification model.
[0055] Function routing module 530 includes: The routing component application unit is used to route each of the aforementioned call requests to the corresponding logical function in the resource layer module through the routing component in the standardized interface; The read / write processing unit is configured to, if the logic function is a read operation function, generate a drive signal corresponding to the read data through the read channel unit in the resource layer module and transmit the drive signal to the target MMU; if the logic function is a write operation function, generate a drive signal corresponding to the write data through the write channel unit in the resource layer module and transmit the drive signal to the target MMU. The response signal feedback unit is used to obtain the response signal of the target MMU in response to the drive signal feedback through the resource layer module, and call the standardized interface to feed the response signal back to the control layer module. The response signal encapsulation unit is used to encapsulate the response signal into response data according to a preset interface data format through the resource layer module, and call a standardized interface to feed the response data back to the control layer module.
[0056] The verification result generation module 540 includes: The state update unit is used to update the state data of the target MMU verification model according to the response data through the control layer module, and generate the target verification result corresponding to the target MMU according to the response data. The result comparison unit is used to compare the target verification result with the preset standard result through the application layer module, and determine the coverage data of the target MMU under different verification indicators.
[0057] The above-described apparatus can execute the methods provided in all the foregoing embodiments of the present invention, and has the corresponding functional modules and beneficial effects for executing the above methods. Technical details not described in detail in the embodiments of the present invention can be found in the methods provided in all the foregoing embodiments of the present invention.
[0058] Figure 6A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.
[0059] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) or a random access memory (RAM), communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the read-only memory 12 or loaded from the storage unit 18 into the random access memory 13. The random access memory 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, the read-only memory 12, and the random access memory 13 are interconnected via a bus 14. Input / output (I / O) interfaces are also connected to the bus 14.
[0060] Multiple components in electronic device 10 are connected to input / output interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of monitors, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0061] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processing (DSP) processors, and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the memory management unit verification method.
[0062] In some embodiments, the memory management unit verification method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via read-only memory 12 and / or communication unit 19. When the computer program is loaded into random access memory 13 and executed by processor 11, one or more steps of the memory management unit verification method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the memory management unit verification method by any other suitable means (e.g., by means of firmware).
[0063] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chips (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0064] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0065] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0066] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0067] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.
[0068] A computing system can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system. It addresses the shortcomings of traditional physical hosts and Virtual Private Servers (VPS) in terms of management difficulty and weak business scalability.
[0069] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.
[0070] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A method for verifying a memory management unit, characterized in that, The method includes: After detecting that a verification request has been triggered in the application layer module of the target memory management unit (MMU), the verification request is transmitted to the control layer module through the application layer module calling the standardized interface. The control layer module executes the control logic corresponding to the verification request and converts the execution result of the control logic into a call request for each functional interface in the standardized interface. The standardized interface routes each call request to the corresponding logic function in the resource layer module, and the resource layer module calls the standardized interface to feed back the execution results of each logic function to the control layer module. The control layer module generates the target verification result corresponding to the target MMU based on the execution results of each logic function, and calls the standardized interface to feed the target verification result back to the application layer module.
2. The method according to claim 1, characterized in that, The control logic corresponding to the verification request is executed through the control layer module, including: The control layer module arbitrates the priority of the verification request and determines the execution order of the verification request based on the arbitration result. The control layer module executes the control logic corresponding to the verification request based on the execution order and the state data of the target MMU verification model.
3. The method according to claim 1, characterized in that, Each call request is routed to the corresponding logical function in the resource layer module through a standardized interface, including: The routing component in the standardized interface routes each call request to the corresponding logical function in the resource layer module.
4. The method according to claim 1, characterized in that, The resource layer module calls standardized interfaces to feed back the execution results of each logical function to the control layer module, including: If the logic function is a read operation function, then the drive signal corresponding to the read data is generated by the read channel unit in the resource layer module, and the drive signal is transmitted to the target MMU; If the logic function is a write operation function, then the drive signal corresponding to the write data is generated by the write channel unit in the resource layer module, and the drive signal is transmitted to the target MMU; The resource layer module obtains the response signal of the target MMU in response to the drive signal, and calls the standardized interface to feed the response signal back to the control layer module.
5. The method according to claim 4, characterized in that, Calling the standardized interface to feed back the response signal to the control layer module includes: The resource layer module encapsulates the response signal into response data according to a preset interface data format, and calls a standardized interface to feed the response data back to the control layer module.
6. The method according to claim 5, characterized in that, The control layer module generates the target verification results corresponding to the target MMU based on the execution results of each logic function, including: The control layer module updates the state data of the target MMU verification model based on the response data, and generates the target verification result corresponding to the target MMU based on the response data.
7. The method according to claim 1, characterized in that, After calling the standardized interface to feed back the target verification result to the application layer module, the following is also included: The application layer module compares the target verification results with the preset standard results and determines the coverage data of the target MMU under different verification indicators.
8. A memory management unit verification device, characterized in that, The device includes: The request triggering module is used to transmit the verification request to the control layer module by calling a standardized interface through the application layer module after detecting that a verification request has been triggered in the application layer module of the target MMU. The control logic execution module is used to execute the control logic corresponding to the verification request through the control layer module, and convert the control logic execution result into a call request for each functional interface in the standardized interface; The function routing module is used to route each call request to the corresponding logical function in the resource layer module through a standardized interface, and to feed back the execution results of each logical function to the control layer module through the standardized interface called by the resource layer module. The verification result generation module is used to generate the target verification result corresponding to the target MMU through the control layer module based on the execution results of each logic function, and call the standardized interface to feed back the target verification result to the application layer module.
9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the memory management unit verification method according to any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the memory management unit verification method according to any one of claims 1-7.