Computing chip, debugging system and data transmission method

Abstract

The present disclosure relates to a computing chip, a debugging system and a data transmission method. The computing chip comprises: an on-chip communication network; N computing cores mounted to the on-chip communication network, N being an integer greater than 1; and N sets of FIFO modules mounted to the on-chip communication network, each set of FIFO modules in the N sets of FIFO modules corresponding to one computing core in the N computing cores, each set of FIFO modules comprising: a receiving FIFO module for writing data by a host and for reading data by the computing core corresponding to the receiving FIFO module; and a sending FIFO module for writing data by the computing core corresponding to the sending FIFO module and for reading data by the host. The present disclosure can meet the demand of debugging multi-core of the computing chip at a lower cost.

Description

Technical Field

[0001] This disclosure relates to the field of chip debugging technology, and in particular to a computing chip, a debugging system, and a data transmission method. Background Technology

[0002] AI chips are chips specifically designed for efficiently processing AI tasks (such as performing calculations on large language models, image recognition networks, and other AI models, including matrix operations and tensor operations); they are also known as AI accelerators. The internal architecture of AI chips is highly parallel and complex. During debugging, traditional embedded debugging methods (such as serial port printing "printf") are slow, interfere with timing, and result in a limited number of supported cores, making it difficult to meet debugging needs. Furthermore, AI chips have multiple computing cores. If each core supported a serial port, it would require a large number of pins in the AI ​​chip design, leading to complex wiring, high deployment and maintenance costs, and inconvenience in operation within data center servers. Therefore, traditional debugging methods are simply insufficient to meet the multi-core debugging requirements of AI chips.

[0003] Currently, to solve this problem, full-stack tracing and ring buffer logs are commonly used to replace serial port printing. However, this approach has drawbacks such as high cost and lack of device-interactive debugging capabilities. Summary of the Invention

[0004] This disclosure provides a computing chip, a debugging system, and a data transmission method to at least address the problem in the related art of how to meet the multi-core debugging needs of AI chips at a lower cost.

[0005] According to a first aspect of this disclosure, a computing chip is provided, comprising: an on-chip communication network; N computing cores, mounted on the on-chip communication network, where N is an integer greater than 1; and N sets of FIFO (First Input First Output) modules, mounted on the on-chip communication network, wherein each of the N sets of FIFO modules corresponds to one of the N computing cores, and each set of FIFO modules includes: a receive FIFO module for allowing a host to write data and for allowing the computing core corresponding to the receive FIFO module to read data; and a transmit FIFO module for allowing the computing core corresponding to the transmit FIFO module to write data and for allowing the host to read data.

[0006] Optionally, each group of FIFO modules occupies a set size of address space. The starting address of each group of FIFO modules in the address space is represented by the sum of the base address and the offset, wherein the base address is the starting address of the first group of FIFO modules, and the offset is related to the set size.

[0007] Optionally, both the receiving FIFO module and the transmitting FIFO module include: a data register for storing written data; a control register for storing the interrupt parameter threshold of the corresponding FIFO module, so as to generate an interrupt signal when the value of the interrupt parameter reaches the interrupt parameter threshold, wherein the interrupt parameter quantifies the state of the data stored in the data register, and the interrupt signal is used to notify the host or the corresponding computing core to read data from the data register; and a status register for storing the read / write pointer, empty / full state, interrupt state, and stored data amount of the corresponding FIFO module.

[0008] Optionally, the interruption parameters include at least one of the following parameters: the amount of stored data and the retention time of the stored data.

[0009] Optionally, the status register is also used to store the switch state of the corresponding FIFO module, which indicates whether the function of the corresponding FIFO module is turned on or off.

[0010] According to a second aspect of this disclosure, a debugging system is provided, comprising: a host computer; and a computing chip according to an embodiment of this disclosure.

[0011] Optionally, the host and the computing chip are connected via a high-speed serial bus interface.

[0012] According to a third aspect of this disclosure, a data transmission method is provided for a debugging system according to embodiments of this disclosure, comprising: writing first debugging data into a receive FIFO module corresponding to a target computing core of a computing chip of the debugging system via a host of the debugging system; reading the first debugging data from the receive FIFO module corresponding to the target computing core via the target computing core; writing second debugging data into a transmit FIFO module corresponding to the target computing core via the target computing core; and reading the second debugging data from the transmit FIFO module corresponding to the target computing core via the host.

[0013] Optionally, reading the first debug data from the receive FIFO module corresponding to the target computing core via the target computing core includes: obtaining the value of an interrupt parameter through the receive FIFO module corresponding to the target computing core, and sending an interrupt signal to the target computing core if the obtained interrupt parameter value exceeds the interrupt parameter threshold of the receive FIFO module; and reading the first debug data from the receive FIFO module corresponding to the target computing core via the target computing core in response to the received interrupt signal. Reading the second debug data from the transmit FIFO module corresponding to the target computing core via the host includes: obtaining the value of an interrupt parameter through the transmit FIFO module corresponding to the target computing core, and sending an interrupt signal to the host if the obtained interrupt parameter value exceeds the interrupt parameter threshold of the transmit FIFO module; and reading the second debug data from the transmit FIFO module corresponding to the target computing core via the host in response to the received interrupt signal.

[0014] Optionally, the data transmission method according to the embodiments of this disclosure further includes: configuring the interrupt parameter threshold of the receive FIFO module corresponding to the target computing core through the host; and configuring the interrupt parameter threshold of the transmit FIFO module corresponding to the target computing core through the target computing core.

[0015] The technical solutions provided by the embodiments of this disclosure bring at least the following beneficial effects.

[0016] According to the embodiments of the present disclosure, the computing chip, debugging system, and data transmission method reserve a set of FIFO modules for each computing core during the hardware design stage and attach them to the on-chip communication network of the computing chip. This enables the host to communicate in parallel with each computing core via the on-chip communication network and the FIFO modules. On the one hand, this solves the problem of timing interference during serial port printing. On the other hand, the FIFO modules are composed of registers on the computing chip, which can be mapped to the address space, allowing the host and computing cores to asynchronously write and read data to the corresponding address space. Therefore, data can be directly transmitted between the host and the computing core without relying on pins and corresponding external wiring, which is convenient for maintenance. Furthermore, since the chip area occupied by the registers is negligible and their number is virtually unlimited, it can support any number of computing cores, solving the problem of limited pin resources in multi-core chips. This meets the needs of debugging multiple computing cores of the computing chip and has high scalability.

[0017] Meanwhile, the embodiments of this disclosure also have the advantage of low cost. Specifically, in terms of hardware cost, the manufacturing cost of a computing chip is strongly correlated with its chip area. Although the end-to-end tracing scheme in related technologies eliminates the dependence on pins by arranging a high-speed tracing bus inside the computing chip to directly monitor the data packet stream of the internal bus, it increases hardware cost due to the need to arrange dedicated monitoring circuits and compression engines. The FIFO module used in this disclosure, as mentioned above, is composed of registers on the computing chip, and its chip area is negligible, thus significantly reducing hardware cost. In terms of labor cost, although the circular buffer log scheme in related technologies allocates a region in memory (RAM) for writing debug logs, which can be directly read by debugging tools in the background without affecting the execution speed of the computing core, and solves the timing interference problem of traditional serial port printing, this scheme requires the use of special APIs (Application Programming Interfaces), thus requiring modification of the original software flow to insert the corresponding APIs, which is highly invasive and leads to increased labor costs. This disclosure communicates with the host via an on-chip communication network, and can be adapted to the existing printf logic at the underlying interface, achieving seamless compatibility with third-party software and existing software. It is less invasive, so it is more friendly to the introduction, development and maintenance of operators in AI systems, and helps to save a lot of software engineering manpower costs.

[0018] Furthermore, the end-to-end tracing and ring buffer log schemes in related technologies are only used for observing data generated during debugging and do not have the ability to interact with the host for debugging. This disclosure, however, is based on the characteristics of FIFO modules being easy to maintain and low-cost, and can conveniently reserve both a receive FIFO module and a transmit FIFO module to realize data interaction and transmission with the host, thereby enabling interactive debugging with the host.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0021] Figure 1 This is a topology diagram illustrating a computing chip according to an exemplary embodiment of the present disclosure.

[0022] Figure 2 This is a schematic diagram illustrating the principle of an interruption mechanism according to an exemplary embodiment of the present disclosure.

[0023] Figure 3 This is a flowchart illustrating a data transmission method according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0025] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following examples do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0026] It should be noted that the phrase "at least one of several items" in this disclosure refers to three parallel cases: "any one of the several items", "a combination of any number of the several items", and "all of the several items". For example, "including at least one of A and B" includes the following three parallel cases: (1) including A; (2) including B; (3) including A and B. Another example is "performing at least one of step one and step two", which means the following three parallel cases: (1) performing step one; (2) performing step two; (3) performing both step one and step two.

[0027] It should be noted that the user information involved in this disclosure (including but not limited to user device information, user personal information, etc.) is all information authorized by the user or fully authorized by all parties.

[0028] Below, we will refer to Figures 1 to 3 A detailed description of a computing chip, a debugging system, and a data transmission method according to exemplary embodiments of the present disclosure.

[0029] Figure 1 This is a topology diagram illustrating a computing chip according to exemplary embodiments of the present disclosure. As an example, the computing chip according to exemplary embodiments of the present disclosure is, for example, but not limited to, an AI chip, and the computing chip may adopt, but is not limited to, a SoC (System on Chip) design, which integrates core components such as CPU, GPU, NPU, memory, bus, and interfaces onto a single chip to form a complete microcomputer system.

[0030] Reference Figure 1 The computing chip includes an on-chip communication network (e.g., including but not limited to Network-on-Chip, or NoC), which is a small communication network packaged inside a single computing chip for transmitting data between the various modules of the computing chip. The computing chip also includes N computing cores (not shown in the figure) and N sets of FIFO modules (e.g., including...) mounted to the on-chip communication network. Figure 1 The diagram shows FIFO module group 1, FIFO module group 2, ..., FIFO module group N. "Mounting" refers to the ability of various modules within the computing chip to access the on-chip communication network for data transmission between modules. Therefore, the data transmission speed of this computing core depends on the internal bus clock, which is typically much higher than the baud rate of UART (Universal Asynchronous Receiver / Transmitter) and supports burst read / write, greatly improving the throughput of debug data. It should be understood that different types of modules on the computing chip may have different mounting methods. For example, the computing core can access the on-chip communication network via the NoC interface, while FIFO modules can access the network via... Figure 1 The bus port shown connects to the on-chip communication network. The bus protocol used by the bus port is, for example, but not limited to, AXI (Advanced eXtensible Interface).

[0031] N is an integer greater than 1. Each of the N FIFO modules corresponds to one of the N computing cores. This computing core can perform operations such as control, configuration, status reading, and data reading / writing on its corresponding FIFO module. In other words, hardware logic (i.e., reserving multiple FIFO modules) can be reserved during the design phase of the computing chip, thus reserving one FIFO module for each computing core, and the computing cores to be debugged can be flexibly specified. The host communicates in parallel with each computing core of the computing chip through the FIFO modules. On the one hand, this solves the timing problem of interference from serial port printing. On the other hand, the FIFO modules are composed of registers on the computing chip, which can be mapped to the address space, allowing the host and computing cores to asynchronously write and read data to the corresponding address space. Therefore, data can be directly transmitted between the host and computing cores without relying on pins and corresponding external wiring, which is convenient for maintenance. Furthermore, since the chip area occupied by registers is negligible, their number is virtually unlimited, so any number of computing cores can be supported. This solves the problem of limited pin resources in multi-core chips, meets the needs of debugging multiple computing cores of the computing chip, and has high scalability. It should be understood that the host can be a relatively complete computer, which may include, for example, a CPU, memory, motherboard and chipset, storage devices such as hard drives, and may also include power supply, network card, heat dissipation and other structures. The computing chip is usually in the form of an expansion card or coprocessor, connected to the host via a bus such as PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard), and is uniformly managed and scheduled by the host, focusing on performing model calculations and returning the calculation results to the host.

[0032] The computing chip according to the exemplary embodiments of this disclosure also has a low-cost advantage. Specifically, in terms of hardware cost, the manufacturing cost of a computing chip is strongly correlated with its chip area. Although the end-to-end tracing scheme in related technologies eliminates the dependence on pins by arranging a high-speed tracing bus inside the computing chip to directly monitor the data packet stream of the internal bus, it increases hardware cost due to the need for dedicated monitoring circuitry and compression engines. The FIFO module used in this disclosure, as mentioned above, is composed of registers on the computing chip, and its chip area is negligible, thus significantly reducing hardware cost. In terms of labor cost, although the circular buffer log scheme in related technologies allocates a region in memory (RAM) for writing debug logs, which can be directly read by debugging tools in the background without affecting the execution speed of the computing core, and solves the timing interference problem of traditional serial port printing, this scheme requires the use of special APIs, thus requiring modification of the original software flow to insert the corresponding APIs, which is highly intrusive and leads to increased labor costs. This disclosure communicates with the host via an on-chip communication network, and can be adapted to the existing printf logic at the underlying interface, achieving seamless compatibility with third-party software and existing software. It is less invasive, so it is more friendly to the introduction, development and maintenance of operators in AI systems, and helps to save a lot of software engineering manpower costs.

[0033] Furthermore, regarding communication between the computing core and the host, the end-to-end tracing scheme and the ring buffer log scheme in related technologies are only used for observing data generated during debugging and do not have the ability to interactively debug with the host. This disclosure, based on the ease of maintenance and low cost of FIFO modules, conveniently designs each FIFO module group to include a receive FIFO module and a transmit FIFO module. The receive FIFO module is used for the host to write data and for the corresponding computing core to read data; the transmit FIFO module is used for the corresponding computing core to write data and for the host to read data. In other words, the receive FIFO module is used for the computing core to receive data sent from the host, and the transmit FIFO module is used for the computing core to send data to the host, realizing data interaction and transmission between the computing core and the host, thereby enabling interactive debugging with the host.

[0034] As an example, the receive FIFO module can be represented as RX FIFO, and the transmit FIFO module can be represented as TX FIFO. If each group of FIFO modules only includes these two types of FIFO modules, then a group of FIFO modules can be regarded as a pair of FIFO modules, and thus can be represented as a FIFO pair.

[0035] When performing data read and write operations, based on the address space mapping described earlier, both the data writing end (the host for the receive FIFO module and the computing core for the transmit FIFO module) and the reading end (the computing core for the receive FIFO module and the host for the transmit FIFO module) need to use the address of the corresponding FIFO module. This address represents the location of the corresponding FIFO module in the address space. Regarding the address representation method, the raw address can be used directly, or the raw address can be processed in some way.

[0036] For the latter, optionally, each group of FIFO modules occupies an address space of a set size. The starting address of each group of FIFO modules in the address space is represented by the sum of a base address and an offset. The base address is the starting address of the first group of FIFO modules, and the offset is related to the set size, for example, the difference between the set size and the group number of the current group of FIFO modules minus 1. By mapping the address of each group of FIFO modules in the address space to the form of base address + offset, it is not necessary to store the original address of each group of FIFO modules. This enables efficient representation of the FIFO module addresses corresponding to each computing core, thereby better supporting multi-core concurrent debugging of computing chips.

[0037] Figure 1 An exemplary address allocation is also shown. As an example, assume the base address is "Base", and the address space occupied by each FIFO module (i.e., the set size) is "0x40", where "0x40" is a hexadecimal number, equal to 64 in decimal. The specific registers in the FIFO module (such as, but not limited to, data registers, control registers, and status registers, which will be described below) are all located within this "0x40" address space. Based on this, the starting address for addressing the first group of FIFO modules is "Base", and the ending address is "Base+0x38". The reason it is 0x38 (equal to 56) instead of 0x3F (equal to 63) is because when performing read / write operations, the read / write address is related to the address bus. Current chip architectures typically have a 64-bit address bus, and the addressable space is 8-byte aligned. Therefore, for an address space of 64 bytes, if the starting address for a read / write operation is "Base", then the ending address is "Base+0x38". The starting address of the Nth FIFO module is “Base+(N-1)×0x40”, and the ending address is “Base+(N-1)×0x40+0x38”.

[0038] Regarding the specific structure of each FIFO module, optionally, both the receiving FIFO module and the transmitting FIFO module include: a data register for storing written data; a control register for storing the interrupt parameter threshold of the corresponding FIFO module, so as to generate an interrupt signal when the value of the interrupt parameter reaches the interrupt parameter threshold. The interrupt parameter quantifies the state of the data stored in the data register, and the interrupt signal is used to notify the host or the corresponding computing core to read data from the data register; and a status register for storing the read / write pointer, empty / full state, interrupt state, and stored data amount of the corresponding FIFO module.

[0039] The data register serves as the read / write window for data transmission, enabling the writing of debug data and the reading of debug instructions, thus achieving basic data read / write functions. Furthermore, a status register is configured to store information reflecting the FIFO module's operational status, ensuring the module's stability and efficiency. Specifically, the read / write pointer indicates the current read / write position within the FIFO module. The empty / full status indicates whether the FIFO module is currently full (Full) or empty (Empty). The interrupt status indicates whether an interrupt has been triggered. The stored data quantity, such as, but not limited to, the current count, displays the number of data items currently stored within the FIFO module.

[0040] Furthermore, the circular buffer log scheme in related technologies has a serious drawback: data overwrite leads to evidence loss. Because this scheme uses a circular overwrite log storage method, if the system crashes and does not immediately trigger a stop, or if the debugging tool's reading speed is not fast enough, the most critical error log may be quickly overwritten by subsequently generated invalid logs, resulting in the loss of critical data. The exemplary embodiments of this disclosure, by configuring a control memory for storing control-related data such as interrupt parameter thresholds and correspondingly storing the interrupt status in a status register, can utilize the interrupt mechanism to notify the reading end to read data. This eliminates the need for the reading end to poll for readings, simplifying the reading end's operation, while ensuring timely data reading and solving the problem of data loss (including but not limited to loss due to data overwrite). Simultaneously, compared to traditional serial port printing, the exemplary embodiments of this disclosure use an interrupt mechanism to transmit data, eliminating the need for frequent CPU polling or waiting for low-speed I / O (Input / Output). Data writing is similar to memory operations, having minimal impact on the timing and performance of the computing core, making it suitable for real-time debugging. As an example, the control register can also be used to clear interrupts, that is, to clear processed interrupt signals during the handshake process.

[0041] Optionally, the interrupt parameters include at least one of the following: the amount of stored data and the retention time of the stored data. Correspondingly, the interrupt parameter thresholds configured in the control register include at least one of a stored data amount threshold (which may be called a watermark) and a stored data retention time threshold (which may be called a timeout). The stored data amount directly reflects the quantity of stored data (e.g., including but not limited to data counting), and can trigger an interrupt signal from the perspective of data volume. The stored data retention time refers to the duration for which data is continuously stored in the data register after being written to it. It reflects the timeliness of the data and triggers an interrupt signal from the perspective of time, thus ensuring that even a small amount of debugging information can be transmitted in a timely manner. This helps to achieve real-time transmission of a large amount of debugging data during the debugging process, which is beneficial for achieving faster debugging speeds. By setting the watermark and / or the timeout, even if the data register of the FIFO module is not full, the data will still be sent out (that is, an interrupt signal will be generated and sent to notify the reading end to read the data), thus ensuring that the data is not overwritten.

[0042] Of course, interrupt parameters can also include other reasonable parameters. As an example, when interrupt parameters include two or more parameters, it can be configured to generate an interrupt signal when the value of any one of the interrupt parameters reaches the corresponding interrupt parameter threshold, or it can be configured to generate an interrupt signal when the values ​​of all interrupt parameters reach the corresponding interrupt parameter threshold, or other configurations can be made, that is, the AND / OR logic between the various interrupt parameters can be reasonably configured, and this disclosure does not limit this.

[0043] Figure 2 This is a schematic diagram illustrating the principle of an interruption mechanism according to an exemplary embodiment of the present disclosure.

[0044] Reference Figure 2 The interrupt mechanism according to the exemplary embodiments of this disclosure is divided into two directions: uplink (the computing core sends logs to the host) and downlink (the host sends instructions to the computing core). It should be understood that in... Figure 2 For ease of illustration, the FIFO modules are mapped to the computing cores in numerical order. This is merely illustrative and not a restriction on the mapping between FIFO modules and computing cores. In practice, other fixed orders can be used, or the mapping can be flexibly specified during debugging without prior establishment. Regardless of the method used to determine the mapping between FIFO modules and computing cores, once the mapping is established, it ensures that each computing core is configured with a dedicated FIFO module.

[0045] Specifically, the uplink debugging process (compute core → send FIFO module → host) is mainly used for the compute core to print debug logs or send back status information, and may include the following steps.

[0046] 1. Initialization: The computing core configures the control register of its corresponding transmit FIFO module, setting the waterline (e.g., data register half full) and timeout duration.

[0047] 2. Data writing: During the operation of the computing core, debugging information is written to the data register of the corresponding transmit FIFO module in a fast manner, similar to writing to memory.

[0048] 3. Interrupt Trigger: When the amount of data written reaches the threshold, or when the data retention time reaches the set timeout period, the FIFO module generates an interrupt signal, which can be called an uplink interrupt signal.

[0049] 4. Notify the host: The uplink interrupt signal is notified to the host via the PCIe bus through the MSI-X (Extended Message Signalled Interrupts) mechanism.

[0050] 5. Data Reading: After receiving the interrupt signal, the host reads the data from the corresponding transmit FIFO module via the PCIe bus, specifically the data in the data register.

[0051] 6. Clear interrupt: After the host finishes reading, it writes to the control register to clear the interrupt flag, thus completing one uplink transmission.

[0052] In this process, the core calculates the waterline and timeout duration for the corresponding transmit FIFO module and writes data to it. When the count of the transmit FIFO module reaches the waterline setting, an interrupt signal is triggered, notifying the host to read data from that transmit FIFO module. Upon receiving the interrupt signal, the host reads the data from the transmit FIFO module via PCIe and clears the interrupt.

[0053] The downlink debugging process (host → receive FIFO module → computing core) is mainly used by the host to issue debugging commands such as breakpoint setting, parameter modification, start and stop commands, and may include the following steps.

[0054] 1. Initialization: Configure the control register of the host to receive the FIFO module, and set the waterline and timeout duration.

[0055] 2. Data writing: The host writes debugging commands or data to the data register of the receiving FIFO module corresponding to the specified computing core of the computing chip via PCIe.

[0056] 3. Interrupt Trigger: When the data received in the receiving FIFO module reaches the threshold or a timeout occurs, the receiving FIFO module sends a local interrupt signal to the corresponding computing core, which may be called a downlink interrupt signal.

[0057] 4. Interrupt Response: The computing kernel responds to a downlink interrupt signal by pausing the current task or entering an interrupt service routine (ISR).

[0058] 5. Data Reading: The computing core reads instruction data from the FIFO module via the internal bus.

[0059] 6. Clear interrupt: After the computing core has finished reading, write to the control register to clear the interrupt and execute the corresponding debugging instructions.

[0060] In this process, the host sets the waterline and timeout duration for the receive FIFO module (this can be done uniformly for each computing core's receive FIFO module, or individually; this disclosure does not impose any restrictions), and writes data to the receive FIFO module corresponding to the specified computing core. When the count of the receive FIFO module reaches the waterline setting, an interrupt signal is triggered, notifying the corresponding computing core to read data from the receive FIFO module. Upon receiving the interrupt signal, the computing core reads the data from the receive FIFO module through its register and clears the interrupt. It should be understood that in other examples, the computing core can also set the waterline and timeout duration for its corresponding receive FIFO module, but the host still writes data to the receive FIFO module.

[0061] It should be understood that this disclosure also includes embodiments that do not employ an interrupt mechanism, but instead use methods such as, but not limited to, polling to read data from the FIFO module.

[0062] Optionally, the status register can also store the on / off state of the corresponding FIFO module, which indicates whether the function of the corresponding FIFO module is enabled or disabled. By storing the on / off state in the status register, the corresponding FIFO module can be enabled, that is, its function can be turned on or off, without having to keep it always enabled, which helps to reduce power consumption in non-debugging mode.

[0063] According to exemplary embodiments of the present disclosure, a debugging system may also be provided, the debugging system including a host and a computing chip according to exemplary embodiments of the present disclosure, thereby forming a high-efficiency computing chip debugging system based on a FIFO module.

[0064] As an example, the host computer can be a PC, tablet device, personal digital assistant, smartphone, or other device capable of executing the aforementioned set of instructions. Here, the host is not necessarily a single electronic device; it can be any collection of devices or circuits capable of executing the aforementioned instructions (or instruction sets) individually or in combination. The host can also be part of an integrated control system or system manager, or can be configured to interconnect with a portable electronic device locally or remotely (e.g., via wireless transmission) through an interface.

[0065] The host may include at least one memory and at least one processor, wherein the at least one memory stores a set of computer-executable instructions and the at least one processor is capable of executing the set of computer-executable instructions stored in the at least one memory.

[0066] In a host computer, the processor may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, the processor may also include analog processors, digital processors, microprocessors, multi-core processors, processor arrays, network processors, etc.

[0067] The processor can execute instructions or code stored in memory, which can also store data. Instructions and data can also be sent and received over a network via a network interface device, which can employ any known transport protocol.

[0068] Memory can be integrated with the processor; for example, RAM or flash memory can be housed within an integrated circuit microprocessor. Alternatively, memory can comprise a separate device, such as an external disk drive, storage array, or other storage device that can be used by any database system. Memory and processor can be operatively coupled, or can communicate with each other, for example, via I / O ports, network connections, etc., enabling the processor to read files stored in the memory.

[0069] In addition, the host may include a video display (such as an LCD) and a user interface (such as a keyboard, mouse, touch input device, etc.). All components of the host can be interconnected via a bus and / or network.

[0070] Optionally, the host and the computing chip are connected via a high-speed serial bus interface. Specifically, the FIFO module in the computing chip can be connected to the on-chip communication network via an internal bus (e.g., including but not limited to the AXI bus), and the host can be connected via a high-speed serial bus interface (e.g., including but not limited to the AXI bus). Figure 2The PCIe interface (shown) communicates with the computing chip, thereby accessing these FIFO modules. Because debugging is uniformly performed through a high-speed serial bus interface, remote debugging and maintenance of large-scale chips can be completed remotely in scenarios such as server rooms without the need for a dedicated physical debugger, solely through software drivers. This offers high maintainability and significantly improves debugging efficiency.

[0071] Figure 3 This is a flowchart illustrating a data transmission method according to an exemplary embodiment of the present disclosure, which can be executed by a debugging system according to an exemplary embodiment of the present disclosure.

[0072] Reference Figure 3 In step S301, the first debugging data is written into the receiving FIFO module corresponding to the target computing core of the debugging system's computing chip through the host of the debugging system.

[0073] The first set of debug data refers to the debug data that the host needs to send to the compute core, such as debug commands including but not limited to breakpoint setting, parameter modification, and start / stop instructions. The target compute core is the compute core that needs to be called during debugging, which can be determined according to the actual needs during the debugging process and is not a fixed compute core.

[0074] In step S302, the first debugging data is read from the receiving FIFO module corresponding to the target computing core through the target computing core.

[0075] Steps S301 and S302 are used to implement debug data transmission from the host to the computing core.

[0076] In step S303, the second debugging data is written into the transmission FIFO module corresponding to the target computing core through the target computing core.

[0077] The second type of debug data is the debug data that the computing core needs to send back to the host, such as debug logs and status information.

[0078] In step S304, the second debugging data is read from the transmission FIFO module corresponding to the target computing core through the host.

[0079] Steps S303 and S304 are used to implement debug data transmission from the computing core to the host.

[0080] Optionally, an interrupt mechanism can be used to transmit debug data. Specifically, step S302 includes: obtaining the value of the interrupt parameter through the receiving FIFO module corresponding to the target computing core, and sending an interrupt signal to the target computing core if the obtained interrupt parameter value exceeds the interrupt parameter threshold of the receiving FIFO module; and reading first debug data from the receiving FIFO module corresponding to the target computing core in response to the received interrupt signal. Step S304 includes: obtaining the value of the interrupt parameter through the transmitting FIFO module corresponding to the target computing core, and sending an interrupt signal to the host if the obtained interrupt parameter value exceeds the interrupt parameter threshold of the transmitting FIFO module; and reading second debug data from the transmitting FIFO module corresponding to the target computing core in response to the received interrupt signal.

[0081] Optionally, the data transmission method according to the embodiments of this disclosure further includes: configuring the interrupt parameter threshold of the receive FIFO module corresponding to the target computing core through the host; and configuring the interrupt parameter threshold of the transmit FIFO module corresponding to the target computing core through the target computing core.

[0082] For details on the above data transmission methods, please refer to the previous introduction on computing chips, which will not be repeated here.

[0083] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0084] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A computing chip, characterized in that, include: On-chip communication network; N computing cores are mounted on the on-chip communication network, where N is an integer greater than 1; and N groups of FIFO modules are mounted on the on-chip communication network. Each group of FIFO modules corresponds to one of the N computing cores. Each group of FIFO modules includes: A receiving FIFO module is used for the host to write data and for the computing core corresponding to the receiving FIFO module to read data. and The sending FIFO module is used to write data to the computing core corresponding to the sending FIFO module and to read data from the host.

2. The computing chip as described in claim 1, characterized in that, Each FIFO module group occupies a set size of address space. The starting address of each FIFO module group in the address space is represented by the sum of the base address and the offset. The base address is the starting address of the first FIFO module group, and the offset is related to the set size.

3. The computing chip as described in claim 1 or 2, characterized in that, Both the receiving FIFO module and the transmitting FIFO module include: Data registers are used to store written data; A control register stores interrupt parameter thresholds for the corresponding FIFO module. An interrupt signal is generated when the value of the interrupt parameter reaches the threshold. The interrupt parameter quantifies the state of the data stored in the data register. The interrupt signal notifies the host or the corresponding computing core to read data from the data register. The status register is used to store the read / write pointer, empty / full status, interrupt status, and amount of data stored for the corresponding FIFO module.

4. The computing chip as described in claim 3, characterized in that, The interruption parameters include at least one of the following parameters: the amount of stored data and the duration of data retention.

5. The computing chip as described in claim 3, characterized in that, The status register is also used to store the on / off state of the corresponding FIFO module, which indicates whether the function of the corresponding FIFO module is turned on or off.

6. A debugging system, characterized in that, include: Host; and The computing chip as described in any one of claims 1 to 5.

7. The debugging system as described in claim 6, characterized in that, The host and the computing chip are connected via a high-speed serial bus interface.

8. A data transmission method for the debugging system as described in claim 6 or 7, characterized in that, include: The first debugging data is written into the receiving FIFO module corresponding to the target computing core of the computing chip of the debugging system through the host of the debugging system. The first debugging data is read from the receiving FIFO module corresponding to the target computing core through the target computing core. The second debugging data is written into the transmission FIFO module corresponding to the target computing core through the target computing core; The host computer reads the second debugging data from the FIFO module corresponding to the target computing core.

9. The data transmission method as described in claim 8, characterized in that, The step of reading the first debugging data from the receiving FIFO module corresponding to the target computing core through the target computing core includes: The interrupt parameter value is obtained through the receiving FIFO module corresponding to the target computing core, and an interrupt signal is sent to the target computing core if the obtained interrupt parameter value exceeds the interrupt parameter threshold of the receiving FIFO module. In response to a received interrupt signal, the first debugging data is read from the receiving FIFO module corresponding to the target computing core through the target computing core. The step of reading the second debugging data from the transmission FIFO module corresponding to the target computing core through the host includes: The interrupt parameter value is obtained through the sending FIFO module corresponding to the target computing core, and an interrupt signal is sent to the host if the obtained interrupt parameter value exceeds the interrupt parameter threshold of the sending FIFO module. In response to a received interrupt signal, the host computer reads the second debugging data from the transmit FIFO module corresponding to the target computing core.

10. The data transmission method as described in claim 9, characterized in that, Also includes: Configure the interrupt parameter threshold of the receive FIFO module corresponding to the target computing core through the host; The interrupt parameter threshold of the sending FIFO module corresponding to the target computing core is configured through the target computing core.

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