A multi-core CPU simulation method
By using multi-core CPU and FPGA co-simulation, combined with load assessment and adaptive step size adjustment, the problems of accuracy and stability in traditional single-core CPU simulation are solved, and efficient and accurate power system simulation is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUHAN SENMU LEISHI TECH CO LTD
- Filing Date
- 2026-02-26
- Publication Date
- 2026-06-02
AI Technical Summary
Traditional single-core CPUs have limited computing power in large-scale power system simulations, resulting in excessively large simulation steps. This makes it impossible to accurately capture the rapid transient processes of the power system, leading to distorted simulation results and risks of accuracy loss and stability.
A multi-core CPU simulation method is adopted, combined with parallel computing of FPGA modules, and data transmission between modules is realized through PCIe 4.0 high-speed communication interface. A multi-dimensional comprehensive load assessment and transient predictive step size adaptive adjustment mechanism are adopted to dynamically balance the load and optimize the simulation step size.
It achieves multi-rate, high-precision simulation, can handle high-frequency and low-frequency dynamic processes of power systems, improves the stability and adaptability of simulation, and meets the diverse needs of complex power systems.
Smart Images
Figure CN122133333A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of multi-core CPU simulation technology, specifically a multi-core CPU simulation method. Background Technology
[0002] With the expansion of modern power systems, the integration of new energy sources into the grid, and the widespread adoption of power electronic equipment, these systems exhibit complex characteristics of high dimensionality, strong nonlinearity, and multi-timescale coupling. Their transient processes (fault impacts, oscillation suppression, etc.) involve rapid changes at the millisecond to microsecond level, placing stringent demands on the accuracy, real-time performance, and processing capabilities of simulations. In large-scale power system simulations, traditional single-core CPUs, due to limitations in computing power, are often forced to adopt larger simulation step sizes, which can lead to significant accuracy losses and stability risks. As a high-dimensional, strong nonlinear, and multi-timescale coupled dynamic system, the transient processes (such as fault impacts and oscillation suppression) of the power system often involve changes at the millisecond or even microsecond level. If the simulation step size is too large, it will be impossible to accurately capture the interaction between rapid electromagnetic transients and electromechanical transients, resulting in distorted simulation results that may mask the actual risks of resonance, instability, etc., that exist in the system. Summary of the Invention
[0003] To address the shortcomings of existing technologies, this invention provides a multi-core CPU simulation method that solves the problems mentioned in the background section.
[0004] To achieve the above objectives, the present invention provides the following technical solution: a multi-core CPU simulation method, comprising the following steps: S1: The host computer sends simulation parameters and mode instructions, the mode instructions including any one of pure CPU simulation, pure FPGA simulation and CPU-FPGA co-simulation; S2: The data processing module parses parameters and instructions, and allocates simulation tasks according to the mode instructions; S3: Parallel computation of each simulation loop unit of the multi-core CPU module, or high-frequency dynamic processing in combination with the FPGA module; S4: The data processing module synchronously receives simulation results, integrates them, and completes data allocation and feedback. S5: Repeat steps S3-S4 until the preset simulation time is completed.
[0005] Furthermore, in the pure CPU simulation mode, the synchronization control unit of the data processing module waits for all CPU simulation loop units to complete the current step size calculation before integrating and distributing the data. The CPU simulation loop unit needs to receive the latest data before starting the next round of calculation.
[0006] Furthermore, in the pure FPGA simulation mode, the FPGA module uploads simulation results periodically according to a specified cycle, and the data transmitted from the CPU to the FPGA is applied to the next round of calculation in real time.
[0007] Furthermore, in the CPU-FPGA co-simulation mode, the data processing module reads the CPU simulation results in real time, waits for the FPGA simulation results, integrates the data, and feeds it back to the CPU and FPGA modules respectively.
[0008] Furthermore, the multi-core CPU simulation method uses the PCIe 4.0 high-speed communication interface to realize data transmission between modules.
[0009] Furthermore, the multi-core CPU module in the multi-core CPU simulation method contains N independent simulation loop units, N≥2, and the tasks are split and allocated in parallel according to the system topology and computational load.
[0010] Furthermore, the multi-core CPU simulation method also includes a dynamic balancing step for multi-dimensional comprehensive load assessment, which quantifies the load status using the following formula: Overall load factor: ,in, , For core occupancy rate, As a percentage of the computational workload, Memory usage; Load balancing metrics:
[0011] in, Standard deviation, The mean; when When a preset threshold is set, migration priority is used as the basis for the subtask. Perform task reassignment to enable Preset threshold.
[0012] Furthermore, the preset threshold is 15%, and the weighting coefficient is set to default. Subtask migration priority is based on Sort by priority from smallest to largest, migrate low-priority subtasks first, and define high-load units as... Low-load unit is defined as .
[0013] Furthermore, the multi-core CPU simulation method also includes a transient predictive step-size adaptive adjustment step, which quantifies transient changes and step-size adjustment using the following formula: Transient change prediction rate:
[0014] in, , For the first Predicted rate of transient change at time step. For the first Time and the A key state variable at a certain time The difference, This is the initial step size; Step size adjustment factor:
[0015] in, This is the step size adjustment coefficient; This is an adjustment factor used to control the sensitivity of step size adjustment; it is an adjustable constant. For the set upper limit of the transient change rate threshold, when When this value is reached or exceeded, it indicates that the system is undergoing drastic transient changes, and the step size needs to be reduced. The lower limit of the set transient change rate threshold, when When the value is below this, it indicates that the system's transient changes are slow, and the step size needs to be increased; New Step And satisfy ; in, The new step size, after adjustment, is the simulation calculation time interval adjusted in real time according to the transient changes of the system. This constraint... Ensuring the step size is within a reasonable range can guarantee both simulation accuracy and computational efficiency.
[0016] Furthermore, the transient threshold is set to default. Adjust the sensitivity coefficient ,like Take if it exceeds the boundary range or As the final step size.
[0017] This invention provides a multi-core CPU simulation method, which has the following beneficial effects: 1. This multi-core CPU simulation method supports collaborative simulation between CPU and FPGA, realizing multi-rate, high-precision simulation. With its hardware parallelism and extremely high operating speed, FPGA can process high-frequency switching dynamics in nanosecond to microsecond ranges in real time, accurately simulating the fast switching behavior of power electronic converters. Meanwhile, CPU leverages its advantages in complex logic processing and large-scale numerical calculation to efficiently simulate large-scale power systems covering generators, transmission networks, and loads, and can easily handle millisecond to second-level power frequency electromechanical transient processes.
[0018] 2. This multi-core CPU simulation method, through a dynamic balancing mechanism based on multi-dimensional comprehensive load assessment, can achieve reasonable allocation and efficient utilization of multi-core resources, avoiding resource waste caused by uneven load. At the same time, with the help of a transient predictive step-size adaptive adjustment mechanism, it can accurately match the transient change characteristics of different subsystems of the power system, effectively balancing simulation accuracy and computational efficiency. Furthermore, combined with the multi-mode flexible adaptability and efficient data interaction design of pure CPU, pure FPGA, and CPU-FPGA joint, it significantly improves the stability, adaptability, and intelligence level of the simulation, and can better meet the diverse needs of complex power system simulation. Attached Figure Description
[0019] Figure 1 This is a pure CPU simulation diagram of a multi-core CPU simulation method according to the present invention; Figure 2 This is a pure FPGA simulation diagram of a multi-core CPU simulation method according to the present invention; Figure 3 This is a schematic diagram of CPU-FPGA co-simulation of a multi-core CPU simulation method according to the present invention. Detailed Implementation
[0020] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.
[0021] like Figures 1-3 As shown, the present invention provides a technical solution: a multi-core CPU simulation method, comprising the following steps: S1: The host computer sends simulation parameters and mode instructions, the mode instructions including any one of pure CPU simulation, pure FPGA simulation and CPU-FPGA co-simulation; S2: The data processing module parses parameters and instructions, and allocates simulation tasks according to the mode instructions; S3: Parallel computation of each simulation loop unit of the multi-core CPU module, or high-frequency dynamic processing in combination with the FPGA module; S4: The data processing module synchronously receives simulation results, integrates them, and completes data allocation and feedback. S5: Repeat steps S3-S4 until the preset simulation duration is completed; In pure CPU simulation mode, the synchronization control unit of the data processing module waits for all CPU simulation loop units to complete the current step size calculation before integrating and distributing the data. The CPU simulation loop unit needs to receive the latest data before starting the next round of calculation. In pure FPGA simulation mode, the FPGA module uploads simulation results at specified intervals, and the data transmitted from the CPU to the FPGA is applied to the next round of calculation in real time. In the CPU-FPGA co-simulation mode, the data processing module reads the CPU simulation results in real time, waits for the FPGA simulation results, integrates the data, and feeds them back to the CPU and FPGA modules respectively. The multi-core CPU simulation method uses the PCIe 4.0 high-speed communication interface to realize data transmission between modules; The multi-core CPU module in the multi-core CPU simulation method contains N independent simulation loop units, N≥2, and the tasks are split and allocated in parallel according to the system topology and computational load. Mode 1: Pure CPU emulation mode 1) The host computer sends simulation parameters (system model, accuracy requirements, initial step size) through the interaction module, and the task scheduling unit of the data processing module receives and parses them; 2) The task scheduling unit decomposes the system into N parallel subtasks based on the system model topology and the computational load of each subsystem, and allocates them to N simulation loop units of the multi-core CPU. 3) The simulation loop units of the multi-core CPU start calculation synchronously according to the initial step size, and solve the subsystem equations in parallel; 4) The synchronization control unit of the data processing module waits for all CPU simulation loop units to complete the current step size calculation and receives the simulation results from each unit; 5) The data distribution unit will integrate the simulation results and host computer instruction data and feed them back to the input end of each CPU simulation loop unit, or upload them to the host computer, according to the model requirements. 6) Repeat steps 3)-5) until the preset simulation duration is completed; Mode 2: Pure FPGA Simulation Mode 1) The host computer sends simulation parameters, and after the data processing module parses them, it transmits the high-frequency switching model parameters and simulation instructions to the FPGA module; 2) The FPGA module starts the simulation in a preset nanosecond step size, processes the dynamics of high-frequency switching in real time, and uploads the simulation results to the data processing module through the timed transmission unit at a specified period (≥100ns); 3) The data processing module receives the FPGA results, combines them with the host computer's instruction data, and distributes them to the FPGA module's input or uploads them to the host computer; 4) The FPGA module receives updated data in real time and applies it to the next round of calculation, repeating steps 2)-3) until the simulation ends; Mode 3: CPU-FPGA co-simulation mode 1) The host computer issues collaborative simulation parameters and clarifies the division of tasks: the multi-core CPU is responsible for the electromechanical transient processes of generators and transmission networks (milliseconds to seconds), and the FPGA is responsible for the high-frequency switching dynamics of the power electronic converter (nanoseconds to microseconds). 2) The task scheduling unit of the data processing module splits the electromechanical transient tasks into simulation loop units of the multi-core CPU and configures the high-frequency switching tasks to the FPGA module; 3) The multi-core CPU performs parallel calculations in each simulation loop unit and uploads the results to the data processing module in real time; the FPGA module performs calculations in nanosecond-level steps and uploads the results periodically. 4) The synchronous control unit of the data processing module waits for the FPGA results to be received and integrates the CPU results. The data distribution unit transmits the cross-feedback data to the CPU and FPGA respectively, and the remaining data is uploaded to the host computer. 5) After receiving the updated data, the CPU simulation loop unit starts the next round of calculation. The FPGA module applies the updated data in real time and repeats steps 3)-4) until the simulation ends. Based on the above description, this invention achieves multi-rate, high-precision simulation by supporting CPU and FPGA co-simulation. With its hardware parallelism and extremely high operating speed, the FPGA can process high-frequency switching dynamics in nanosecond to microsecond ranges in real time and accurately simulate the fast switching behavior of power electronic converters. Meanwhile, the CPU leverages its advantages in complex logic processing and large-scale numerical calculation to efficiently simulate large-scale power systems covering generators, transmission networks, and loads, and can easily handle millisecond to second-level power frequency electromechanical transient processes.
[0022] A multi-core CPU simulation method also includes a dynamic balancing step for multi-dimensional comprehensive load assessment, which quantifies the load status using the following formula: Overall load factor: used to quantify the first The load status of each CPU simulation loop unit is calculated by considering three dimensions: core utilization, computational load percentage, and memory utilization. The formula is as follows:
[0023] in, , For core occupancy rate, As a percentage of the computational workload, Memory usage; Load balancing metric: The multi-core load balancing status is quantified using the coefficient of variation of the comprehensive load coefficient, as shown in the following formula:
[0024] in, The standard deviation of the combined load factor for all CPU simulation loop units. This is the average of the combined load coefficients of all CPU simulation loop units. The smaller the value, the better the load balancing. when When a preset threshold is set, migration priority is used as the basis for the subtask. Perform task reassignment to enable Preset threshold Used to determine the first The first high-load unit The migration priority of each subtask, among which... For the first The first unit The computational complexity weights of each subtask The higher the complexity, the greater the weight. No. The sub-tasks start from the first The migration cost of migrating one unit to the target unit. This includes the proportion of time spent on data transmission and resource reallocation; The preset threshold is 15%, and the weighting coefficient is set to default. Subtask migration priority is based on Sort by priority from smallest to largest, migrate low-priority subtasks first, and define high-load units as... Low-load unit is defined as ; It also includes a transient predictive step-size adaptive adjustment step, which quantifies transient changes and step-size adjustment using the following formula: Transient change prediction rate: Predicting the rate of change based on the difference between the first three simulation steps. The transient change trend of the step is expressed by the following formula:
[0025] in, , For the first Predicted rate of transient change at time step. For the first Time and the A key state variable at a certain time The difference, This is the initial step size; Step size adjustment coefficient: The step size is dynamically adjusted based on the predicted rate of transient change, as shown in the following formula:
[0026] in, This is the step size adjustment coefficient; This is an adjustment factor used to control the sensitivity of step size adjustment; it is an adjustable constant. For the set upper limit of the transient change rate threshold, when When this value is reached or exceeded, it indicates that the system is undergoing drastic transient changes, and the step size needs to be reduced. The lower limit of the set transient change rate threshold, when When the value is below this, it indicates that the system's transient changes are slow, and the step size needs to be increased; New Step And satisfy ; in, The new step size, after adjustment, is the simulation calculation time interval adjusted in real time according to the transient changes of the system. This constraint... To ensure that the step size is within a reasonable range, both simulation accuracy and computational efficiency can be guaranteed; Transient threshold (default) Adjust the sensitivity coefficient ,like Take if it exceeds the boundary range or As the final step size; Based on the above description, the specific execution steps are as follows: 1) The load-step intelligent adjustment unit monitors the computing resource utilization rate (i.e., core utilization rate) of each CPU simulation cycle unit in real time, with a monitoring cycle of 3 simulation steps. Queue length is the percentage of computational load. Memory usage Calculate the load strength of each unit. and overall load variation coefficient ; 2) Load balancing control: If The preset threshold is 15%, initiating the load redistribution process: Identify high-load units With low-load units ; Calculate the execution priority of each subtask in the high-load unit. ,according to Sort the subtasks from smallest to largest and migrate them to the lowest load units in turn; Recalculate after migration and until Preset threshold: 15%; 3) Transient prediction and step size adjustment: The load-step size intelligent adjustment unit calculates the changes in state variables of each subsystem. Substitute the values into the prediction model to obtain the rate of state change. ; according to With setting threshold , Relationship calculation step size adjustment coefficient Get a new step size ; like Exceeding The range is determined by taking the boundary value as the final step size. 4) Issuance of adjustment instructions: The load redistribution results and new step size instructions are issued to the corresponding simulation loop unit in real time through data processing loop to ensure that the adjustment takes effect in real time; 5) Repeat steps 1)-4) to achieve dynamic and predictive optimization of load and step size.
[0027] In this example, the simulation object is a complex power system with 2000 nodes (including 5 highly complex new energy subsystems and 15 conventional subsystems), and the following mechanism is enabled: The host computer sends the following parameters: initial step size 5 The load balancing threshold is 15%, and the transient threshold is... Adjust the sensitivity coefficient Weighting coefficient ; The task scheduling unit decomposes the system into 8 sub-tasks, which are then assigned to 8 CPU simulation loop units, with 2 units assigned to the high-complexity new energy subsystem. ), 6 units are allocated to conventional subsystems ( ); After the third simulation step is completed, start load monitoring: Data collected from each unit: High-load unit A High-load unit B ; Low-load unit CF , , ; Calculate the overall load factor:
[0028]
[0029] low load unit mean Standard deviation Load balancing This is determined to be a load imbalance; Load redistribution: Identify high-load units (A, B) and low-load units (C, D), and calculate the migration priority of the two subtasks in unit A: Subtask A1: , ,
[0030] Subtask A2: , ,
[0031] according to From smallest to largest, prioritize migrating subtask A2 to unit C; recalculate after migration:
[0032]
[0033] overall It still does not meet the standard; Continue migrating subtask B2 in Unit B ( ) to unit D, finally Load balancing is complete; Transient prediction and step size adjustment: After the 5th simulation step, calculate the difference in the new energy subsystem X: , , Substituting into the formula, we get ; Calculate the step size adjustment coefficient New Step , in Within the specified range, execute the step size; The difference in the conventional subsystem Y: , , , ; Calculate the step size adjustment coefficient New Step Execute the step size; Based on the above description, this invention, through a dynamic balancing mechanism of multi-dimensional comprehensive load assessment, can achieve reasonable allocation and efficient utilization of multi-core resources, avoiding resource waste caused by uneven load. At the same time, with the help of a transient predictive step-size adaptive adjustment mechanism, it can accurately match the transient change characteristics of different subsystems of the power system, effectively balancing simulation accuracy and computational efficiency. Furthermore, combined with the multi-mode flexible adaptability and efficient data interaction design of pure CPU, pure FPGA, and CPU-FPGA joint, it significantly improves the stability, adaptability, and intelligence level of the simulation, and can better meet the diverse needs of complex power system simulation.
[0034] The embodiments of the present invention are given for illustrative and descriptive purposes only, and are not intended to be exhaustive or to limit the invention to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to better illustrate the principles and practical application of the invention, and to enable those skilled in the art to understand the invention and to design various embodiments with various modifications suitable for a particular purpose.
Claims
1. A multi-core CPU simulation method, characterized in that: Includes the following steps: S1: The host computer sends simulation parameters and mode instructions, the mode instructions including any one of pure CPU simulation, pure FPGA simulation and CPU-FPGA co-simulation; S2: The data processing module parses parameters and instructions, and allocates simulation tasks according to the mode instructions; S3: Parallel computation of each simulation loop unit of the multi-core CPU module, or high-frequency dynamic processing in combination with the FPGA module; S4: The data processing module synchronously receives simulation results, integrates them, and completes data allocation and feedback. S5: Repeat steps S3-S4 until the preset simulation time is completed.
2. The multi-core CPU simulation method according to claim 1, characterized in that: In the pure CPU simulation mode, the synchronization control unit of the data processing module waits for all CPU simulation loop units to complete the current step size calculation before integrating and distributing the data. The CPU simulation loop unit needs to receive the latest data before starting the next round of calculation.
3. The multi-core CPU simulation method according to claim 1, characterized in that: In the pure FPGA simulation mode, the FPGA module uploads simulation results periodically according to a specified cycle, and the data transmitted from the CPU to the FPGA is applied to the next round of calculation in real time.
4. The multi-core CPU simulation method according to claim 1, characterized in that: In the CPU-FPGA co-simulation mode, the data processing module reads the CPU simulation results in real time, waits for the FPGA simulation results, integrates the data, and feeds them back to the CPU and FPGA modules respectively.
5. The multi-core CPU simulation method according to claim 1, characterized in that: The multi-core CPU simulation method uses the PCIe 4.0 high-speed communication interface to realize data transmission between modules.
6. The multi-core CPU simulation method according to claim 1, characterized in that: The multi-core CPU module in the multi-core CPU simulation method contains N independent simulation loop units, N≥2, and the tasks are split and allocated in parallel according to the system topology and computational load.
7. A multi-core CPU simulation method according to claim 1, characterized in that: The multi-core CPU simulation method also includes a dynamic balancing step for multi-dimensional comprehensive load evaluation, which quantifies the load status using the following formula: Overall load factor: ,in, , For core occupancy rate, As a percentage of the computational workload, Memory usage; Load balancing metrics: ； in, Standard deviation, The mean; when When a preset threshold is set, migration priority is used as the basis for the subtask. Perform task reassignment to enable Preset threshold.
8. A multi-core CPU simulation method according to claim 7, characterized in that: The preset threshold is 15%, and the weighting coefficient is set to default. Subtask migration priority is based on Sort by priority from smallest to largest, migrate low-priority subtasks first, and define high-load units as... Low-load unit is defined as .
9. A multi-core CPU simulation method according to claim 8, characterized in that: The multi-core CPU simulation method also includes a transient predictive step-size adaptive adjustment step, which quantifies transient changes and step-size adjustment using the following formula: Transient change prediction rate: ； in, , For the first Predicted rate of transient change at time step. For the first Time and the A key state variable at a certain time The difference, This is the initial step size; Step size adjustment factor: ； in, This is the step size adjustment coefficient; This is an adjustment factor used to control the sensitivity of step size adjustment; it is an adjustable constant. For the set upper limit of the transient change rate threshold, when When this value is reached or exceeded, it indicates that the system is undergoing drastic transient changes, and the step size needs to be reduced. The lower limit of the set transient change rate threshold, when When the value is below this, it indicates that the system's transient changes are slow, and the step size needs to be increased; New Step And satisfy ; in, The new step size, after adjustment, is the simulation calculation time interval adjusted in real time according to the transient changes of the system. This constraint... Ensuring the step size is within a reasonable range can guarantee both simulation accuracy and computational efficiency.
10. A multi-core CPU simulation method according to claim 9, characterized in that: The transient threshold is default. Adjust the sensitivity coefficient ,like Take if it exceeds the boundary range or As the final step size.