Development method and PDK library based on 2D MoS2 process PDK

Abstract

This invention provides a development method and PDK library based on a two-dimensional MoS2 process PDK, relating to the field of semiconductor technology. The method includes: acquiring process input data for the two-dimensional MoS2 process; creating a directory framework for the two-dimensional MoS2 process PDK library in an electronic design automation (EDA) tool, which contains multiple subdirectories divided by function; generating and storing multiple component files required for the PDK library in the corresponding subdirectories of the directory framework according to the process input data, thus obtaining a preliminary two-dimensional MoS2 process PDK library; building a test circuit by calling the device units in the preliminary PDK library and performing multiple verifications; if any verification fails to meet preset requirements, correcting the corresponding component file and re-verifying until all verifications pass, thus obtaining a complete two-dimensional MoS2 process PDK library. This invention achieves seamless integration of the two-dimensional MoS2 process with the EDA environment, supports pre- and post-circuit simulation verification, and can shorten the iteration cycle.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a development method and PDK library for a two-dimensional MoS2 process design kit (PDK). Background Technology

[0002] With the rapid development of microelectronic devices, silicon-based transistors face fundamental challenges such as short-channel effects, quantum tunneling, and a surge in power density as they continue to shrink. Two-dimensional transition metal dichalcogenides, represented by molybdenum disulfide (MoS2), have become ideal candidate materials for building next-generation ultra-low-power integrated circuits.

[0003] However, there is still a lack of standardized design processes for integrating two-dimensional materials into large-scale circuit designs. Currently, two-dimensional MoS2 circuit design typically employs the following approach: researchers experimentally fabricate discrete devices and extract electrical parameters, then manually build simple functional circuits for simulation verification; the layout design stage relies on manual drawing and point-to-point rule checking, with parasitic parameter extraction and post-simulation steps missing or disconnected from the front-end design. This approach has the following technical problems in practical applications: First, simulation results deviate significantly from actual performance, and design reliability cannot be guaranteed; second, there is a lack of design rules and physical verification documents for the specific process constraints of two-dimensional MoS2 (such as layer transfer alignment, edge effects, etc.), resulting in layout verification relying on manual experience and having a very low degree of automation; third, there is a lack of a closed-loop iterative mechanism between pre-simulation and post-simulation, and design defects can only be discovered through multiple experimental tape-outs, leading to long development cycles and high costs.

[0004] Therefore, how to achieve seamless integration of 2D MoS2 process data with Electronic Design Automation (EDA) tools, establish a closed-loop design process covering pre-simulation, physical verification to post-simulation, and shorten the iteration cycle of devices and circuits has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This invention provides a development method and PDK library based on two-dimensional MoS2 process PDK, which solves the problems of lack of unified pre-simulation-post-simulation closed loop, low integration of process data and EDA tools, and long iteration cycle in existing two-dimensional MoS2 circuit design.

[0006] This invention provides a development method for a 2D MoS2 process PDK. The method includes: acquiring process input data for the 2D MoS2 process, and creating a directory framework for a 2D MoS2 process PDK library in an electronic design automation (EDA) tool based on the process input data. The directory framework contains multiple subdirectories divided by function. According to the process input data, multiple component files required for the PDK library are generated and stored in the corresponding subdirectories of the directory framework to obtain a preliminary 2D MoS2 process PDK library. The device units in the preliminary 2D MoS2 process PDK library are used to build a test circuit and perform multiple verifications. If any verification fails to meet the preset requirements, the corresponding component file is corrected and re-verified until all verifications pass, resulting in a complete 2D MoS2 process PDK library.

[0007] According to the present invention, a development method based on a two-dimensional MoS2 process PDK includes multiple component files, such as: process technology files, device units and graphic symbols, parameterized units, simulation model files, layout components, physical verification rule files, and parasitic parameter extraction files.

[0008] According to the present invention, a development method based on a two-dimensional MoS2 process PDK includes multiple verifications: circuit simulation verification, design rule checking verification, and layout and schematic verification. Figure 1 Consistency verification and parasitic parameter extraction verification.

[0009] According to the present invention, a development method based on a two-dimensional MoS2 process PDK is provided. The process input data includes: technical documents, development documents, a list of two-dimensional MoS2 process devices and device definition descriptions, graphic symbol descriptions for circuit schematic design, device attribute description files and parameter descriptions, device model files, design rule check design manuals, and layout and schematic diagrams. Figure 1 Design manual for integrity testing and design manual for parasitic parameter extraction.

[0010] According to the present invention, a development method for a two-dimensional MoS2 process PDK is provided, which creates a directory framework for a two-dimensional MoS2 process PDK library in an electronic design automation (EDA) tool based on process input data. The method includes: creating a main directory for the two-dimensional MoS2 process PDK library in the EDA tool; and creating, within the main directory, at least the following folders are included: a device attribute description file parameter folder, a model folder, a design rule check folder, and a layout and schematic folder. Figure 1 The consistency check folder and parasitic parameter extraction folder's subdirectories are used to create a directory framework.

[0011] According to the present invention, a development method based on a two-dimensional MoS2 process PDK is provided. The method further includes: creating a library mapping file in the main directory. The library mapping file is used to map and call the two-dimensional MoS2 process PDK library to the electronic design automation tool.

[0012] According to the present invention, a development method based on a two-dimensional MoS2 process PDK is provided. This method further includes: configuring path parameters in an electronic design automation tool, including the model folder path, design rule check folder path, and layout and schematic paths. Figure 1 The paths to the consistency check folder and the parasitic parameter extraction folder are associated with their respective subdirectories.

[0013] According to the present invention, a development method for a two-dimensional MoS2 process PDK is provided, which further includes: creating technical documents for the two-dimensional MoS2 process based on technical documents, wherein the technical documents include at least layer definition documents, layer display documents, layer mapping documents and substrate information documents.

[0014] According to the present invention, a development method based on a two-dimensional MoS2 process PDK is provided. The method further includes: creating a two-dimensional MoS2 device cell library according to a two-dimensional MoS2 process device list and device definition description; creating at least one two-dimensional MoS2 device cell in the two-dimensional MoS2 device cell library; and creating corresponding graphic symbols for circuit schematic design for each two-dimensional MoS2 device cell according to the graphic symbol description.

[0015] According to the present invention, a development method based on a two-dimensional MoS2 process PDK is provided. The method further includes: generating a device attribute description file to describe the parameter attributes of each device unit according to the parameter description of the device attribute description file; and configuring callback function in the device attribute description file.

[0016] According to the present invention, a development method based on a two-dimensional MoS2 process PDK is provided. This method further includes: converting the device model file into a simulation model file recognizable by electronic design automation tools and storing it in a model folder; checking the design manual according to design rules, compiling a design rule check file and storing it in a design rule check folder; and checking the layout and schematic. Figure 1 Conformity check design manual, write layout and schematics Figure 1 Consistency check rule file and save it in layout and principle Figure 1 Create a parasitic parameter extraction folder; based on the parasitic parameter extraction design manual, write a parasitic parameter extraction rule file and save it in the parasitic parameter extraction folder.

[0017] According to the present invention, a development method based on a two-dimensional MoS2 process PDK is provided. This method further includes: loading a preliminary two-dimensional MoS2 process PDK library through a library mapping file; calling a test device cell for pre-simulation; and correcting the simulation model file if the simulation results do not meet preset requirements; building a test layout; calling a design rule check rule file to perform design rule checks; and correcting the design rule check rule file if the requirements are not met; building the corresponding test schematic and test layout; and calling the layout and schematic... Figure 1 The consistency check rule document performs a consistency check; if the requirements are not met, the layout and schematic are modified. Figure 1 The system checks the parasitic parameter extraction rule file; it calls the parasitic parameter extraction rule file to extract parasitic parameters and performs post-simulation. If the requirements are not met, the parasitic parameter extraction rule file is modified.

[0018] This invention also provides a PDK library based on two-dimensional MoS2 technology. The PDK library includes a main directory, which integrates the following components: process technology documents; device units and graphic symbols; parameterized units; simulation model files; layout components; physical verification rule files; parasitic parameter extraction files; and explanatory documents.

[0019] According to the present invention, a PDK library based on two-dimensional MoS2 process is provided. The process technology file includes layer definition file, layer display file, layer mapping file and substrate information file of two-dimensional MoS2 process; the device unit and graphic symbol include device unit created under two-dimensional MoS2 process and corresponding graphic symbol for circuit schematic design.

[0020] According to the present invention, a PDK library based on two-dimensional MoS2 technology is provided. The parameterization unit includes a device attribute description file describing the parameter attributes of the device unit and a callback function integrated in the device attribute description file; the simulation model file is a model file that can be read by electronic design automation tools and is fitted based on the measured data of two-dimensional MoS2 devices.

[0021] According to the present invention, a PDK library based on two-dimensional MoS2 technology is provided, wherein the layout component includes the physical layout of device cells; the physical verification rule file includes design rule check files and layout and schematic diagrams. Figure 1 The consistency check file; the parasitic parameter extraction file is used to extract the parasitic parameters of interconnects from the layout.

[0022] According to the present invention, a PDK library based on two-dimensional MoS2 technology is provided. The documentation is used to guide the installation, calling and use of the PDK library. The parasitic parameters extracted by the parasitic parameter extraction file include parasitic capacitance, parasitic resistance and parasitic inductance, which are used to back-annotate the parasitic parameters to the circuit netlist to support post-simulation.

[0023] The present invention also provides an electronic device for executing a PDK development method based on a two-dimensional MoS2 process, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the PDK development method based on a two-dimensional MoS2 process as described in any of the preceding claims.

[0024] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the development method based on the two-dimensional MoS2 process PDK as described in any of the preceding claims.

[0025] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the development method based on the two-dimensional MoS2 process PDK as described in any of the preceding claims.

[0026] The present invention provides a development method and PDK library based on 2D MoS2 process PDK. By acquiring the process input data of 2D MoS2 process and creating a directory framework, a standardized organizational foundation is provided for the subsequent generation of component files, ensuring orderly integration between process data and EDA tools. Then, based on the process input data, multiple component files required for the PDK library are generated and stored in the corresponding subdirectories of the directory framework, constructing a preliminary complete PDK library, covering a full set of design resources from device models and parameterized units to physical verification rules. Then, the device units in the preliminary PDK library are called to build test circuits and perform multiple verifications, forming a closed loop of pre-simulation and post-simulation. When any verification fails to meet the preset requirements, the corresponding component file is corrected and re-verified until all verifications pass, so as to achieve iterative optimization of the PDK library quality. This achieves seamless integration of 2D MoS2 process and EDA environment, supports circuit pre- and post-simulation verification, and can shorten the iteration cycle. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the architecture of a PDK library based on two-dimensional MoS2 technology provided in an embodiment of the present invention.

[0029] Figure 2 This is a flowchart illustrating a development method for a two-dimensional MoS2 process PDK provided in an embodiment of the present invention.

[0030] Figure 3This is a schematic diagram of a complete development process of a 2D MoS2 process PDK provided by an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the structure of an electronic device for executing a PDK development method based on two-dimensional MoS2 process, provided by an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0033] The following is combined with Figure 1 This invention describes a PDK library based on two-dimensional MoS2 technology.

[0034] Figure 1 This is a schematic diagram of the structure of a PDK library based on two-dimensional MoS2 technology provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the PDK library 101 contains a main directory, which integrates the following components: process technology files 102, device units and graphic symbols 103, parameterization units 104, simulation model files 105, layout components 106, physical verification rule files 107, parasitic parameter extraction files 108, and documentation 109.

[0035] In some embodiments, the process technology document 102 includes a layer definition file, a layer display file, a layer mapping file, and a substrate information file for a two-dimensional MoS2 process.

[0036] In some embodiments, the layer definition file is used to uniquely identify all process layers involved in the two-dimensional MoS2 process, ensuring that the numbering of each process layer is not repeated; the layer display file is used to define the display attributes of each process layer in the layout design tool, such as color, fill style, and line width; the layer mapping file is used to establish a one-to-one correspondence between the internal layer number of the EDA tool and the actual wafer manufacturing process layer number; and the substrate information file is used to define the basic parameters of the two-dimensional MoS2 device, such as substrate type, doping concentration, and thickness.

[0037] For example, the layer definition file will define key process layers such as substrate layer, MoS2 channel layer, source metal layer, drain metal layer, gate dielectric layer, gate metal layer, and passivation layer.

[0038] Specifically, when creating the layer definition file, the process flow of the actual two-dimensional MoS2 preparation process must be strictly followed to ensure that the process information is completely consistent with the actual manufacturing requirements.

[0039] In some embodiments, the device unit and graphic symbol 103 include device units created under a two-dimensional MoS2 process and corresponding graphic symbols for circuit schematic design.

[0040] In some embodiments, the device units include, but are not limited to, core device units such as MoS2 transistors, MoS2 phototubes, MoS2 synapses, and MoS2 memristors, as well as basic circuit units such as inverters, adders, and multipliers composed of the core device units.

[0041] For example, the MoS2 transistor device cell defines the electrical properties and connection relationships of the three ports: source, drain, and gate.

[0042] Specifically, each device unit corresponds to a unique graphic symbol. The graphic symbol corresponds one-to-one with the port of the device unit through standardized pin identification, which facilitates calling and connection in circuit schematic design.

[0043] In some embodiments, the parameterization unit 104 includes a device attribute description file that describes the parameter attributes of the device unit and a callback function integrated in the device attribute description file.

[0044] In some embodiments, the device attribute description file is a Component Description Format (CDF) file, which is used to define the device's parameter items, default values, value ranges, and constraint relationships; the callback function is implemented using the SKILL language, which is used to implement parameter linkage, parameter validity verification, and user interface interaction functions.

[0045] For example, the parameterization unit also includes a netlist process and a layout graph. The netlist process is used to automatically generate the corresponding circuit netlist based on the configured device parameters, and the layout graph is used to automatically generate the corresponding physical layout based on the configured device parameters.

[0046] Specifically, when a user modifies the channel length parameter of the MoS2 transistor in the schematic, the Callback function automatically checks whether the parameter is within the range allowed by the process. If it exceeds the range, a prompt message will pop up, and the corresponding parameters in the netlist process and the layout diagram will be updated at the same time to ensure the consistency between the schematic, netlist and layout.

[0047] In some embodiments, the simulation model file 105 is a model file that can be read by electronic design automation tools and is fitted based on measured data of a two-dimensional MoS2 device.

[0048] In some embodiments, the simulation model file is a Simulation Program with Integrated Circuit Emphasis (SPICE) model file, which contains key electrical characteristic parameters of the two-dimensional MoS2 device, such as mobility, threshold voltage, subthreshold swing, and defect states.

[0049] For example, SPICE model files can match the current-voltage (Id-Vd, Id-Vg) characteristic curves and capacitance-voltage (CV) characteristic curves of two-dimensional MoS2 devices with different sizes (such as different channel lengths and channel widths) and different process conditions (such as different annealing temperatures and different gate dielectric thicknesses).

[0050] Specifically, SPICE model files establish a mapping relationship between device pins and corresponding device units, enabling EDA tools to automatically call the corresponding model parameters when performing circuit simulation.

[0051] In some embodiments, layout component 106 includes a physical layout of device cells.

[0052] In some embodiments, the layout component is a parametric physical layout developed using the SKILL language, which includes the size and material parameter definitions of the device's electrodes, channels, gates, and other structures.

[0053] For example, the layout components of a MoS2 transistor define key dimensional parameters such as the width and spacing of the source metal, the width and spacing of the drain metal, the length and width of the channel, and the length and overlap of the gate.

[0054] Specifically, the layout component inherits the layer definitions and display rules from the process technology document to ensure that the generated layout meets the design requirements of the two-dimensional MoS2 process.

[0055] In some embodiments, the physical verification rule file 107 includes a design rule check file and layout and principles. Figure 1 Consistency check documents.

[0056] In some embodiments, Design Rule Check (DRC) files are stored in the DRC folder and are used to check whether the layout design conforms to the specific constraints of the 2D MoS2 process, such as layer transfer alignment accuracy, edge effect influence, minimum linewidth, minimum spacing, minimum area, etc.; layout and schematic Figure 1 The consistency check (Layout Versus Schematic, LVS) file is stored in the LVS folder and is used to verify whether the electrical connections in the layout are completely consistent with the electrical connections in the schematic.

[0057] For example, the minimum overlap between the MoS2 channel layer and the source metal layer is defined in the DRC rule file to ensure good ohmic contact.

[0058] Specifically, the physical verification rule document is formulated based on the yield data of the actual two-dimensional MoS2 fabrication process, which can effectively improve the manufacturability of the chip.

[0059] In some embodiments, the parasitic parameter extraction file 108 is used to extract parasitic parameters of interconnects from the layout.

[0060] Among them, parasitic parameters include parasitic capacitance, parasitic resistance, and parasitic inductance.

[0061] For example, parasitic parameters are used to back-annotate the circuit netlist to support post-simulation.

[0062] In some embodiments, parasitic extraction (PEX) files are stored in the PEX folder, which can extract parasitic capacitance, parasitic resistance, and parasitic inductance between interconnects and between interconnects and the substrate in the layout.

[0063] For example, the extracted parasitic parameters are back-annotated to the circuit netlist in a standard format, replacing the original ideal device model and forming a circuit netlist that includes parasitic effects.

[0064] Specifically, post-simulation based on circuit netlists that include parasitic effects can accurately predict the chip's performance, timing, and power consumption after actual manufacturing.

[0065] In some embodiments, documentation 109 is used to guide the installation, invocation, and use of the PDK library.

[0066] In some embodiments, the documentation includes a 2D MoS2 process PDK user manual, a DRC user manual, an LVS user manual, and a PEX user manual.

[0067] For example, the PDK user manual for the 2D MoS2 process details the installation steps of the PDK library, the environment configuration method, the device calling method, and solutions to common problems.

[0068] Specifically, each user manual includes corresponding screenshots and sample code to help users get started quickly.

[0069] In the PDK library based on two-dimensional MoS2 technology provided by this invention, standardized layer definitions and process constraints for two-dimensional MoS2 devices are provided by integrating process technology files in the main directory; device units, graphic symbols, and parameterized units work together to realize configurable calls and callback verification of device parameters; simulation model files and layout components work together to support pre-simulation and layout design; physical verification rule files and parasitic parameter extraction files are linked to enable design rule checks and layout principle verification. Figure 1 Consistency verification and parasitic parameter back-annotation simulation form a closed loop; the documentation ensures the correct use of the library. The organic integration of various components realizes seamless integration of 2D MoS2 process data with the EDA environment, supports pre- and post-circuit simulation verification, and effectively shortens the iteration cycle of devices and circuits.

[0070] The following is combined with Figure 2 and Figure 3 This invention describes the development method of a two-dimensional MoS2 process PDK. For consistency, the entity executing this method will be uniformly named "system" and will not be described further thereafter.

[0071] In this embodiment of the invention, the electronic design automation tool is a custom integrated circuit design platform commonly used in the industry (such as the Cadence Virtuoso platform). This platform is a mainstream EDA tool widely used in the field of integrated circuit design, supporting the entire design process from circuit schematic design and simulation to layout design and physical verification.

[0072] Figure 2 This is a flowchart illustrating the development method of a two-dimensional MoS2 process PDK provided in an embodiment of the present invention. Figure 2 As shown, the method includes the following steps: S201. Obtain the process input data for the two-dimensional MoS2 process.

[0073] In this embodiment of the invention, the process input data includes: technical documents, development documents, a list of two-dimensional MoS2 process devices and device definition descriptions, graphic symbol descriptions for circuit schematic design, device attribute description files and parameter descriptions, device model files, design rule check design manuals, and layout and schematic diagrams. Figure 1 Design manual for integrity testing and design manual for parasitic parameter extraction.

[0074] In some embodiments, the technical documentation includes the fabrication process flow of the two-dimensional MoS2 device, the parameter requirements for each process step, and the process tolerances; the development documentation includes the overall planning, schedule, and quality standards for PDK development; the two-dimensional MoS2 process device list and device definition descriptions clarify all device types that the PDK library needs to support, as well as their port definitions and functional descriptions; the graphic symbol description for circuit schematic design specifies the size ratio, pin positions, and identification methods of each device's graphic symbol; the device attribute description file parameter description lists all configurable parameters of each device, their default values, and value ranges; the device model file contains the electrical characteristic model of the two-dimensional MoS2 device obtained based on preliminary experimental data; and the design rule check includes the design manual, layout, and schematic. Figure 1 The Design Manual for Conformity Check and the Design Manual for Parasitic Parameter Extraction respectively specify the verification rules and acceptance criteria for DRC, LVS, and PEX.

[0075] For example, the process input data also includes measured data obtained by experimentally preparing and testing two-dimensional MoS2 process devices, which are used for subsequent fitting and calibration of device models.

[0076] Specifically, the measured data include the Id-Vd characteristic curves, Id-Vg characteristic curves, and CV characteristic curves of two-dimensional MoS2 devices of different sizes and under different process conditions.

[0077] S202. Based on the process input data, create a directory framework for a two-dimensional MoS2 process PDK library in the electronic design automation tool.

[0078] The directory framework contains multiple subdirectories divided by function.

[0079] In some embodiments, a main directory of a two-dimensional MoS2 process PDK library can be created in an electronic design automation tool.

[0080] For example, the name of the main directory can be set to "mos2_pdk_v1.0" to identify the process type and version number of the PDK library.

[0081] Specifically, the main directory is the root directory of the PDK library, and all PDK-related files and folders are stored in the main directory.

[0082] Furthermore, create at least the following folders in the main directory: a device attribute description file folder, a model folder, a design rule check folder, and a layout and schematic folder. Figure 1 The consistency check folder and parasitic parameter extraction folder's subdirectories are used to create a directory framework.

[0083] In some embodiments, a technical file folder, a graphic symbol folder, a layout component folder, and a documentation folder may also be created in the main directory to store process technology files, device graphic symbols, layout components, and documentation, respectively.

[0084] For example, the device property description file parameter folder is named "cdf", the model folder is named "models", the design rule check folder is named "drc", and the layout and schematics folder is named "drc". Figure 1 Name the consistency check folder "lvs" and the parasitic parameter extraction folder "pex".

[0085] Specifically, the naming of all subdirectories follows the default conventions of EDA tools, making it easier for EDA tools to automatically recognize and call them.

[0086] Thus, this invention provides a standardized storage location for all component files of the PDK library, ensuring that the PDK library has a clear structure and is easy to maintain and upgrade.

[0087] Optionally, path parameters can also be configured in the electronic design automation tool to specify the path to the model folder, the design rule check folder, and the layout and schematics. Figure 1 The paths to the consistency check folder and the parasitic parameter extraction folder are associated with their respective subdirectories.

[0088] In some embodiments, the path parameter is configured in the environment variable settings interface of the EDA tool.

[0089] For example, the "MODEL_PATH" environment variable is set to the absolute path of the model folder, and the "DRC_PATH" environment variable is set to the absolute path of the DRC folder.

[0090] Specifically, by configuring path parameters, EDA tools can automatically locate the corresponding subdirectory when they need to call the corresponding file, without requiring the user to manually specify the file path.

[0091] Thus, this invention achieves seamless integration between the PDK library and EDA tools, improving the ease of use of the PDK library.

[0092] In some embodiments, a library mapping file (cds.lib file) also needs to be created in the home directory.

[0093] For example, the cds.lib file contains a line of configuration code "DEFINE mos2_pdk . / mos2_pdk_v1.0", which maps the main directory of the PDK library to the "mos2_pdk" logical library in the EDA tool.

[0094] Specifically, by loading the cds.lib file in the EDA tool, users can see and call all devices and resources in the 2D MoS2 process PDK library in the library manager.

[0095] S203. Based on the process input data, generate and store multiple component files required for the PDK library in the corresponding subdirectories of the directory framework to obtain the preliminary two-dimensional MoS2 process PDK library.

[0096] In this embodiment of the invention, multiple component files include: process technology files, device units and graphic symbols, parameterized units, simulation model files, layout components, physical verification rule files, and parasitic parameter extraction files.

[0097] In one alternative implementation, a process technology document for a two-dimensional MoS2 process can be created based on technical documents.

[0098] The process technology documents include at least layer definition documents, layer display documents, layer mapping documents, and substrate information documents.

[0099] In some embodiments, when creating process technology documents, it is necessary to ensure that the definitions of all process layers are unique and non-repeating, and that the process information is completely consistent with the actual two-dimensional MoS2 preparation process requirements.

[0100] For example, the layer definition file will define the substrate layer, MoS2 channel layer, source metal layer, drain metal layer, gate dielectric layer, gate metal layer, passivation layer, etc. in the order of process sequence, and each layer will be assigned a unique integer number.

[0101] Specifically, the layer mapping file establishes a one-to-one correspondence between the internal layer number of the EDA tool and the GDSII layer number actually used by the wafer fab, ensuring that the designed layout can be directly used for tape-out.

[0102] Thus, this invention provides a unified process basis for subsequent device cell creation and layout design.

[0103] In another alternative implementation, a two-dimensional MoS2 device cell library can be created based on the two-dimensional MoS2 process device list and device definition description, and corresponding graphic symbols can be created for each device cell.

[0104] In some embodiments, the device cell library is created in the library manager of the EDA tool and needs to import the previously created process technology file so that the device cell library inherits the layer definitions and display rules in the process technology file.

[0105] For example, the name of the device cell library can be set to "mos2_devices" and exist as a sub-library of the PDK library.

[0106] Specifically, the device cell library is a container for all two-dimensional MoS2 device cells, and all device cells are stored in the device cell library.

[0107] Furthermore, at least one two-dimensional MoS2 device cell is created in the two-dimensional MoS2 device cell library.

[0108] For example, first, a core MoS2 transistor device unit is created, defining the electrical properties of the three ports: source, drain, and gate, such as port type as input / output and port voltage range.

[0109] Specifically, other device units such as MoS2 phototubes, MoS2 synapses, and MoS2 memristors can also be created, as well as basic circuit units such as inverters, adders, and multipliers composed of these core device units.

[0110] Furthermore, based on the graphic symbol descriptions, corresponding graphic symbols for circuit schematic design are created for each two-dimensional MoS2 device unit.

[0111] Specifically, the pins of the graphic symbols correspond one-to-one with the ports of the device unit, and the pin names are consistent with the port names of the device unit.

[0112] Thus, this invention provides a standardized component calling interface for circuit schematic design, improving the efficiency of circuit design.

[0113] In another alternative implementation, a display resource file (display.drf) for a two-dimensional MoS2 process can be created and loaded.

[0114] In some embodiments, the display.drf file is used to define the graphic display attributes of each process layer in the layout design, including color, fill style, line width, line style, etc.

[0115] For example, the display.drf file defines the MoS2 channel layer as a solid blue fill, the source metal layer as a hollow red line, the drain metal layer as a hollow green line, and the gate metal layer as a solid yellow fill.

[0116] Specifically, after creation, the storage path of the display.drf file needs to be added to the environment variables of the EDA tool so that the tool can automatically load the file when it starts.

[0117] Thus, this invention unifies the display style of each process layer, improves the readability and usability of the layout design, and reduces design errors.

[0118] In another alternative implementation, a device attribute description file can be generated based on the parameter description in the device attribute description file to describe the parameter attributes of each device unit, and callback function can be configured in it.

[0119] In some embodiments, the device property description file is a CDF file, which is developed using the SKILL scripting language.

[0120] For example, the CDF file of the MoS2 transistor defines parameters such as channel length, channel width, gate overlap, and source-drain contact length, and sets the default values ​​and ranges for each parameter. For example, the default value for the channel length is 100nm, and the range is 50nm to 1000nm.

[0121] Specifically, the CDF file also defines how parameters are displayed and edited in the schematic interface, such as which parameters are displayed on the main interface and which parameters are displayed in the advanced options.

[0122] Furthermore, configure callback functions in the device property description file.

[0123] In some embodiments, the callback function is written in the SKILL language and integrated into the CDF file.

[0124] For example, when a user modifies the channel length parameter, the Callback function will automatically check whether the parameter is greater than the minimum channel length allowed by the process (e.g., 50nm). If it is less than the minimum channel length allowed by the process, an error message box will pop up, indicating to the user that the parameter entered is outside the process range.

[0125] Specifically, the Callback function can also implement parameter linkage functionality. For example, when the channel width is modified, the source and drain widths are automatically adjusted to maintain a match, while the corresponding parameters in the netlist process and layout graphics are automatically updated to ensure that the schematic, netlist, and layout are synchronized. Figure 3 Consistency among individuals.

[0126] Thus, this invention enables configurable and automated verification of device parameters, ensuring the legality of design parameters and reducing human error.

[0127] In another alternative implementation, the device model file can be converted into a simulation model file that can be recognized by electronic design automation tools and stored in a model folder.

[0128] In some embodiments, it is necessary to convert the initial device model obtained by fitting measured data into a standard SPICE model format that can be recognized by EDA tools.

[0129] For example, the SPICE model file contains the current equation, capacitance equation, and related model parameters of the two-dimensional MoS2 device, such as mobility, threshold voltage, and subthreshold swing.

[0130] Specifically, after the conversion is complete, the SPICE model file needs to be associated with the corresponding device unit so that the EDA tool can automatically load the corresponding model parameters when calling the device for simulation.

[0131] Thus, this invention provides an accurate device model for circuit simulation, ensuring the reliability of the pre-simulation results.

[0132] In another alternative implementation, the design manual, layout, and schematics can be checked according to the design rules. Figure 1 For the consistency check design manual and the parasitic parameter extraction design manual, write the corresponding rule files and save them in the corresponding folders.

[0133] In some embodiments, the DRC rule file is written in the Calibre rule language and contains all the design rules for two-dimensional MoS2 processes.

[0134] For example, the DRC rule file defines rules such as minimum line width, minimum spacing, minimum area, layer overlap, and layer enclosing.

[0135] Specifically, the DRC rule document also sets out special design rules for the special constraints of the two-dimensional MoS2 process, such as layer transfer alignment accuracy and edge effect. For example, it defines the minimum overlap between the MoS2 channel layer and the source metal layer as 20nm to ensure good ohmic contact.

[0136] In some embodiments, the LVS rule file is also written in the Calibre rule language to extract electrical connections in the layout and compare them with electrical connections in the schematic.

[0137] For example, the LVS rule file defines the identification methods for each device, the extraction methods for ports, and the network connection relationships.

[0138] Specifically, LVS rule files can identify problems such as short circuits, open circuits, missing components, incorrect component types, and incorrect port connections in published diagrams.

[0139] In some embodiments, the PEX rule file is written in the Calibre rule language to extract parasitic parameters from the layout.

[0140] For example, the PEX rule file defines the extraction methods and accuracy requirements for parasitic capacitance, parasitic resistance, and parasitic inductance.

[0141] Specifically, the PEX rule file can extract parameters such as the coupling capacitance between interconnects, the series resistance of interconnects, and the parasitic inductance of interconnects.

[0142] Thus, this invention achieves fully automated verification of the physical design process, ensuring the correctness and manufacturability of the layout design.

[0143] S204. Use the device cells in the preliminary two-dimensional MoS2 process PDK library to build a test circuit and perform multiple verifications. If any verification fails to meet the preset requirements, correct the corresponding component file and re-verify until all verifications pass, and obtain the complete two-dimensional MoS2 process PDK library.

[0144] In this embodiment of the invention, multiple verifications include: circuit simulation verification, design rule checking verification, and layout and schematic verification. Figure 1 Consistency verification and parasitic parameter extraction verification.

[0145] In some embodiments, the verification test phase also includes CDF parameter verification and Callback function verification to ensure that the parameterized unit can function properly.

[0146] For example, the verification test is performed iteratively. If any verification fails, the corresponding component file is corrected and the verification is performed again until all verifications pass.

[0147] Specifically, all verification acceptance criteria are based on the design manual and measured data in the process input data.

[0148] The above verifications will be explained in detail below.

[0149] In one alternative implementation, a preliminary two-dimensional MoS2 process PDK library can be loaded through a library mapping file, and a test device cell can be called for pre-simulation. If the simulation results do not meet the preset requirements, the simulation model file can be corrected.

[0150] In some embodiments, the initial two-dimensional MoS2 process PDK library is first added to the library manager of the EDA tool by loading the cds.lib file.

[0151] For example, a single-transistor test circuit is built using the MoS2 transistor device unit, and Id-Vd characteristic simulation, Id-Vg characteristic simulation and CV characteristic simulation are performed respectively.

[0152] Specifically, the characteristic curves obtained from the simulation are compared with the measured characteristic curves. If the error between the two is within the allowable range (e.g., less than 5%), the simulation model file is considered qualified. If the error exceeds the allowable range, the parameters in the SPICE model file need to be adjusted, and the simulation verification needs to be performed again until the error meets the requirements.

[0153] Thus, this invention ensures the accuracy of the simulation model file, providing a reliable simulation basis for subsequent circuit design.

[0154] In another alternative implementation, a test layout can be built, and the design rule check rule file can be called to perform design rule checks. If the requirements are not met, the design rule check rule file can be modified.

[0155] In some embodiments, the test layout includes all possible layout structures, such as metal lines of different widths, metal lines of different spacings, contact holes of different sizes, and layer structures with different overlaps.

[0156] For example, the DRC rule file is invoked to check the test layout for any violations of design rules.

[0157] Specifically, if the DRC check results show errors that should not have appeared, or if intentionally set errors are not detected, it indicates that there is a problem with the DRC rule file. The DRC rule file needs to be corrected and the check needs to be repeated until the DRC rule file can accurately detect all violations of the design rules.

[0158] Thus, this invention ensures the correctness and completeness of the DRC rule file and can effectively check for process violations in the design of the publication drawing.

[0159] In another alternative implementation, a corresponding test schematic and test layout can be built, and the layout and schematic can be called. Figure 1 The consistency check rule document performs a consistency check; if the requirements are not met, the layout and schematic are modified. Figure 1 Consistency check rules document.

[0160] In some embodiments, a simple test schematic, such as an inverter circuit, is first built, and then the corresponding test layout is drawn based on the schematic.

[0161] For example, the LVS rule file is invoked to perform a consistency check on the test schematic and test layout to see if there are any inconsistencies in electrical connections.

[0162] Specifically, if errors such as device mismatch, network mismatch, or port mismatch are found in the LVS check results, it is necessary to check whether the LVS rule file is correct or whether the test layout is drawn correctly. After correction, the check should be repeated until the LVS check passes.

[0163] Thus, this invention ensures the correctness of the LVS rule file and can accurately verify the electrical consistency between the layout and the schematic.

[0164] In another alternative implementation, parasitic parameters can be extracted by calling a parasitic parameter extraction rule file and then post-simulation can be performed. If the requirements are not met, the parasitic parameter extraction rule file can be modified.

[0165] In some embodiments, parasitic parameters are first extracted from the test layout to obtain a netlist containing parasitic parameters.

[0166] For example, the netlist containing parasitic parameters is imported into a simulation tool for post-simulation. The results of pre-simulation and post-simulation are compared to analyze the impact of parasitic parameters on circuit performance.

[0167] Specifically, if the extracted parasitic parameters have a large error compared to the actual measured parasitic parameters, the extracted parameters in the PEX rule file need to be corrected, and the extraction and post-simulation should be performed again until the extracted results meet the accuracy requirements.

[0168] Thus, the present invention ensures the accuracy of parasitic parameter extraction, enabling post-simulation results to accurately predict the actual performance of the chip.

[0169] In some embodiments, after all verification tests have passed, it is also necessary to write user manuals for the 2D MoS2 process PDK, DRC, LVS, and PEX, and store these manuals in a manual folder.

[0170] For example, the documentation details the installation steps of the PDK library, the environment configuration method, the device calling method, the verification process, and solutions to common problems.

[0171] Specifically, the documentation is written in accordance with the principles of clarity, ease of understanding, and comprehensiveness, making it easy for users of different skill levels to use.

[0172] In the development method of PDK based on 2D MoS2 process provided by this invention, by acquiring the process input data of 2D MoS2 process and creating a directory framework, a standardized organizational basis is provided for the subsequent generation of component files, ensuring orderly connection between process data and EDA tools. Then, according to the process input data, multiple component files required for the PDK library are generated and stored in the corresponding subdirectories of the directory framework, constructing a preliminary complete PDK library, covering a full set of design resources from device models, parameterized units to physical verification rules. Then, the device units in the preliminary PDK library are called to build test circuits and perform multiple verifications, forming a closed loop of pre-simulation and post-simulation. When any verification fails to meet the preset requirements, the corresponding component file is corrected and re-verified until all verifications pass, so as to achieve iterative optimization of the PDK library quality, thereby realizing seamless integration of 2D MoS2 process and EDA environment, supporting circuit pre- and post-simulation verification, and shortening the iteration cycle.

[0173] Figure 3 This is a schematic diagram of a complete development process of a 2D MoS2 process PDK provided by an embodiment of the present invention.

[0174] like Figure 3 As shown, the complete development process is strictly divided into three stages: preparation, development, and verification / testing. These three core stages are progressive and iterative in a closed loop. Each stage contains clearly defined sub-steps with strict sequential dependencies. The output of the previous sub-step directly serves as the sole input for the next sub-step. After all sub-steps are completed, the final output is an industrially deliverable 2D MoS2 process PDK library.

[0175] For example, the preparation phase is the foundation of the entire development process, and it involves completing two core tasks in sequence: 1) Input 2D MoS2 process data: Collect and organize all original data related to the fabrication and performance testing of 2D MoS2 devices, including process manuals, design documents, device test data, initial model files, etc., to provide data basis for all subsequent development work.

[0176] 2) Create a 2D MoS2PDK library: In the EDA tool, establish a standardized PDK library root directory and functional subdirectory structure, and complete the initialization of the PDK library and the configuration of the basic environment.

[0177] For example, the development phase is the core of the entire process. Following the logical order of "process fundamentals → device definition → simulation support → physical verification", seven core development tasks are completed sequentially, and the outputs of all tasks are stored in the corresponding subdirectories created in the preparation phase: 1) Create a device library / path parameter configuration: Create a sub-library specifically for storing device cells, and configure the search path for each function file in the EDA tool to ensure that the tool can automatically locate and call all subsequently generated components.

[0178] 2) Create technical documents: Develop core technical documents that define all layer information and process rules of the two-dimensional MoS2 process, providing a unified process standard for subsequent device layout design.

[0179] 3) Define the device library / design graphic symbols: Create all supported 2D MoS2 device cells in the device sub-library and design standardized circuit schematic graphic symbols for each device cell.

[0180] 4) Create DRF file: Develop display resource file (display.drf) to define the display attributes of each process layer in the layout editor, improving the readability and ease of use of the layout design.

[0181] 5) Configure CDF parameters / develop callback functions: Develop a device attribute description file for each device unit, define all configurable parameters, and write callback functions to realize automatic parameter verification and linkage update.

[0182] 6) Convert SPICE model: Convert the original device model fitted based on measured data into the standard SPICE format that can be recognized by EDA tools, and complete the association mapping between the model and device units.

[0183] 7) Create DRC, LVS, and PEX files: Write design rule checks, layout, and schematic files respectively. Figure 1 The rule files for consistency checks and parasitic parameter extraction enable automated verification of the entire physical design process.

[0184] For example, the verification and testing phase is a crucial step in ensuring the quality of the PDK library. It adopts a closed-loop iterative model of "verification-correction-reverification" to complete two core tasks sequentially: 1) Verify device call / verify DRC, LVS, PEX rules: Build standard test circuits and test layouts, and verify the device call function, circuit simulation accuracy, and the correctness and completeness of physical verification rules in sequence. Make targeted corrections to the problems found and re-verify until all indicators meet the requirements.

[0185] 2) Write documentation: Write a complete set of PDK usage and maintenance documentation, and complete the final packaging and delivery preparation of the PDK library.

[0186] Thus, this invention, through a three-stage closed-loop iteration of preparation, development, and verification, ensures that the component files are generated completely and accurately, achieves seamless integration of two-dimensional MoS2 technology and EDA, supports pre- and post-circuit simulation verification, and effectively shortens the iteration cycle.

[0187] Figure 4 A schematic diagram of an electronic device is provided, which can serve as a hardware platform for running electronic design automation tools and for executing the development method based on the two-dimensional MoS2 process PDK provided in the embodiments of the present invention.

[0188] like Figure 4As shown, the electronic device may include a processor 410, a communications interface 420, a memory 430, and a communications bus 440. The processor 410, communications interface 420, and memory 430 communicate with each other via the communications bus 440. The communications interface 420 is used for data interaction with electronic design automation tools, including acquiring process input data for the two-dimensional MoS2 process, loading library mapping files, calling simulation model files, and outputting verification results.

[0189] The processor 410 can call logic instructions in the memory 430. The logic instructions include instructions for controlling the electronic design automation (EDA) tool to perform the following operations: acquiring process input data for the two-dimensional MoS2 process, and creating a directory framework for the two-dimensional MoS2 process PDK library in the EDA tool based on the process input data. The directory framework contains multiple subdirectories divided by function. According to the process input data, generating and storing multiple component files required for the PDK library in the corresponding subdirectories of the directory framework to obtain a preliminary two-dimensional MoS2 process PDK library. Calling the device cells in the preliminary two-dimensional MoS2 process PDK library to build a test circuit and perform multiple verifications. If any verification fails to meet the preset requirements, the corresponding component file is corrected and re-verified until all verifications pass, resulting in a complete two-dimensional MoS2 process PDK library.

[0190] It should be noted that the above operations are performed within an electronic design automation (EDA) tool environment, executed by the processor through tool instructions and in conjunction with user interaction, rather than being fully automated software program execution. When the logical instructions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. This computer software product, stored in a storage medium, includes several instructions to cause a computer device (which may be a personal computer, server, network device, or dedicated workstation) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0191] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the development method based on the two-dimensional MoS2 process PDK provided by the above methods. The method includes: obtaining process input data of the two-dimensional MoS2 process, and creating a directory framework of the two-dimensional MoS2 process PDK library in an electronic design automation tool based on the process input data. The directory framework contains multiple subdirectories divided by function. According to the process input data, generating and storing multiple component files required for the PDK library in the corresponding subdirectories of the directory framework to obtain a preliminary two-dimensional MoS2 process PDK library. Calling the device units in the preliminary two-dimensional MoS2 process PDK library to build a test circuit and perform multiple verifications. If any verification does not meet the preset requirements, the corresponding component file is corrected and re-verified until all verifications pass, and a complete two-dimensional MoS2 process PDK library is obtained.

[0192] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the development method based on the two-dimensional MoS2 process PDK provided by the above methods. The method includes: acquiring process input data of the two-dimensional MoS2 process, and creating a directory framework of the two-dimensional MoS2 process PDK library in an electronic design automation tool based on the process input data. The directory framework contains multiple subdirectories divided by function. According to the process input data, generating and storing multiple component files required for the PDK library in the corresponding subdirectories of the directory framework to obtain a preliminary two-dimensional MoS2 process PDK library. Calling the device units in the preliminary two-dimensional MoS2 process PDK library to build a test circuit and perform multiple verifications. If any verification fails to meet the preset requirements, the corresponding component file is corrected and re-verified until all verifications pass, thus obtaining a complete two-dimensional MoS2 process PDK library.

[0193] The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0194] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0195] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A development method for a PDK based on two-dimensional MoS2 process, characterized in that, The method includes: Obtain the process input data for the two-dimensional MoS2 process, and based on the process input data, create a directory framework for the two-dimensional MoS2 process PDK library in the electronic design automation tool. The directory framework contains multiple subdirectories divided by function. Based on the process input data, multiple component files required for the PDK library are generated and stored in the corresponding subdirectories of the directory framework to obtain a preliminary two-dimensional MoS2 process PDK library. The device units in the preliminary two-dimensional MoS2 process PDK library are used to build a test circuit and perform multiple verifications. If any verification fails to meet the preset requirements, the corresponding component file is corrected and re-verified until all verifications pass, thus obtaining the complete two-dimensional MoS2 process PDK library.

2. The method according to claim 1, characterized in that, The multiple component files include: process technology files, device units and graphic symbols, parameterized units, simulation model files, layout components, physical verification rule files, and parasitic parameter extraction files.

3. The method according to claim 1, characterized in that, The multiple verifications include: circuit simulation verification, design rule check verification, layout and schematic consistency verification, and parasitic parameter extraction verification.

4. The method according to claim 1, characterized in that, The process input data includes: technical documents, development documents, a list of two-dimensional MoS2 process devices and device definition descriptions, graphic symbol descriptions for circuit schematic design, device attribute description files and parameter descriptions, device model files, design rule check design manual, layout and schematic consistency check design manual, and parasitic parameter extraction design manual.

5. The method according to claim 4, characterized in that, The directory framework for creating a two-dimensional MoS2 process PDK library in an electronic design automation tool based on the process input data includes: Create the main directory of the two-dimensional MoS2 process PDK library in the electronic design automation tool; Create the directory framework by creating at least the following subdirectories under the main directory: a device attribute description file parameter folder, a model folder, a design rule check folder, a layout and schematic consistency check folder, and a parasitic parameter extraction folder.

6. The method according to claim 5, characterized in that, The method further includes: Configure path parameters in the electronic design automation tool to associate the model folder path, design rule check folder path, layout and schematic consistency check folder path, and parasitic parameter extraction folder path to their respective subdirectories.

7. The method according to claim 5, characterized in that, The multiple component files required for generating and storing the PDK library include: A process technology document for a two-dimensional MoS2 process is created based on the aforementioned technical document. The process technology document includes at least a layer definition document, a layer display document, a layer mapping document, and a substrate information document.

8. The method according to claim 5, characterized in that, The multiple component files required for generating and storing the PDK library include: Based on the list of two-dimensional MoS2 process devices and device definition descriptions, create a two-dimensional MoS2 device cell library; Create at least one two-dimensional MoS2 device cell in the two-dimensional MoS2 device cell library; Based on the graphic symbol description, corresponding graphic symbols for circuit schematic design are created for each two-dimensional MoS2 device unit.

9. The method according to claim 5, characterized in that, The multiple component files required for generating and storing the PDK library include: Based on the parameter description in the device attribute description file, a device attribute description file is generated to describe the parameter attributes of each device unit. Configure callback functions in the device property description file.

10. The method according to claim 5, characterized in that, The multiple component files required for generating and storing the PDK library include: Create a library mapping file in the main directory. The library mapping file is used to map and call the two-dimensional MoS2 process PDK library to the electronic design automation tool.

11. The method according to claim 10, characterized in that, The multiple component files required for generating and storing the PDK library include: Based on the device model file, convert it into a simulation model file that can be recognized by electronic design automation tools and save it into the model folder; According to the design rules, check the design manual, compile a design rule check rule file and save it in the design rule check folder; Based on the layout and schematic consistency check design manual, write a layout and schematic consistency check rule file and save it in the layout and schematic consistency check folder; According to the parasitic parameter extraction design manual, write a parasitic parameter extraction rule file and save it in the parasitic parameter extraction folder.

12. The method according to claim 11, characterized in that, The test circuit is built by calling the device cells in the preliminary two-dimensional MoS2 process PDK library to perform multiple verifications, including: The preliminary two-dimensional MoS2 process PDK library is loaded through the library mapping file, and the test device unit is called to perform pre-simulation. If the simulation results do not meet the preset requirements, the simulation model file is corrected. Build a test layout, call the design rule check rule file to perform design rule checks, and if the requirements are not met, modify the design rule check rule file. Build the corresponding test schematic and test layout, call the consistency check rule file between the layout and schematic to perform a consistency check, and if the requirements are not met, modify the consistency check rule file between the layout and schematic. The parasitic parameters are extracted by calling the parasitic parameter extraction rule file and then post-simulation is performed. If the requirements are not met, the parasitic parameter extraction rule file is modified.

13. A PDK library generated based on the method described in any one of claims 1 to 12, characterized in that, The PDK library contains a main directory, which integrates the following components: Process technology documents (102); Device Units and Graphic Symbols (103); Parameterized unit (104); Simulation model file (105); Layout components (106); Physical verification rules document (107); Parasitic parameter extraction file (108); Documentation (109).

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