A method, system, device, and medium for adding chip layout labels.

Abstract

This invention proposes a method, system, device, and medium for adding chip layout labels. The method includes obtaining a target circuit diagram; modifying an initial layout based on the target circuit diagram to obtain the target layout, and updating the connection labels of the module leads in the target layout; wherein the initial layout is generated based on the initial circuit diagram, and each module lead in the initial layout has a connection label; comparing the connection labels of all module leads in the target layout with the connection labels of all module leads in the corresponding target circuit diagram, and filtering out the connection labels in the target circuit diagram and the connection labels in the target layout that are different from each other; updating the connection labels in the corresponding target layout based on the filtered connection labels in the target circuit diagram. This invention, by adding and correcting connection labels in the target layout in batches, can greatly shorten the working time and greatly improve the working efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip layout design technology, and in particular to a method, system, device and medium for adding chip layout labels. Background Technology

[0002] Chip layout is a crucial link between circuit systems and integrated circuit technology. Through layout design, a three-dimensional circuit system can be transformed into a two-dimensional planar graphic, which, after semiconductor processing, can form a three-dimensional structure based on silicon materials. For example... Figure 1 If the layout is generated directly from the components in the circuit diagram, the layout and the circuit diagram will have completely corresponding component names, module levels and connection definitions, and the labels of each connection on the layout will also be consistent with the names of the corresponding connections in the circuit diagram.

[0003] However, in actual chip iterative development, it is often necessary to design a new chip B based on a chip A that has already been tape-out and verified, by modifying its circuit diagram and layout. In this case, engineers typically modify the initial layout of chip A, which has already been verified, to improve design efficiency and reduce verification risks. While this process improves the efficiency of physical design, it disrupts the consistency between the wiring labels in the original circuit diagram and the wiring labels in the layout. This means that after the design of chip B is completed, the target circuit diagram and the target layout cannot be automatically matched directly through wiring labels. Therefore, there is room for improvement. Summary of the Invention

[0004] This invention provides a method, system, device, and medium for adding chip layout labels, in order to improve the technical problem in the prior art where the connection labels of module leads in the target circuit diagram do not correspond to the connection labels of module leads in the target layout diagram in scenarios where the initial layout is modified to obtain the target layout.

[0005] This invention proposes a method for adding chip layout labels, comprising:

[0006] Obtain the target circuit diagram; wherein the target circuit diagram is obtained by modifying the initial circuit diagram, and the module lead-out connections of the target circuit diagram all have connection labels; Based on the target circuit diagram, the initial layout is modified to obtain the target layout, and the connection labels of the module leads in the target layout are updated; wherein, the initial layout is generated based on the initial circuit diagram, and each module lead in the initial layout has a connection label; The connection labels of all module leads in the target layout are compared with the connection labels of all module leads in the corresponding target circuit diagram. The connection labels in the target circuit diagram and the connection labels in the target layout that are different in comparison result are filtered out. Update the corresponding connection labels in the target layout based on the selected connection labels in the target circuit diagram.

[0007] In one embodiment of the present invention, the step of modifying the initial layout to obtain the target layout based on the target circuit diagram, and updating the connection labels of the module leads of the target layout, includes: The target circuit diagram and initial layout are input into the Virtuoso design platform, and the initial layout is modified according to the target circuit diagram to obtain the target layout in the Virtuoso design platform. The modified connections in the target layout are verified using design rule checking standards, and after verification, the connection labels of the module outgoing connections in the target layout are updated.

[0008] In one embodiment of the present invention, the step of verifying the design rule check standard for modified connections in the target layout, and updating the connection labels of the module outgoing connections in the target layout after the verification is completed, includes: The geometric dimensions of the modified connections in the target layout are compared with a preset geometric dimension threshold range; wherein, the geometric dimensions of the layout connections include connection width, connection spacing, connection extension value, and the enclosure size of the connection to vias / contact holes; When the modified geometry of the connection is within the geometry threshold range, the connection labels of the module lead-out connections in the target layout are updated; Otherwise, the geometric dimensions of the modified connections in the target layout are adjusted, and when the adjusted geometric dimensions of the modified connections are within the geometric dimension threshold range, the connection labels of the module lead-out connections in the target layout are updated.

[0009] In one embodiment of the present invention, updating the connection labels of the module outgoing lines of the target layout includes: Establish and activate the correspondence between the devices in the target layout and the devices in the target circuit diagram, so as to force the target circuit diagram and the target layout into a non-corresponding synchronization connection state; In the synchronized connection state, a preset connection tag is added to the module outgoing connection of the target layout, or the connection name of the module outgoing connection in the target layout is obtained and the connection name of the module outgoing connection is added as its connection tag.

[0010] In one embodiment of the present invention, the step of comparing the connection labels of all module leads in the target layout with the connection labels of all module leads in the corresponding target circuit diagram, and filtering out the connection labels in the target circuit diagram and the connection labels in the target layout that have different comparison results, includes: Call the physical verification tool calibre to compare the connection labels of all module leads in the target layout with the connection labels of all module leads on the corresponding target circuit diagram, and automatically generate a report text from the comparison results; A script capable of recognizing text content is invoked to extract the comparison results from the report text and filter out the connection labels in the target circuit diagram and the connection labels in the target layout that have different comparison results.

[0011] In one embodiment of the present invention, the step of calling the physical verification tool calibre to compare the connection labels of all module leads in the target layout with the connection labels of all module leads on the corresponding target circuit diagram, and automatically generating a report text with a fixed format for the comparison results, including: Use the physical verification tool calibre to locate the same device in the target layout and the target circuit diagram; Using the physical verification tool calibre, the connection labels of the module leads of the same device in the target layout are compared with the connection labels of the module leads in the target circuit diagram, and the comparison results are automatically generated into a report text with a fixed format.

[0012] In one embodiment of the present invention, updating the connection labels in the corresponding target layout based on the selected connection labels in the target circuit diagram includes: Using the built-in skill function in the Virtuoso design platform, perform a search operation for connection labels within the visual editing interface of the target layout to find and mark the selected connection labels in the target layout. A script with text editing capabilities is invoked, and the script is used to update the connection labels in the selected target circuit diagram to the corresponding connection labels in the target layout.

[0013] This invention also proposes an automatic chip layout label adding system, comprising: An acquisition unit is used to acquire a target circuit diagram; wherein the target circuit diagram is obtained by modifying an initial circuit diagram, and the module lead-out connections of the target circuit diagram all have connection labels; An adjustment unit is used to modify an initial layout to obtain a target layout based on the target circuit diagram, and to update the connection labels of the module leads of the target layout; wherein the initial layout is generated based on the initial circuit diagram, and each module lead of the initial layout has a connection label. The filtering unit is used to compare the connection labels of all module leads in the target layout with the connection labels of all module leads in the corresponding target circuit diagram, and filter out the connection labels in the target circuit diagram and the connection labels in the target layout that are different in comparison results. The update unit is used to update the corresponding connection labels in the target layout based on the connection labels in the selected target circuit diagram.

[0014] The present invention also proposes an electronic device, the electronic device comprising: One or more processors; A storage device for storing one or more programs that, when executed by one or more processors, cause the electronic device to implement the chip layout labeling method as described in any of the above.

[0015] The present invention also proposes a computer-readable storage medium, characterized in that it stores a computer program thereon, which, when executed by a computer processor, causes the computer to perform any of the chip layout label addition methods described above.

[0016] The beneficial effects of this invention: This invention proposes a method, system, device, and medium for adding chip layout labels. This invention automatically updates the labels of module leads in the target layout and performs a Live Layout Matching (LVS) verification between the connection labels of the target layout and the connection labels of the target circuit diagram. Because the automatically updated labels for the module leads in the target layout are not correct, the (incorrect) connection labels of the module leads in the target layout do not correspond to the connection labels of the module leads in the target circuit diagram. Therefore, the LVS verification result will show a mismatch between the connection labels in the target circuit diagram and the connection labels in the target layout. By filtering out the mismatched connection labels in the target circuit diagram and the connection labels in the target layout, and batch updating the (incorrect) connection labels of the module leads in the target layout to the correct connection labels in the target circuit diagram, the automatic addition of (correct) connection labels to the module leads in the target layout is completed. Therefore, it can greatly shorten the working time and greatly improve work efficiency. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] In the attached diagram: Figure 1 This is a schematic diagram of the circuit diagram window and layout window in the Virtuoso design platform provided in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram illustrating the steps of a method for adding chip layout labels according to an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of modified wiring in a target layout provided in an embodiment of the present invention.

[0021] Figure 4 This is a structural block diagram of a chip layout label adding system provided in an embodiment of the present invention.

[0022] Figure 5 This is a structural block diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0023] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0024] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0025] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0026] Before providing specific embodiments of the present invention, the application scenarios involved in the present invention will be introduced to facilitate a better understanding of the technical solutions of the present invention.

[0027] Chip layout is a crucial step between circuit systems and integrated circuit manufacturing processes. Through layout design, a three-dimensional circuit system can be transformed into a two-dimensional planar graphic. This graphic, after being processed using semiconductor techniques, forms a three-dimensional structure based on silicon. Layout design relies on Virtuoso XL software, such as... Figure 1 As shown, if the layout is generated directly from components retrieved from the schematic, the layout and schematic will have completely corresponding component names, module levels, and net definitions. In this case, selecting a component or net in either the schematic or the layout will automatically highlight the corresponding part in the other graphic, facilitating engineer operations.

[0028] However, in actual design, many layouts are not generated by retrieving components from the circuit diagram. For example, in the iteration of the same series of chips, it is necessary to develop an upgraded or reduced-cost version of chip B based on the existing chip A with minor modifications. Engineers will not redraw the target circuit diagram of chip B from scratch. Instead, they will modify the initial circuit diagram of chip A to obtain the target circuit diagram of chip B. Furthermore, engineers will not directly retrieve components from the target circuit diagram of chip B in Virtuoso XL software to generate the corresponding target layout. This is because even if the target circuit diagram is obtained by minor modifications to the initial circuit diagram, the process of generating the target layout from the target circuit diagram requires replanning the placement of components. That is, it requires layout, routing, and physical verification from scratch, which requires a lot of work and is far more efficient than directly modifying the initial layout of chip A to obtain the target layout. And since the initial layout of chip A has already been physically verified, engineers will choose to modify the initial layout of chip A to obtain the target layout of chip B.

[0029] Specifically, the initial layout of chip A in GDS file format is imported into the layout window of Virtuoso XL software, and the initial circuit diagram of chip A is also displayed in the circuit diagram window. Modifications are made to the initial circuit diagram of chip A to obtain the target circuit diagram of chip B. Modifications are then made to the initial layout of chip A to obtain the target layout of chip B. Finally, the net labels between the target circuit diagram and the target layout of chip B are mapped. However, because both the initial circuit diagram and initial layout of chip A are modified to obtain the target circuit diagram and target layout of chip B, it becomes impossible to automatically map the net labels between the target circuit diagram and the target layout of chip B using the naming rules for the nets in chip A. In existing technology, engineers need to manually locate components in the target layout of chip B by referring to the target circuit diagram of chip B, label the nets after clarifying the net relationships, and then perform layout-to-circuit diagram comparison (LVS, LayoutVersus Schematics) verification. For circuits with several similar structures and dimensions in the target circuit diagram, it is difficult to find the correct components in the target layout. Even after clarifying the connection relationships, a significant amount of time is still required due to the large number of labels. Furthermore, if incorrect labels are inadvertently added to the target layout due to human error, it will lead to errors in Layout Layout Comparison (LVS) verification. This may require repeated modification and adjustment of the connection labels in the target layout, greatly increasing the time cost.

[0030] Please see Figures 1 to 5 This invention proposes a method, system, device, and medium for adding chip layout labels, applicable to the field of chip layout design technology. In scenarios where an initial circuit diagram is modified to obtain a target circuit diagram, and an initial layout is modified to obtain a target layout, this invention automatically adds labels to the module leads in the target layout and performs Layout-to-Screen (LVS) verification. Because the automatically added labels to the module leads in the target layout are not correct, the (incorrect) connection labels for the module leads in the target layout do not correspond to the connection labels for the module leads in the target circuit diagram. Therefore, the Layout-to-Screen (LVS) verification result will show the mismatch between the (incorrect) connection labels for the module leads in the target layout and the connection labels for the module leads in the target circuit diagram.

[0031] This invention automatically adds (correct) connection tags to the target circuit diagram by filtering out mismatched connection tags from the target circuit diagram and the target layout, and then batch-updates the (incorrect) connection tags of the module leads in the target layout with the connection tags of the module leads in the target circuit diagram. This significantly reduces working time and greatly improves work efficiency. Specific embodiments are described in detail below.

[0032] Please see Figure 2 In one embodiment of the present invention, a method for adding chip layout labels is proposed, which may include the following steps.

[0033] Step S10: Obtain the target circuit diagram; wherein the target circuit diagram is obtained by modifying the initial circuit diagram, and the module lead-out lines of the target circuit diagram all have connection labels.

[0034] Specifically, the target circuit diagram is not a completely new design, but rather a modified version of an already completed and validated initial circuit diagram, created to meet new performance specifications, functional requirements, or for design iteration. In the target circuit diagram, every line representing the electrical connections of devices and modules extending outwards—that is, module lead-out connections—must be explicitly assigned a connection label. These connection labels are crucial attributes used in circuit design tools to identify network nodes. Obtaining a target circuit diagram with complete connection labels is the logical source and basis for all subsequent automated comparison and correction operations.

[0035] Step S20: Based on the target circuit diagram, modify the initial layout to obtain the target layout, and update the connection labels of the module leads of the target layout; wherein, the initial layout is generated based on the initial circuit diagram, and each module lead of the initial layout has a connection label.

[0036] Specifically, the initial layout is a physical arrangement drawn based on the previous initial circuit diagram, with corresponding connection labels already attached to the internal circuit connections. In layout design platforms such as Virtuoso, this initial layout is edited as necessary, referencing the new target circuit diagram. These modifications may include changing the paths of circuit connections, adjusting the placement of components, adding or deleting certain circuit connections, to ensure that the physical implementation of the target layout matches the electrical design intent of the target circuit diagram. After modification, the resulting layout corresponds to the target circuit diagram.

[0037] Next, the system automatically generates or refreshes the attached text labels (connection tags) for the module leads in the target layout. At this point, the content of the generated connection tags is inconsistent with the corresponding connection tags for the module leads in the target circuit diagram. Furthermore, the purpose of this step is not to immediately correct this inconsistency, but rather to leverage the tool's automation capabilities to quickly and in batches ensure that every module lead in the target layout has an identifiable and operable (incorrect) connection tag, preparing for the next step of comparing the connection tags of the module leads in the target layout with those in the target circuit diagram.

[0038] In one embodiment of the present invention, step S20 may include the following steps.

[0039] Based on the target circuit diagram, the initial layout is modified to obtain the target layout, and the connection labels of the module leads in the target layout are updated, including: Step S210: Input the target circuit diagram and the initial layout into the Virtuoso design platform, and modify the initial layout in the Virtuoso design platform according to the target circuit diagram to obtain the target layout.

[0040] Specifically, in the Virtuoso design platform, both the target circuit diagram and the initial layout file are imported or opened simultaneously. The target circuit diagram provides new electrical connection specifications and wiring labels, while the initial layout is the physical layout basis drawn according to the original design intent. In Virtuoso's integrated design environment, the initial layout is edited by referring to the device connections and signal paths shown in the target circuit diagram. This editing operation is a direct graphical modification, which may include moving or replacing the physical positions of devices such as transistors and capacitors, redrawing metal or polysilicon layers to change the routing paths of circuit connections, adding new connections to implement new functions, or deleting existing connections that are no longer needed. Through these operations, the initial layout is gradually adjusted so that its physical implementation strictly corresponds to the electrical design intent of the target circuit diagram, ultimately forming a new physical layout file that meets the requirements of the target circuit diagram, i.e., the target layout.

[0041] Step S220: Verify the design rule check standard for the modified connections in the target layout, and update the connection labels of the module lead-out connections in the target layout after the verification is completed.

[0042] Specifically, after the target layout's graphic editing is complete, a Design Rule Check (DRC) must be performed on the modified interconnects. Design Rule Check is a mandatory verification step in chip physical design. Based on the process design rule documents provided by the chip manufacturer, it verifies the physical dimensions and spacing of all graphics in the layout. The check primarily targets modified circuit interconnect areas. The appropriate DRC tool is called within the Virtuoso platform to perform this check on the target layout. The tool automatically scans and marks all graphic locations that violate design rules, examines and corrects these violations one by one, such as widening excessively thin interconnects or adjusting excessively close line spacing, until all design rule violations related to the modified interconnects are cleared, and the verification status shows "completely passed."

[0043] Only after the design rules have been checked and verified can the step of updating the connection labels for the module leads in the target layout proceed. At this point, the target layout is correct at the physical graphic level. The operation of updating connection labels is performed within the Virtuoso platform. By executing specific commands or scripts, based on the connection relationships of the current layout graphics, the text identifiers attached to the visible module leads, i.e., connection labels, are automatically generated or refreshed. At this point, the text string of the connection label automatically generated for the module leads in the target layout is inconsistent with the connection label defined for the corresponding module leads in the target circuit diagram. The purpose of this step is to utilize the automation function of the Virtuoso platform to quickly and batch complete the generation and attachment of module lead label entities for the target layout, providing a clear text object that can be recognized and manipulated by the software for all circuit connections that need to be compared, while the correctness of the label content is left to subsequent comparison and correction steps.

[0044] In one embodiment of the present invention, step S220 may include the following steps.

[0045] The modified connections in the target layout are validated according to design rule checking standards, and the connection labels of the module outgoing connections in the target layout are updated after the validation is completed, including: Step S221: Compare the geometric dimensions of the modified connection lines in the target layout with a preset geometric dimension threshold range; wherein, the geometric dimensions of the layout connection lines include the connection width, connection spacing, connection extension value, and the enclosure size of the connection lines to vias / contact holes.

[0046] Specifically, design rule checks are performed on modified connections in the target layout, including verification and necessary adjustments to geometric dimensions. During verification, the various geometric dimensions of the modified connections, including connection width, connection spacing, connection extension value, and the enclosure size of the connection to vias / contact holes, are compared with the preset geometric dimension threshold range in the process rules.

[0047] Step S222: When the geometric dimensions of the modified connection are within the geometric dimension threshold range, update the connection labels of the module lead-out connections of the target layout.

[0048] Specifically, when all geometric dimensions of a modified connection are within the corresponding threshold range, it is determined to pass the verification, and then the connection label is updated.

[0049] Step S223: Otherwise, adjust the geometric dimensions of the modified lines in the target layout, and when the adjusted geometric dimensions of the modified lines are within the geometric dimension threshold range, update the connection labels of the module lead-out lines in the target layout.

[0050] Specifically, if any geometric dimension of a modified connection does not meet the threshold range requirements, the geometric dimension of that connection must first be adjusted in the target layout, for example, by widening an insufficient width or increasing an excessively small spacing. After adjustment, its geometric dimensions are compared with the threshold range again until all requirements are met. Only after passing the verification can the connection labels of the module outgoing connections in the target layout be updated.

[0051] In one embodiment of the present invention, updating the connection labels of the module lead-out lines of the target layout includes: Establish and activate the correspondence between the devices in the target layout and the devices in the target circuit diagram to force the target circuit diagram and the target layout into a non-corresponding synchronization connection state.

[0052] Specifically, to update the connection labels of the module leads of the target layout, it is first necessary to establish the correspondence between the target layout devices and the target circuit diagram devices in the Virtuoso design platform, thereby forcing them into a special state, namely the non-corresponding synchronized connection state. In this state, automated labeling operations are allowed.

[0053] Additionally, it's important to note that since the target layout is not directly generated from the current target circuit diagram, there is no automatic association between the two within the platform. Therefore, the Virtuoso design platform cannot directly use its automatic tagging function. A mapping relationship between the target layout components and the target circuit diagram components must first be established, putting the platform into a special "non-corresponding synchronized connection state." By forcibly establishing this mapping relationship, Virtuoso's automatic tagging mechanism can be activated. In this state, Virtuoso can batch-add tags to modified connections in the target layout.

[0054] In the synchronized connection state, a preset connection tag is added to the module outgoing connection of the target layout, or the connection name of the module outgoing connection in the target layout is obtained and the connection name of the module outgoing connection is added as its connection tag.

[0055] Specifically, through automation, connection tags are generated in batches for the modules leading out of the target layout. There are two methods: one is to add a pre-defined, universal tag text to all module leading out connections; the other is to directly read the inherent internal connection name of each module leading out connection from the target layout database and attach that name text as a connection tag to the corresponding connection, such as... Figure 3 As shown. Regardless of the method used, the connection label content of the module leads in the generated target layout is inconsistent with the connection labels set for the module leads in the target circuit diagram. The goal of this step is to quickly and in batches create label entities to provide operation objects for subsequent comparison and correction.

[0056] Step S30: Compare the connection labels of all module leads in the target layout with the connection labels of all module leads in the corresponding target circuit diagram, and filter out the connection labels in the target circuit diagram and the connection labels in the target layout that are different in comparison results.

[0057] Specifically, a systematic automated comparison is performed to identify and filter all erroneous connection labels on the module leads in the target layout. Specifically, each module lead in the target layout is matched with the corresponding module lead in the target circuit diagram. For each pair of corresponding module leads, the actual connection label on the target layout module lead is compared with the connection label on the target circuit diagram module lead. Subsequently, all inconsistent comparison results are automatically filtered out and compiled into a clear list. This list precisely records each mismatch, i.e., which module lead labels in the target layout do not match the corresponding module lead labels in the target circuit diagram. Through this automated filtering process, the location and collection of all erroneous labels in the target layout are efficiently and accurately completed, providing a direct and clear basis for subsequent steps to batch correct and update erroneous connection labels to correct ones.

[0058] In one embodiment of the present invention, step S30 may include the following steps.

[0059] The connection labels in the target layout are compared with the connection names of the corresponding circuit connections on the target circuit diagram. Connection labels and names that do not match are selected, including: Step S310: Call the physical verification tool calibre to compare the connection labels of all module leads in the target layout with the connection labels of all module leads on the corresponding target circuit diagram, and automatically generate a report text from the comparison results.

[0060] Specifically, the physical verification tool Calibre is used to verify the consistency between the target layout and the target circuit diagram. Calibre automatically compares the connection label text on each module's lead-out line in the target layout with the corresponding connection label on the lead-out line in the target circuit diagram, and automatically outputs all comparison results to generate a detailed report text file.

[0061] Step S320: Call a script that recognizes text content, use the script to extract the comparison results from the report text, and filter out the connection labels in the target circuit diagram and the connection labels in the target layout that are different in comparison results.

[0062] Specifically, in the existing technology, based on the report text file, the (incorrect) connection labels of the target layout module leads are identified, and the connection labels of the target circuit diagram module leads are compared. The (incorrect) connection labels of the target layout module leads are then manually modified to the correct connection labels of the target circuit diagram module leads.

[0063] In this embodiment, a specially written text processing script is invoked, which automatically reads and parses the report text file generated by Calibre. Through built-in text recognition logic, the script accurately locates all error messages in the report regarding mismatched connection labels, and extracts two key data points from each message: the (incorrect) connection label of the module's lead-out connection on the target layout, and the connection label of the corresponding module's lead-out connection in the target circuit diagram. The script organizes and outputs these extracted mismatches, thus automatically completing the task of filtering out all connection labels with inconsistent comparison results from the complex report. The entire process requires no manual review of the report, achieving highly efficient extraction of error information.

[0064] In one embodiment of the present invention, step S310 may include the following steps.

[0065] The physical verification tool calibre is invoked to compare the connection labels of all module leads in the target layout with the connection labels of all module leads on the corresponding target circuit diagram. The comparison results are automatically generated into a report text with a fixed format, including: Step S311: Call the physical verification tool calibre to find the same device in the target layout and the target circuit diagram.

[0066] Specifically, Calibre performs device matching, which means it automatically finds and establishes a one-to-one correspondence between each device in the target layout and the target circuit diagram. This is the basis for subsequent wiring comparison.

[0067] Step S312: Using the physical verification tool calibre, compare the connection labels of the module leads of the same device in the target layout with the connection labels of the module leads in the target circuit diagram, and automatically generate a report text with a fixed format for the comparison results.

[0068] Specifically, after device matching is completed, Calibre further compares the connection relationships of each pair of matched devices. It extracts the connection tags attached to the module leads connecting the device in the target layout, and at the same time extracts the connection tags defined on the corresponding module leads connecting the same device in the target circuit diagram, and performs a precise comparison of these two text strings.

[0069] Step S40: Update the corresponding connection labels in the target layout according to the selected connection labels in the target circuit diagram.

[0070] Specifically, the system automatically locates the incorrect connection labels for each module's leads in the target layout and replaces them in batches with the corresponding connection labels for the module leads in the target circuit diagram. This automatically adds correct connection labels to the module leads in the target layout. This process eliminates the need for manual modification, correcting all incorrect labels at once, ensuring that the connection labels in the target layout are completely consistent and correspond to those in the target circuit diagram.

[0071] Therefore, this invention eliminates the need to search for corresponding connections in the target layout based on the connections in the target circuit diagram, and then add connection tags to each connection line one by one. Furthermore, this invention does not require a direct correspondence between the connection tags in the target layout and those in the target circuit diagram to automatically add and update connection tags in the target layout. In addition, this invention is highly effective for modifying a layout from one version to another when there are multiple similar circuit structures in the target circuit diagram. By adding connection tags to the target layout in batches, it can significantly shorten working time and greatly improve work efficiency.

[0072] In one embodiment of the present invention, step S40 may include the following steps.

[0073] Based on the connection labels in the selected target circuit diagram, update the corresponding connection labels in the target layout, including: Step S410: Using the built-in skill function in the Virtuoso design platform, perform a search operation for connection labels in the visual editing interface of the target layout to find and mark the selected connection labels in the target layout.

[0074] Specifically, based on the list of filtered results, such as listing (incorrect) connection labels and their corresponding connection names, the program calls Virtuoso's built-in Skill function to automatically find all connection label objects in the visual editing interface of the target map whose text content matches the (incorrect) connection labels in the list, and locates and marks them.

[0075] Step S420: Call a script that can edit text content, and use the script to update the connection labels in the selected target circuit diagram to the corresponding connection labels in the target layout.

[0076] Specifically, an editing script is invoked. This script reads the connection names from the list and automatically replaces the text content of each (incorrect) connection label object marked in the previous step with the corresponding correct connection label. This replacement operation is performed in batches, directly modifying the layout database without manual intervention, thus completing the correction of all incorrect labels in one go.

[0077] Please see Figure 4 The present invention also proposes an automatic chip layout label adding system 100, which may include an acquisition unit 110, an adjustment unit 120, a filtering unit 130 and an update unit 140.

[0078] The acquisition unit 110 is used to acquire a target circuit diagram; wherein the target circuit diagram is obtained by modifying an initial circuit diagram, and the module lead-out connections of the target circuit diagram all have connection labels.

[0079] The adjustment unit 120 is used to modify the initial layout according to the target circuit diagram to obtain the target layout, and update the connection labels of the module lead-out connections of the target layout; wherein, the initial layout is generated according to the initial circuit diagram, and each module lead-out connection of the initial layout has a connection label.

[0080] The filtering unit 130 is used to compare the connection labels of all module leads in the target layout with the connection labels of all module leads in the corresponding target circuit diagram, and filter out the connection labels in the target circuit diagram and the connection labels in the target layout that are different in comparison results.

[0081] The updating unit 140 is used to update the connection labels in the corresponding target layout according to the connection labels in the selected target circuit diagram.

[0082] Please see Figure 5 In one embodiment of the present invention, an electronic device 200 may also be provided. The electronic device 200 may include a memory 210, a processor 220 and a bus, and may also include a computer program stored in the memory 210 and executable on the processor 220, such as an automatic chip layout label addition program.

[0083] The memory 210 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 210 can be an internal storage unit of the electronic device 200, such as the portable hard drive of the electronic device 200. In other embodiments, the memory 210 can also be an external storage device of the electronic device 200, such as a plug-in portable hard drive, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device 200. Furthermore, the memory 210 can include both internal and external storage units of the electronic device 200. The memory 210 can be used not only to store application software and various types of data installed on the electronic device 200, such as automatically added code for chip layout labels, but also to temporarily store data that has been output or will be output.

[0084] In some embodiments, processor 220 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits packaged with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. Processor 220 is the control unit of the electronic device 200, connecting various components of the electronic device 200 via various interfaces and lines. It executes programs or modules stored in the memory 210 (e.g., an automatic chip layout label addition program) and calls data stored in the memory 210 to perform various functions and process data of the electronic device 200.

[0085] The processor 220 executes the operating system of the electronic device 200 and various installed applications. The processor 220 executes the applications to implement the steps in the above-described method for adding chip layout labels.

[0086] For example, the computer program may be divided into one or more modules, which are stored in the memory 210 and executed by the processor 220 to complete this application. The one or more modules may be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the electronic device 200. For example, the computer program may be divided into an acquisition unit 110, an adjustment unit 120, a filtering unit 130, and an update unit 140.

[0087] The integrated unit implemented as a software functional module described above can be stored in a computer-readable storage medium, which can be non-volatile or volatile. The software functional module, stored in the storage medium, includes several instructions to cause a computer device (which may be a personal computer, computer equipment, or network device, etc.) or processor to perform some functions of the chip layout label adding method described in the various embodiments of this application.

[0088] In summary, this invention proposes a method, system, device, and medium for adding chip layout labels. This invention automatically updates the labels of module leads in the target layout and performs a Live Layout Matching (LVS) verification between the connection labels of the target layout and the connection labels of the target circuit diagram. Because the automatically updated labels for the module leads in the target layout are not correct, the (incorrect) connection labels of the module leads in the target layout do not correspond to the connection labels of the module leads in the target circuit diagram. Therefore, the LVS verification result will show a mismatch between the connection labels in the target circuit diagram and the connection name labels in the target layout. By filtering out the mismatched connection labels in the target circuit diagram and the connection name labels in the target layout, and batch updating the (incorrect) connection labels of the module leads in the target layout to the correct connection labels, the automatic addition of (correct) connection labels to the module leads in the target layout is completed. Therefore, this greatly shortens the working time and significantly improves work efficiency.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for adding a chip layout label, characterized in that, include: Obtain the target circuit diagram; wherein the target circuit diagram is obtained by modifying the initial circuit diagram, and the module lead-out connections of the target circuit diagram all have connection labels; Based on the target circuit diagram, the initial layout is modified to obtain the target layout, and the connection labels of the module leads in the target layout are updated; wherein, the initial layout is generated based on the initial circuit diagram, and each module lead in the initial layout has a connection label; The connection labels of all module leads in the target layout are compared with the connection labels of all module leads in the corresponding target circuit diagram. The connection labels in the target circuit diagram and the connection labels in the target layout that are different in comparison results are selected. Update the corresponding connection labels in the target layout based on the selected connection labels in the target circuit diagram.

2. The method for adding chip layout labels according to claim 1, characterized in that, The step of modifying the initial layout to obtain the target layout based on the target circuit diagram, and updating the connection labels of the module leads in the target layout, includes: The target circuit diagram and initial layout are input into the Virtuoso design platform, and the initial layout is modified according to the target circuit diagram to obtain the target layout in the Virtuoso design platform. The modified connections in the target layout are verified using design rule checking standards, and after verification, the connection labels of the module outgoing connections in the target layout are updated.

3. The method for adding chip layout labels according to claim 2, characterized in that, The process of verifying the design rule check criteria for modified connections in the target layout, and updating the connection labels of the module outgoing connections in the target layout after verification, includes: The geometric dimensions of the modified connections in the target layout are compared with a preset geometric dimension threshold range; wherein, the geometric dimensions of the layout connections include connection width, connection spacing, connection extension value, and the enclosure size of the connection to vias / contact holes; When the modified geometry of the connection is within the geometry threshold range, the connection labels of the module lead-out connections in the target layout are updated. Otherwise, the geometric dimensions of the modified connections in the target layout are adjusted, and when the adjusted geometric dimensions of the modified connections are within the geometric dimension threshold range, the connection labels of the module lead-out connections in the target layout are updated.

4. The method for adding chip layout labels according to claim 2 or 3, characterized in that, The step of updating the connection labels of the module outgoing lines in the target layout includes: Establish and activate the correspondence between the devices in the target layout and the devices in the target circuit diagram, so as to force the target circuit diagram and the target layout into a non-corresponding synchronization connection state; In the synchronized connection state, a preset connection label is added to the module outgoing connection of the target layout, or the connection name of the module outgoing connection in the target layout is obtained and the connection name of the module outgoing connection is added as its connection label.

5. The method for adding chip layout labels according to claim 2, characterized in that, The step of comparing the connection labels of all module leads in the target layout with the connection labels of all module leads in the corresponding target circuit diagram, and filtering out the connection labels in the target circuit diagram and the connection labels in the target layout that have different comparison results, includes: Call the physical verification tool calibre to compare the connection labels of all module leads in the target layout with the connection labels of all module leads on the corresponding target circuit diagram, and automatically generate a report text from the comparison results; A script capable of recognizing text content is invoked to extract the comparison results from the report text and filter out the connection labels in the target circuit diagram and the connection labels in the target layout that have different comparison results.

6. The method for adding chip layout labels according to claim 5, characterized in that, The process involves calling the physical verification tool calibre to compare the connection labels of all module leads in the target layout with the connection labels of all module leads on the corresponding target circuit diagram, and automatically generating a report text with a fixed format, including: Use the physical verification tool calibre to locate the same device in the target layout and the target circuit diagram; Using the physical verification tool calibre, the connection labels of the module leads of the same device in the target layout are compared with the connection labels of the module leads in the target circuit diagram, and the comparison results are automatically generated into a report text with a fixed format.

7. The method for adding chip layout labels according to claim 1, characterized in that, The step of updating the corresponding connection labels in the target layout based on the selected connection labels in the target circuit diagram includes: Using the built-in skill function in the Virtuoso design platform, perform a search operation for connection labels within the visual editing interface of the target layout to find and mark the selected connection labels in the target layout. A script with text editing capabilities is invoked, and the script is used to update the connection labels in the selected target circuit diagram to the corresponding connection labels in the target layout.

8. An automatic chip layout label adding system, characterized in that, include: An acquisition unit is used to acquire a target circuit diagram; wherein the target circuit diagram is obtained by modifying an initial circuit diagram, and the module lead-out connections of the target circuit diagram all have connection labels; An adjustment unit is used to modify an initial layout to obtain a target layout based on the target circuit diagram, and to update the connection labels of the module leads of the target layout; wherein the initial layout is generated based on the initial circuit diagram, and each module lead of the initial layout has a connection label. The filtering unit is used to compare the connection labels of all module leads in the target layout with the connection labels of all module leads in the corresponding target circuit diagram, and filter out the connection labels in the target circuit diagram and the connection labels in the target layout that are different in comparison results. The update unit is used to update the corresponding connection labels in the target layout based on the connection labels in the selected target circuit diagram.

9. An electronic device, characterized in that, The electronic device includes: One or more processors; A storage device for storing one or more programs that, when executed by one or more processors, cause the electronic device to implement the chip layout labeling method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by the computer's processor, causes the computer to perform the method for adding a chip layout label as described in any one of claims 1 to 7.

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