Display driving circuit, chip and display device

Abstract

This disclosure relates to the field of display technology, including display driver circuits, chips, and display devices. By adding a first transistor connected to a startup current source and a second transistor connected to the first transistor to a conventional startup module; in a first stage, the third and sixth transistors are turned off, causing the first, second, seventh, and eighth transistors to turn off as well. This allows the startup current output from the startup current source to be used entirely to charge the fourth and fifth transistors, resulting in the gate voltage of the fourth transistor continuously increasing to a level greater than the voltage at which the loop stabilizes. At this point, the current flowing through the fourth transistor is greater than the current flowing through the fourth transistor when the loop stabilizes, thereby improving the pull-down slew rate in the first stage and further increasing the current build-up speed; alternatively, it can reduce the parasitic capacitance of the fourth transistor's gate, thereby improving the loop stability in the small-signal stage.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display driver circuit, chip, and display device. Background Technology

[0002] Currently, display devices typically include a display panel composed of multiple light-emitting units. The brightness of each light-emitting unit is determined by its driving current; that is, the greater the driving current, the brighter the light-emitting unit.

[0003] When the driving current of the light-emitting unit needs to change, the driving current will not immediately jump from the current value to the target value. Instead, it will take a period of time for the current value to stabilize at the target value. The time it takes for the current value to change to the target value and to stabilize at the target value is called the current settling time.

[0004] A longer current settling time results in a slower current build-up speed, which can lead to a decrease in the display performance of the device. Therefore, reducing the current settling time and increasing the current build-up speed is a problem that urgently needs to be solved. Summary of the Invention

[0005] In view of this, this disclosure proposes a display driver circuit, chip, and display device that can improve the pull-down slew rate in the first stage of the current build-up process or improve the loop stability in the small signal stage.

[0006] According to one aspect of this disclosure, a display driving circuit is provided, comprising: a startup module connected to a current replication module to start the current replication module; the current replication module is used to replicate a reference current of a global reference current source to drive a light-emitting unit connected to the current replication module to emit light; the startup module includes:

[0007] The startup branch includes: a startup current source for providing startup current, a first transistor connected to the startup current source, and a second transistor connected to the first transistor;

[0008] The first branch includes: a third transistor connected to the current replication module, a fourth transistor connected to the third transistor and the startup current source respectively, and a fifth transistor connected to the second transistor and the startup current source respectively.

[0009] The second branch includes: a sixth transistor connected to the current replication module and the first transistor respectively, a seventh transistor connected to the first transistor, and an eighth transistor connected to the seventh transistor and the second transistor respectively.

[0010] In the initial stage of the current build-up process, the third and sixth transistors are turned off, causing the first, second, seventh, and eighth transistors to turn off as well, so that the startup current output by the startup current source is used entirely to charge the fourth and fifth transistors.

[0011] In one possible implementation, the fourth transistor and the fifth transistor are N-type MOS transistors, and the gates of the fourth transistor and the fifth transistor are connected to the output terminal of the startup current source.

[0012] In one possible implementation, the first transistor and the second transistor are N-type MOS transistors, and the gate of the first transistor is connected to the gate of the second transistor.

[0013] The drain of the second transistor is connected to the output terminal of the startup current source, and the source of the second transistor is connected to the fifth transistor.

[0014] The drain of the first transistor is connected to the sixth transistor, and the drain of the first transistor is shorted to the gate; the source of the first transistor is connected to the seventh transistor.

[0015] In one possible implementation, in a second stage following the first stage, the third and sixth transistors are turned on, causing the first, second, seventh, and eighth transistors to turn on, so that a portion of the startup current output by the startup current source is used to charge the fourth and fifth transistors, and another portion flows into the fifth and eighth transistors through the second transistor.

[0016] Wherein, the ratio of the current flowing through the third transistor to the current flowing through the sixth transistor is A; the ratio of the current flowing through the fourth transistor to the current flowing through the fifth transistor is N; the equivalent transconductance of the third transistor is proportional to B and N, and inversely proportional to A; the current regulation amplitude in the second stage is smaller than the current regulation amplitude in the first stage.

[0017] In one possible implementation, the gate parasitic capacitance of the fourth transistor makes the pull-down slew rate of the first stage a desired slew rate, which is the pull-down slew rate of the first stage when the first and second transistors are not configured and the startup current is shunt by the fifth and eighth transistors; at the same time, the frequency of the pole corresponding to the gate parasitic capacitance of the fourth transistor is within a desired range.

[0018] In one possible implementation, the third transistor and the sixth transistor are P-type MOS transistors, and the seventh transistor and the eighth transistor are N-type MOS transistors; the sources of the third transistor and the sixth transistor are connected to the power supply voltage, and the gate of the sixth transistor is connected to the current replication module;

[0019] The drain of the third transistor is connected to the drain of the fourth transistor, the gate of the fourth transistor is connected to the gate of the fifth transistor, and the source of the fourth transistor and the source of the fifth transistor are connected to a reference ground.

[0020] The drain of the sixth transistor is coupled to the drain of the seventh transistor through the first transistor; the gate of the seventh transistor is connected to the gate of the eighth transistor, the source of the seventh transistor and the source of the eighth transistor are connected to reference ground, and the gate and drain of the seventh transistor are short-circuited.

[0021] The drains of the fifth transistor and the eighth transistor are connected to the second transistor.

[0022] In one possible implementation, the current replication module includes a capacitor and a switching network;

[0023] The capacitor is connected between the gate of the third transistor and the global reference current source;

[0024] The switching network configures the third transistor as a diode connection during the sampling phase and charges the capacitor;

[0025] During the hold phase, the switching network configures the third and fourth transistors as common-source amplifiers.

[0026] According to another aspect of this disclosure, a chip is provided that includes the display driver circuit described above.

[0027] According to another aspect of this disclosure, a display device is provided, including a display unit and a display driving circuit as described above, wherein the display driving circuit is connected to a light-emitting unit in the display unit to drive the light-emitting unit to emit light.

[0028] In one possible implementation, the display unit includes a display panel, which includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0029] By adding a first transistor MN5 connected to a startup current source and a second transistor MN6 connected to the first transistor MN5 to the traditional startup module; in the initial stage of the current build-up process, the third transistor MP3 and the sixth transistor MP4 are turned off, causing the first transistor, the second transistor MN6, the seventh transistor MN4, and the eighth transistor MN3 to be turned off, so that the startup current output by the startup current source is used entirely to charge the fourth transistor MN1 and the fifth transistor MN2; in the first stage, the startup current source can directly charge the gates of the fourth transistor MN1 and the fifth transistor MN2, causing the gate voltage of the fourth transistor MN1 to continuously rise to a level greater than the voltage when the loop is stable. At this time, the current flowing through the fourth transistor MN1 is greater than the current flowing through the fourth transistor MN1 when the loop is stable, thereby improving the pull-down slew rate in the first stage and further improving the current build-up speed; or, the parasitic capacitance of the gate of the fourth transistor MN1 can be reduced, thereby improving the loop stability in the second stage.

[0030] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0031] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0032] Figure 1 A schematic diagram of a conventional display driving circuit according to an embodiment of the present disclosure is shown;

[0033] Figure 2 A schematic diagram of a conventional display driving circuit according to another embodiment of the present disclosure is shown;

[0034] Figure 3 A schematic diagram showing the equivalent transconductance of a loop in a conventional display driving circuit according to an embodiment of the present disclosure is shown.

[0035] Figure 4 A schematic diagram of a display driving circuit according to an embodiment of the present disclosure is shown. Detailed Implementation

[0036] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0037] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0039] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0040] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0041] Currently, a drive current is typically output to the light-emitting units in the display panel of a display device through a display driver circuit to drive the light-emitting units to emit light. Figure 1 A schematic diagram of a conventional display driving circuit according to an embodiment of the present disclosure is shown. For example... Figure 1 As shown, a conventional display driving circuit includes: a startup module 100, a current replication module 200, and a global reference current source 300.

[0042] The startup module 100 is connected to the current replication module 200 to start the current replication module 200. For example... Figure 1As shown, the startup module 100 includes: a bias current source IDC, a third transistor MP3, a fourth transistor MN1, and a fifth transistor MN2. The bias current source IDC is used to provide a constant reference current.

[0043] For example, the fourth transistor MN1 and the fifth transistor MN2 are N-type MOS transistors. The gates of the fourth transistor MN1 and the fifth transistor MN2 are connected. The drain of the fifth transistor MN2 is connected to the output terminal of the bias current source IDC. The drain of the fifth transistor MN2 is shorted to its gate, and the source of the fifth transistor MN2 is grounded. The drain of the fourth transistor MN1 is connected to the drain of the third transistor MP3, and the source of the fourth transistor MN1 is connected to the reference ground. The source of the third transistor MP3 is connected to the power supply voltage.

[0044] The fifth transistor MN2 is used to convert the reference current into the gate voltage of the fifth transistor MN2, thereby providing the gate voltage for the gate of the fourth transistor MN1; the fourth transistor MN1 outputs a bias current through its drain based on the gate voltage.

[0045] The global reference current source 300 is used to provide a reference current IREF2 to the current replication module 200. The current replication module 200 is used to replicate the reference current of the global reference current source 300 and use the replicated drive current IOUT to drive the light-emitting unit LED connected to the current replication module 200 to emit light.

[0046] The current replication module 200 includes a capacitor, a switching network, and a ninth transistor MP2 and a tenth transistor MP1. The capacitor is connected between the gate of the third transistor MP3 and the global reference current source 300. During the sampling phase, the switching network configures the third transistor MP3 as a diode connection and charges the capacitor; during the holding phase, the switching network configures the third transistor MP3 and the fourth transistor MN1 as a common-source amplifier.

[0047] For example, the ninth transistor MP2 and the tenth transistor MP1 are P-type MOS transistors. One end of the capacitor is connected to the gate of the third transistor MP3. The switching network includes a first switch, a second switch, a third switch, and a fourth switch. The first terminals of the first and second switches are connected to the other end of the capacitor; the second terminal of the first switch is connected to the reference voltage VCRES of the capacitor; and the second terminal of the second switch is connected to the drain of the ninth transistor MP2.

[0048] The first terminal of the third switch is connected to the gate of the third transistor MP3, and the second terminal is connected to the drain of the third transistor MP3; the first terminal of the fourth switch is connected to the gate of the tenth transistor MP1, and the second terminal is connected to the drain of the third transistor MP3.

[0049] The drain of the ninth transistor MP2 is connected to the source of the tenth transistor MP1. The source of the ninth transistor MP2 is connected to the power supply voltage, and the gate of the ninth transistor MP2 is connected to the global reference current source 300. The drain of the tenth transistor MP1 is connected to the reference ground through the light-emitting unit LED.

[0050] For example, the global reference current source 300 includes an amplifier OPA1 and an eleventh transistor MP0. The eleventh transistor MP0 is a P-type MOSFET. The amplifier OPA1 includes a non-inverting input terminal, an inverting input terminal, and an output terminal; the inverting input terminal is used to input the reference voltage Vref, the non-inverting input terminal is connected to the drain of the eleventh transistor MP0, and the output terminal is connected to the gate of the eleventh transistor MP0 and the gate of the ninth transistor MP2. The drain of the eleventh transistor MP0 is grounded through the reference current source IREF2.

[0051] The display driver circuit operates in either a sampling or holding phase under the control of a switching network. In the sampling phase, the voltage difference between the gate voltage Vgatep of the third transistor MP3 (corresponding to the drain current output from the fourth transistor MN1) and the reference voltage VCRES of the capacitor is stored in the capacitor. In the holding phase, the stored charge is used to force the drain voltage of the ninth transistor MP2 to be equal to the reference voltage VCRES through a loop formed by the third transistor MP3, the fourth transistor MN1, the ninth transistor MP2, and the tenth transistor MP1. This allows the ninth transistor MP2 to accurately replicate the current of the eleventh transistor MP0, achieving constant current driving of the light-emitting unit.

[0052] Based on the above principle, during the sampling phase, the first and third switches are closed, while the second and fourth switches are open. At this time, the gate and drain of the third transistor MP3 are short-circuited, making MP3 equivalent to a diode. The gate voltage Vgatep of MP3 is determined by the drain current output of the fourth transistor MN1, which is provided by the bias current source IDC and the third transistor MP3. The drain of the ninth transistor MP2 is floating and has no current; the gate of the tenth transistor MP1 is floating and does not operate. Correspondingly, the magnitude of the charge Q stored in the capacitor is: Q = (Vgatep - VCRES) Cap. Where VCRES represents the reference voltage of the capacitor, Vgatep represents the gate voltage of the third transistor MP3, and Cap represents the capacitance value of the capacitor.

[0053] During the holding phase, the first and third switches are open, and the second and fourth switches are closed. At this time, the third transistor MP3 and the fourth transistor MN1 form a common-source amplifier. The input is the gate of the third transistor MP3, and the output is the drain of the third transistor MP3. The tenth transistor MP1, the ninth transistor MP2, the third transistor MP3, and the fourth transistor MN1 form a loop.

[0054] The holding phase includes a first stage (or large-signal stage) at the initial stage of the current build-up process and a second stage (or small-signal stage) following the first stage. The first stage involves rapidly increasing the drive current to bring it as close as possible to the target value. The second stage involves precisely adjusting the current to the target value once it is close, with the adjustment range being smaller than that of the first stage. In one example, the drive circuit can switch from the first stage to the second stage when Vgatep - Vov ≤ a preset voltage value; where Vgatep represents the gate voltage of the third transistor MP3, and Vov represents the preset overdrive voltage, which can be 200mV or other values. This embodiment does not limit the value of the preset voltage. Alternatively, the drive circuit can determine the timing of switching from the first stage to the second stage in other ways; this embodiment does not limit the method by which the drive circuit determines the timing of switching to the second stage.

[0055] In the initial stage of the holding phase, the initial value of the VCR potential is the power supply voltage AVDD. Due to the conservation of charge in the capacitor, the voltage Vgatep of the gate of the third transistor MP3 will be raised, causing the third transistor MP3 to be turned off.

[0056] The rate at which the gate voltage of the tenth transistor MP1 builds up determines the rate at which the drive current IOUT builds up. That is, the faster the gate voltage of the tenth transistor MP1 builds up, the faster the drive current IOUT builds up, and the shorter the current build-up time of IOUT.

[0057] In the first stage, the rate at which the gate voltage of the tenth transistor MP1 builds up is determined by the drain current output from the fourth transistor MN1, i.e., the pull-down slew rate is I. MN1 / C1, where I MN1 C1 represents the drain current of the fourth transistor MN1, and C1 represents the parasitic capacitance of the gate of the fourth transistor MN1. Slew rate refers to the maximum rate at which the gate voltage of the tenth transistor MP1 can change per unit time.

[0058] In the second stage, the rate at which the gate voltage of the ten transistors builds up is determined by the loop bandwidth, which refers to the loop's response speed to changing signals. In this embodiment, the loop bandwidth indicates the speed at which the drive current eventually adjusts to the target value. The loop bandwidth is related to the transconductance gm of the third transistor MP3.

[0059] When the loop reaches a stable state, that is, when the loop voltage is stable and the current is balanced, the gate voltage of the fourth transistor MN1 stabilizes at V1, and the current flowing through the fourth transistor MN1 is N. IREF. The gate voltage of the third transistor MP3 remains consistent with the gate voltage during the sampling phase, which is still Vgatep. Since the charge stored in the capacitor remains unchanged during the sampling and holding phases, the drain voltage VCR of the ninth transistor MP2 is equal to VCRES. This allows the ninth transistor MP2 to accurately replicate the current value of the eleventh transistor MP0, thereby achieving constant current output.

[0060] As can be seen from the above principle, the loop bandwidth and slew rate affect the current build-up speed of the drive current. The smaller the current build-up speed, the larger the channel current may need to be turned on in order to ensure that the light-emitting unit reaches the desired brightness, resulting in wasted power consumption.

[0061] Based on the above-mentioned technical problems, some implementations propose an alternative display driving circuit. Figure 2 A schematic diagram of another display driving circuit according to an embodiment of the present disclosure is shown. Figure 2 As shown, Figure 2 Another display driver circuit shown is Figure 1 The difference in the display driver circuit shown lies in the startup module 100.

[0062] Figure 2 In the startup module 100, in addition to the bias current source, the third transistor MP3, the fourth transistor MN1, and the fifth transistor MN2, it also includes a sixth transistor MP4, a seventh transistor MN4, and an eighth transistor MN3. Exemplarily, the seventh transistor MN4 and the eighth transistor MN3 are N-type MOSFETs, and the sixth transistor MP4 is a P-type MOSFET. The source of the sixth transistor MP4 is connected to the power supply voltage, and the gate of the sixth transistor MP4 is connected to the current replication module 200 (specifically, to one end of a capacitor).

[0063] The drain of the sixth transistor MP4 is connected to the drain of the seventh transistor MN4; the gate of the seventh transistor MN4 is connected to the gate of the eighth transistor MN3; the source of the seventh transistor MN4 and the source of the eighth transistor MN3 are connected to the reference ground; and the gate and drain of the seventh transistor MN4 are short-circuited; the drain of the eighth transistor MN3 is connected to the output terminal of the bias current source.

[0064] The current at the output of the bias current source supplies power to the drain of the fifth transistor MN2 and the drain of the eighth transistor MN3, resulting in the sum of the current flowing through the fifth transistor MN2 and the current flowing through the eighth transistor MN3 being the current IREF supplied to the output of the bias current source.

[0065] Furthermore, the ratio of the current I_MP3 flowing through the third transistor MP3 to the current I_MP4 flowing through the sixth transistor MP4 is A; the ratio of the current I_MN1 flowing through the fourth transistor MN1 to the current I_MN2 flowing through the fifth transistor MN2 is N; and the ratio of the current I_MN3 flowing through the eighth transistor MN3 to the current I_MN4 flowing through the seventh transistor MN4 is B. That is, I_MP3:I_MP4=A:1, I_MN2:I_MN1=1:N, I_MN4:I_MN3=1:B. If the current flowing through MN2 is I_MN2=I, then according to the above ratios, I_MN1=N. I, I_MP4=N I / A, I_MN4=BNI / A. Optionally, N, A, and B are specific values ​​or a range of values; N, A, and B can be set according to actual circuit requirements, and this embodiment does not limit the setting method of N, A, and B.

[0066] based on Figure 2 The operation of the startup module 100 and the display driver circuit includes:

[0067] During the sampling phase, S1 and S3 are closed, and S2 and S4 are open. At this time, MP3 is connected in diode form. According to the principle of the sampling phase above, the magnitude of the charge Q stored in capacitor Cap is: Q = (Vgate - VCRES). Cap. Meanwhile, MP4 replicates the current of MP3 at a ratio of 1:A, MN3 replicates the current of MN4 at a ratio of B:1, and MN1 replicates the current of MN2 at a ratio of N:1.

[0068] During the hold phase, S1 and S3 are open, and S2 and S4 are closed. MP3 and MN1 form a common-source amplifier, with the gate of MP3 as the input and the drain of MP3 as the output. Initially, the VCR potential is AVDD. Due to the conservation of charge in capacitor Cap, the gate voltage Vgatep of MP3 is raised, causing MP3 to turn off. The turn-off of MP3 then causes MP4, MN4, and MN3 to all turn off. At this time, the current flowing through MN1 is N. IREF.

[0069] In the first stage, the pull-down slewing rate IMN1 / C1 = N IREF / C1.

[0070] In the second stage, refer to Figure 3 The diagram shows the equivalent transconductance Gm of the loop, when the gate of MP3 has If the voltage V changes, then MP3 has gm3. The current change of V, where gm3 represents the transconductance of MP3. Correspondingly, MP4 has gm3. A current change of V / A, NM3 has B gm3 The current change of V / A, since I_NM3+I_NM2=IREF, therefore, if NM3 has B gm3 For a current change of V / A, to ensure that IREF remains constant, MN2 needs to have a current change of the same magnitude but opposite direction to NM3. Correspondingly, MN1 needs a current change BN. gm3 The current changes by V / A. At this time, the magnitude of the drive current Iout is (BN / A+1). gm3 V. The equivalent transconductance of the loop is Gm = Iout / V = (BN / A + 1) gm3. At this time, the loop bandwidth is greater than... Figure 1 The loop bandwidth of the second stage is shown, which makes the current build-up speed of the second stage faster.

[0071] For details on the stability of the loop consisting of MP1, MP2, MP3, and MN1, please refer to the above embodiments. This embodiment will not repeat the details here.

[0072] exist Figure 2 In another display driver circuit shown, by properly setting the values ​​of B, N, and A, the slew rate in the first stage can be guaranteed to be greater than [value missing]. Figure 1 The swing rate of the first stage is shown. Specifically, according to Figure 2 From the structure, if the current flowing through MN2 is I_MN2=I, then we can obtain:

[0073] IREF = BNI / A + I (1);

[0074] Let the total power consumption of the entire loop be Itotal, then we can obtain

[0075] Itotal = NI + NI / A (2);

[0076] Substituting formula (2) into formula (1) yields:

[0077] Itotal = [(A+1)] N / (BN+A)] IREF+ IREF (3).

[0078] Assume IREF = 1 A, B=2, A=4, N=8; then the total power consumption Itotal=3 A.

[0079] Equivalent transconductance Gm = (BN / A + 1) gm3=5 gm3;

[0080] SR = N IREF / C1=8 / C1;

[0081] The current value of the MP3 branch is 1.6. A, In the above formula, gm3 represents PM3 and the current is 1.6. The result of A.

[0082] Assumption Figure 1 The current value of MN1 is 3 A, then the equivalent transconductance of MP3 is:

[0083] Gm=3 A / 1.6uA gm3=1.875 gm3; slew rate SR=3 A / C1;

[0084] so Figure 2 The display driver circuit shown is superior to other circuits in terms of both slew rate and gm. Figure 1 The display driver circuit shown is shown. Therefore, Figure 2 The display driver circuit shown has a faster current build-up speed in both the first and second stages than... Figure 1 The display driver circuit shown is shown.

[0085] However, Figure 2 The slew rate optimization of the display driving circuit shown is still limited. Based on this, this embodiment... Figure 2 Based on the display driver circuit shown, the startup module 100 is further optimized, and the slew rate can be increased as needed to further improve the current build-up speed of the display driver circuit. Figure 4 A schematic diagram of a display driving circuit according to an embodiment of the present disclosure is shown. For example... Figure 4 As shown, the display driving circuit includes: a startup module 100.

[0086] The startup module 100 is connected to the current replication module 200 to start the current replication module 200. The current replication module 200 is used to replicate the reference current of the global reference current source 300 to drive the light-emitting unit connected to the current replication module 200 to emit light. The functions and related descriptions of the current replication module 200 and the global reference current source 300 are detailed in the above embodiments and will not be repeated here. In this embodiment, the startup module 100 includes:

[0087] The startup branch includes: a startup current source IDC for providing startup current, a first transistor MN5 connected to the startup current source, and a second transistor MN6 connected to the first transistor MN5;

[0088] The first branch includes: a third transistor MP3 connected to the current replication module 200, a fourth transistor MN1 connected to the third transistor and the startup current source respectively, and a fifth transistor MN2 connected to the second transistor MN6 and the startup current source respectively.

[0089] The second branch includes: a sixth transistor MP4 connected to the current replication module 200 and the first transistor MN5 respectively, a seventh transistor MN4 connected to the first transistor MN5 respectively, and an eighth transistor MN3 connected to the seventh transistor MN4 and the second transistor MN6 respectively.

[0090] In the first stage, the third transistor MP3 and the sixth transistor MP4 are turned off, which causes the first transistor, the second transistor MN6, the seventh transistor MN4 and the eighth transistor MN3 to be turned off, so that the starting current output by the starting current source is used entirely to charge the fourth transistor MN1 and the fifth transistor MN2.

[0091] For example, taking the fourth transistor MN1 and the fifth transistor as N-type MOS transistors, the gates of the fourth transistor MN1 and the fifth transistor are connected to the output terminal of the startup current source. In this way, when the first transistor, the second transistor MN6, the seventh transistor MN4 and the eighth transistor MN3 are all turned off, the startup current is all input to the gates of the fourth transistor MN1 and the fifth transistor, thereby increasing the voltage of the gate of the fourth transistor MN1.

[0092] For example, the first transistor MN5 and the second transistor MN6 are N-type MOS transistors. The gate of the first transistor MN5 is connected to the gate of the second transistor MN6. The drain of the second transistor MN6 is connected to the output terminal of the startup current source, and the source of the second transistor MN6 is connected to the fifth transistor MN2. The drain of the first transistor MN5 is connected to the sixth transistor MP4, and the drain of the first transistor MN5 is shorted to its gate. The source of the first transistor MN5 is connected to the seventh transistor MN4.

[0093] The third transistor MP3 and the sixth transistor MP4 are P-type MOSFETs, and the seventh transistor MN4 and the eighth transistor MN3 are N-type MOSFETs. The sources of the third transistor MP3 and the sixth transistor MP4 are connected to the power supply voltage, and the gate of the sixth transistor MP4 is connected to the current replication module 200. The drain of the third transistor MP3 is connected to the drain of the fourth transistor MN1, the gate of the fourth transistor MN1 is connected to the gate of the fifth transistor MN2, and the sources of the fourth transistor MN1 and the fifth transistor MN2 are connected to the reference ground. The drain of the sixth transistor MP4 is coupled to the drain of the seventh transistor MN4 through the first transistor MN5; that is, the drain of the sixth transistor MP4 is connected to the drain of the first transistor MN5, and the source of the first transistor MN5 is connected to the drain of the seventh transistor MN4.

[0094] The gate of the seventh transistor MN4 is connected to the gate of the eighth transistor MN3. The source of the seventh transistor MN4 and the source of the eighth transistor MN3 are connected to the reference ground, and the gate and drain of the seventh transistor MN4 are shorted. The drain of the fifth transistor MN2 and the drain of the eighth transistor MN3 are connected to the second transistor MN6 (i.e., to the source of the second transistor MN6).

[0095] As described in the above embodiment, in the initial stage of the holding phase, the initial value of the VCR potential is AVDD. Due to the conservation of capacitor charge, the gate voltage Vgatep of MP3 will be raised, causing MP3 and MP4 to be cut off, and thus MN4 and MN5 to be cut off. The cutoff of MN5 causes MN6 to be cut off, and the cutoff of MN4 causes MN3 to be cut off. Therefore, the startup current source directly charges the gates of MN2 and MN1, causing the VGN potential to rise. If the VGN potential continues to rise to a level greater than the loop stabilization potential V1 (i.e., the VGN potential reaches the overshoot voltage), the current flowing through MN1 (i.e., the overshoot current) is greater than the current N flowing through MN1 when the loop is stable. IREF. The pull-down slew rate is the ratio of the current flowing through MN1 to the capacitance C1 of the parasitic gate capacitance of MN1. Therefore, if the current flowing through MN1 is greater than N... IREF, the corresponding pulldown slew rate is greater than N IREF / C1, which is greater than Figure 2 and Figure 3 The pull-down slew rate of the display driver circuit shown in the first stage can thus improve the loop establishment speed in the first stage.

[0096] In the second stage, the process of establishing the loop is referenced. Figure 3At this time, the third transistor MP3 and the sixth transistor MP4 are turned on, which causes the first transistor, the second transistor MN6, the seventh transistor MN4 and the eighth transistor MN3 to be turned on, so that part of the starting current output by the starting current source is used to charge the fourth transistor MN1 and the fifth transistor MN2, and the other part flows into the fifth transistor MN2 and the eighth transistor MN3 through the second transistor MN6.

[0097] The ratio of the current flowing through the third transistor MP3 to the current flowing through the sixth transistor MP4 is A; the ratio of the current flowing through the fourth transistor MN1 to the current flowing through the fifth transistor MN2 is N; the ratio of the current flowing through the fourth transistor MN1 to the current flowing through the fifth transistor MN2 is N; the equivalent transconductance of the third transistor MP3 is proportional to B and N, and inversely proportional to A.

[0098] In other embodiments, if Figure 2 The pull-down slew rate of the display driver circuit shown is already large enough (e.g., meeting the user's desired pull-down slew rate), meaning there's no need to further increase the pull-down slew rate. Therefore, the parasitic capacitance C1 of the gate of MN1 can be reduced. At this point, since a smaller C1 results in less charge stored in the parasitic capacitance, the overshoot voltage at the VGN potential is lower, thereby reducing the overshoot current. Figure 4 The pull-down slew rate of the display driver circuit shown in the initial stage of the holding phase is... Figure 2 The display driving circuit shown maintains a relatively consistent pull-down slew rate during the initial stage of the holding phase. This means the gate parasitic capacitance of the fourth transistor MN1 ensures that the pull-down slew rate in the first stage is the desired slew rate. The desired slew rate refers to the pull-down slew rate in the first stage when the first transistor MN5 and the second transistor MN6 are not configured, and the startup current is shunted by the fifth transistor MN2 and the eighth transistor MN3. Figure 2 The pull-down slew rate N of the display driver circuit shown IREF / C1). Simultaneously, in the second stage, each node with resistance and capacitance to ground in the loop composed of MP1, MP2, MP3, and MN1 introduces a pole. The parasitic capacitance of the MP1 gate is the primary pole, and all other poles are secondary poles. That is, the parasitic capacitance of the MN1 gate is a secondary pole, and the lower the frequency of the secondary pole, the less stable the loop. The frequency of this secondary pole is negatively correlated with the parasitic capacitance of the MN1 gate; that is, the smaller the parasitic capacitance of the MN1 gate, the higher the frequency of the secondary pole, and the more stable the loop. Based on this, the gate parasitic capacitance of the fourth transistor MN1 ensures that the frequency of the pole corresponding to the gate parasitic capacitance of the fourth transistor MN1 (i.e., the secondary pole) is within the desired range, thereby improving the stability of the loop and ensuring that the drive current IOUT is relatively stable compared to... Figure 2 The display driver circuit shown can establish up more smoothly without overshoot.

[0099] Optionally, the relevant descriptions of the current replication module 200 and the global reference current source 300 in this embodiment are detailed in the above embodiments, and will not be repeated here.

[0100] In summary, the display driving circuit provided in this embodiment, by adding a first transistor MN5 connected to a startup current source and a second transistor MN6 connected to the first transistor MN5 on the basis of a traditional startup module, in the first stage, the third transistor MP3 and the sixth transistor MP4 are turned off, causing the first transistor, the second transistor MN6, the seventh transistor MN4 and the eighth transistor MN3 to be turned off, so that the startup current output by the startup current source is used entirely to charge the fourth transistor MN1 and the fifth transistor MN2. In the first stage, the startup current source can directly charge the gates of the fourth transistor MN1 and the fifth transistor MN2, causing the gate voltage of the fourth transistor MN1 to continuously rise to a level greater than the voltage when the loop is stable. At this time, the current flowing through the fourth transistor MN1 is greater than the current flowing through the fourth transistor MN1 when the loop is stable, thereby improving the pull-down slew rate in the first stage and further improving the current build-up speed; or, the parasitic capacitance of the gate of the fourth transistor MN1 can be reduced, thereby improving the loop stability in the second stage.

[0101] This application also provides a chip that includes the display driving circuit described in at least one of the above embodiments.

[0102] This application also provides a display device, which includes a display unit and a display driving circuit provided in at least one of the above embodiments. The display driving circuit is connected to a light-emitting unit in the display unit to drive the light-emitting unit to emit light.

[0103] Optionally, the display unit includes a display panel, which includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0104] This application also provides an electronic device, which includes the display driver circuit or chip or display device described in at least one of the above embodiments.

[0105] For example, the electronic devices in this embodiment include, but are not limited to, desktop computers, televisions, mobile devices with large screens such as mobile phones and tablets, and other common electronic devices that require multiple chips to be cascaded together to achieve driving.

[0106] For example, electronic devices can also be user equipment (UE), mobile devices, user terminals, terminals, handheld devices, computing devices, or in-vehicle devices, etc. Examples of terminals include: displays, smartphones or portable devices, mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, a server can be a local server or a cloud server.

[0107] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention, which is determined by the appended claims.

[0108] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0109] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0111] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A display driving circuit, characterized in that, include: A startup module is connected to the current replication module to start the current replication module from working. The current replication module is used to replicate the reference current of the global reference current source in order to drive the light-emitting unit connected to the current replication module to emit light. The startup module includes: The startup branch includes: a startup current source for providing startup current, a first transistor connected to the startup current source, and a second transistor connected to the first transistor; The first branch includes: a third transistor connected to the current replication module, a fourth transistor connected to the third transistor and the startup current source respectively, and a fifth transistor connected to the second transistor and the startup current source respectively. The second branch includes: a sixth transistor connected to the current replication module and the first transistor respectively, a seventh transistor connected to the first transistor, and an eighth transistor connected to the seventh transistor and the second transistor respectively. In the initial stage of the current build-up process, the third and sixth transistors are turned off, causing the first, second, seventh, and eighth transistors to turn off as well, so that the startup current output by the startup current source is used entirely to charge the fourth and fifth transistors.

2. The display driving circuit according to claim 1, characterized in that, The fourth and fifth transistors are N-type MOS transistors, and their gates are connected to the output terminal of the startup current source.

3. The display driving circuit according to claim 2, characterized in that, The first transistor and the second transistor are N-type MOS transistors, and the gate of the first transistor is connected to the gate of the second transistor; The drain of the second transistor is connected to the output terminal of the startup current source, and the source of the second transistor is connected to the fifth transistor. The drain of the first transistor is connected to the sixth transistor, and the drain of the first transistor is shorted to the gate; the source of the first transistor is connected to the seventh transistor.

4. The display driving circuit according to claim 2, characterized in that, In the second stage following the first stage, the third and sixth transistors are turned on, causing the first, second, seventh, and eighth transistors to turn on, so that a portion of the startup current output by the startup current source is used to charge the fourth and fifth transistors, and another portion flows into the fifth and eighth transistors through the second transistor. Wherein, the ratio of the current flowing through the third transistor to the current flowing through the sixth transistor is A; the ratio of the current flowing through the fourth transistor to the current flowing through the fifth transistor is N; the equivalent transconductance of the third transistor is proportional to B and N, and inversely proportional to A; the current regulation amplitude in the second stage is smaller than the current regulation amplitude in the first stage.

5. The display driving circuit according to claim 4, characterized in that, The gate parasitic capacitance of the fourth transistor makes the pull-down slew rate of the first stage the desired slew rate, which refers to the pull-down slew rate in the first stage when the first and second transistors are not set and the startup current is shunted by the fifth and eighth transistors; at the same time, it makes the frequency of the pole corresponding to the gate parasitic capacitance of the fourth transistor within the desired range.

6. The display driving circuit according to claim 4, characterized in that, The third and sixth transistors are P-type MOS transistors, and the seventh and eighth transistors are N-type MOS transistors; the sources of the third and sixth transistors are connected to the power supply voltage, and the gate of the sixth transistor is connected to the current replication module; The drain of the third transistor is connected to the drain of the fourth transistor, the gate of the fourth transistor is connected to the gate of the fifth transistor, and the source of the fourth transistor and the source of the fifth transistor are connected to a reference ground. The drain of the sixth transistor is coupled to the drain of the seventh transistor through the first transistor; the gate of the seventh transistor is connected to the gate of the eighth transistor, the source of the seventh transistor and the source of the eighth transistor are connected to reference ground, and the gate and drain of the seventh transistor are short-circuited. The drains of the fifth transistor and the eighth transistor are connected to the second transistor.

7. The display driving circuit according to claim 6, characterized in that, The current replication module includes a capacitor and a switching network; The capacitor is connected between the gate of the third transistor and the global reference current source; The switching network configures the third transistor as a diode connection during the sampling phase and charges the capacitor; During the hold phase, the switching network configures the third and fourth transistors as common-source amplifiers.

8. A chip comprising the display driving circuit according to any one of claims 1 to 7.

9. A display device, characterized in that, The device includes a display unit and a display driving circuit as described in any one of claims 1 to 7, wherein the display driving circuit is connected to a light-emitting unit in the display unit to drive the light-emitting unit to emit light.

10. The display device according to claim 9, characterized in that, The display unit includes a display panel, which includes at least one of the following: liquid crystal display panel, micro light-emitting diode display panel, light-emitting diode display panel, mini light-emitting diode display panel, quantum dot light-emitting diode display panel, organic light-emitting diode display panel, cathode ray tube display panel, digital light processing display panel, field emission display panel, plasma display panel, electrophoretic display panel, electrowetting display panel, and small-pitch display panel.

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