Laser chips and light-emitting devices

Abstract

This invention relates to the field of semiconductor manufacturing technology, and particularly to a laser chip and a light-emitting device. The laser chip includes a semiconductor stack, a first electrode, and a second electrode. The semiconductor stack includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially stacked along its lower surface to its upper surface. The first electrode is disposed on one side of the lower surface of the semiconductor stack and electrically connected to the first semiconductor layer. The second electrode is disposed on one side of the upper surface of the semiconductor stack and electrically connected to the second semiconductor layer. The second semiconductor layer has a ridge protrusion, and the second electrode is at least partially disposed on the ridge protrusion. The first minimum horizontal distance between at least a portion of the outer wall of the second electrode and the outer wall or cavity surface of the ridge protrusion is >0 μm. This configuration effectively avoids leakage current problems in the laser chip at the outer wall or cavity surface of the ridge protrusion, thereby improving the device's lifespan and reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a laser chip and a light-emitting device. Background Technology

[0002] Laser chips are the core functional units of semiconductor lasers, belonging to optoelectronic integrated devices. They achieve electro-optic energy conversion based on the stimulated emission effect of semiconductor materials and are core components in fields such as optical communication, lidar, and consumer electronics. The core structure of a laser chip consists of an active region, a confinement layer, and electrodes. The active region typically uses III-V compound semiconductors such as GaN, and energy level differences are formed through doping or quantum well design to provide conditions for carrier recombination and luminescence. The confinement layer utilizes the refractive index difference and barrier effect of the heterojunction to confine photons and carriers within the active region, significantly improving stimulated emission efficiency. The electrodes are responsible for injecting current to drive population inversion in the active region.

[0003] Laser chips offer advantages such as small size, low power consumption, fast response speed, and direct modulation. Based on gain medium and structure, they can be categorized into edge-emitting laser (EEL) chips and vertical-cavity surface-emitting laser (VCSEL) chips. The former exhibits strong beam directionality and is primarily used for long-distance optical communication; the latter enables two-dimensional array integration and is widely applied in 3D sensing, short-range data center interconnects, and other scenarios. Technological iterations are focusing on higher power, narrower linewidth, and higher integration.

[0004] Currently, laser chips commonly employ a ridge design to improve device performance. However, this poses a risk of leakage current, where current can diffuse from the ohmic contact layer to the ridge sidewalls, causing leakage. Conversely, current can also diffuse from the ohmic contact layer to the cavity surface, leading to leakage. This impacts the device's lifespan and reliability.

[0005] Therefore, how to avoid leakage current in lasers has become one of the technical problems that urgently need to be solved by those skilled in the art.

[0006] It should be noted that the information disclosed in this background section is intended only to enhance the understanding of the overall background of the present invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The present invention provides a laser chip, which includes a semiconductor stack, a first electrode and a second electrode.

[0008] The semiconductor stack has opposing upper and lower surfaces, and includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially stacked along the direction from the lower surface to the upper surface. A first electrode is disposed on one side of the lower surface of the semiconductor stack and electrically connected to the first semiconductor layer. A second electrode is at least partially disposed on one side of the upper surface of the semiconductor stack and electrically connected to the second semiconductor layer. The second semiconductor layer has a ridge protrusion, the ridge protrusion having an outer wall and a cavity surface. The second electrode is disposed on the ridge protrusion, and a first minimum horizontal distance from at least a portion of the outer wall of the second electrode to the outer wall or cavity surface of the ridge protrusion is >0 μm.

[0009] The present invention also provides a light-emitting device that employs any of the laser chips provided above.

[0010] The present invention provides a laser chip and a light-emitting device, which, by shrinking the second electrode inward, makes the first minimum horizontal distance between at least part of the outer side wall of the second electrode and the outer side wall or cavity surface of the ridge protrusion > 0 μm, thereby effectively reducing the possibility of current leakage from the outside and avoiding leakage problems of the laser chip on the outer side wall or cavity surface of the ridge protrusion, thereby improving the lifespan and reliability of the device.

[0011] Other features and advantages of the present invention will be set forth in the following description, and some of the technical features and advantages may be apparent from the description or learned by practicing the invention. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, some of the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of the laser chip provided in the first embodiment of the present invention; Figure 2 This is a partial three-dimensional schematic diagram of the laser chip provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the laser chip provided in the second embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the laser chip provided in the third embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the laser chip provided in the fourth embodiment of the present invention; Figure 6This is a schematic diagram of the structure of the laser chip provided in the fifth embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of the laser chip provided in the sixth embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of the laser chip provided in the seventh embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of the laser chip provided in the eighth embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of the laser chip provided in the ninth embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of the laser chip provided in the tenth embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of the laser chip provided in the eleventh embodiment of the present invention; Figure 13 This is a schematic diagram of the structure of the laser chip provided in the twelfth embodiment of the present invention.

[0014] Figure label: 10-First semiconductor layer; 12-Light-emitting layer; 14-Second semiconductor layer; 16-Ridge protrusion; 18-First electrode; 20-Second electrode; 22-Ohmic contact layer; 24-First ion implantation layer; 26-Second ion implantation layer; 28-Pad electrode; 30-Insulating layer; 32-Substrate; 50-Outer wall of the second electrode; 52-Outer wall of the ridge protrusion; 54-Outer wall of the ohmic contact layer; 60-Cavity surface; L1-First minimum horizontal spacing; L2-Second minimum horizontal spacing; W1-Width of the second electrode; W2-Width of the ridge protrusion; W3-Width of the ohmic contact layer; W5-Width of the first ion implantation layer; W6-Width of the second ion implantation layer; W7-Width of the overlap between the second electrode and the first ion implantation layer; W8-Width of the overlap between the ohmic contact layer and the second ion implantation layer; H1-Thickness of the first ion implantation layer; H2-Thickness of the ohmic contact layer; H3-Thickness of the second ion implantation layer; H4-Thickness of the ridge protrusion. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0016] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof mean "at least comprising."

[0017] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of the laser chip provided in the first embodiment of the present invention. Figure 2 This is a partial three-dimensional schematic diagram of a laser chip provided in the first embodiment of the present invention. To achieve at least one or more of the aforementioned advantages, the first embodiment of the present invention provides a laser chip. As shown in the figure, the laser chip includes a semiconductor stack, a first electrode 18, and a second electrode 20.

[0018] The semiconductor stack has opposing upper and lower surfaces, and includes a first semiconductor layer 10, a light-emitting layer 12, and a second semiconductor layer 14 stacked sequentially along the direction from the lower surface to the upper surface.

[0019] The first semiconductor layer 10 can be an N-type semiconductor layer, which can provide electrons to the light-emitting layer 12 under the influence of a power source. In some embodiments, the first semiconductor layer 10 includes an N-type doped nitride layer. The N-type doped nitride layer may include N-type impurities. N-type impurities may include one or a combination of Si, Ge, and Sn.

[0020] The light-emitting layer 12 can be a quantum well (QW) structure. In some embodiments, the light-emitting layer 12 can also be a multiple quantum well (MQW) structure, wherein the multiple quantum well structure includes multiple quantum well layers (Wells) and multiple quantum barrier layers arranged alternately in a repeating manner, such as a GaN / AlGaN, InAlGaN / InAlGaN, or InGaN / AlGaN multi-quantum well structure. Furthermore, the composition and thickness of the well layers within the light-emitting layer 12 determine the wavelength of the generated light. To improve the luminous efficiency of the light-emitting layer 12, this can be achieved by changing the depth of the quantum wells, the number of paired quantum wells and quantum barriers, the thickness, and / or other characteristics within the light-emitting layer 12.

[0021] The second semiconductor layer 14 can be a P-type semiconductor layer, which can provide holes to the light-emitting layer 12 under power. In some embodiments, the second semiconductor layer 14 includes a P-type doped nitride layer. The P-type doped nitride layer may include one or more P-type impurities. The P-type impurities may include one or a combination of Mg, Zn, and Be. The second semiconductor layer 14 can be a single-layer structure or a multi-layer structure with different compositions.

[0022] In some embodiments, the first semiconductor layer 10, the light-emitting layer 12, and the second semiconductor layer 14 may be formed from materials such as aluminum gallium indium nitride, gallium nitride, aluminum gallium nitride, aluminum indium phosphide, aluminum gallium indium phosphide, gallium arsenide, or aluminum gallium arsenide. The first semiconductor layer 10 or the second semiconductor layer 14 includes a capping layer that provides electrons or holes and may include other layer materials, such as a current spreading layer, a window layer, etc., configured as different multilayers depending on the doping concentration or composition content. The light-emitting layer 12 is the region that provides light radiation for electron-hole recombination, and different materials may be selected depending on the emission wavelength. The light-emitting layer 12 may be a periodic structure of a single quantum well or multiple quantum wells. By adjusting the composition ratio of the semiconductor materials in the light-emitting layer 12, it is desired to radiate light of different wavelengths.

[0023] The first electrode 18 is disposed on one side of the lower surface of the semiconductor stack and is electrically connected to the first semiconductor layer 10. The material of the first electrode 18 may include metallic materials, such as Cu, Al, Au, etc.

[0024] The second electrode 20 is disposed on one side of the upper surface of the semiconductor stack and is electrically connected to the second semiconductor layer 14. In some embodiments, the second electrode 20 can be a metal electrode or a transparent conductive electrode. The metal electrode can refer to a single layer of metal such as Ni, Pd, Ti, Pt, Cr, or a mixed stack of metals or alloys thereof. The transparent conductive electrode is made of a transparent conductive material, which may include indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium-doped zinc oxide (GZO), tungsten-doped indium oxide (IWO), or zinc oxide (ZnO), but the embodiments disclosed herein are not limited thereto. Preferably, the transparent conductive electrode is made of indium tin oxide (ITO). The second electrode 20 made of ITO is more prone to metal element migration. Therefore, shrinking it inward can reduce the possibility of current leakage from the outside, avoid leakage problems in the laser chip, and thus improve the lifespan and reliability of the device.

[0025] The second semiconductor layer 14 has a ridge protrusion 16. The ridge protrusion 16 has an outer sidewall 52 and a cavity surface 60. The surface where the outer sidewall 52 is located and the cavity surface 60 can be perpendicular to each other, and the outer sidewall 52 can be connected to the cavity surface 60. The ridge protrusion 16 can confine the photons generated by the light-emitting layer 12 to the light-emitting layer 12 below the ridge for directional propagation, reducing the leakage loss of the light field in the lateral direction, increasing the round-trip gain of photons in the light-emitting layer 12, thereby reducing the threshold current of the laser chip, while ensuring the mode purity of the output laser. The two sides of the ridge protrusion 16 can be covered with an insulating layer 30, and the second electrode 20 is deposited only on the ridge protrusion 16. Since the insulating layer 30 is non-conductive, the injected current can only flow vertically downwards along the ridge protrusion 16, avoiding the current diffusion in the lateral direction, so that the current density is concentrated in the effective light-emitting area, greatly improving the recombination efficiency of charge carriers, reducing the energy loss caused by non-radiative recombination, and preventing local overheating of the chip due to current diffusion. In some embodiments, the lateral divergence angle of the laser can be controlled by adjusting the width W2 and height of the ridge protrusion 16. A narrower ridge can compress the light field distribution, reduce the beam divergence angle, and improve the far-field coupling efficiency of the laser, making it more suitable for applications with high requirements for beam collimation, such as fiber optic communication and lidar. The ridge protrusion 16 can be formed by etching the second semiconductor layer 14 on the side portion.

[0026] The second electrode 20 may be at least partially disposed on the ridge protrusion 16. The first minimum horizontal distance L1 between at least a portion of the outer sidewall 50 of the second electrode 20 and the outer sidewall 52 or cavity surface 60 of the ridge protrusion 16 is greater than 0 μm. Compared to the conventional method where the outer sidewall 50 of the second electrode 20 and the outer sidewall 52 of the ridge protrusion 16 are on the same vertical plane, this invention, by etching away a portion of the second electrode 20, causes the second electrode 20 to shrink inward, forming a first minimum horizontal distance L1 greater than 0 μm. This effectively reduces the possibility of current leakage from the outer sidewall 52 or cavity surface 60 of the ridge protrusion 16, preventing leakage problems in the laser chip at the ridge protrusion 16, thereby improving the device's lifespan and reliability. Optionally, the first minimum horizontal distance L1 is less than 50 μm to avoid affecting effective current transmission. The first minimum horizontal distance L1 can also be less than 40 μm, 30 μm, 20 μm, etc., to avoid affecting effective current transmission.

[0027] In some embodiments, the thickness of the second electrode 20 ranges from 5 to 500 nm. If the thickness of the second electrode 20 is too thin (e.g., less than 5 nm), it will not be conducive to its function as an electrode. If the thickness of the second electrode 20 is too thick (e.g., greater than 500 nm), more current will flow through its edges, affecting the device performance.

[0028] In some embodiments, the second electrode 20 is completely disposed on the ridge protrusion 16, and the width W1 of the second electrode 20 is smaller than the width W2 of the ridge protrusion 16. This width refers to the width in the same direction, such as the lateral width in the figure. In some embodiments, the ridge protrusion 16 is elongated, with the outermost region in the length direction of the ridge protrusion 16 being the outer wall 52, and the outermost region in the width direction of the ridge protrusion 16 being the cavity surface 60.

[0029] In some embodiments, the second electrode 20 may be recessed on only one side, while the other side remains in the same vertical plane as the outer wall 52 of the ridge protrusion 16. Alternatively, it may be recessed on both sides, or it may be recessed all around (e.g., Figure 2 (As shown). With all four sides recessed, leakage protection is enhanced, thereby improving the device's lifespan and reliability.

[0030] In some embodiments, an ohmic contact layer 22 is disposed on the ridge protrusion 16, and the second electrode 20 is disposed on the ohmic contact layer 22. That is, the ohmic contact layer 22 is located between the ridge protrusion 16 and the second electrode 20. The ohmic contact layer 22 can be a p-type gallium nitride layer, such as P++GaN, P-GaN, etc. P++GaN refers to heavily doped p-type gallium nitride, whose impurity doping concentration is much higher than that of P-GaN, and the hole concentration can reach 10. 19 cm 3 The resistivity is significantly reduced, resulting in excellent conductivity.

[0031] Please see Figure 3 , Figure 3 This is a schematic diagram of the laser chip structure provided in the second embodiment of the present invention. Compared to Figure 1 The main difference between this embodiment and the laser chip of the first embodiment is that the second minimum horizontal distance L2 from at least a portion of the outer wall 52 of the ohmic contact layer 22 to the outer wall 52 of the ridge protrusion 16 or the cavity surface 60 is greater than 0 μm. Compared to the conventional method where the outer wall 54 of the ohmic contact layer 22 and the outer wall 52 of the ridge protrusion 16 are on the same vertical plane, this invention, by etching away a portion of the ohmic contact layer 22, causes the ohmic contact layer 22 to shrink inward, forming a second minimum horizontal distance L2 greater than 0 μm. This effectively reduces the possibility of current leakage from the outer wall 52 of the ridge protrusion 16 or the cavity surface 60, preventing leakage problems in the laser chip at the ridge protrusion 16, thereby improving the device's lifespan and reliability. Optionally, the second minimum horizontal distance L2 is less than 30 μm to avoid affecting effective current transmission. The second minimum horizontal distance L2 can also be less than 20 μm, 10 μm, etc., to avoid affecting effective current transmission.

[0032] In some embodiments, the ohmic contact layer 22 is completely disposed on the ridge protrusion 16, and the width W3 of the ohmic contact layer 22 is smaller than the width W2 of the ridge protrusion 16. This width refers to the width in the same direction, such as the lateral width in the figure. Figure 3 As shown, the first minimum horizontal spacing L1 is greater than the second minimum horizontal spacing L2.

[0033] In some embodiments, leakage at the ridge protrusion 16 of the laser chip can be avoided solely by reducing the ohmic contact layer 22. That is, in Figure 3 Based on this, the second electrode 20 can be expanded outward so that the outer wall 50 of the second electrode 20 and the outer wall 52 of the ridge protrusion 16 are on the same vertical plane. At this point, leakage at the ridge protrusion 16 can still be avoided by shrinking the ohmic contact layer 22. Being on the same vertical plane can be understood as the projection points of the two outer walls on the horizontal plane coinciding. For example, the point where the outer wall 50 of the second electrode 20 is vertically projected onto the horizontal plane overlaps with the point where the outer wall 52 of the ridge protrusion 16 is vertically projected onto the horizontal plane. In some cases, when the outer walls are inclined or curved, the outermost point of each outer wall can be used for determination.

[0034] In this embodiment, the stepped inward design from L1 to L2 can further avoid leakage problems of the laser chip at the ridge protrusion 16, thereby improving the lifespan and reliability of the device.

[0035] In some embodiments, such as Figure 4 As shown, the first minimum horizontal spacing L1 can be equal to the second minimum horizontal spacing L2 to facilitate process preparation and simplify the process preparation process.

[0036] In some embodiments, such as Figure 5 As shown, the first minimum horizontal spacing L1 can also be smaller than the second minimum horizontal spacing L2, which can form a larger area of ​​the second electrode 20 and improve the performance of the laser.

[0037] Please see Figure 6 , Figure 6 This is a schematic diagram of the laser chip structure provided in the fifth embodiment of the present invention. Compared to Figure 3The main difference between this embodiment and the laser chip in the second embodiment is that the laser chip further includes a first ion implantation layer 24, which is located at the edge of the upper surface of the ridge protrusion 16 and connected to the ohmic contact layer 22. Regarding the edge, it can be understood that the distance from the outermost wall of the first ion implantation layer 24 to the outermost endpoint of the upper surface of the ridge protrusion 16 is less than 1 μm; for example, the distance in the illustrated embodiment is 0 μm. The upper surface of the first ion implantation layer 24 can be flush with the upper surface of the ohmic contact layer 22. The first ion implantation layer 24 can be formed by implanting first ions into the ohmic contact layer 22, including ions such as He, O, F, N, Ti, Fe, Cr, V, or P. The first ion implantation layer 24 is a high-resistivity region, which can effectively block current flow and reduce leakage. By providing the first ion implantation layer 24, leakage problems at the ridge protrusion 16 of the laser chip can be further avoided, thereby improving the lifespan and reliability of the device.

[0038] In some embodiments, the width W5 of the first ion implantation layer 24 ranges from 1 to 30 μm to ensure effective current blocking and reduce leakage. In this embodiment, the width W5 of the first ion implantation layer 24 is equal to L2.

[0039] In some embodiments, the thickness H1 of the first ion implantation layer 24 may be less than or equal to the thickness H2 of the ohmic contact layer 22. In this embodiment, the thickness H1 of the first ion implantation layer 24 is equal to the thickness H2 of the ohmic contact layer 22 to facilitate fabrication and without affecting the underlying ridge protrusion 16. In some cases, when the thickness H1 of the first ion implantation layer 24 is less than the thickness H2 of the ohmic contact layer 22, the outer wall 54 of the ohmic contact layer 22 may refer to the outer wall covered by the first ion implantation layer 24.

[0040] In some embodiments, such as Figure 7 As shown, the first ion implantation layer 24 extends from the outer sidewall 52 of the ridge protrusion 16 toward the second electrode 20, that is, it extends inward and connects to the second electrode 20, and its extension stops upon contact with the second electrode 20. In other words, the inwardly extending end sidewall of the first ion implantation layer 24 is on the same vertical plane as the outer sidewall 50 of the second electrode 20. This further enhances the blocking effect and reduces leakage current.

[0041] In some embodiments, such as Figure 8As shown, the first ion implantation layer 24 can extend from the outer wall 52 of the ridge protrusion 16 toward the second electrode 20, that is, extend inward and connect to the second electrode 20. A portion of the first ion implantation layer 24 exists beneath the second electrode 20 to further enhance the blocking effect and reduce leakage. Optionally, the width W7 of the overlap between the second electrode 20 and the first ion implantation layer 24 ranges from 1 to 20 μm to ensure effective current spread while preventing leakage.

[0042] In some embodiments, the first ion implantation layer 24 may continue to extend downward, i.e., towards the light-emitting layer 12, but it should avoid extending to the waveguide layer to avoid affecting laser emission.

[0043] Please see Figure 9 , Figure 9 This is a schematic diagram of the laser chip structure provided in the seventh embodiment of the present invention. Compared to Figure 3 The main difference between this embodiment and the laser chip in the second embodiment is that the laser chip further includes a second ion implantation layer 26, which is disposed on the upper surface of the semiconductor stack and connected to the ridge protrusion 16. The upper surface of the second ion implantation layer 26 can be flush with the upper surface of the ridge protrusion 16. The second ion implantation layer 26 can be formed by implanting second ions into the second semiconductor layer 14, including ions such as He, O, F, N, Ti, Fe, Cr, V, or P. The second ion implantation layer 26 is disposed near the outer wall 52 of the ridge protrusion 16. The second ion implantation layer 26 is a high-resistivity region, which can effectively block current flow and reduce leakage. By providing the second ion implantation layer 26, leakage problems at the ridge protrusion 16 of the laser chip can be further avoided, thereby improving the lifespan and reliability of the device.

[0044] In some embodiments, the width W6 of the second ion implantation layer 26 ranges from 1 to 50 μm to ensure effective blocking of current flow and reduce leakage.

[0045] In some embodiments, the thickness H3 of the second ion implantation layer 26 is less than the thickness H4 of the ridge protrusion 16 to ensure device performance.

[0046] In some embodiments, such as Figure 10 As shown, the second ion implantation layer 26 extends from the outer sidewall 52 of the ridge protrusion 16 towards the ohmic contact layer 22, that is, it extends inward and connects to the ohmic contact layer 22, and its extension stops upon contacting the ohmic contact layer 22. In other words, the inwardly extending end sidewall of the second ion implantation layer 26 is on the same vertical plane as the outer sidewall 54 of the ohmic contact layer 22. This further enhances the blocking effect and reduces leakage current.

[0047] In some embodiments, such as Figure 11 As shown, the second ion implantation layer 26 extends from the outer wall 52 of the ridge protrusion 16 toward the ohmic contact layer 22, that is, it extends inward and connects to the ohmic contact layer 22. A portion of the second ion implantation layer 26 exists beneath the ohmic contact layer 22 to further enhance the blocking effect and reduce leakage. Optionally, the width W8 of the overlap between the ohmic contact layer 22 and the second ion implantation layer 26 ranges from 1 to 20 μm to ensure effective current spread while preventing leakage.

[0048] Please see Figure 12 , Figure 12 This is a schematic diagram of the laser chip structure provided in the eleventh embodiment of the present invention. Compared to Figure 1 The main difference between this embodiment and the laser chip in the first embodiment is that the laser chip may also include pad electrodes 28 and an insulating layer 30.

[0049] An insulating layer 30 covers a portion of the semiconductor stack, a portion of the ohmic contact layer 22, and a portion of the second electrode 20. The insulating layer 30 has an opening exposing the second electrode 20. The material of the insulating layer 30 comprises a non-conductive material. The non-conductive material is preferably an inorganic material or a dielectric material. The inorganic material may include silicone. The dielectric material includes electrically insulating materials such as aluminum oxide, silicon nitride, silicon oxide, titanium oxide, or magnesium fluoride. For example, the insulating layer 30 may be silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or a combination thereof, such as a Bragg mirror (DBR) formed by repeatedly stacking two materials with different refractive indices.

[0050] The pad electrode 28 is disposed on the insulating layer 30 and electrically connected to the second electrode 20 through an opening. The pad electrode 28 can be a metal pad, and the metal material can be, for example, Cu, Au, Al, etc. The width of the pad electrode 28 can be greater than the width W2 of the ridge protrusion 16, and can be greater than the width W3 of the ohmic contact layer 22, and can almost completely cover the insulating layer 30.

[0051] A substrate 32 may also be disposed between the first electrode 18 and the semiconductor stack, such as a gallium nitride substrate 32.

[0052] It should be noted that the pad electrode 28 and the insulating layer 30 can also be used in the second to tenth embodiments and the twelfth embodiment.

[0053] Please see Figure 13 , Figure 13 This is a schematic diagram of the laser chip structure provided in the twelfth embodiment of the present invention. Compared to Figure 7Regarding the laser chip of the sixth embodiment, the main difference in this embodiment is that, when the first ion implantation layer 24 is provided, the second electrode 20 no longer needs to be recessed (for example, the width W1 of the second electrode 20 can be greater than or equal to the width W2 of the ridge protrusion 16; in the illustrated embodiment, W1=W2, and the same width is used for illustration). Instead, the current is mainly blocked by 24, reducing the possibility of current leakage from the outside and avoiding leakage problems of the laser chip on the outer wall 52 or cavity surface 60 of the ridge protrusion 16, thereby improving the lifespan and reliability of the device.

[0054] In summary, the laser chip and light-emitting device provided by the present invention, by indenting the second electrode 20, ensures that the first minimum horizontal distance L1 between at least a portion of the outer sidewall 50 of the second electrode 20 and the outer sidewall 52 or cavity surface 60 of the ridge protrusion 16 is greater than 0 μm, thereby effectively reducing the possibility of current leakage from the outside and preventing leakage problems of the laser chip at the outer sidewall 52 or cavity surface 60 of the ridge protrusion 16, thereby improving the lifespan and reliability of the device.

[0055] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of the present invention can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or the background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A laser chip, characterized in that: The laser chip includes: A semiconductor stack having opposing upper and lower surfaces, the semiconductor stack comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially stacked along the direction from the lower surface to the upper surface; A first electrode is disposed on one side of the lower surface of the semiconductor stack and is electrically connected to the first semiconductor layer; The second electrode is disposed on one side of the upper surface of the semiconductor stack and is electrically connected to the second semiconductor layer; The second semiconductor layer has a ridge protrusion, the ridge protrusion has an outer wall and a cavity surface, the second electrode is at least partially disposed on the ridge protrusion, and the first minimum horizontal distance from the outer wall of the second electrode to the outer wall or the cavity surface of the ridge protrusion is >0 μm.

2. The laser chip according to claim 1, characterized in that: The second electrode is completely disposed on the ridge protrusion, and the width of the second electrode is smaller than the width of the ridge protrusion.

3. The laser chip according to claim 1, characterized in that: The first minimum horizontal spacing is <50μm.

4. The laser chip according to claim 1, characterized in that: An ohmic contact layer is also provided on the ridge protrusion, the ohmic contact layer is located between the ridge protrusion and the second electrode, and the second minimum horizontal distance from at least a portion of the outer sidewall of the ohmic contact layer to the outer sidewall or cavity surface of the ridge protrusion is >0 μm and <30 μm.

5. The laser chip according to claim 4, characterized in that: The first minimum horizontal spacing is greater than or equal to the second minimum horizontal spacing.

6. The laser chip according to claim 4, characterized in that: The first minimum horizontal spacing is less than the second minimum horizontal spacing.

7. The laser chip according to claim 4, characterized in that: The laser chip further includes a first ion implantation layer, which is located at the upper surface edge of the ridge and connected to the ohmic contact layer.

8. The laser chip according to claim 7, characterized in that: The first ion implantation layer extends from the outer wall of the ridge protrusion toward the second electrode and connects to the second electrode.

9. The laser chip according to claim 7, characterized in that: The first ion implantation layer is formed by implanting a first ion into the ohmic contact layer, the first ion including He, O, F, N, Ti, Fe, Cr, V or P ions.

10. The laser chip according to claim 7, characterized in that: The width of the first ion implantation layer ranges from 1 to 30 μm.

11. The laser chip according to claim 7, characterized in that: The thickness of the first ion implantation layer is less than or equal to the thickness of the ohmic contact layer.

12. The laser chip according to claim 4, characterized in that: The laser chip further includes a second ion implantation layer, which is disposed on the upper surface of the semiconductor stack and connected to the ridge protrusion.

13. The laser chip according to claim 12, characterized in that: The second ion implantation layer extends from the outer sidewall of the ridge protrusion toward the ohmic contact layer and connects to the ohmic contact layer.

14. The laser chip according to claim 12, characterized in that: The second ion implantation layer is formed by implanting a second ion into the second semiconductor layer, the second ion including He, O, F, N, Ti, Fe, Cr, V or P ions.

15. The laser chip according to claim 12, characterized in that: The width of the second ion implantation layer ranges from 1 to 50 μm.

16. The laser chip according to claim 12, characterized in that: The thickness of the second ion implantation layer is less than the thickness of the ridge.

17. The laser chip according to claim 1, characterized in that: The second electrode is a metal electrode or a transparent conductive electrode.

18. The laser chip according to claim 17, characterized in that: The material of the transparent conductive electrode includes indium tin oxide.

19. The laser chip according to claim 1, characterized in that: The thickness of the second electrode ranges from 5 to 500 nm.

20. A light-emitting device, characterized in that: The light-emitting device employs a laser chip as described in any one of claims 1 to 19.

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