Power management integrated circuit, storage device including the same, and power management method thereof

Abstract

The power management integrated circuit includes a DC-DC converter configured to generate an internal voltage and output an internal power supply voltage based on the internal voltage. The DC-DC converter includes: a first switch connected between an external power supply voltage and a second node from which the internal voltage is output; a second switch connected between the second node and ground; and a third switch connected between the second node and the external power supply voltage via a resistor. When the internal voltage is normal, the DC-DC converter generates an internal voltage with a level between a first voltage and a second voltage lower than the first voltage by repeatedly switching the first and second switches on and off. When the internal voltage exceeds the first voltage, the DC-DC converter reduces the internal voltage by repeatedly switching the second and third switches on and off.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0176914, filed with the Korean Intellectual Property Office on December 2, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The exemplary embodiments of this disclosure described herein relate to semiconductor memory devices, and more specifically, to power management integrated circuits, memory devices including power management integrated circuits, and power management methods for memory devices. Background Technology

[0003] Semiconductor memories can be mainly classified into volatile memories and non-volatile memories. Volatile memories have fast read and write speeds, but the data stored in volatile memories is lost when power is turned off. In contrast, non-volatile memories can retain data even when power is off. Therefore, non-volatile memories can be used to store content that must be retained regardless of whether power is supplied.

[0004] A prime example of non-volatile memory is flash memory. Flash memory is widely used as a storage medium for audio and video data in information devices such as computers and smartphones. Recently, there has been active research into high-capacity, high-speed input / output, and low-power technologies for flash memory for installation in mobile devices such as smartphones.

[0005] Storage devices can use volatile memory devices as temporary storage alongside non-volatile memory devices to improve read or write performance. Storage devices can use power management integrated circuits (ICs) to power both volatile and non-volatile memory devices. However, if the power management IC immediately cuts off power to protect internal circuitry when the internal voltage temporarily spikes, data temporarily stored in the volatile memory device may be lost. Therefore, when the internal voltage abnormally spikes, the power management IC may need to continue providing reduced power. Summary of the Invention

[0006] An exemplary embodiment of this disclosure provides a storage device including a power management integrated circuit that, instead of immediately cutting off power when the internal voltage temporarily rises, gradually adjusts the increased internal voltage to a predetermined voltage.

[0007] According to an example embodiment, a power management integrated circuit includes a DC-DC converter configured to generate an internal intermediate voltage based on an external power supply voltage and to output an internal power supply voltage based on the internal intermediate voltage. The DC-DC converter includes: a first switch connected between a first node from which an external power supply voltage is applied and a second node from which the internal intermediate voltage is output, and configured to repeatedly turn on and off based on a first switch signal; a second switch connected between the second node and a ground node, and configured to repeatedly turn on and off based on a second switch signal; a resistor connected between the first node and a third node; a third switch connected between the third node and the second node, and configured to repeatedly turn on and off based on a third switch signal; a pulse width modulation control circuit configured to generate the first switch signal to the third switch signal based on the level of the internal intermediate voltage; and a voltage distribution circuit connected between the second node and a fourth node, configured to output the internal power supply voltage from the fourth node based on the internal intermediate voltage. When the internal intermediate voltage is lower than or equal to the first reference voltage, the DC-DC converter is configured to: repeatedly turn the first and second switches on and off in response to the activation of the first and second switch signals, and turn off the third switch in response to the deactivation of the third switch signal, thereby generating an internal intermediate voltage with a level between the first reference voltage and a second reference voltage lower than the first reference voltage. When the internal intermediate voltage exceeds the first reference voltage, the DC-DC converter is configured to: repeatedly turn the second and third switches on and off in response to the activation of the second and third switch signals, and turn off the first switch in response to the deactivation of the first switch signal, thereby reducing the internal intermediate voltage to the second reference voltage.

[0008] According to an example embodiment, a storage device includes: a non-volatile storage device including a plurality of storage cells; a volatile storage device configured to temporarily store data stored in the plurality of storage cells of the non-volatile storage device; a storage controller configured to transfer data between the non-volatile storage device and the volatile storage device; and a power management integrated circuit configured to generate an internal intermediate voltage and output an internal power supply voltage to at least one of the non-volatile storage device, the volatile storage device, and the storage controller based on the internal intermediate voltage. The power management integrated circuit includes a DC-DC converter. The DC-DC converter includes: a first switch connected between a first node to which an external power supply voltage is applied and a second node from which an internal intermediate voltage is output, and configured to be turned on and off based on a first switch signal; a second switch connected between the second node and a ground node, and configured to be turned on and off based on a second switch signal; a resistor connected between the first node and a third node; a third switch connected between the third node and the second node, and configured to be turned on and off based on a third switch signal; a pulse width modulation control circuit configured to generate the first switch signal to the third switch signal based on the level of the internal intermediate voltage; and a voltage distribution circuit connected between the second node and a fourth node, and configured to output the internal power supply voltage from the fourth node based on the internal intermediate voltage. When the internal intermediate voltage is lower than or equal to a first reference voltage, the DC-DC converter is configured to: repeatedly turn the first and second switches on and off in response to activation of the first and second switch signals and turn off the third switch in response to deactivation of the third switch signal, generating an internal intermediate voltage with a level between the first reference voltage and a second reference voltage lower than the first reference voltage. When the internal intermediate voltage exceeds the first reference voltage, the DC-DC converter is configured to reduce the internal intermediate voltage to the second reference voltage by repeatedly turning the second and third switches on and off in response to the activation of the second and third switch signals and turning off the first switch in response to the deactivation of the first switch signal.

[0009] According to an example embodiment, a power management method for a storage device includes: generating an internal intermediate voltage with a level between a first reference voltage and a second reference voltage lower than the first reference voltage by repeatedly switching a first switch connected to an external power supply voltage and repeatedly switching a second switch connected to a ground voltage; reducing the internal intermediate voltage by repeatedly switching the second switch and a third switch connected to the external power supply voltage via a resistor and turning off the first switch when the internal intermediate voltage exceeds the first reference voltage; generating an internal power supply voltage based on the internal intermediate voltage and outputting the internal power supply voltage to at least one of a non-volatile storage device, a volatile storage device, and a storage controller. The generation of the internal intermediate voltage is performed based on the level of the internal intermediate voltage and the external power supply voltage. Attached Figure Description

[0010] The above and other objects and features of this disclosure will become apparent from the example embodiments described in detail with reference to the accompanying drawings.

[0011] Figure 1 This is a block diagram illustrating a user device according to an example embodiment.

[0012] Figure 2 This illustrates an example embodiment. Figure 1 A diagram of a DC-DC converter with a power management integrated circuit.

[0013] Figure 3 This illustrates an example embodiment. Figure 2 Timing diagram of the operation of the DC-DC converter.

[0014] Figure 4 It shows Figure 1 A diagram of a DC-DC converter with a power management integrated circuit.

[0015] Figure 5 This illustrates an example embodiment. Figure 4 Timing diagram of the operation of the DC-DC converter.

[0016] Figure 6 This illustrates an example embodiment. Figure 1 A diagram of a DC-DC converter with a power management integrated circuit.

[0017] Figure 7 This illustrates an example embodiment. Figure 1 A diagram of a DC-DC converter.

[0018] Figure 8 This illustrates an example embodiment. Figure 1 A diagram of a DC-DC converter.

[0019] Figure 9 This illustrates an example embodiment. Figure 1 A diagram of a DC-DC converter.

[0020] Figure 10 This is a block diagram illustrating a user equipment or storage system according to an example embodiment.

[0021] Figure 11 This illustrates an example embodiment. Figure 10 A block diagram of the storage device.

[0022] Figure 12 It shows Figure 11 A circuit diagram of an example embodiment of the memory block (BLK1) of the memory cell array described herein.

[0023] Figure 13 It shows Figure 12 The circuit diagram of the cell string selected by the first selection line SSL1 in the cell string of the memory block BLK1 described in the figure.

[0024] Figure 14 This illustrates an example embodiment. Figure 10 A flowchart of the power management method for storage devices.

[0025] Figure 15 This illustrates an example embodiment. Figure 10 The flowchart describes the power management method for storage devices. Detailed Implementation

[0026] The exemplary embodiments of this disclosure will now be described in detail and clearly to the extent that those skilled in the art can readily implement the inventive concept.

[0027] Figure 1 This is a block diagram illustrating a user device according to an example embodiment. (Reference) Figure 1 User equipment 100 may include power management integrated circuit (PMIC) 110 and main equipment 120.

[0028] The power management integrated circuit 110 can receive an external power supply voltage VEXT. The power management integrated circuit 110 can provide an internal power supply voltage VINT to the master device 120 based on the external power supply voltage VEXT. Both the external power supply voltage VEXT and the internal power supply voltage VINT can be DC power supply voltages.

[0029] For example, the power management integrated circuit 110 may include a DC-DC converter 110a. The DC-DC converter 110a may generate an internal intermediate voltage based on an external power supply voltage VEXT.

[0030] The power management integrated circuit 110 can generate the internal power supply voltage VINT required by the main device 120 based on an internal intermediate voltage. For example, the DC-DC converter 110a of the power management integrated circuit 110 may include a voltage distribution circuit. The voltage distribution circuit can output the internal power supply voltage VINT based on the internal intermediate voltage.

[0031] The host device 120 may include various electronic devices. For example, the host device 120 may include storage devices (e.g., dynamic random access memory (DRAM), solid-state drives (SSDs), universal flash memory (UFS), memory cards, etc.). The host device 120 may perform operations based on its internal power supply voltage VINT.

[0032] although Figure 1 The illustration shows a master device 120 as an example, but the user equipment 100 may include multiple master devices 120. In some example embodiments that include multiple master devices 120, the power management integrated circuit 110 may generate multiple internal power supply voltages VINT (e.g., a first internal power supply voltage, a second internal power supply voltage, etc.) corresponding to the multiple master devices 120 respectively.

[0033] As an example, the power management integrated circuit 110 can generate an internal intermediate voltage via a DC-DC converter 110a, and generate an internal power supply voltage VINT via the voltage distribution circuit of the DC-DC converter 110a. As another example, the power management integrated circuit 110 may include multiple DC-DC converters 110a corresponding to multiple internal power supply voltages VINT.

[0034] Figure 2 This illustrates an example embodiment. Figure 1 A diagram of a DC-DC converter 110a of a power management integrated circuit 110. (Reference) Figure 2 The DC-DC converter 110a may include pulse width modulation (PWM) control circuitry 111 and multiple switches. Each of the multiple switches may be configured as a metal-oxide-semiconductor field-effect transistor (MOSFET). As an example, in Figure 2 In the diagram, the first switch 112, the second switch 113, and the third switch 115 are shown as N-type MOSFETs. However, this is exemplary, and the first switch 112, the second switch 113, and / or the third switch 115 may be configured as either an N-type MOSFET or a P-type MOSFET.

[0035] A first switch 112 may be connected between a first node N1 and a second node N2. For example, the first switch 112 may include a drain connected to the first node N1, a source connected to the second node N2, and a gate to which a first switch signal SW1 is input. The first switch 112 may be repeatedly turned on and off based on the first switch signal SW1. The first switch 112 may increase the voltage of the second node N2 (e.g., an internal intermediate voltage VIM) based on the voltage of the first node N1 (e.g., an external power supply voltage VEXT).

[0036] The second switch 113 can be connected between the second node N2 and the ground node. For example, the second switch 113 may include a drain connected to the second node N2, a source connected to the ground node, and a gate to which the second switch signal SW2 is input. In this document, for ease of description, the terms ground node, ground, and ground voltage are used interchangeably. The second switch 113 can be repeatedly turned on and off based on the second switch signal SW2. The second switch 113 can operate complementaryly to the first switch 112. In this case, the second switch signal SW2 can be complementary to the first switch signal SW1. The second switch 113 can reduce the voltage of the second node N2 (e.g., the internal intermediate voltage VIM) based on the ground voltage.

[0037] The pulse width modulation control circuit 111 can initiate power management operation based on the enable signal EN. For example, under normal conditions, the pulse width modulation control circuit 111 can output or activate the first switch signal SW1 and the second switch signal SW2. For example, the DC-DC converter 110a can output an internal intermediate voltage VIM by repeatedly switching the first switch 112 and the second switch 113 on and off based on the activation of the first switch signal SW1 and the second switch signal SW2. The DC-DC converter 110a of the power management integrated circuit 110 can output an internal intermediate voltage VIM based on the external power supply voltage VEXT.

[0038] The pulse width modulation control circuit 111 can receive the internal intermediate voltage VIM as a feedback signal FB. The pulse width modulation control circuit 111 can compare the internal intermediate voltage VIM with a reference voltage (not shown). When the internal intermediate voltage VIM rises above the reference voltage, the pulse width modulation control circuit 111 can turn off the first switch 112 based on the deactivation of the first switch signal SW1, and turn on the second switch 113 and the third switch 115 based on the activation of the second switch signal SW2 and the third switch signal SW3.

[0039] The third switch 115 can be connected to the first node N1 via a resistor 114. The resistor 114 can be connected between the first node N1 and the third node N3. For example, the third switch 115 may include a drain connected to the third node N3, a source connected to the second node N2, and a gate to which a third switch signal SW3 is input. The third switch 115 can be connected between the third node N3 and the second node N2. The third switch 115 can be repeatedly turned on and off based on the third switch signal SW3. The third switch 115 can increase the voltage of the second node N2 (e.g., the internal intermediate voltage VIM) based on the voltage of the third node N3. The third switch 115 can operate complementaryly to the second switch 113. In this case, the third switch signal SW3 can be complementary to the second switch signal SW2. For example, the current-carrying capacity of the third switch 115 can be equal to or less than the current-carrying capacity of the first switch 112.

[0040] Because of resistor 114, the current flowing through the third switch 115 can be less than the current flowing through the first switch 112. For example, when the internal intermediate voltage VIM rises to the first reference voltage (e.g., Figure 3 When the voltage Vref1 is above a certain value, the internal intermediate voltage VIM can be gradually reduced to below the first reference voltage by repeatedly turning off the first switch 112 and repeatedly turning the second switch 113 and the third switch 115 on and off. When the internal intermediate voltage VIM reaches the normal voltage (e.g., ...), Figure 3 When Vref2), the pulse width modulation control circuit 111 can turn off the third switch 115 and turn on the first switch 112 again.

[0041] Therefore, when the internal intermediate voltage VIM rises abnormally, the DC-DC converter 110a can control the output of the internal intermediate voltage VIM to gradually return to the normal voltage without interrupting the output of the internal intermediate voltage VIM. The power management integrated circuit 110 can supply the internal power supply voltage VINT to the main device 120 based on the internal intermediate voltage VIM without interrupting the internal power supply voltage VINT.

[0042] In an example embodiment, the DC-DC converter 110a may further include a voltage distribution circuit. For example, the voltage distribution circuit may include an LC filter. The LC filter may include an inductor L and a capacitor C connected to each other. For example, a first terminal of the inductor L may be connected to a second node N2 from which an internal intermediate voltage VIM is output, and a second terminal of the inductor L may be connected to a fourth node N4 from which an internal power supply voltage VINT is output. A first terminal of the capacitor C may be connected to the fourth node N4, and a second terminal of the capacitor C may be connected to ground. For example, the voltage distribution circuit may receive the internal intermediate voltage VIM at the second node N2 and may output the internal power supply voltage VINT from the fourth node N4. However, the inventive concept is not limited thereto. For example, the LC filter may include multiple inductors L and multiple capacitors C connected to each other. In an example embodiment, the LC filter of the voltage distribution circuit may be mounted outside the power management integrated circuit 110. For example, the power management integrated circuit 110 may be implemented as a single package, and the LC filter of the voltage distribution circuit may be disposed separately from that package.

[0043] In an example embodiment, the LC filter of the voltage distribution circuit can be located outside the power management integrated circuit 110. In this case, the power management integrated circuit 110 can output an internal intermediate voltage VIM to the LC filter via a DC-DC converter 110a, and the LC filter can output an internal power supply voltage VINT to the master device 120 based on the internal intermediate voltage VIM.

[0044] Figure 3 This illustrates an example embodiment. Figure 2 Timing diagram for the operation of DC-DC converter 110a. (Refer to...) Figure 2 and Figure 3 When the internal intermediate voltage VIM rises abnormally, the DC-DC converter 110a can control the output of the internal intermediate voltage VIM to gradually reach the normal voltage without interrupting the output of the internal intermediate voltage VIM. The normal voltage can be the second reference voltage Vref2. For example, when the internal intermediate voltage VIM is within the range between the first reference voltage Vref1 and the second reference voltage Vref2, which is lower than the first reference voltage Vref1, the internal power supply voltage VINT can have a specific level.

[0045] Before the first time point t1, the pulse width modulation control circuit 111 can output or activate the first switch signal SW1 and the second switch signal SW2 based on the first duty cycle. In this case, the second switch signal SW2 can be complementary to the first switch signal SW1. Therefore, before the first time point t1, the internal intermediate voltage VIM can be maintained below the first reference voltage Vref1 and above the second reference voltage Vref2. For example, the DC-DC converter 110a can perform pulse width modulation operation by repeatedly turning the first and second switches 112 and 113 on and off based on the activation of the first switch signal SW1 and the second switch signal SW2, and by turning off the third switch 115 based on the deactivation of the third switch signal SW3.

[0046] Starting from the first time point t1, the internal intermediate voltage VIM may increase and exceed the first reference voltage Vref1 due to various reasons (e.g., duty cycle fluctuations of the first switching signal SW1). For example, the internal intermediate voltage VIM may increase when the duty cycle of the first switching signal SW1 increases.

[0047] At the second time point t2, when the internal intermediate voltage VIM exceeds the first reference voltage Vref1, the pulse width modulation control circuit 111 can stop or deactivate the first switch signal SW1, and output or activate the second switch signal SW2 and the third switch signal SW3. In this case, the second switch signal SW2 can complement the third switch signal SW3. Therefore, the DC-DC converter 110a can turn off the first switch 112 based on the deactivation of the first switch signal SW1, and repeatedly turn on and off the second switch 113 and the third switch 115 based on the activation of the second switch signal SW2 and the third switch signal SW3, performing pulse width modulation operation with a second duty cycle. Therefore, starting from the second time point t2, the internal intermediate voltage VIM can gradually decrease to below the first reference voltage Vref1.

[0048] At the third time point t3, when the internal intermediate voltage VIM drops to the second reference voltage Vref2, the pulse width modulation control circuit 111 can stop or deactivate the third switch signal SW3 and re-output or activate the first switch signal SW1 and the second switch signal SW2. In this case, the second switch signal SW2 can complement the first switch signal SW1. Therefore, the DC-DC converter 110a can perform pulse width modulation operation again with the first duty cycle by turning off the third switch 115 and repeatedly turning the first switch 112 and the second switch 113 on and off. For example, after the third time point t3, the internal intermediate voltage VIM can remain below the first reference voltage Vref1 and above the second reference voltage Vref2.

[0049] According to the example embodiment, when the internal intermediate voltage VIM exceeds the third reference voltage Vref3, which is greater than the first reference voltage Vref1, the pulse width modulation control circuit 111 can block or deactivate all switching signals to protect the power management integrated circuit 110 and / or the master device 120.

[0050] Figure 4 It shows Figure 1 A figure of another embodiment of the DC-DC converter 110a of the power management integrated circuit 110. Figure 5 This illustrates an example embodiment. Figure 4 Timing diagram of the operation of DC-DC converter 110a. Figure 4 In the DC-DC converter 110a, the first switch 112, the second switch 113, the third switch 115, and the resistor 114 are connected to a reference. Figure 2 The content described is the same, therefore the reference above is omitted. Figure 2 The given description is the same as the given description.

[0051] refer to Figure 4 and Figure 5 When the internal intermediate voltage VIM rises abnormally, the DC-DC converter 110a can supply power to external devices (e.g., Figure 10 The storage controller 1200 sends an interrupt signal IRPT. Figure 5 The timing diagram and reference for the internal intermediate voltage VIM, the first switch signal to the third switch signals SW1, SW2, and SW3 are shown in the figure. Figure 3 The timing diagram described is the same, therefore the reference above is omitted. Figure 3 The given description is the same as the given description.

[0052] For example, the pulse width modulation control circuit 111 can monitor the feedback signal FB of the internal intermediate voltage VIM. At a second time point t2, when the internal intermediate voltage VIM exceeds the first reference voltage Vref1, the pulse width modulation control circuit 111 can output or activate the interrupt signal IRPT. For example, the DC-DC converter 110a can send a signal to the memory controller (e.g., Figure 10 The memory controller sends an interrupt signal IRPT to the buffer memory (e.g., 1200). Upon receiving the interrupt signal IRPT, the memory controller can release the buffer memory (e.g., Figure 10 Data stored in 1300) is moved to non-volatile memory (e.g., Figure 10 (1100). Therefore, storage devices (e.g., Figure 10 The 1000) can prevent the loss of data stored only in the buffer memory. At the third time point t3, when the internal intermediate voltage VIM drops to the second reference voltage Vref2, the pulse width modulation control circuit 111 can stop or deactivate the interrupt signal IRPT.

[0053] Figure 6 It shows Figure 1 A diagram of the DC-DC converter 110a of the power management integrated circuit 110. In Figure 6 In the DC-DC converter 110a, the first switch 112, the second switch 113, and the third switch 115 are connected to a reference. Figure 2 The content described is the same, therefore the reference above is omitted. Figure 2 The description is the same as the one given.

[0054] refer to Figure 6 The DC-DC converter 110a may include a variable resistor 116 connected between a first node N1 and a third node N3. As an example, the variable resistor 116 may be connected between the first node N1 and the third node N3 instead of... Figure 4 Resistor 114. As another example, variable resistor 116 can be connected in parallel with resistor 114 between the first node N1 and the third node N3. In this case, variable resistor 116 and resistor 114 can be connected in parallel between the first node N1 and the third node N3.

[0055] The pulse width modulation control circuit 111 can output a variable resistor control signal VR to control the resistance value of the variable resistor 116. The pulse width modulation control circuit 111 can control the variable resistor 116 so that the current flowing through the third switch 115 decreases as the amplitude of the feedback internal intermediate voltage VIM increases.

[0056] For example, when the internal intermediate voltage VIM exceeds the first reference voltage Vref1, the pulse width modulation control circuit 111 can control the variable resistor 116 to have a first resistance value. When the internal intermediate voltage VIM exceeds the third reference voltage Vref3, which is larger than the first reference voltage Vref1, the pulse width modulation control circuit 111 can control the variable resistor 116 to have a second resistance value that is larger than the first resistance value.

[0057] Figure 7 This illustrates an example embodiment. Figure 1 A diagram of the DC-DC converter 110a. In Figure 7 In the middle, the first switch 112 and the second switch 113 of the DC-DC converter 110a are connected to the reference. Figure 2 The content described is the same, therefore the reference above is omitted. Figure 2 The given description is the same as the given description.

[0058] refer to Figure 7Resistor 214 and third switch 215 can be mounted externally to the power management integrated circuit 110. In another embodiment, one of resistor 214 and third switch 215 can be mounted externally to the power management integrated circuit 110. The power management integrated circuit 110 may include external ports 201, 202, and 203 connected to resistor 214 and third switch 215. In this document, resistor 214 and third switch 215 can respectively correspond to... Figure 2 Resistor 114 and third switch 115. (Reference) Figure 2 The voltage distribution circuit, including the LC filter, can be located externally or internally to the power management integrated circuit 110.

[0059] Figure 8 This illustrates an example embodiment. Figure 1 A diagram of the DC-DC converter 110a. In Figure 8 In the DC-DC converter 110a, the first switch 112, the second switch 113, and the third switch 215 are connected to a reference. Figure 7 The content described is the same, therefore the reference above is omitted. Figure 7 The given description is the same as the given description.

[0060] refer to Figure 8 The variable resistor 216 and the third switch 215 can be mounted externally to the power management integrated circuit 110. In another embodiment, one of the variable resistor 216 and the third switch 215 can be mounted externally to the power management integrated circuit 110. The power management integrated circuit 110 may include external ports 201, 202, and 203 connected to the variable resistor 216 and the third switch 215. Hereinafter, the third switch 215 may correspond to... Figure 6 The third switch 115. The variable resistor control signal VR for controlling the variable resistor 216 can be provided from an external device (e.g., a storage controller). In an example embodiment, the variable resistor control signal VR can be output from the pulse width modulation control circuit 111.

[0061] As an example, the variable resistor 216 can be connected between the first node N1 and the third node N3 instead of Figure 7 Resistor 214. As another example, variable resistor 216 can be connected in parallel with resistor 214 between the first node N1 and the third node N3. In this case, variable resistor 216 and resistor 214 can be connected in parallel between the first node N1 and the third node N3.

[0062] Figure 9 This illustrates an example embodiment. Figure 1 A diagram of the DC-DC converter 110a. In Figure 9In the middle, the first switch 112, the second switch 113, and the pulse width modulation control circuit 111 are connected to the reference. Figure 2 The content described is the same, therefore the reference above is omitted. Figure 2 The given description is the same as the given description.

[0063] refer to Figure 9 The third switch 115 can be connected between the first node N1 and the third node N3. A resistor 114 can be connected between the third node N3 and the second node N2. Due to the resistor 114, the current flowing through the third switch 115 is less than the current flowing through the first switch 112. Therefore, the internal intermediate voltage VIM can gradually decrease to the normal voltage (e.g., Vref2). When the internal intermediate voltage VIM reaches the normal voltage, the pulse width modulation control circuit 111 can turn off the third switch 115 and turn the first switch 112 back on.

[0064] Therefore, when the internal intermediate voltage VIM rises abnormally, the DC-DC converter 110a can control the output of the internal intermediate voltage VIM to gradually restore it to the normal voltage without interrupting the output of the internal intermediate voltage VIM. The power management integrated circuit 110 can supply the internal power supply voltage VINT to the main device 120 based on the internal intermediate voltage VIM without interruption.

[0065] Figure 10 This is a block diagram illustrating a user equipment or storage system according to an example embodiment of the present disclosure. Reference Figure 10 User equipment or storage system 100_1 may include storage device 1000 and host 1500. Storage device 1000 and host 1500 can be connected via host interface 1201. Host interface 1201 may be a standard interface, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Universal Serial Bus (USB), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Serial Bus Architecture IEEE 1394, Interface Design Description (IDE), and / or card interface, etc.

[0066] Storage device 1000 may be a storage device based on non-volatile memory. For example, storage device 1000 may include storage device 1100, storage controller 1200, and / or buffer memory 1300. Additionally, storage device 1000 may include power management integrated circuit (PMIC) 1400. Power management integrated circuit 1400 may have... Figures 1 to 9 The power management integrated circuit 110 shown has the same or similar configuration and characteristics.

[0067] Storage device 1100 may be non-volatile memory, such as flash memory or phase-change memory (PRAM). When storage device 1100 is flash memory, storage device 1000 may be a flash-based flash storage device. For example, storage device 1000 may be an SSD, UFS, and / or a memory card, etc. Buffer memory 1300 may include volatile memory (e.g., DRAM).

[0068] Storage device 1100 can be connected to storage controller 1200 via storage interface 1202. Storage device 1100 may include a storage cell array and peripheral circuitry. Peripheral circuitry may include all analog or digital circuitry required to store or retrieve data in the storage cell array.

[0069] The peripheral circuitry can receive commands, addresses, and data from the storage controller 1200, and store the data in the storage cell array according to control signals. Additionally, the peripheral circuitry can read data stored in the storage cell array and provide the data to the storage controller 1200.

[0070] A storage cell array may include multiple storage blocks. Each storage block may have a vertical three-dimensional structure. Each storage block may include multiple storage cells. Multiple bits of data may be stored in each storage cell. For example, storage device 1100 may be a TLC flash memory capable of storing 3 bits of data in a single storage cell.

[0071] Due to their design and layout, memory cell arrays can be located next to or above peripheral circuitry. A structure where the memory cell array is above the peripheral circuitry is called a COP (Cell-on-Periphery) structure. The memory cell array can be manufactured as a separate chip from the peripheral circuitry. A bonding method can be used to connect the upper chip containing the memory cell array and the lower chip containing the peripheral circuitry to each other. This structure is called a C2C (Chip-to-Chip) structure.

[0072] The storage controller 1200 can be connected between the storage device 1100 and the host 1500. Alternatively, the storage controller 1200 can be connected between the buffer memory 1300 and the host 1500. The storage controller 1200 can control read or write operations on the storage device 1100 and / or the buffer memory 1300 in response to requests from the host 1500. The storage controller 1200 can receive host data from the host 1500 and provide the host data to the storage device 1100 and / or the buffer memory 1300.

[0073] The storage controller 1200 may include a control unit and working memory. The control unit can control the overall operation of the storage controller 1200. For example, the control unit can control the flash translation layer (FTL) to perform address mapping operations. The control unit may be a commercially available or custom-made microprocessor.

[0074] The working memory can be a cache memory (e.g., static random access memory (SRAM)). The working memory can act as a buffer for temporary data storage. Alternatively, the working memory can be the drive memory for the memory controller 1200. The working memory can drive the FTL.

[0075] The FTL can be firmware or a program used to effectively manage the storage device 1100. Unlike a hard disk drive, the storage device 1100 may not support overwrite functionality. Therefore, the storage device 1100 can perform the following process when updating data written to a page: First, the storage device 1100 can copy all valid data in a first storage block to which the written page belongs to an empty second storage block. Second, the storage device 1100 can erase the first storage block and make it an empty storage block. During this process, the storage device 1100 can perform a large number of page copy operations (e.g., page read operations and / or page write operations) and erase operations.

[0076] An Open Layer Transport (FTL) can be used between the host 1500 and the storage device 1100 to reduce the number of page copying and erase operations. The FTL can perform address mapping, garbage collection, and wear leveling functions. When a write request is received from the host 1500, the address mapping function can write the corresponding data to another empty page instead of overwriting the original page, thereby reducing additional page copying and block erase operations. For this purpose, an address mapping table of a specified size can be maintained in the working memory and the buffer memory 1300. In this way, the FTL can manage the mapping of logical addresses received from the host 1500 to physical addresses in the storage device 1100.

[0077] Buffer memory 1300 can be connected to memory controller 1200 via buffer interface 1203. For example, buffer memory 1300 can be used to temporarily store data to be stored in or read from memory device 1100. Additionally, a cache region capable of storing cached data can be allocated to buffer memory 1300. Buffer memory 1300 can be implemented using DRAM, SRAM, etc. Buffer memory 1300 can be included in memory device 1100 or memory controller 1200.

[0078] The host 1500 may include a processor and host memory. The processor and host memory may be connected via an address / data bus. The host 1500 may be a personal digital assistant (PDA), a computer, a digital audio player, a digital camera, and / or a mobile phone, etc. The host memory may be a non-volatile or volatile memory in the form of cache, read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, SRAM, DRAM, etc.

[0079] Host memory can drive multiple software or firmware components. For example, host memory can drive operating systems (OS), applications, file systems, storage managers, and I / O drives.

[0080] The power management integrated circuit 1400 can provide internal power supply voltages to the storage device 1100, the storage controller 1200, and / or the buffer memory 1300 based on the external power supply voltage VEXT. For example, the power management integrated circuit 1400 can supply a first internal power supply voltage VINT1 to the storage device 1100. The power management integrated circuit 1400 can supply a second internal power supply voltage VINT2 to the storage controller 1200. The power management integrated circuit 1400 can supply a third internal power supply voltage VINT3 to the buffer memory 1300. The first internal power supply voltage VINT1, the second internal power supply voltage VINT2, and / or the third internal power supply voltage VINT3 can be set to be the same as or different from each other.

[0081] The power management integrated circuit 1400 may include a DC-DC converter 110a. The DC-DC converter 110a may generate an internal intermediate voltage (e.g., an internal intermediate voltage VIM) based on an external power supply voltage VEXT. The power management integrated circuit 1400 may generate a first internal power supply voltage VINT1, a second internal power supply voltage VINT2, and / or a third internal power supply voltage VINT3 based on the internal intermediate voltage VIM. As an example, the power management integrated circuit 1400 may include multiple DC-DC converters 110a corresponding to the first internal power supply voltage VINT1, the second internal power supply voltage VINT2, and / or the third internal power supply voltage VINT3, respectively.

[0082] When the internal intermediate voltage exceeds the reference voltage (e.g., the first reference voltage Vref1), the DC-DC converter 110a can perform... Figures 2 to 9 The pulse width modulation operation described herein. Therefore, even when the internal intermediate voltage rises abnormally, the internal power supply voltage can be supplied to the storage device 1100, the storage controller 1200, and / or the buffer memory 1300 without interruption.

[0083] Furthermore, when the internal intermediate voltage exceeds the reference voltage (e.g., the first reference voltage Vref1), the DC-DC converter 110a (or the power management integrated circuit 1400) can send an interrupt signal IRPT to the storage controller 1200. Upon receiving the interrupt signal IRPT, the storage controller 1200 can preferably move the data held in the buffer memory 1300 to the storage device 1100. Therefore, the storage device 1000 can prevent the loss of data stored only in the buffer memory 1300.

[0084] Figure 11 This illustrates an example embodiment. Figure 10 Block diagram of storage device 1100. Figure 10 The storage device 1000 can be a flash storage device based on flash memory. For example, the storage device 1000 can be implemented as an SSD, UFS, and / or a memory card, etc.

[0085] refer to Figure 10 and Figure 11 The storage device 1100 may include a memory cell array 1110 and peripheral circuitry. The peripheral circuitry may include an address decoder 1120, a page buffer circuit 1130, an input / output (I / O) circuit 1140, a word line (WL) voltage generator 1150, and control logic circuitry 1160.

[0086] The storage cell array 1110 may include multiple storage blocks BLK1 to BLKn, where n is a natural number equal to or greater than 2. Each storage block may be configured with multiple pages. Each page may include multiple storage cells. Each storage cell may store multiple bits of data (e.g., two or more bits of data). Each storage block may correspond to an erase cell, and each page may correspond to a read or write cell.

[0087] The memory cell array 1110 can be formed in a direction perpendicular to the substrate. Gate electrode layers and insulating layers can be deposited alternately on the substrate. Each memory block (e.g., BLK1) can be connected to one or more string select lines SSL, multiple word lines WL1 to WLm, and one or more ground select lines GSL. WLk is the selected word line sWL, and the remaining word lines (WL1 to WLk-1, WLk+1 to WLm) are the unselected word lines uWL.

[0088] Address decoder 1120 can be connected to memory cell array 1110 via select lines SSL and GSL and word lines WL1 to WLm, where m is a natural number equal to or greater than 2. Address decoder 1120 can select word lines during programming or read operations. Address decoder 1120 can receive word line voltage VWL from word line voltage generator 1150 and provide programming or read voltages to the selected word lines.

[0089] Page buffer circuit 1130 can be connected to memory cell array 1110 via bit lines BL1 to BLz, where z is a natural number equal to or greater than 2. Page buffer circuit 1130 can temporarily store data to be stored in or read from memory cell array 1110. Page buffer circuit 1130 may include page buffers PB1 to PBz connected to the corresponding bit lines. Each page buffer may include multiple latches for storing or retrieving multi-bit data.

[0090] The input / output circuit 1140 can be internally connected to the page buffer circuit 1130 via data lines, and externally connected to the memory controller via input / output lines IO1 to IOn (see [link]). Figure 10 (1200). The input / output circuit 1140 can receive programming data from the memory controller 1200 during programming operations. In addition, the input / output circuit 1140 can provide data read from the memory cell array 1110 to the memory controller 1200 during read operations.

[0091] The word line voltage generator 1150 can receive internal power from the control logic circuit 1160 and generate the word line voltage VWL required for reading or writing data. The word line voltage VWL can be provided to the selected word line sWL or the unselected word line uWL through the address decoder 1120.

[0092] The word line voltage generator 1150 may include a programming voltage generator (PGM VGEN) 1151 and a pass voltage generator (PASS VGEN) 1152. The programming voltage generator 1151 generates a programming voltage Vpgm supplied to the selected word line sWL during programming operations. The pass voltage generator 1152 generates a pass voltage Vpass supplied to the selected word line sWL and the unselected word line uWL.

[0093] The word line voltage generator 1150 may include a read voltage generator (RD VGEN) 1153 and a read pass voltage generator (RDPS VGEN) 1154. The read voltage generator 1153 generates a selectable read voltage Vrd supplied to the selected word line uWL during a read operation. The read pass voltage generator 1154 generates a read pass voltage Vrdps supplied to the unselected word line uWL. The read pass voltage Vrdps may be a voltage sufficient to turn on a memory cell connected to the unselected word line uWL during a read operation.

[0094] The control logic circuit 1160 can use commands CMD, addresses ADDR, and control signals CTRL provided from the memory controller 1200 to control operations such as read, write, and erase on the memory device 1100. The address ADDR may include a block selection address for selecting a memory block, a row address for selecting a page, and a column address for selecting a bit line. The control logic circuit 1160 can supply internal power to each component based on a first internal power supply voltage VINT1 received from the PMIC 1400.

[0095] Figure 12 It shows Figure 11 The circuit diagram shown is an example embodiment of the memory block BLK1 of the memory cell array. (Refer to...) Figure 12 In memory block BLK1, multiple cell strings STR11 to STR8z can be formed between bit lines BL1 to BLz and the common source line CSL. Each cell string includes a string select transistor SST, multiple memory cells MC1 to MCm, and a ground select transistor GST.

[0096] The series select transistor SST can be connected to the series select lines SSL1 through SSL8 respectively. The ground select transistor GST can be connected to the ground select lines GSL1 through GSL8 respectively. The series select transistor SST can be connected to the bit lines BL1 through BLz respectively, and the ground select transistor GST can be connected to the common source line CSL.

[0097] The first bit line WL1 to the m-th bit line WLm can be connected to multiple memory cells MC1 to MCm along the row direction. The first bit line BL1 to the z-th bit line BLz can be connected to multiple memory cells MC1 to MCm along the column direction.

[0098] The first word line WL1 can be placed above the first ground select lines GSL1 to GSL8. The first memory cell MC1, placed at the same height from the substrate, can be connected to the first word line WL1. The m-th word line WLm can be placed below the first select lines SSL1 to GSL8. The m-th memory cell MCm, placed at the same height from the substrate, can be connected to the m-th word line WLm. Similarly, the second memory cells MC2 to the (m-1)-th memory cells MCm-1, placed at the same height from the substrate, can be connected to the second word lines WL2 to the (m-1)-th word lines WLm-1, respectively.

[0099] Figure 13 It shows Figure 12The diagram shows a circuit diagram of the cell strings in memory block BLK1 selected by the first string selection line SSL1. Cell strings STR11 through STR1z can be selected by the first string selection line SSL1. Cell strings STR11 through STR1z can be connected to the first bit line BL1 through the z-th bit line BLz, respectively. Page buffers PB1 through PBz can be connected to the first bit line BL1 through the z-th bit line BLz, respectively.

[0100] The 11th unit string STR11 can be connected between the first bit line BL1 and the common source line CSL. The 11th unit string STR11 may include a string select transistor SST selected by the first string select line SSL1, first memory cells MC1 to m-th memory cells MCm connected to the first word line WL1 to the m-th word line WLm respectively, and a ground select transistor GST selected by the first ground select line GSL1. The 12th unit string STR12 can be connected between the second bit line BL2 and the common source line CSL. The 1zth unit string STR1z can be connected between the z-th bit line BLz and the common source line CSL.

[0101] The first character line WL1 and the m-th character line WLm can be edge characters (edge ​​WL). The second character line WL2 and the (m-1)-th character line WLm-1 can be adjacent edge characters (adjacent edge WL). The k-th character line WLk can be the selected character line sWL. The (k-1)-th character line WLk-1 and the (k+1)-th character line WLk+1 can be adjacent character lines located next to the selected character line (adjacent WL). When the k-th character line WLk is the selected character line sWL, the remaining character lines (WL1 to WLk-1 and WLk+1 to WLm) can be unselected character lines uWL.

[0102] The first storage cell MC1 and the m-th storage cell MCm can be edge storage cells (edge ​​MCs). The second storage cell MC2 and the (m-1)-th storage cell MCm-1 can be edge-adjacent storage cells (edge-adjacent MCs). The k-th storage cell MCk can be the selected storage cell sMC. The (k-1)-th storage cell MCk-1 and the (k+1)-th storage cell MCk+1 can be storage cells adjacent to the selected storage cell (hereinafter referred to as adjacent storage cells (adjacent MCs)). When the k-th storage cell MCk is the selected storage cell sMC, the remaining storage cells MC1 to MCk-1 and MCk+1 to MCm can be unselected storage cells uMCs.

[0103] A group of storage units selected by a string select line and connected to a word line can constitute a page. For example, storage units WLk selected by the first string select line SSL1 and connected to the k-th word line can constitute a page. For example, eight pages can be configured in the k-th word line WLk. Among these eight pages, the page connected to the first string select line SSL1 is the selected page, and the pages connected to the second string select lines SSL2 through the eighth string select lines SSL8 are unselected pages.

[0104] Figure 14 This illustrates an example embodiment. Figure 10 A flowchart illustrating the power management method for storage devices. (See reference) Figures 2 to 10 The power management integrated circuit 1400 included in the storage device 1000 may include Figures 2 to 9 The DC-DC converter 110a is described in the document.

[0105] In operation S110, the DC-DC converter 110a of the power management integrated circuit 1400 can output an internal intermediate voltage VIM by repeatedly switching the first switch 112 and the second switch 113 on and off. For example, in normal operation, the pulse width modulation control circuit 111 can deactivate or deactivate the third switch signal SW3, and output or activate the first switch signal SW1 and the second switch signal SW2. The DC-DC converter 110a can perform pulse width modulation operation based on the activation or output of the first switch signal SW1 and the second switch signal SW2. For example, the DC-DC converter 110a can perform pulse width modulation operation by repeatedly switching the first switch 112 and the second switch 113 on and off based on the activation of the first switch signal SW1 and the second switch signal SW2.

[0106] Under normal conditions, the first switch 112 can transmit the external power supply voltage VEXT to the second node N2. The second switch 113 can transmit the ground voltage to the second node N2. Therefore, the second node N2 can output a specified internal intermediate voltage VIM. For example, under normal conditions, the DC-DC converter 110a can output an internal intermediate voltage VIM with a level lower than the first reference voltage Vref1 and equal to or higher than the second reference voltage Vref2. In this case, the level of the internal intermediate voltage VIM can be in a normal state.

[0107] In operation S120, when the internal intermediate voltage VIM exceeds the first reference voltage Vref1, the DC-DC converter 110a of the power management integrated circuit 1400 can stop the first switch 112 and output the internal intermediate voltage VIM through the third switch 115 and the second switch 113. For example, when the internal intermediate voltage VIM abnormally rises above the first reference voltage Vref1, the pulse width modulation control circuit 111 can deactivate or stop the first switch signal SW1 and activate or output the third switch signal SW3 and the second switch signal SW2. For example, the pulse width modulation control circuit 111 can perform pulse width modulation operation by repeatedly turning the third switch 115 and the second switch 113 on and off based on the activation of the third switch signal SW3 and the second switch signal SW2. For example, the DC-DC converter 110a can perform pulse width modulation operation by turning off the first switch 112 based on the deactivation of the first switch signal SW1, and repeatedly turning the second switch 113 and the third switch 115 on and off based on the activation of the second switch signal SW2 and the third switch signal SW3.

[0108] In this configuration, the third switch 115 can transmit the reduced voltage through resistor 114 to the second node N2. Therefore, the internal intermediate voltage VIM can be gradually reduced.

[0109] In operation S130, when the internal intermediate voltage VIM drops to a second reference voltage Vref2 that is lower than the first reference voltage Vref1, the power management integrated circuit 1400 can turn off the third switch 115 and repeatedly turn the first switch 112 and the second switch 113 on and off to re-output the internal intermediate voltage VIM. For example, the internal intermediate voltage VIM can be set to remain between the first reference voltage Vref1 and the second reference voltage Vref2. Accordingly, the pulse width modulation control circuit 111 can deactivate or deactivate the third switch signal SW3 and reactivate or output the first switch signal SW1 and the second switch signal SW2 so that the internal intermediate voltage VIM no longer decreases. For example, the DC-DC converter 110a can perform pulse width modulation operation again by turning off the third switch 115 based on the deactivation of the third switch signal SW3 and repeatedly turning the first switch 112 and the second switch 113 on and off based on the activation of the first switch signal SW1 and the second switch signal SW2. Therefore, the internal intermediate voltage VIM can be maintained in the normal state again.

[0110] Figure 15 This illustrates an example embodiment. Figure 10 A flowchart illustrating the power management method for storage devices described herein. (See reference...) Figures 2 to 10 The power management integrated circuit 1400 included in the storage device 1000 may include Figures 2 to 9 The DC-DC converter 110a is described in the document.

[0111] In operation S210, the power management integrated circuit 1400 can output an internal intermediate voltage VIM by repeatedly switching the first switch 112 and the second switch 113 on and off. For example, under normal conditions, the pulse width modulation control circuit 111 can deactivate or deactivate the third switch signal SW3, and output or activate the first switch signal SW1 and the second switch signal SW2. The DC-DC converter 110a can perform pulse width modulation operation based on the activation or output of the first switch signal SW1 and the second switch signal SW2.

[0112] In operation S220, when the internal intermediate voltage VIM exceeds the first reference voltage Vref1, the power management integrated circuit 1400 can turn off the first switch 112 and output the internal intermediate voltage VIM through the third switch 115 and the second switch 113. For example, when the internal intermediate voltage VIM abnormally rises above the first reference voltage Vref1, the pulse width modulation control circuit 111 can deactivate or deactivate the first switch signal SW1 and activate or output the third switch signal SW3 and the second switch signal SW2. For example, the pulse width modulation control circuit 111 can perform pulse width modulation operation by repeatedly turning the third switch 115 and the second switch 113 on and off based on the activation of the third switch signal SW3 and the second switch signal SW2.

[0113] In operation S230, when the internal intermediate voltage VIM exceeds the first reference voltage Vref1, the DC-DC converter 110a of the power management integrated circuit 1400 can send an interrupt signal IRPT to the storage controller 1200. For example, upon receiving the interrupt signal IRPT, the storage controller 1200 can move the data stored in the buffer memory 1300 to the storage device 1100.

[0114] In operation S240, when the internal intermediate voltage VIM drops to a second reference voltage Vref2 that is lower than the first reference voltage Vref1, the DC-DC converter 110a of the power management integrated circuit 1400 can turn off the third switch 115 and repeatedly turn the first switch 112 and the second switch 113 on and off to re-output the internal intermediate voltage VIM. For example, the internal intermediate voltage VIM can be set to remain between the first reference voltage Vref1 and the second reference voltage Vref2. Accordingly, the pulse width modulation control circuit 111 can turn off or stop the third switch signal SW3 and reactivate or output the first switch signal SW1 and the second switch signal SW2 so that the internal intermediate voltage VIM no longer decreases. Therefore, the internal intermediate voltage VIM can be maintained in the normal state again.

[0115] In operation S250, when the internal intermediate voltage VIM drops to the second reference voltage Vref2, the DC-DC converter 110a of the power management integrated circuit 1400 can stop sending the interrupt signal IRPT. When the internal intermediate voltage VIM returns to normal, the storage controller 1200 no longer needs to move the data stored in the buffer memory 1300 to the storage device 1100.

[0116] According to this disclosure, when the internal voltage temporarily increases, the internal voltage can be gradually adjusted back to the specified voltage.

[0117] According to this disclosure, even when the internal voltage temporarily increases, the loss of data stored in the buffer memory can be prevented.

[0118] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A power management integrated circuit, comprising: A DC-DC converter is configured to generate an internal intermediate voltage based on an external power supply voltage, and to output an internal power supply voltage based on said internal intermediate voltage. The DC-DC converter includes: A first switch is connected between a first node to which the external power supply voltage is applied and a second node from which the internal intermediate voltage is output, and is configured to repeatedly turn on and off based on a first switch signal. A second switch is connected between the second node and the ground node and is configured to repeatedly turn on and off based on a second switch signal; A resistor is connected between the first node and the third node; A third switch is connected between the third node and the second node and is configured to repeatedly turn on and off based on a third switch signal; A pulse width modulation control circuit is configured to generate the first switching signal, the second switching signal, and the third switching signal based on the level of the internal intermediate voltage; and A voltage distribution circuit, connected between the second node and the fourth node, is configured to output the internal power supply voltage from the fourth node based on the internal intermediate voltage. Wherein, when the internal intermediate voltage is lower than or equal to the first reference voltage, the DC-DC converter is configured to: repeatedly turn the first and second switches on and off in response to the activation of the first and second switch signals, and turn off the third switch in response to the deactivation of the third switch signal, thereby generating the internal intermediate voltage with a level between the first reference voltage and a second reference voltage lower than the first reference voltage. Wherein, when the internal intermediate voltage exceeds the first reference voltage, the DC-DC converter is configured to: repeatedly turn the second switch and the third switch on and off in response to the activation of the second switch signal and the third switch signal, and turn off the first switch in response to the deactivation of the first switch signal, thereby reducing the internal intermediate voltage to the second reference voltage.

2. The power management integrated circuit according to claim 1, wherein, The voltage distribution circuit includes: An inductor, connected between the second node and the fourth node; and A capacitor is connected between the fourth node and the ground node.

3. The power management integrated circuit according to claim 1, wherein, When the internal intermediate voltage is reduced to the second reference voltage by turning off the first switch, the DC-DC converter is configured to: repeatedly turn the first switch and the second switch on and off in response to the activation of the first switch signal and the second switch signal, and turn off the third switch in response to the deactivation of the third switch signal, thereby generating the internal intermediate voltage with a level between the first reference voltage and the second reference voltage.

4. The power management integrated circuit according to claim 1, wherein, The pulse width modulation control circuit is configured to block all the first switch signal, the second switch signal, and the third switch signal when the internal intermediate voltage exceeds a third reference voltage that is greater than the first reference voltage.

5. The power management integrated circuit according to claim 1, wherein, The first switch includes a drain connected to the first node, a source connected to the second node, and a gate to which the first switch signal is input. The second switch includes a drain connected to the second node, a source connected to the ground node, and a gate to which the second switch signal is input. The third switch includes a drain connected to the third node, a source connected to the second node, and a gate to which the third switch signal is input.

6. The power management integrated circuit according to claim 5, wherein, The pulse width modulation control circuit is configured to receive the internal intermediate voltage as a feedback signal.

7. The power management integrated circuit according to claim 1, wherein, The resistor includes a variable resistor, and When the internal intermediate voltage exceeds the first reference voltage, the pulse width modulation control circuit is configured to output a variable resistor control signal to adjust the resistance value of the variable resistor based on the level of the internal intermediate voltage.

8. The power management integrated circuit according to claim 1, further comprising: A variable resistor is connected in parallel between the first node and the third node. When the internal intermediate voltage exceeds the first reference voltage, the pulse width modulation control circuit is configured to output a variable resistor control signal to adjust the resistance value of the variable resistor based on the level of the internal intermediate voltage.

9. A storage device, comprising: Non-volatile storage devices, comprising multiple storage cells; A volatile storage device is configured to temporarily store data stored in the plurality of storage cells of the non-volatile storage device; A storage controller is configured to transfer data between the non-volatile storage device and the volatile storage device; as well as A power management integrated circuit is configured to generate an internal intermediate voltage and, based on the internal intermediate voltage, output an internal power supply voltage to at least one of the non-volatile memory device, the volatile memory device, and the memory controller. The power management integrated circuit includes a DC-DC converter, which includes: A first switch is connected between a first node from which an external power supply voltage is applied and a second node from which the internal intermediate voltage is output, and is configured to repeatedly turn on and off based on a first switch signal. A second switch is connected between the second node and the ground node and is configured to repeatedly turn on and off based on a second switch signal; A resistor is connected between the first node and the third node; A third switch is connected between the third node and the second node and is configured to repeatedly turn on and off based on a third switch signal; A pulse width modulation control circuit is configured to generate the first switching signal, the second switching signal, and the third switching signal based on the level of the internal intermediate voltage; and A voltage distribution circuit, connected between the second node and the fourth node, is configured to output the internal power supply voltage from the fourth node based on the internal intermediate voltage. Wherein, when the internal intermediate voltage is lower than or equal to the first reference voltage, the DC-DC converter is configured to: repeatedly turn the first and second switches on and off in response to the activation of the first and second switch signals, and turn off the third switch in response to the deactivation of the third switch signal, thereby generating the internal intermediate voltage with a level between the first reference voltage and a second reference voltage lower than the first reference voltage. Wherein, when the internal intermediate voltage exceeds the first reference voltage, the DC-DC converter is configured to: repeatedly turn the second switch and the third switch on and off in response to the activation of the second switch signal and the third switch signal, and turn off the first switch in response to the deactivation of the first switch signal, thereby reducing the internal intermediate voltage to the second reference voltage.

10. The storage device according to claim 9, wherein, The pulse width modulation control circuit is configured to output an interrupt signal to the memory controller when the internal intermediate voltage exceeds the first reference voltage, and The storage controller is configured to move data stored in the volatile storage device to the non-volatile storage device based on the activation of the interrupt signal.

11. The storage device according to claim 10, wherein, When the internal intermediate voltage is reduced to the second reference voltage by turning off the first switch, the DC-DC converter is configured to: repeatedly turn the first switch and the second switch on and off in response to the activation of the first switch signal and the second switch signal, and turn off the third switch in response to the deactivation of the third switch signal, thereby generating the internal intermediate voltage with a level between the first reference voltage and the second reference voltage.

12. The storage device according to claim 11, wherein, The pulse width modulation control circuit is configured to output an interrupt signal that is activated when the internal intermediate voltage exceeds the first reference voltage and deactivated when the internal intermediate voltage drops to the second reference voltage.

13. The storage device according to claim 9, wherein, The resistor includes a variable resistor, and When the internal intermediate voltage exceeds the first reference voltage, the variable resistor is configured such that the resistance value of the variable resistor is adjusted in response to the variable resistor control signal.

14. The storage device according to claim 13, wherein, The variable resistor is located outside the power management integrated circuit, and The storage controller is configured to output the control signal for the variable resistor, or The pulse width modulation control circuit is configured to output the control signal for the variable resistor.

15. The storage device according to claim 9, further comprising: A variable resistor is connected in parallel between the first node and the third node. When the internal intermediate voltage exceeds the first reference voltage, the pulse width modulation control circuit is configured to output a variable resistor control signal to adjust the resistance value of the variable resistor based on the level of the internal intermediate voltage.

16. A power management method for a storage device, the method comprising: By repeatedly switching a first switch connected to an external power supply voltage and repeatedly switching a second switch connected to ground voltage, an internal intermediate voltage with a level between a first reference voltage and a second reference voltage that is lower than the first reference voltage is generated. When the internal intermediate voltage exceeds the first reference voltage, the internal intermediate voltage is reduced by repeatedly turning the second switch and the third switch connected to the external power supply voltage via a resistor and turning off the first switch. When the internal intermediate voltage drops to the second reference voltage, the internal intermediate voltage with a level between the first reference voltage and the second reference voltage is generated again by repeatedly turning the first switch and the second switch on and off and turning off the third switch. as well as An internal power supply voltage is generated based on the internal intermediate voltage, and the internal power supply voltage is output to at least one of the non-volatile memory device, the volatile memory device, and the memory controller. The generation of the internal intermediate voltage is performed based on the level of the internal intermediate voltage and the external power supply voltage.

17. The method of claim 16, further comprising: When the internal intermediate voltage exceeds the first reference voltage, an interrupt signal is sent to the memory controller; as well as In response to the interrupt signal, the data stored in the volatile storage device is moved to the non-volatile storage device.

18. The method of claim 17, further comprising: When the internal intermediate voltage drops to the second reference voltage after exceeding the first reference voltage, the transmission of the interrupt signal stops.

19. The method of claim 16, wherein, The current-carrying capacity of the third switch is less than or equal to that of the first switch.

20. The method of claim 16, wherein, The resistor includes a variable resistor, and The reduction of the internal intermediate voltage includes adjusting the resistance value of the variable resistor based on the level of the internal intermediate voltage.

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