A Dynamic Power Cooperative Allocation and Control Method for Multiple Constraints

Abstract

This invention relates to the field of power transmission and distribution and control equipment manufacturing technology, and discloses a dynamic power collaborative allocation and control method for multiple constraints. The method includes: acquiring transient power distribution data of the internal shared DC bus and the power modulation switching sequence of high-power load units; identifying power off-time windows; extracting discrete transient power consumption command packets from low-power logic nodes; and shifting the trigger clock of the command packets to within the off-time window, generating a reconstructed power allocation timing sequence and sending scheduling commands, provided that the duration of the command packets is not greater than the off-time window. This invention eliminates the superposition of transient peak currents on the bus by offsetting the clock peaks of multiple units, reducing nonlinear parasitic heat dissipation in the system, and improving overall operational stability.

Description

Technical Field

[0001] This invention belongs to the field of power transmission and distribution and control equipment manufacturing technology, and particularly relates to a dynamic power cooperative allocation and control method for multiple constraints. Background Technology

[0002] Currently, for systems with limited internal space that rely on a shared DC bus for power supply, conventional power allocation strategies dynamically adjust the bus output power based on temperature signals or voltage parameters collected from each physical node. However, as the high-frequency drive frequency of the motor and the sampling frequency of the control circuit continue to rise, the single-dimensional threshold response control reveals physical limitations. Since the pulse width modulation turn-on window of the motor driver and the high-frequency task trigger clock of the main control chip are in a disordered and independent state on the time axis, the transient large currents on the shared bus are physically superimposed. The peak current after superposition is excited by Joule's law, resulting in exponentially increasing nonlinear parasitic heat dissipation on the battery internal resistance and DC bus traces.

[0003] To address the system stability risks caused by parasitic heat dissipation, the industry sets stringent temperature alarm thresholds or reduces the overall power limit to delay heat accumulation. However, this hysteresis feedback mechanism, which relies on heat accumulation as a pre-trigger condition, fails to eliminate the heat source and instead leads to a decrease in the mechanical efficiency of the equipment. For example, Chinese invention patent CN109215350B discloses a short-term traffic state prediction method based on RFID electronic license plate data. It uses fuzzy state division and Markov models to predict nonlinear characteristic data streams, anchoring to the overall statistical laws with large physical inertia and time scales of seconds or minutes. Under the microsecond-level hardware conditions of a shared DC bus, the controlled objects are nanosecond-level low-level timer interrupts and high-frequency switching pulse sequences. The traffic prediction mechanism lacks the ability to capture electrical attributes such as transient voltage drops on the bus in real time. The logic architecture does not include atomic-level control instructions for hardware clock offset. There is a scale mismatch between the overall prediction model and the physical laws of the power circuit, making it impossible to achieve pre-avoidance of current superposition spikes from the source of the physical circuit.

[0004] Therefore, the technical problem to be solved by this invention is how to reconstruct the peak-shaving scheduling mechanism on the shared bus at the microsecond time scale while ensuring mechanical output power, and suppress the superposition of nonlinear transient current spikes from the source of the physical circuit. Summary of the Invention

[0005] This invention provides a dynamic power cooperative allocation and control method for multiple constraints, comprising the following steps: Step 101: Obtain transient power distribution data characterizing the internal shared DC bus, and obtain power modulation switching sequence characterizing the high-power load unit; Step 102: Extract the waveform phase parameters and duty cycle parameters from the power modulation switching sequence, and determine the power off time window of the high-power load unit in the current operating cycle based on the waveform phase parameters and duty cycle parameters; Step 103: Generate the task power consumption time sequence for low-power logic nodes to execute the task to be processed based on transient power distribution data, and extract discrete transient power consumption instruction packets from the task power consumption time sequence based on a preset power reference threshold. Step 104: Obtain the instruction execution duration of the discrete transient power consumption instruction packet. For discrete transient power consumption instruction packets whose instruction execution duration is not greater than the time span of the power shutdown time window, perform a clock offset operation based on the system's underlying hardware timer to shift the trigger clock of the discrete transient power consumption instruction packet into the power shutdown time window and generate a reconstructed power allocation timing sequence. Step 105: Send power supply scheduling instructions to low-power logic nodes according to the reconfigured power distribution timing, so that the drive current sequence of high-power load units and the power consumption sequence of low-power logic nodes are in a non-overlapping distribution state on the time axis of the internal shared DC bus.

[0006] Preferably, step 101 specifically includes the following steps: step 201, in each power switching cycle of the high-power load unit, real-time voltage data and real-time current data of the internal shared DC bus are collected at a set sampling frequency; step 202, the real-time voltage data and real-time current data are algebraically multiplied to generate transient power distribution data.

[0007] Preferably, step 103 specifically includes the following steps: Step 301, obtaining the average power consumption characteristic value of the low-power logic node executing the task to be processed within the historical time period; Step 302, generating the task power consumption time sequence based on the average power consumption characteristic value and the preset compensation coefficient; Step 303, when it is determined that the instantaneous power consumption in the task power consumption time sequence meets the preset calculation model, extracting the corresponding discrete transient power consumption instruction packet; The preset calculation model is: P=k×E, where P is the instantaneous power consumption, k is the preset compensation coefficient, and E is the average power consumption characteristic value.

[0008] Preferably, step 102 specifically includes the following steps: step 401, determining the power turn-on start point of the high-power load unit based on waveform phase parameters; step 402, calculating the time span from the power turn-on start point to the power turn-off start point based on duty cycle parameters; step 403, establishing the time interval between the power turn-off start point and the power turn-on start point of the next cycle as the power turn-off time window.

[0009] Preferably, step 105 specifically includes the following steps: step 501, extracting the hardware interrupt trigger identifier of the discrete transient power consumption instruction packet; step 502, updating the priority execution parameters of the hardware interrupt trigger identifier according to the reconstructed power allocation timing; step 503, generating a power supply scheduling instruction and sending it to the low-power logic node according to the updated priority execution parameters.

[0010] Preferably, the tasks to be processed include data uplink transmission tasks and high-frequency sampling tasks of environmental parameters.

[0011] Preferably, the dynamic power collaborative allocation and control method for multiple constraints further includes the following steps: Step 701, obtaining the transient voltage drop amplitude and preset line parasitic impedance parameters on the internal shared DC bus; Step 702, calculating the parasitic heat dissipation increment of the internal shared DC bus in the peak operating range based on the transient voltage drop amplitude and the line parasitic impedance parameters; Step 703, comparing the parasitic heat dissipation increment with a preset physical threshold; Step 704, generating a timing reconstruction trigger signal when the parasitic heat dissipation increment is greater than or equal to the preset physical threshold, to initiate the execution of steps 101 to 105.

[0012] Preferably, step 702 specifically includes the following steps: step 801, extracting the voltage data sequence of the internal shared DC bus in multiple consecutive sampling periods; step 802, identifying the lowest voltage value and the reference voltage value in the voltage data sequence; step 803, calculating the difference between the reference voltage value and the lowest voltage value, and determining the difference as the transient voltage drop amplitude; step 804, dividing the square of the transient voltage drop amplitude by the line parasitic impedance parameter to calculate the parasitic heat dissipation increment.

[0013] Preferably, the dynamic power cooperative allocation and control method for multiple constraints further includes the following steps: Step 901, acquiring real-time remaining energy data of the system power supply unit and real-time space temperature data inside the physical cavity; Step 902, generating a set of multi-constraint evaluation parameters based on the real-time remaining energy data and real-time space temperature data; Step 903, updating the global operating frequency parameters of the high-power load unit based on the set of multi-constraint evaluation parameters.

[0014] Preferably, step 902 specifically includes the following steps: step 1001, extracting the temperature rise slope of real-time spatial temperature data within a historical time window; step 1002, calculating the corresponding thermal interference state value based on the temperature rise slope; step 1003, logically combining the thermal interference state value with real-time residual energy data to generate a set of multi-constraint evaluation parameters.

[0015] Compared with existing technologies, the dynamic power cooperative allocation and control method of the present invention, which is oriented towards multiple constraints, has the following advantages: 1. In dynamic power coordination allocation under multiple constraints, the real-time carrier period and duty cycle parameters of the motor drive signal are extracted by the power scheduling module to identify the time windows for power on and off. Based on this, the tasks to be processed by the auxiliary functional modules are decomposed into discrete transient power consumption command packets. The trigger clock of the above command packets is mapped to the dead time window of the motor drive signal, so that the motor drive current sequence and the main control logic power consumption sequence are staggered on the time axis of the shared DC bus. The orthogonal reconstruction of the power supply timing eliminates the physical superposition of peak currents on the shared bus. Without reducing the mechanical power of the motor, the nonlinear parasitic heat dissipation of the battery internal resistance and the line is suppressed from the source of the physical circuit.

[0016] 2. This technical solution collects the transient voltage drop amplitude on the shared DC bus and calculates the parasitic heat dissipation increment within the peak time window by combining it with the preset line parasitic impedance parameters. When the heat dissipation increment is detected to be close to the preset physical threshold, the time-division power interleaving logic is actively activated. This mechanism changes the technical path of the conventional system that only relies on temperature accumulation to passively reduce the frequency. By transforming the overall heat accumulation problem into an objective and measurable bus transient current control problem, the system can reorganize the energy distribution sequence in advance at the initial stage of thermal interference in the local physical space, thereby achieving the prevention of local overheating risks in the hardware.

[0017] 3. For the working conditions of multiple power-consuming components working together in a small enclosed cavity, this technical architecture aims to minimize the square integral of the transient peak current of the bus. It dynamically modifies the underlying interrupt triggering timing of the controller and coordinates the power supply logic of the motor driver and main control chip through physical-level clock offset operation. This underlying timing peak allocation mechanism transforms the total power limit into the peak scheduling of charge packets, ensuring the power supply continuity of each power-consuming unit and the stability of the system under continuous load conditions, and improving the product's endurance conversion efficiency and overall operational reliability during continuous high-voltage working cycles. Attached Figure Description

[0018] Figure 1 This is a flowchart of the dynamic power collaborative allocation and peak-shaving control method of the present invention; Figure 2 This is a system hardware topology and signal interaction diagram of the shared DC bus of this invention. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0020] It should be noted that all directional and positional terms used in this invention, such as: up, down, left, right, front, back, vertical, horizontal, inner, outer, top, bottom, transverse, longitudinal, center, etc., are only used to explain the relative positional relationship and connection between components in a specific state (as shown in the accompanying drawings). They are only for the convenience of describing this invention and do not require that this invention be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention. In addition, the descriptions of "first," "second," etc., in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated.

[0021] In the description of this invention, unless otherwise explicitly specified and limited, the terms installation, connection, and linking should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0022] In the description of this specification, references to the terms "an embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example, and the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0023] A dynamic power cooperative allocation and control method oriented towards multiple constraints includes the following steps: Step 101: Obtain transient power distribution data characterizing the internal shared DC bus, and obtain power modulation switching sequence characterizing the high-power load unit; Step 102: Extract the waveform phase parameters and duty cycle parameters from the power modulation switching sequence, and determine the power off time window of the high-power load unit in the current operating cycle based on the waveform phase parameters and duty cycle parameters; Step 103: Generate the task power consumption time sequence for low-power logic nodes to execute the task to be processed based on transient power distribution data, and extract discrete transient power consumption instruction packets from the task power consumption time sequence based on a preset power reference threshold. Step 104: Obtain the instruction execution duration of the discrete transient power consumption instruction packet. For discrete transient power consumption instruction packets whose instruction execution duration is not greater than the time span of the power shutdown time window, perform a clock offset operation based on the system's underlying hardware timer to shift the trigger clock of the discrete transient power consumption instruction packet into the power shutdown time window and generate a reconstructed power allocation timing sequence. Step 105: Send power supply scheduling instructions to low-power logic nodes according to the reconfigured power distribution timing, so that the drive current sequence of high-power load units and the power consumption sequence of low-power logic nodes are in a non-overlapping distribution state on the time axis of the internal shared DC bus.

[0024] Preferably, step 101 specifically includes the following steps: step 201, in each power switching cycle of the high-power load unit, real-time voltage data and real-time current data of the internal shared DC bus are collected at a set sampling frequency; step 202, the real-time voltage data and real-time current data are algebraically multiplied to generate transient power distribution data.

[0025] Preferably, step 103 specifically includes the following steps: Step 301, obtaining the average power consumption characteristic value of the low-power logic node executing the task to be processed within the historical time period; Step 302, generating the task power consumption time sequence based on the average power consumption characteristic value and the preset compensation coefficient; Step 303, when it is determined that the instantaneous power consumption in the task power consumption time sequence meets the preset calculation model, extracting the corresponding discrete transient power consumption instruction packet; The preset calculation model is: P=k×E, where P is the instantaneous power consumption, k is the preset compensation coefficient, and E is the average power consumption characteristic value.

[0026] Preferably, step 102 specifically includes the following steps: step 401, determining the power turn-on start point of the high-power load unit based on waveform phase parameters; step 402, calculating the time span from the power turn-on start point to the power turn-off start point based on duty cycle parameters; step 403, establishing the time interval between the power turn-off start point and the power turn-on start point of the next cycle as the power turn-off time window.

[0027] Preferably, step 105 specifically includes the following steps: step 501, extracting the hardware interrupt trigger identifier of the discrete transient power consumption instruction packet; step 502, updating the priority execution parameters of the hardware interrupt trigger identifier according to the reconstructed power allocation timing; step 503, generating a power supply scheduling instruction and sending it to the low-power logic node according to the updated priority execution parameters.

[0028] Preferably, the tasks to be processed include data uplink transmission tasks and high-frequency sampling tasks of environmental parameters.

[0029] Preferably, the dynamic power collaborative allocation and control method for multiple constraints further includes the following steps: Step 701, obtaining the transient voltage drop amplitude and preset line parasitic impedance parameters on the internal shared DC bus; Step 702, calculating the parasitic heat dissipation increment of the internal shared DC bus in the peak operating range based on the transient voltage drop amplitude and the line parasitic impedance parameters; Step 703, comparing the parasitic heat dissipation increment with a preset physical threshold; Step 704, generating a timing reconstruction trigger signal when the parasitic heat dissipation increment is greater than or equal to the preset physical threshold, to initiate the execution of steps 101 to 105.

[0030] Preferably, step 702 specifically includes the following steps: step 801, extracting the voltage data sequence of the internal shared DC bus in multiple consecutive sampling periods; step 802, identifying the lowest voltage value and the reference voltage value in the voltage data sequence; step 803, calculating the difference between the reference voltage value and the lowest voltage value, and determining the difference as the transient voltage drop amplitude; step 804, dividing the square of the transient voltage drop amplitude by the line parasitic impedance parameter to calculate the parasitic heat dissipation increment.

[0031] Preferably, the dynamic power cooperative allocation and control method for multiple constraints further includes the following steps: Step 901, acquiring real-time remaining energy data of the system power supply unit and real-time space temperature data inside the physical cavity; Step 902, generating a set of multi-constraint evaluation parameters based on the real-time remaining energy data and real-time space temperature data; Step 903, updating the global operating frequency parameters of the high-power load unit based on the set of multi-constraint evaluation parameters.

[0032] Preferably, step 902 specifically includes the following steps: step 1001, extracting the temperature rise slope of real-time spatial temperature data within a historical time window; step 1002, calculating the corresponding thermal interference state value based on the temperature rise slope; step 1003, logically combining the thermal interference state value with real-time residual energy data to generate a set of multi-constraint evaluation parameters.

[0033] Example 1: In a specific industrial deployment scenario, an internal shared DC bus provides continuous power to multiple electrical units. This environment involves high-power load units drawing large currents from the system, while low-power logic nodes concurrently perform high-frequency data uplink transmission tasks and high-frequency environmental parameter sampling tasks. This objectively creates power conflicts at the electrical hardware level. If the power-on phase of the high-power load unit and the high-frequency sampling pulse of the low-power logic node are allowed to coincide on the time axis without order, they will generate a transient peak current superposition on the internal shared DC bus. This superposition current, according to Joule's law, induces exponentially increasing nonlinear parasitic heat dissipation in the battery internal resistance and DC bus wiring, causing heat loss on the internal shared DC bus. This method addresses the transient voltage drop amplitude by focusing on the hardware-level control dimension of the microsecond-level power supply timing. It transforms the physical space's heat suppression requirements into peak-shifting reconstruction logic for the transient power topology on the internal shared DC bus. Specifically, the system utilizes a 32-bit underlying hardware timer within the main control chip to increment at a clock frequency of 100MHz. By configuring preemption priority through a nested vector interrupt controller, the logical judgment delay from detecting the transient voltage drop signal to generating the timing reconstruction trigger signal is controlled within 2µs. Furthermore, the output comparison register of the hardware timer directly triggers the underlying power supply scheduling instruction, enabling peak-shifting mapping of charge packets to be completed at the microsecond level without CPU software intervention.

[0034] The power scheduling module within the main control chip continuously acquires transient power distribution data representing the internal shared DC bus and power modulation switching sequences representing high-power load units at a set sampling frequency. To eliminate high-frequency switching noise during dynamic power changes and avoid phase delay caused by traditional filtering, this invention embeds an adaptive noise cancellation model based on state estimation into the power scheduling module. This model dynamically weights the predicted power state from the previous moment with the current sensor measurement, achieving a bias towards smooth filtering during power stability periods and a bias towards rapid following during power abrupt changes. This process ensures that the phase parameters extracted in subsequent step 102 and the charge packet peak-shifting reconstruction in step 104 have microsecond-level time-domain accuracy, supporting the transient stability of the physical circuit from an algorithmic perspective. The layer hardware timer extracts waveform phase parameters and duty cycle parameters from the power modulation switch sequence. Based on this set of underlying electrical characteristics, the system determines the power on-start point and power off-start point of the high-power load unit in the current operating cycle. The system establishes the time interval from the power off-start point to the power on-start point of the next cycle as the power off time window. Based on this synchronization benchmark, the system obtains the average power consumption characteristic value E of the low-power logic node executing the task to be processed in the historical time cycle. Based on the average power consumption characteristic value E and the preset compensation coefficient k, the system generates the task power consumption sequence. Specifically, the system determines that the instantaneous power consumption P in the task power consumption sequence satisfies the preset calculation model, i.e.: P=k×E, where P is the instantaneous power consumption, k is the preset compensation coefficient, and E is the average power consumption characteristic value.

[0035] The system extracts discrete transient power consumption command packets based on a preset power reference threshold. After the control unit determines that the execution duration of the discrete transient power consumption command packet is no greater than the time span of the power shutdown time window, it starts the system's underlying hardware timer to perform a clock offset operation, shifting the trigger clock of the discrete transient power consumption command packet into the power shutdown time window. The system extracts the hardware interrupt trigger flag of the discrete transient power consumption command packet, updates the priority execution parameters of the hardware interrupt trigger flag according to the reconstructed power allocation timing, and sends the generated power dispatch command to the low-power logic node. This ensures that the drive current sequence of the high-power load unit and the power consumption sequence of the low-power logic node are non-overlapping on the time axis of the internally shared DC bus, through microsecond-level... To achieve orthogonality of the power-taking sequence of the load units, the peak current superposition phenomenon on the internal shared DC bus is eliminated. While maintaining the mechanical power of the high load units, the nonlinear parasitic heat dissipation of the battery internal resistance and the line is suppressed. In step 103, the power consumption sequence of the low-power logic node executing the task to be processed is generated by calling the task power consumption feature template library pre-stored in the main control chip memory. The template library contains typical current feature envelopes of data uplink transmission tasks and environmental parameter high-frequency sampling tasks. During the device self-test cycle, a narrow pulse current of known amplitude is injected into the internal shared DC bus through the power scheduling module. The transient voltage response data of the internal shared DC bus under pulse excitation is collected synchronously by the current sensor, and the equivalent parasitic resistance of the internal shared DC bus is calculated. The preset compensation coefficient k is based on the maximum allowable voltage fluctuation amplitude ΔV of the internal shared DC bus and the equivalent parasitic resistance. The physical mapping relationship is determined, and the specific formula is as follows: Where k is the preset compensation coefficient, ΔV is the maximum allowable voltage fluctuation amplitude of the internal shared DC bus, and I is the peak power consumption current of the low-power logic node. This is the equivalent parasitic resistance.

[0036] For the clock offset operation in step 104, the underlying hardware timer input capture channel is used to lock the level flip edge of the power modulation switch sequence, and the timer value corresponding to the level flip edge is established as the power shutdown start point. To compensate for the crystal oscillator frequency shift caused by the temperature rise in the underground charging pile environment, calibration pulses are periodically sent to the internal shared DC bus to extract the time delay deviation of the reflected waveform. The ratio of the calculated deviation to the original period of the calibration pulse is used to correct the increment of the underlying hardware timer count, and the target offset count value. The calculation logic is as follows ,in The target offset count value. The count value represents the power shutdown start point, and ΔT represents the preset phase alignment deviation time. The target offset count value is determined by the real-time operating frequency of the underlying hardware timer. When the count value of the underlying hardware timer reaches the target value, the hardware triggers the low-power logic node interrupt service routine to send a power supply scheduling instruction. In the reconstructed power distribution timing stability control, the execution duration of the discrete transient power consumption instruction packet is determined according to the pulse width of the current waveform when the low-power logic node executes the task instruction set. A safety protection timing interval with a duration of 10% is set within the power shutdown time window. The trigger clock of the discrete transient power consumption instruction packet is limited to shifting within the window outside the safety protection timing interval. When the increase in parasitic heat dissipation is detected to be greater than the preset physical threshold and the power shutdown time window span is reduced to less than the instruction execution duration, the secondary adjustment program is started. The power shutdown time window span is expanded by reducing the carrier switching frequency of the high-power load unit, so that the drive current sequence and the power consumption sequence are in a non-overlapping distribution state on the internal shared DC bus time axis.

[0037] Example 2: In a hardware-in-the-loop test platform simulating the internal power conversion environment of an underground AC charging pile, the test system includes a DC power distribution network simulating an internal shared DC bus, a high-power load unit, and a low-power logic node performing high-frequency sampling. To suppress background electromagnetic interference in the test environment and simulate a real electrical environment, Gaussian white noise with a signal-to-noise ratio of 20dB and 50Hz power frequency interference harmonics are superimposed on the test signal source. The determination of the sampling period involves an engineering trade-off between the spectral bandwidth of the monitored signal and the system's processing load. When the voltage ripple spectral bandwidth on the internal shared DC bus is relatively wide, in order to satisfy the Nyquist sampling theorem and reduce the risk of signal aliasing, the sampling period is set to the lower limit of the range, i.e., 10μs. Under this deterministic procedure, the test system continuously collects temperature rise data and current waveform changes of the DC bus under different load rates.

[0038] The experimental design included a control group using existing technology and a sample group using the present invention. The raw input data of the control group under standard operating conditions was obtained. When the high-power load unit was powered by 300V DC and operating at a 50% duty cycle, the transient peak current measured on the internal shared DC bus of the control group was 45.6A, with a corresponding bus voltage ripple amplitude of 12.5V. At this time, the average power consumption characteristic value E of the low-power logic node was 5.2W. Based on the calculation model P=k×E, where the preset compensation coefficient k is selected as 1.2, the calculated instantaneous power consumption P is 6.24W, where P is the instantaneous power consumption and k is the preset value. The compensation coefficient is E, which is the average power consumption characteristic value. Due to the physical overlap between the high-power turn-on phase and the sampling pulse, the temperature rise of the DC bus wiring in the control group after 10 minutes of continuous operation was 18.5℃. Subsequently, under the same operating conditions, the main control chip of the present invention extracted the power modulation switch sequence, identified a power turn-off time window with a duration of 5.2ms, and the control unit shifted the discrete transient power consumption command packet to the center point of the power turn-off time window for execution. The measured transient peak current of the present invention sample group was 28.4A, the voltage ripple amplitude converged to 4.6V, and the corresponding DC bus wiring temperature rise was reduced to 10.2℃.

[0039] Under the boundary condition of 90% load rate, the power turn-off time window of the high-power load unit is reduced to 1.1ms. The transient peak current measured in the control group increases to 85.6A and triggers an overheat warning. However, the sample of this invention limits the transient peak current to 58.2A through microsecond-level timing reconstruction, and the system operates stably. Subsequent gradient verification data show that when the load rate of the high-power load unit further increases, causing the power turn-off time window to be less than the instruction execution duration of the discrete transient power consumption instruction packet, the growth trend of the temperature rise suppression rate tends to level off and exhibits nonlinear saturation characteristics. This data inflection point confirms the effectiveness of the logical constraint that the instruction execution duration is not greater than the power turn-off time window in suppressing the nonlinear parasitic heat dissipation of the internal shared DC bus. The final experimental data proves that this method suppresses system heat loss while maintaining output power through the physical orthogonalization of the power topology.

[0040] Example 3: When the system is in a physical environment where the control circuit and power conversion module are integrated within an underground AC charging pile, the high-frequency communication task executed by the main control board and the sensor sampling task, due to the asynchronous nature of the trigger clock, will transiently overlap with the drive pulse peak of the power conversion module on a microsecond time scale. This results in a transient peak current that induces nonlinearly increasing parasitic heat dissipation on the internal shared DC bus, leading to a decrease in the logic sampling accuracy of the control circuit. This method, through dynamic mapping of the underlying timer count value, limits the randomly distributed power-consuming load within the power transistor's turn-off dead zone, thus separating the heat source from the physical circuit level. The system addresses this by adjusting the compensation coefficient. Establish a calibration procedure based on physical impedance feedback. During the equipment startup self-test cycle, the control unit obtains the equivalent parasitic resistance of the internal shared DC bus. Equivalent series resistance with filter capacitor The pulse load injection process is initiated, and the bus voltage fluctuation response curves under different current change rates are measured. The proportional factor that keeps the bus transient voltage drop amplitude ΔV within the preset voltage safety threshold is determined and established as the compensation coefficient k. The calculation model of the compensation coefficient k is as follows: Where k is the compensation coefficient. For equivalent parasitic resistance, This is the equivalent series resistance.

[0041] The system establishes a sliding time window with a sampling period length of 100 cycles to continuously collect real-time power consumption current data of low-power logic nodes. Each sampling point within the sliding time window is assigned a weighting factor that increases with time to calculate the weighted average, which is then established as the average power consumption characteristic value E. When the system identifies the current value of the underlying timer corresponding to the power shutdown start point of a high-power load unit... At that time, the system calculates the target offset count value. Target offset count value The calculation logic is as follows: ,in, The target offset count value is a dimensionless integer. The count value is the starting point of power shutdown, and ΔT is the preset phase alignment deviation time. The system writes the target offset count value to the hardware timer's compare register to determine the timer's operating frequency. The hardware interrupt trigger time of the low-power logic node is updated. This operation forcibly shifts the discrete transient power consumption instruction on the physical time axis to the midpoint of the power transistor's turn-off dead zone for execution. After 1000 hours of continuous operation, the temperature rise rate of the internal shared DC bus remained within the set temperature gradient range, and the bit error rate of the high-frequency communication link was measured to be 0.002%. This indicates that the underlying timing reconstruction logic suppresses electrical noise interference caused by thermal stress, thereby ensuring the system stability and orderly power distribution within the confined space of the underground charging equipment.

[0042] Example 4: In the field deployment scenario of the underground AC charging pile control system, due to the differences in the physical wiring length of the DC bus and the layout of the filter capacitors caused by changes in the electrical topology of the installation environment, the system starts a clock offset calibration program for the hardware timer before entering the task scheduling cycle. The main control unit sends a controlled narrow pulse sequence to the internal shared DC bus and monitors the resulting reflected waveform delay deviation. The physical transmission rate of the pulse sequence in the DC power distribution network is extracted, and the obtained rate is algebraically compared with the internal crystal oscillator frequency to determine the operating frequency of the timer under the current operating conditions. The operating frequency of the timer The calculation model is as follows: ,in, ζ is the operating frequency of the timer, and ζ is the preset synchronization correction factor. This represents the time delay deviation of the reflected waveform.

[0043] After determining the hardware baseline parameters of the underlying timer, the system obtains the static leakage current of the low-power logic node in standby mode and determines it as the dynamic reference zero point of the task power consumption timing. It continuously monitors the transient voltage drop amplitude ΔV of the bus under different load rates to correct the weight of the compensation coefficient k. The peak envelope period of the switching noise of the power conversion module at different duty cycles is determined as the selection basis for the preset phase alignment deviation time ΔT. In the environment of bus parasitic impedance drift caused by underground high humidity conditions, the system shifts the trigger clock of the logic task to the midpoint of the turn-off dead zone of the high-power load unit. The internal shared DC bus is maintained in the preset power distribution steady state.

[0044] Example 5: In the scenario of calibrating the physical parasitic parameters of the shared DC bus inside an underground AC charging pile, since the DC wiring impedance varies with the physical topology, the system inputs a pulse current excitation with a set slope to the internal shared DC bus through the power scheduling module. The transient waveform response data of the bus under the pulse current excitation is obtained by the current sensor. The main control chip matches the damped oscillation characteristics in the transient waveform response data with the preset impedance reference to determine the characteristic impedance matrix characterizing the high-frequency electrical characteristics of the bus. This determines the initial calibration value of the preset phase alignment deviation time ΔT, and the system acquires the characteristic impedance matrix. Then, the task power consumption timing baseline construction procedure of the low-power logic node in the working state is initiated. The low-power logic node is instructed to run a discrete transient power consumption instruction package with N instruction cycles in a loop. The main control unit reads the count value of the underlying register and calculates the corresponding instantaneous power consumption. By calculating the instantaneous power consumption over N cycles The mean value is used to determine the reference component of the average power consumption characteristic value E. The calculation formula is as follows: Where E is the average power consumption characteristic value, and N is the number of instruction cycles. Let be the instantaneous power consumption during the i-th cycle.

[0045] After establishing the baseline component of the average power consumption characteristic value E, a dynamic calibration procedure based on signal-to-noise ratio discrimination is executed for the electromagnetic noise coupling background of the underground environment. The control unit obtains the background noise energy sequence of the internal shared DC bus under no-load conditions. The peak value of the sequence is calculated, and the feature envelope coefficient λ is determined based on the task attributes of the task to be processed. This is then used to analyze the background noise energy sequence. The algebraic product of the peak value and the characteristic envelope coefficient λ is established as the preset power reference threshold Th. The calculation model for the preset power reference threshold Th is as follows: Where Th is the preset power reference threshold, and λ is the feature envelope coefficient. The background noise energy sequence; in the priority configuration procedure for microcontroller low-level hardware interrupts, when updating priority execution parameters, the system directly accesses the nested vector interrupt controller register of the central processing unit, converts the clock offset in the reconstructed power allocation timing into the preemption priority weight of the hardware interrupt, and writes it into the priority bit field of the corresponding register. This procedure locks the preemption order of the interrupt vector, ensuring that the interrupt service subroutine of the low-power logic node only resumes operation when the count value of the underlying timer reaches the target offset count value. The timing is forcibly triggered by hardware, thereby completing the physical locking of the power supply phase on a microsecond scale without changing the task code logic, ensuring that the power consumption sequence of low-power logic nodes and the drive current sequence of high-power load units satisfy the non-overlapping constraint on the time axis.

[0046] Example 6: Under the high-interference conditions of underground AC charging piles, complex electromagnetic noise is superimposed on the internal shared DC bus due to the frequent switching of the power conversion module. To optimize and eliminate noise data during dynamic power changes, an adaptive filtering method is adopted. This method is based on a physical model of power changes and dynamically adjusts the filter gain through two stages: prediction and updating. Its core lies in establishing state equations and measurement equations to avoid the fixed delay of low-pass filtering. First, state equations are established to describe the evolution of the predicted power value: ,in, For the present The prior prediction of power at time t; The state transition matrix is ​​set based on the constant power model or the uniform power physical model and is used to characterize the evolution trend of power over time. For the previous moment The optimal power state estimate; To address system process noise; secondly, to establish measurement equations to correlate with real-time data acquired by sensors: ,in, For current or voltage sensors Real-time measurements containing noise collected at all times; For measuring the gain matrix; Gaussian measurement noise is introduced into the measurement environment; during dynamic operation, the system adjusts the filter gain through the following logic. When the main control unit detects that a high-power load unit is in a stable power operating range, the system automatically reduces the gain. This causes the filter weights to be biased towards the measured value. The statistical smoothing results are used to suppress bus ripple; when the main control unit detects a jump in the power modulation switching sequence, the system automatically increases the gain. This causes the filter weights to be biased towards the predicted value. This enables rapid tracking of power change edges; the final output value follows the formula below: ,in, The transient power distribution data after noise cancellation is filtered out to remove pseudo spike data caused by switching actions without causing phase delay, so that the extraction of discrete transient power consumption command packets is more in line with the real physical power consumption law.

[0047] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit of this application and the scope of protection of this invention, and all of these forms are within the protection scope of this application.

Claims

1. A dynamic power cooperative allocation and control method oriented towards multiple constraints, characterized in that, Includes the following steps: Step 101: Obtain transient power distribution data characterizing the internal shared DC bus, and obtain power modulation switching sequence characterizing the high-power load unit; Step 102: Extract the waveform phase parameters and duty cycle parameters from the power modulation switching sequence, and determine the power off time window of the high-power load unit in the current operating cycle based on the waveform phase parameters and duty cycle parameters; Step 103: Generate the task power consumption time sequence for low-power logic nodes to execute the task to be processed based on transient power distribution data, and extract discrete transient power consumption instruction packets from the task power consumption time sequence based on a preset power reference threshold. Step 104: Obtain the instruction execution duration of the discrete transient power consumption instruction packet. For discrete transient power consumption instruction packets whose instruction execution duration is not greater than the time span of the power shutdown time window, perform a clock offset operation based on the system's underlying hardware timer to shift the trigger clock of the discrete transient power consumption instruction packet into the power shutdown time window and generate a reconstructed power allocation timing sequence. Step 105: Send power supply scheduling instructions to low-power logic nodes according to the reconfigured power distribution timing, so that the drive current sequence of high-power load units and the power consumption sequence of low-power logic nodes are in a non-overlapping distribution state on the time axis of the internal shared DC bus.

2. The dynamic power cooperative allocation and control method for multiple constraints as described in claim 1, characterized in that, Step 101 specifically includes the following steps: Step 201, in each power switching cycle of the high-power load unit, real-time voltage data and real-time current data of the internal shared DC bus are collected at a set sampling frequency; Step 202, the real-time voltage data and real-time current data are algebraically multiplied to generate transient power distribution data.

3. The dynamic power cooperative allocation and control method for multiple constraints according to claim 1, characterized in that, Step 103 specifically includes the following steps: Step 301, obtaining the average power consumption characteristic value of the low-power logic node executing the task to be processed within the historical time period; Step 302, generating the task power consumption time sequence based on the average power consumption characteristic value and the preset compensation coefficient; Step 303, when it is determined that the instantaneous power consumption in the task power consumption time sequence meets the preset calculation model, extracting the corresponding discrete transient power consumption instruction packet; The preset calculation model is: P=k×E, where P is the instantaneous power consumption, k is the preset compensation coefficient, and E is the average power consumption characteristic value.

4. The dynamic power cooperative allocation and control method for multiple constraints as described in claim 1, characterized in that, Step 102 specifically includes the following steps: Step 401, determine the power turn-on start point of the high-power load unit based on the waveform phase parameters; Step 402, calculate the time span from the power turn-on start point to the power turn-off start point based on the duty cycle parameters; Step 403, establish the time interval between the power turn-off start point and the power turn-on start point of the next cycle as the power turn-off time window.

5. The dynamic power cooperative allocation and control method for multiple constraints as described in claim 1, characterized in that, Step 105 specifically includes the following steps: Step 501, extract the hardware interrupt trigger identifier of the discrete transient power consumption instruction packet; Step 502, update the priority execution parameters of the hardware interrupt trigger identifier according to the reconstructed power allocation timing; Step 503, generate a power supply scheduling instruction and send it to the low-power logic node according to the updated priority execution parameters.

6. The dynamic power cooperative allocation and control method for multiple constraints according to claim 1, characterized in that, The tasks to be processed include data uplink transmission tasks and high-frequency sampling of environmental parameters.

7. The dynamic power cooperative allocation and control method for multiple constraints according to claim 1, characterized in that, The dynamic power cooperative allocation and control method for multiple constraints further includes the following steps: Step 701, obtaining the transient voltage drop amplitude and preset line parasitic impedance parameters on the internal shared DC bus; Step 702, calculating the parasitic heat dissipation increment of the internal shared DC bus in the peak operating range based on the transient voltage drop amplitude and the line parasitic impedance parameters; Step 703, comparing the parasitic heat dissipation increment with a preset physical threshold; Step 704, generating a timing reconstruction trigger signal when the parasitic heat dissipation increment is greater than or equal to the preset physical threshold, to initiate the execution of steps 101 to 105.

8. The dynamic power cooperative allocation and control method for multiple constraints according to claim 7, characterized in that, Step 702 specifically includes the following steps: Step 801, extracting the voltage data sequence of the internal shared DC bus in multiple consecutive sampling periods; Step 802, identifying the lowest voltage value and the reference voltage value in the voltage data sequence; Step 803, calculating the difference between the reference voltage value and the lowest voltage value, and determining the difference as the transient voltage drop amplitude; Step 804, dividing the square of the transient voltage drop amplitude by the line parasitic impedance parameter to calculate the parasitic heat dissipation increment.

9. A dynamic power cooperative allocation and control method for multiple constraints according to claim 1, characterized in that, The dynamic power cooperative allocation and control method for multiple constraints also includes the following steps: Step 901, acquiring real-time remaining energy data of the system power supply unit and real-time space temperature data inside the physical cavity; Step 902, generating a set of multi-constraint evaluation parameters based on the real-time remaining energy data and real-time space temperature data; Step 903, updating the global operating frequency parameters of the high-power load unit based on the set of multi-constraint evaluation parameters.

10. A dynamic power cooperative allocation and control method for multiple constraints according to claim 9, characterized in that, Step 902 specifically includes the following steps: Step 1001, extract the temperature rise slope of the real-time spatial temperature data within the historical time window; Step 1002, calculate the corresponding thermal interference state value based on the temperature rise slope; Step 1003, logically combine the thermal interference state value with the real-time residual energy data to generate a set of multi-constraint evaluation parameters.

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