A chopper amplifier

Abstract

This invention relates to a chopper amplifier, comprising a clock generator module, an input chopper module, an amplifier module, and an output chopper module. The clock generator module includes a zero-crossover aligned clock circuit, which outputs an intermediate clock based on the differential input signal and detects the zero-crossover point, aligning the edge of the intermediate clock to the zero-crossover point to generate an aligned chopper clock. The output chopper module is connected to a self-filling circuit, which, in conjunction with the chopper clock, samples the differential output voltage during the chopper steady-state phase and, during the chopper transition phase, forms a short circuit between the differential output nodes, causing the current polarity of the amplifier module to internally reverse, while simultaneously performing self-filling. By utilizing zero-crossover aligned chopper technology and / or self-filling technology, intermodulation distortion caused by chopping is suppressed or eliminated mechanistically without increasing power consumption or noise, significantly improving the linearity and usable input frequency range of the chopper amplifier.

Description

Technical Field

[0001] The present invention relates to the technical field of chopper amplifiers, and particularly relates to a chopper amplifier. Background Art

[0002] In high-precision CMOS operational amplifiers, input offset voltage and 1 / f noise severely limit the measurement accuracy of low-frequency signals. For this reason, the industry generally adopts the chopping technology: by modulating the signal to the chopping frequency FCH at the input end, shifting the DC and low-frequency noise to high frequencies, and then filtering out the high-frequency ripples through a simple low-pass filter (LPF) at the output end, so as to obtain extremely low offset and low 1 / f noise within the effective signal bandwidth.

[0003] However, the bandwidth of the actual operational amplifier is limited, and the chopping process will introduce intermodulation distortion (IMD).

[0004] Such as Figure 1 , the limited bandwidth causes a delay and time misalignment between the chopped input waveform V1 and the amplifier output V2, making the edges of the chopping clock (CH) not strictly coincide with the output flip, and generating spikes at the output end at each chopping clock edge. Such as Figure 2 , these spikes are manifested in the frequency domain as a series of IMD spectral components located at , (n is an even number). When in-band chopping (FCH < FIN) is adopted, these intermodulation distortion components fall within the signal bandwidth and cannot be filtered out by the low-pass filter, thus becoming the key factor restricting the linearity of the chopper amplifier. Especially when the input frequency is close to an integer multiple of the chopping frequency, strong intermodulation distortion will occur.

[0005] To reduce the ripples and intermodulation distortion caused by chopping, various ripple suppression and offset compensation schemes have been proposed in the prior art, such as: ripple-reduction loop (RRL), trimming, and auto-zeroing, etc. These methods detect and compensate the output ripple or offset through an additional feedback loop or a sample-and-hold structure, and can effectively reduce the output ripple, but they are aimed at the chopping ripple itself, rather than intermodulation distortion (IMD).

[0006] The spread-spectrum chopping clock in the prior art can only suppress the main intermodulation distortion components to a certain extent, but there are problems such as not being able to fundamentally eliminate the generation mechanism of intermodulation distortion, being ineffective for higher-order intermodulation distortion, poor noise performance, large area / power consumption overhead, and being sensitive to mismatches. Summary of the Invention

[0007] To address the aforementioned problems, the present invention aims to provide a chopper amplifier that solves the technical issues of existing chopper amplifiers, such as their inability to fundamentally eliminate the intermodulation distortion generation mechanism, their ineffectiveness against higher-order intermodulation distortion, their poor noise performance, their large area / power consumption overhead, and their sensitivity to mismatch. This will be described in detail below.

[0008] This embodiment provides a chopper amplifier, including:

[0009] The clock generator module connects to the differential input signal and outputs a chopped clock based on the differential input signal;

[0010] The input chopper module is used to receive differential input signals and use a chopper clock to perform chopper modulation to generate modulated signals;

[0011] Amplifier modules are used to amplify modulated signals; and

[0012] The output chopper module is used to demodulate the amplified modulated signal and generate a differential output signal using a chopper clock.

[0013] The clock generator module includes a zero-crossover aligned clock circuit. The zero-crossover aligned clock circuit outputs an intermediate clock based on the differential input signal and detects the zero-crossover point at the common-mode level. It also locks and aligns the edge of the intermediate clock to the zero-crossover point to generate a chopper clock aligned with the zero-crossover point, which is used to suppress the intermodulation distortion of the chopper op-amp.

[0014] The output chopper module is connected to a self-filling circuit. The self-filling circuit, in conjunction with the chopper clock, samples and maintains the differential output voltage during the chopper steady-state phase. During the chopper conversion phase, it forms a short circuit between the differential output nodes in conjunction with the chopper clock, causing the current polarity of the amplifier module to internally reverse. At the same time, it uses the sampled differential output voltage for self-filling to suppress the intermodulation distortion of the chopper op-amp.

[0015] In the zero-crossover alignment embodiment, the zero-crossover alignment clock circuit includes a zero-crossover detector and a selection multiplexer. The zero-crossover detector is connected to the differential input signal, outputs an intermediate clock based on the differential input signal, and detects the zero-crossover point of the differential input signal at the common-mode level. The selection multiplexer selects to lock the clock edge to the zero-crossover point at the rising or falling edge of each intermediate clock, thereby generating an aligned chopper clock aligned with the zero-crossover point.

[0016] In the zero-crossover alignment embodiment, an aligned chopper clock is used to drive both the input chopper module and the output chopper module.

[0017] In one embodiment, the zero-crossover detector includes a differential crossover detection stage and a common-mode threshold inverter, with the pull-up network of the differential crossover detection stage connected in parallel to a programmable PMOS array.

[0018] In one embodiment, the output of the selector multiplexer is connected to a divider, which divides the aligned chopper clock into a first complementary clock (CK4P) and a second complementary clock (CK4N) with a duty cycle of 50%.

[0019] In practice, the programmable PMOS array includes an MSB control terminal and an LSB control terminal.

[0020] When coarse adjustment is combined with fine adjustment, the input of the selection multiplexer is connected to the output of the zero-crossover detector. The selection multiplexer includes an alignment control terminal. The MSB control terminal of the programmable PMOS array is selected by the alignment control terminal to align the edge of the intermediate clock to the zero-crossover point, thereby realizing the coarse adjustment of the intermediate clock. The LSB control terminal is used to finely adjust the threshold and charging current of the zero-crossover detector.

[0021] In addition, the differential cross-detection stage includes a discharge path, which includes a tail NMOS transistor fixedly connected to the positive power supply to provide a stable discharge path.

[0022] In the self-filling embodiment, the self-filling circuit includes a first load capacitor disposed at the first differential output node and a second load capacitor disposed at the second differential output node. A first on switch is connected in series between the first load capacitor and the first differential output node, and a second on switch is connected in series between the second load capacitor and the second differential output node. A short-circuit switch is disposed between the first differential output node and the second differential output node.

[0023] The first on switch, the second on switch, and the shorting switch are connected to the control logic circuit. During the chopper steady-state phase, the control logic circuit coordinates with the chopper clock, disconnects the shorting switch, and connects the first on switch and the second on switch, so that the first load capacitor and the second load capacitor sample and maintain the differential output voltage. During the chopper conversion phase, the control logic circuit coordinates with the chopper clock, turns on the shorting switch, and disconnects the first on switch and the second on switch, so that the internal switching current of the amplifier module is closed and the polarity is reversed. At the same time, the sampled differential output voltage is used to self-fill the differential output signal.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] By utilizing zero-crossover alignment chopping technology and / or self-filling technology, intermodulation distortion caused by chopping can be suppressed or eliminated from the mechanism without increasing power consumption and noise, thereby significantly improving the linearity and usable input frequency range of the chopper amplifier.

[0026] In zero-crossover aligned chopping technology, a zero-crossover detector and a pair selection multiplexer are used to forcibly move each chopping edge to the input zero-crossover point, so that the instantaneous signal amplitude at the chopping moment is close to zero, thereby directly reducing the amplitude of intermodulation distortion from the formula.

[0027] In the self-filling technique, the amplifier module employs an operational transconductance amplifier (OTA). OTAs exhibit finite transient processes during chopping transitions, which cannot be completely smoothed out by clock alignment alone. Therefore, this invention introduces self-filling (SFI) technology into the output chopping module. SFI utilizes a load capacitor and three simple switches to temporarily isolate the output within the chopping transition window, short-circuit the OTA output node, and self-fill the output using the correct voltage pre-stored in the load capacitor, thus cutting off the remaining chopping spikes internally. Therefore, without introducing additional complex loops, intermodulation distortion is further reduced, simultaneously achieving the goals of high linearity, low noise, low power consumption, and small area. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the basic structure of an existing operational transconductance amplifier;

[0029] Figure 2 The frequency domain diagram of an existing operational transconductance amplifier;

[0030] Figure 3 The time-domain waveform of the chopper operational transconductance amplifier;

[0031] Figure 4 This is a schematic diagram of the chopper amplifier module in this embodiment, which employs both zero-crossing and self-filling technologies.

[0032] Figure 5 This is a basic structural diagram of the chopper amplifier in this embodiment;

[0033] Figure 6 This is a structural diagram of the zero-crossover clock generator of the chopper amplifier in this embodiment;

[0034] Figure 7 This is the schematic diagram of the zero-crossover detector in this embodiment;

[0035] Figure 8 This is a waveform diagram of the zero-crossover detector in this embodiment;

[0036] Figure 9 This is a diagram of the self-filling circuit structure of the chopper amplifier in this embodiment;

[0037] Figure 10 The following is a timing diagram and waveform diagram of the self-filling circuit of the chopper amplifier in this embodiment. Detailed Implementation

[0038] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0039] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0040] The serial numbers assigned to components in this document, such as "first" and "second," are used solely to distinguish the described objects and have no sequential or technical meaning. "Multiple" means two or more. Unless otherwise specified, "connection" or "linkage" in this application includes both direct and indirect connections (linkages).

[0041] Please refer to Figure 3 As shown Figure 1 as well as Figure 2 The time-domain waveform diagram of the existing chopper operational transconductance amplifier.

[0042] The chopping of existing operational transconductance amplifiers occurs at the worst chopping point.

[0043] In one embodiment of this application, a zero-crossover aligned clock circuit is used to ensure that the chopping of the amplifier module occurs at the optimal chopping point.

[0044] Please refer to this as well. Figure 1 as well as Figure 3 ,exist Figure 3 In the waveform diagram, the top three rows of waveforms represent: the chopping input V1, the output V2 of the chopping operational transconductance amplifier (OTA), and the chopping clock CH. The bottom last row of waveforms represents the output VO, showing the worst-case chopping point on the left and the best-case chopping point on the right.

[0045] At the worst-case chopping point: the chopping clock CH edge falls at the peak of input V1, and each chopping edge generates a spike with an amplitude of approximately 2V1,W. These spikes... Intermodulation distortion (IMD) components are formed at (n is an even number).

[0046] Conversely, at the optimal chopping point in this application: the chopping clock CH edge falls at the zero crossover point, and the spike amplitude is approximately 2V1,B, as shown on the right side of the optimal chopping point, where V1,B is very small.

[0047] Therefore, based on the above principle, this embodiment can fundamentally reduce intermodulation distortion by ensuring that the edge of each chopper falls at the zero crossover point.

[0048] The chopper amplifier in this embodiment is briefly described below:

[0049] like Figure 4 as well as Figure 5 As shown, the chopper amplifier in this embodiment includes a clock generator module 5, an input chopper module 1, an amplifier module 2, and an output chopper module 3.

[0050] The clock generator module 5 connects to the differential input signals (VIP, VIN) and outputs a chopper clock CH based on these signals. The input chopper module receives the differential input signals (VIP, VIN) and uses the chopper clock CH to perform chopper modulation, generating a modulated signal. The amplifier module 2 amplifies the modulated signal. The output chopper module 5 uses the chopper clock CH to demodulate the amplified modulated signal, generating a differential output signal.

[0051] Clock generator module 5 includes a zero-crossover aligned clock circuit. The zero-crossover aligned clock circuit outputs an intermediate clock based on the differential input signal and detects the zero-crossover point at the common-mode level. It also locks the edge of the intermediate clock to the zero-crossover point to generate a chopper clock aligned with the zero-crossover point, which is used to suppress the intermodulation distortion of the chopper op-amp.

[0052] And / or the output chopper module 3 is connected to the self-filling circuit 6. The self-filling circuit 6, in conjunction with the chopper clock, samples and holds the differential output voltage during the chopper steady-state phase. During the chopper transition phase, it forms a short circuit between the differential output nodes, causing the current polarity of the amplifier module to internally reverse. At the same time, it uses the sampled differential output voltage for self-filling, which is used alone or in combination with the zero-crossover alignment clock circuit to further suppress the intermodulation distortion of the chopper op-amp.

[0053] The chopper amplifier of this invention proposes two technical solutions to address intermodulation distortion: Zero-Crossing Aligned Chopping (ZCAC) and Self-Fill-In (SFI). These techniques can be used individually to suppress intermodulation distortion or combined to suppress it. These will be described in detail below.

[0054] The following section introduces the zero-crossover alignment chopper technique.

[0055] The Zero-Crossing Aligned Chopping (ZCAC) technique in this embodiment introduces a zero-crossing aligned clock circuit on the basis of a traditional chopper operational amplifier structure. This zero-crossing aligned clock circuit includes a zero-crossing detector (ZCD) and a selection multiplexer for clock alignment, ensuring that each chopping clock edge is aligned to the zero-crossing point of the input signal. This minimizes the instantaneous amplitude of the input signal at the moment of chopping, fundamentally reducing the spike voltage generated by each chopping edge, and thus suppressing intermodulation distortion (IMD).

[0056] like Figure 5 as well as Figure 8 As shown, the input signal ports of the chopper amplifier include differential input signals VIP and VIN, and the common-mode level is VCM.

[0057] The input chopper module 1 consists of several cross-connected MOS switches, which receive differential input and chopper clock CH aligned with the zero crossover point; the polarity of the input signal is flipped in each chopper cycle to achieve modulation.

[0058] In this embodiment, amplifier module 2 can adopt a current-limited chopper operational transconductance amplifier (OTA) structure to achieve a unity-gain bandwidth (GBW) of approximately 4 MHz; the transconductance amplifier may contain a folded common-source input stage, a gain stage, and a compensation network, etc., which are not limited in this invention.

[0059] Output chopper module 3 receives the transconductance amplifier (OTA) output and the chopper clock CH aligned with the zero crossover point to demodulate the signal.

[0060] In this embodiment, the differential input signals VIP and VIN are simultaneously fed into the input chopper module 1 and the zero-crossover alignment clock circuit. The alignment clock CH output by the zero-crossover alignment clock circuit drives both the input chopper module 1 and the output chopper module 3. The amplifier module 2 is connected between the input chopper module 1 and the output chopper module 3. The output chopper module 3 outputs differential output signals VOP and VON.

[0061] The Zero-Crossing Aligned Chopping Clock Generator (ZCAC) is a key module of this invention. Figure 6 As shown, the zero-crossover aligned clock circuit receives differential inputs VIP and VIN, and outputs a pair of aligned and complementary chopper clocks CK4P / CK4N.

[0062] Please refer to Figure 6 The diagram shown is a block diagram of a zero-crossover aligned clock circuit.

[0063] The zero-crossover aligned clock circuit includes a zero-crossover detector 51, a selection multiplexer 52, and a divider 53. The zero-crossover detector 51 and the selection multiplexer 52 are configured with programmable control logic. In one embodiment, the selection multiplexer 52 uses a 2:1 multiplexer, such as... Figure 6 The 2:1 MUX is used in the 4-way divider 53. The 4-way divider 53 uses the 4-way divider DIV4.

[0064] Please refer to this as well. Figure 7 as well as Figure 8 The zero-crossover detector 51 is connected to the differential input signals VIP and VIN. Based on the differential input signals, it outputs an intermediate clock and detects the zero-crossover point of the differential input signals at the common-mode level VCM. The output of the zero-crossover detector 51 is a pair of complementary digital signals VON,ZCD and VOP,ZCD with edge alignment, and their edges correspond to the zero-crossover points of the input signals.

[0065] The zero-crossover detector 51 includes an MSB control terminal DM,B<1:0> and an LSB control terminal DL,T <3> .

[0066] The MSB control terminal DM,B<1:0> uses binary control code. DM,B<1:0> controls the size of the PMOS array preceding the zero-crossover alignment clock circuit, thereby changing the charging current and achieving coarse adjustment. Fine adjustment of the threshold and charging current of the zero-crossover alignment clock circuit is achieved through the 3-bit binary control code of the MSB control terminal and the 4-bit control code of the LSB control terminal, used to align the detected zero-crossover point under variations in process, voltage, and temperature (PVT).

[0067] LSB control terminals DL,T <3> It is a 4-bit hot code, where DL and T <0> A permanent pull-down is used to ensure the existence of a minimum charging path; the remaining bits are used to fine-tune the trigger point by selecting different numbers of PMOS transistors to be turned on, thereby changing the pull-up current.

[0068] Select multiplexer 52 selects to lock the clock edge aligned to the zero crossover point on either the rising or falling edge of each intermediate clock, thereby generating an aligned chopper clock aligned to the zero crossover point.

[0069] The input terminals of the multiplexer 52 are connected to the two outputs of the zero-crossover detector 51. The multiplexer 52 includes alignment control terminals DM and B. <2> The alignment control terminal DM,B <2> For selection Figure 8 In this process, one edge of the intermediate digital signals VMIDN and VMIDP serves as the basis for subsequent clock signals, enabling coarse-grained adjustment of clock edge advance / lag.

[0070] The selector multiplexer 52 regenerates the steep digital edge of the crossover point of the differential crossover detection stage 511 of the zero-crossover detector 51 and outputs it as the intermediate clock CK.

[0071] The frequency divider 53 divides the aligned intermediate clock CK into a pair of complementary aligned chopper clocks with a duty cycle of 50%, including a first complementary clock CK4P and a second complementary clock CK4N. The frequency divider 53 ensures that all rising edges occur at the same phase point, i.e., near the zero crossover point, within the input signal period by controlling the frequency division logic.

[0072] Please refer to this as well. Figure 7 as well as Figure 8 The zero-crossover detector 51 includes a differential crossover detection stage 511 and a common-mode threshold inverter 512, and the pull-up network of the differential crossover detection stage 511 is connected in parallel with a programmable PMOS array 513.

[0073] The differential crossover detection stage 511 is connected to two differential inputs, VIP and VIN. The sources of the two NMOS differential pairs and the two PMOS differential pairs of the stage 511 are connected together. This structure, combining parallel PMOS and NMOS sources, can accurately determine the crossover point of the differential inputs near the common mode, enabling VMIDP and VMIDN to switch high and low levels near zero crossover.

[0074] The differential crossover detection stage 511 also includes a discharge path, which comprises a tail NMOS transistor fixedly connected to the positive power supply to provide a stable discharge path. This tail NMOS transistor provides the discharge path. The tail NMOS transistor is fixedly connected to the VDD power supply to provide a stable discharge path, ensuring that the zero-crossover detector 51 still has sufficient swing amplitude and switching speed under various PVT conditions.

[0075] This common-mode threshold inverter 512 is a custom inverter with a threshold set in common mode. It employs a pair of custom-sized CMOS inverters, whose switching voltage is precisely set near the common-mode level VCM. The common-mode threshold inverter 512 takes VMIDP and VMIDN as inputs and outputs VON, ZCD, VOP, and ZCD. Because the threshold of this common-mode threshold inverter 512 is close to VCM, such as... Figure 8As shown in the third row of digital waveforms, the crossover points of the first-level differential crossover detection stage 511 can be regenerated to produce steep digital edges.

[0076] The programmable PMOS array 513 incorporates several parallel PMOS transistors into the pull-up network of the differential cross-detection stage 511 in the first stage. The programmable PMOS array 513 is controlled by the MSB control terminal DM,B<1:0> and the LSB control terminal DL,T. <3> The programmable PMOS array 513 controls the number of PMOS transistors turned on. By controlling the number of transistors turned on, the equivalent size of the PMOS transistors is changed, which in turn changes the charging current, thereby fine-tuning the crossover position of VMIDP and VMIDN and compensating for PVT drift.

[0077] When combining coarse and fine adjustments, connect the input of multiplexer 52 to the output of zero-crossing detector 51. Connect the alignment control terminals DM and B of multiplexer 52. <2> The MSB control terminal of the programmable PMOS array 513 is connected to the alignment control terminal to select the edge of the intermediate clock to be aligned to the zero crossover point, thereby achieving coarse adjustment of the intermediate clock. The LSB control terminal is connected to the host control terminal 100 for fine adjustment of the threshold and charging current of the zero crossover detector.

[0078] In this embodiment, the zero-crossover detector 51 is configured with a two-stage structure consisting of a differential crossover detection stage 511 and a common-mode threshold inverter 512. By connecting a programmable PMOS array 513 in parallel, the charging current / threshold is adjusted using the binary code of the MSB control terminal combined with the hot code of the LSB control terminal, thereby achieving coarse and fine adjustment of the zero-crossover point.

[0079] Please refer to Figure 8 The waveform of the zero-crossover detector 51 is shown.

[0080] The upper part shows the input signal waveform: the differential input VIP positive phase signal waveform and the VIN negative phase signal waveform change sinusoidally around the common-mode level VCM. The zero crossover point is when VIP=VIN=VCM.

[0081] The middle section is the waveform of the middle node, which is not yet zero crossover aligned: the crossover point of VMIDP and VMIDN is slightly off from VCM, and this offset can be adjusted by the PMOS array. Figure 8 The deviation between the intersection point and the ideal zero intersection point is indicated by a dashed line.

[0082] The lower half shows the output waveform of the zero-crossing detector 51. VON, ZCD and VOP, ZCD are two complementary pulse signals. Without zero-crossing alignment, their rising or falling edges deviate from the input zero-crossing point. By selecting and fine-tuning the multiplexer 52, the rising edge that is ultimately used as the chopping clock coincides with the input zero-crossing point.

[0083] The zero-crossover aligned chopping technique in this embodiment accurately detects the crossover moment of the input differential signal at the common-mode level VCM using a zero-crossover detector 51. The edge of the chopping clock is locked at this zero-crossover moment through a clock generation module and programmable delay / threshold control. The aligned chopping clock drives the input chopping module 1 and the output chopping module 3, ensuring that each polarity reversal occurs at the optimal chopping point.

[0084] The following section introduces self-filling technology.

[0085] The self-fill-in technique (SFI) of this embodiment is a circuit and method for suppressing intermodulation distortion (IMD) caused by chopping in a chopper operational amplifier without significantly increasing power consumption and area.

[0086] Please refer to Figure 9 In the self-filling embodiment, the self-filling circuit 6 includes a first load capacitor CL1 disposed at the first differential output node and a second load capacitor CL2 disposed at the second differential output node. A first on-switch Pass1 is connected in series between the first load capacitor CL1 and the first differential output node, and a second on-switch Pass2 is connected in series between the second load capacitor CL2 and the second differential output node. A short-circuit switch Short is disposed between the first differential output node and the second differential output node.

[0087] The first on switch Pass1, the second on switch Pass2, and the short switch Short are connected to the control logic circuit (not shown in the figure).

[0088] During the steady-state phase of the chopper cycle, the control logic circuit coordinates with or aligns with the chopper clock CH, disconnects the short-circuit switch Short, and connects the first on switch Pass1 and the second on switch Pass2, enabling the first load capacitor CL1 and the second load capacitor CL2 to sample and maintain the differential output voltage. During the steady-state phase of the chopper cycle, the output load capacitor CL is used to sample and maintain the current output voltage V1(t) of amplifier module 2.

[0089] During the chopper conversion phase, the control logic circuit coordinates with or aligns with the chopper clock CH, turns on the short-circuit switch Short and turns off the first on switch Pass1 and the second on switch Pass2, causing the amplifier module's internal switching current to close and reverse its polarity. Simultaneously, the sampled differential output voltage is used to self-fill the differential output signal waveform. For example... Figure 10As shown, during the chopper conversion stage, the load capacitor CL is temporarily isolated from the output by controlling the on and short switches. The correct voltage across the load capacitor CL performs waveform self-filling at the output node; simultaneously, the output node of amplifier module 2 is shorted, allowing amplifier module 2 to internally complete polarity reversal and current steady-state. After the reversal is complete, the short switch Short is turned on again, so that almost no chopper spikes are visible outside the chopper amplifier, and intermodulation distortion is directly suppressed instead of being converted into broadband noise. The self-filling technology in this embodiment only adds three MOS switches to the chopper operational amplifier, without requiring additional transconductance amplifiers or large capacitors, thus resulting in minimal power consumption and area overhead.

[0090] like Figure 10 As shown, amplifier module 2 outputs OTA differential pairs VMDP and VMDN. The output nodes of self-filling circuit 6 are labeled VOP and VON.

[0091] A first on-state switch, Pass1, is connected in series between the output differential VMDP and VOP. A second on-state switch, Pass2, is connected in series between the output differential VMDN and VON. When the on-state switches are closed, the output VMDP and VMDN connected to amplifier module 2 are connected to the corresponding load capacitor CL, and the output voltage is sampled onto the capacitor.

[0092] The short circuit switch is connected between the differential pairs VMDP and VMDN.

[0093] When the short-circuit switch Short is closed, the two ends of the differential pair VMDP and VMDN are shorted, which is equivalent to forming a short circuit between the output differential nodes of amplifier module 2. This ensures that the switching current of amplifier module 2 during chopper conversion is closed internally and does not directly affect the external output.

[0094] During self-filling, with the on switch = 1 and the short switch = 0: the output node of amplifier module 2 is connected to the load capacitor CL, which is the normal amplification and sampling state. With the on switch = 0 and the short switch = 1: the self-filled output node is filled by the voltage of the load capacitor CL, and the differential output node of amplifier module 2 is shorted, which is the self-filling window state. The control timing of the three additional switches is generated by the control logic and coordinated with the chopper clock CH.

[0095] Please refer to Figure 10 The self-filled timing diagram is shown.

[0096] CH clock waveform: The chopper clock waveform has a frequency of FCH, and chopping occurs at each rising and falling edge.

[0097] Pass control signal (conduction switch): It is in the same frequency as the clock waveform CH, but leaves a low-level gap near each chopping edge - fill-in window. That is, the conduction switch is high most of the time, corresponding to the switch being turned on, and is pulled low for a short period of time before and after the chopping transition, corresponding to the switch being turned off.

[0098] Short control signal (short circuit switch): A short high-level pulse is formed in the middle of the fill window. That is, it is only briefly pulled high during the period when the Pass control signal is off, so as to close the short circuit switch.

[0099] Intermediate Node Voltage (VMD): The differential voltage waveform at the output node of amplifier module 2, showing the internal voltage polarity reversal and transient changes during chopper switching. Due to the short-circuit switch, the intermediate node voltage can freely build up internally during this period until the current converges.

[0100] External output voltage (VO): The output waveform after being connected to the load capacitor via a switching switch. Because the switching switch is closed during the chopper conversion, the output voltage is continuously maintained at the previous moment by the load capacitor CL, preventing chopper spikes from being transmitted to the output. When the switching switch is turned on again after the conversion, the output voltage smoothly transitions to a new steady-state value, achieving a spike-free output.

[0101] The working process of self-filling technology is explained below:

[0102] 1) Steady-state stage, i.e., non-transition stage:

[0103] a) The chopper clock waveform remains unchanged, situated in the middle of either a high or low level. Figure 10 When the Pass control signal is high, the first conduction switch Pass1 and the second conduction switch Pass2 are closed. When the Short control signal is low, the shorting switch is open.

[0104] b) The output nodes VOP and VON of the self-filling circuit 6 are connected to the corresponding load capacitor CL. The output voltage of the amplifier module 2 after output chopping is sampled and stored on the corresponding load capacitors CL on both sides; at this time, the voltage on the corresponding load capacitor CL is the correct output voltage under the current chopping polarity.

[0105] 2) Chopper conversion preparation phase, i.e., the start of window filling:

[0106] As the CH clock waveform is about to flip, the control logic pulls the Pass control signal low in advance, turning off the two on switches: the output node of amplifier module 2 is disconnected from the corresponding load capacitor CL, and the self-filled output terminal is maintained by the voltage of the corresponding load capacitor CL. Amplifier module 2 is decoupled from the load, avoiding the large current caused by chopping from directly impacting the load.

[0107] 3) Chopper conversion and internal short-circuit stage:

[0108] a) When the CH clock waveform flips at the edge, the input / output chopper switch switches, and amplifier module 2 needs to flip the output differential voltage from positive to negative.

[0109] b) The control logic pulls the Short control signal high in the middle of the filling window, briefly closing the two on switches. The two output nodes VMDP and VMDN of amplifier module 2 are shorted. The switching current of amplifier module 2 is closed internally, quickly completing charging, discharging, and polarity reversal. Since the output has been turned off by the on switches, the voltage on the load capacitor CL is not affected by this internal reversal, and the output remains smooth.

[0110] 4) Amplifier Module 2 Stabilization and Reconnection to Load Phase:

[0111] a) After a sufficiently long period of high-level time for the Short control signal, the differential output of amplifier module 2 has basically entered a new steady state.

[0112] b) The control logic pulls the Short control signal low, disconnects the short-circuit switch, and removes the short circuit.

[0113] c) The control logic then pulls the Pass control signal high again, closing the two on / off switches. The output of amplifier module 2 is reconnected to the load capacitor CL. After fine-tuning the voltage across the load capacitor CL relative to the current state of amplifier module 2, the output transitions to the new correct value. Throughout the process, the externally observed Vo shows almost no spikes, only a smooth transition near the chopper transition point.

[0114] The above description provides a further detailed explanation of the embodiments of the present invention in conjunction with specific implementation methods. It should not be construed that the specific implementation of the present invention is limited to these descriptions. In the above embodiments, the connection relationships mentioned can be direct connections, and in some cases, indirect connections, such as those involving switches or relays. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A chopper amplifier, characterized in that, include: A clock generator module is connected to a differential input signal and is used to output a chopped clock based on the differential input signal. An input chopper module is used to receive the differential input signal and perform chopper modulation using the chopper clock to generate a modulated signal; An amplifier module is used to amplify the modulation signal; as well as The output chopper module is used to demodulate the amplified modulation signal and generate a differential output signal using the chopper clock. The clock generator module includes a zero-crossover aligned clock circuit. The zero-crossover aligned clock circuit outputs an intermediate clock based on the differential input signal and detects the zero-crossover point at the common-mode level. It also locks and aligns the edge of the intermediate clock to the zero-crossover point to generate a chopper clock aligned with the zero-crossover point, which is used to suppress the intermodulation distortion of the chopper operational amplifier. And / or the output chopper module is connected to a self-filling circuit. The self-filling circuit, in conjunction with the chopper clock, samples and maintains the differential output voltage during the chopper steady-state phase. During the chopper conversion phase, it works with the chopper clock to form a short circuit between the differential output nodes, causing the current polarity of the amplifier module to internally reverse. At the same time, it uses the sampled differential output voltage for self-filling to suppress the intermodulation distortion of the chopper op-amp.

2. The chopper amplifier as described in claim 1, characterized in that, The zero-crossover aligned clock circuit includes a zero-crossover detector and a selection multiplexer. The zero-crossover detector is connected to the differential input signal, outputs an intermediate clock based on the differential input signal, and detects the zero-crossover point of the differential input signal at the common-mode level. The selection multiplexer selects to lock and align the clock edge to the zero-crossover point at the rising or falling edge of each intermediate clock, thereby generating an aligned chopper clock aligned with the zero-crossover point.

3. The chopper amplifier as described in claim 2, characterized in that, The input chopper module and the output chopper module are driven by the aligned chopper clock.

4. The chopper amplifier as described in claim 1, characterized in that, The self-filling circuit includes a first load capacitor disposed at a first differential output node and a second load capacitor disposed at a second differential output node. A first on switch is connected in series between the first load capacitor and the first differential output node, and a second on switch is connected in series between the second load capacitor and the second differential output node. A short-circuit switch is disposed between the first differential output node and the second differential output node.

5. The chopper amplifier as described in claim 4, characterized in that, The first on switch, the second on switch, and the shorting switch are connected to the control logic circuit. During the chopper steady-state phase, in coordination with the chopper clock, the shorting switch is disconnected and the first on switch and the second on switch are connected, so that the first load capacitor and the second load capacitor sample and maintain the differential output voltage. During the chopper conversion phase, the control logic circuit coordinates with the chopper clock to turn on the short-circuit switch and turn off the first and second on switches, causing the internal switching current of the amplifier module to close and reverse its polarity. At the same time, the sampled differential output voltage is used to self-fill the differential output signal.

6. The chopper amplifier as described in claim 2, characterized in that, The zero-crossover detector includes a differential crossover detection stage and a common-mode threshold inverter, wherein the pull-up network of the differential crossover detection stage is connected in parallel with a programmable PMOS array.

7. The chopper amplifier as described in claim 2, characterized in that, The output of the selector multiplexer is connected to a frequency divider, which divides the aligned chopper clock into a first complementary clock (CK4P) and a second complementary clock (CK4N) with a duty cycle of 50%.

8. The chopper amplifier as described in claim 6, characterized in that, The programmable PMOS array includes an MSB control terminal and an LSB control terminal.

9. The chopper amplifier as described in claim 8, characterized in that, The input of the selection multiplexer is connected to the output of the zero-crossover detector. The selection multiplexer includes an alignment control terminal. The MSB control terminal of the programmable PMOS array is selected by the alignment control terminal to align the edge of the intermediate clock to the zero-crossover point, thereby achieving coarse adjustment of the intermediate clock. The LSB control terminal is used to finely adjust the threshold and charging current of the zero-crossover detector.

10. The chopper amplifier as described in claim 8, characterized in that, The differential cross-detection stage includes a discharge path, which includes a tail NMOS transistor fixedly connected to the positive power supply to provide a stable discharge path.

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