Clock skew compensation circuit, chip and electronic device

Abstract

The present disclosure relates to a clock deviation compensation circuit, a chip and an electronic device, the clock deviation compensation circuit comprising a reference channel and at least one compensation channel, the reference channel comprising an input buffer, K frequency division generating units, a first output selector, the compensation channel comprising a first decoder, a multi-path clock selector, K frequency division synchronization units, a second output selector. The clock deviation compensation circuit of the present disclosure can adaptively output a clock frequency, and the clock deviation compensation range is constant.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a clock skew compensation circuit, chip, and electronic device. Background Technology

[0002] In scenarios such as the Internet of Things and autonomous driving, the frequency of the output clock needs to be switched frequently (e.g., communication protocol switching, sensor sampling rate adjustment, etc.). However, in clock deviation compensation circuits based on reference input phase, the reference clock frequency is fixed. When the output clock switches between different frequencies, the corresponding clock deviation compensation range can only cover a range of output clock frequencies, which greatly affects its application scope. Summary of the Invention

[0003] In view of this, this disclosure presents a clock skew compensation circuit, chip, and electronic device.

[0004] According to one aspect of this disclosure, a clock skew compensation circuit is provided, the clock skew compensation circuit including a reference channel and at least one compensation channel, the reference channel including an input buffer, K frequency divider generation units, and a first output selector, the compensation channel including a first decoder, a multiplexed clock selector, K frequency divider synchronization units, and a second output selector, where K=2. P -1, where P is a positive integer; wherein, the input buffer is used to send the reference clock delayed to K frequency division generation units, each frequency division generation unit performs frequency division processing on the reference clock to obtain K selectable reference frequency division clocks, the first output selector is used to output the reference frequency division clock according to the K selectable reference frequency division clocks; the first decoder is used to generate the selection signal of the multiplex clock selector so that the multiplex clock selector generates the compensation clock based on the selection signal and the adjustment clock, each frequency division synchronization unit performs frequency division processing on the compensation clock when it is turned on at the same time as the frequency division generation unit at the corresponding position, to obtain K selectable compensation frequency division clocks, the second output selector is used to output the compensation frequency division clock according to the K selectable compensation frequency division clocks.

[0005] In one possible implementation, the j-th frequency divider generation unit among the K frequency divider generation units is used to perform 2x division on the reference clock. j Frequency division is performed to obtain the j-th selectable reference frequency division clock, where the value of j ranges from 1 to K; when the j-th frequency division synchronization unit among the K frequency division synchronization units and the j-th frequency division generation unit among the K frequency division generation units are simultaneously activated, the compensation clock is subjected to 2... j Frequency division yields the j-th optional compensated frequency division clock.

[0006] In one possible implementation, the reference channel further includes a first logic gate circuit, and the compensation channel further includes a second logic gate circuit; wherein, the output terminal of the input buffer is connected to the first input terminal of the first logic gate circuit, the first output terminal of the first logic gate circuit is connected to the first input terminal of the first frequency divider generation unit, the first output terminal of the i-th frequency divider generation unit is connected to the first input terminal of the (i+1)-th frequency divider generation unit, the second output terminal of the first logic gate circuit and the second output terminal of each frequency divider generation unit are respectively connected to different input terminals of the first output selector, so that the first output selector outputs a reference frequency divider clock, where the value of i ranges from 1 to K-1; the first output terminal of the first decoder is connected to the second input terminal of the multiplexer clock selector, the second output terminal of the first decoder is respectively connected to the third input terminal of each frequency divider synchronization unit, the output terminal of the multiplexer clock selector is connected to the first input terminal of the second logic gate circuit, and the first output terminal of the first logic gate circuit is connected to the second input terminal of the first logic gate circuit. The first output of the two logic gate circuits is connected to the first input of the first frequency division synchronization unit, the first output of the i-th frequency division synchronization unit is connected to the first input of the (i+1)-th frequency division synchronization unit, the third output of the i-th frequency division generation unit is connected to the second input of the i-th frequency division synchronization unit, the second output of the second logic gate circuit and the second output of each frequency division synchronization unit are respectively connected to different inputs of the second output selector so that the second output selector outputs a compensated frequency division clock; the second input of the first decoder, the second input of the first logic gate circuit, the second input of the second logic gate circuit, the second input of each frequency division generation unit, and the fourth input of each frequency division synchronization unit are used to receive the frequency selection level signal, the input of the input buffer is used to receive the reference clock, the first input of the first decoder is used to receive the phase selection level signal, and the first input of the multiplex clock selector is used to receive the adjustment clock.

[0007] In one possible implementation, the input buffer includes a plurality of serially connected first NOT gates, the number of which is determined by the number of stages of the multiplexer.

[0008] In one possible implementation, the frequency divider generation unit includes a first D flip-flop, a second NOT gate, and a third logic gate circuit. The clock input terminal of the first D flip-flop serves as the first input terminal of the frequency divider generation unit. The data input terminal of the first D flip-flop is connected to the output terminal of the second NOT gate. The input terminals of the second NOT gate, the output terminal of the first D flip-flop, and the first input terminal of the third logic gate circuit are connected to a first node. The first node serves as the third output terminal of the frequency divider generation unit. The second input terminal of the third logic gate circuit serves as the second input terminal of the frequency divider generation unit. The first output terminal of the third logic gate circuit serves as the first output terminal of the frequency divider generation unit. The second output terminal of the third logic gate circuit serves as the second output terminal of the frequency divider generation unit.

[0009] In one possible implementation, the frequency division synchronization unit includes a second D flip-flop, a first switch, a third NOT gate, a fourth NOT gate, and a fourth logic gate circuit. The clock input terminal of the second D flip-flop serves as the first input terminal of the frequency division synchronization unit, and the data input terminal of the second D flip-flop serves as the second input terminal of the frequency division synchronization unit. The output terminal of the second D flip-flop, the first terminal of the first switch, and the input terminal of the fourth NOT gate are connected together. The second terminal of the first switch, the output terminal of the fourth NOT gate, and the first input terminal of the fourth logic gate circuit are connected together. The input terminal of the third NOT gate, the first control terminal of the first switch, and the control terminal of the fourth NOT gate are connected to a second node, which serves as the third input terminal of the frequency division synchronization unit. The output terminal of the third NOT gate is connected to the second control terminal of the first switch. The second input terminal of the fourth logic gate circuit serves as the fourth input terminal of the frequency division synchronization unit, the first output terminal of the fourth logic gate circuit serves as the first output terminal of the frequency division synchronization unit, and the second output terminal of the fourth logic gate circuit serves as the second output terminal of the frequency division synchronization unit.

[0010] In one possible implementation, the logic gate circuit includes an AND gate, a fifth NOT gate, and a first NAND gate. The first input of the AND gate is connected to the second input of the first NAND gate at a third node, and the third node is the first input of the logic gate circuit. The second input of the AND gate is connected to the output of the fifth NOT gate. The input of the fifth NOT gate is connected to the first input of the first NAND gate at a fourth node, and the fourth node is the second input of the logic gate circuit. The output of the AND gate serves as the first output of the logic gate circuit, and the output of the first NAND gate serves as the second output of the logic gate circuit.

[0011] In one possible implementation, the output selector includes a NOR gate and at least one second NAND gate, with the output of each second NAND gate connected to a different input of the NOR gate.

[0012] In one possible implementation, the frequency selection gear signal includes 2 P The clock skew compensation circuit further includes a second decoder, which converts the input P-bit binary initial signal into a 2-bit binary signal. P The output signal serves as the frequency selection level signal.

[0013] According to another aspect of this disclosure, a chip is provided that includes the clock skew compensation circuit described above.

[0014] According to another aspect of this disclosure, an electronic device is provided, including the clock skew compensation circuit described above.

[0015] The clock skew compensation circuit of this disclosure embodiment may include a reference channel and at least one compensation channel. The reference channel includes an input buffer, K frequency divider generation units, and a first output selector. The compensation channel includes a first decoder, a multiplexed clock selector, K frequency divider synchronization units, and a second output selector, where K=2. P -1, where P is a positive integer; wherein, the input buffer is used to send the reference clock delay to K frequency division generation units to match the delay of the multi-channel clock selector, each frequency division generation unit performs frequency division processing on the reference clock to obtain K selectable reference frequency division clocks, the first output selector is used to select a reference frequency division clock according to the K selectable reference frequency division clocks; the first decoder is used to generate a selection signal for the multi-channel clock selector, so that the multi-channel clock selector generates a compensation clock based on the selection signal and the adjustment clock, each frequency division synchronization unit, when simultaneously turned on with the frequency division generation unit at the corresponding position, performs frequency division processing on the compensation clock to obtain K selectable compensation frequency division clocks, the second output selector is used to output the compensation frequency division clock according to the K selectable compensation frequency division clocks. The clock deviation compensation circuit of this embodiment can adaptively output the clock frequency, and its clock deviation compensation range is constant.

[0016] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0018] Figure 1 A block diagram of a clock skew compensation circuit according to an embodiment of the present disclosure is shown.

[0019] Figure 2A schematic diagram of a clock skew compensation circuit according to an embodiment of the present disclosure is shown.

[0020] Figure 3 A schematic diagram of another clock skew compensation circuit according to an embodiment of the present disclosure is shown.

[0021] Figure 4 A schematic diagram of adjusting a clock according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic diagram of a logic gate circuit according to an embodiment of the present disclosure is shown.

[0023] Figure 6 A circuit diagram of a frequency division generation unit according to an embodiment of the present disclosure is shown.

[0024] Figure 7 A circuit diagram of a frequency division synchronization unit according to an embodiment of the present disclosure is shown.

[0025] Figure 8 A circuit diagram of an output selector according to an embodiment of the present disclosure is shown.

[0026] Figure 9 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0027] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0028] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0030] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0031] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0032] Figure 1 A block diagram of a clock skew compensation circuit according to an embodiment of the present disclosure is shown. Figure 1 As shown, the clock skew compensation circuit includes a reference channel 1 and at least one compensation channel 2. The reference channel 1 includes an input buffer 3, K frequency divider generation units 4, and a first output selector 5. The compensation channel 2 includes a first decoder 6, a multiplexer clock selector 7, K frequency divider synchronization units 8, and a second output selector 9, where K=2. P -1, where P is a positive integer;

[0033] The input buffer 3 is used to send the reference clock delay to K frequency divider generation units 4 to match the delay of the multiplex clock selector 7. Each of the K frequency divider generation units 4 performs frequency division processing on the reference clock to obtain K optional reference frequency divider clocks (for example, the first frequency divider generation unit of the K frequency divider generation units 4 can output the first optional reference frequency divider clock, the second frequency divider generation unit of the K frequency divider generation units 4 can output the second optional reference frequency divider clock, and so on, the Kth frequency divider generation unit of the K frequency divider generation units 4 can output the Kth optional reference frequency divider clock). The first output selector 5 is used to output the reference frequency divider clock according to the K optional reference frequency divider clocks (for example, the first optional reference frequency divider clock to the Kth optional reference frequency divider clock).

[0034] The first decoder 6 generates a selection signal for the multiplexer 7, enabling the multiplexer 7 to generate a compensation clock based on the selection signal and the adjustment clock. Each of the K frequency division synchronization units 8, when simultaneously activated with the corresponding frequency division generation unit in the K frequency division generation units 4, performs frequency division processing on the compensation clock to obtain K selectable compensation frequency division clocks. (For example, when the first frequency division synchronization unit in the K frequency division synchronization units 8 is activated simultaneously with the first frequency division generation unit in the K frequency division generation units 4, this first frequency division synchronization unit can output the first selectable compensation frequency division clock; the second frequency division...) When the synchronization unit is turned on simultaneously with the second frequency division generation unit in the K frequency division generation units 4, the second frequency division synchronization unit can output the second optional compensated frequency division clock; and so on, when the Kth frequency division synchronization unit in the K frequency division synchronization units 8 is turned on simultaneously with the Kth frequency division generation unit in the K frequency division generation units 4, the Kth frequency division synchronization unit can output the Kth optional compensated frequency division clock; in this way, it is beneficial to synchronize the operating frequency of each frequency division synchronization unit and the frequency division generation unit at the corresponding position. The second output selector 9 is used to output the compensated frequency division clock according to the K optional compensated frequency division clocks (e.g., the first optional compensated frequency division clock to the Kth optional compensated frequency division clock).

[0035] In one possible implementation, the clock skew compensation circuit of an embodiment of this disclosure can be applied to time synchronization and clock skew compensation in various fields such as communication networks, the Internet of Things, artificial intelligence, and autonomous driving. For the input reference clock, the clock skew compensation circuit of this disclosure can provide K selectable reference frequency division clocks and K corresponding selectable compensation frequency division clocks. When the output reference frequency division clock switches between K different frequencies, the corresponding compensation frequency division clock can adapt to the frequency of the reference frequency division clock, and its clock skew compensation range is constant.

[0036] In one possible implementation, the clock skew compensation circuit can employ a parallel structure of reference channel 1 and compensation channel 2. Reference channel 1 provides a reference frequency-divided clock for the clock skew compensation circuit, and compensation channel 2 provides a compensation frequency-divided clock for the clock skew compensation circuit. Different compensation channels 2 can be used to provide compensation frequency-divided clocks with different phases for the clock skew compensation circuit. The number of compensation channels 2 can be set according to the actual application scenario; the embodiments of this disclosure do not limit the specific number of compensation channels 2.

[0037] In one possible implementation, the reference channel 1 may consist of at least an input buffer 3, K frequency divider generation units 4, and a first output selector 5.

[0038] The input buffer 3 can be composed of cascaded NOT gates (also known as inverters) to match the delay of the multiple clock selector 7 in the compensation channel 2, so that the time when the reference clock arrives at the K frequency division generation unit 4 is synchronized or aligned with the time when the compensation clock arrives at the K frequency division synchronization unit 8.

[0039] The K frequency division generation units 4 may include the first frequency division generation unit to the Kth frequency division generation unit, wherein the j-th frequency division generation unit among the K frequency division generation units 4 is used to perform 2x frequency division on the reference clock. j Frequency division is used to obtain the j-th selectable reference frequency divider clock, where j ranges from 1 to K. The first to the Kth frequency divider generation units can be cascaded. Each frequency divider generation unit consists of a divide-by-two module (e.g., a divide-by-two module composed of D flip-flops and NOT gates), transmission gates, and other digital circuits to extend the operating frequency of the clock skew compensation circuit. In the example, at most K frequency divider generation units can achieve a reference clock M=2 through cascading. K Frequency division. The first (j=1) frequency divider generation unit divides the reference clock by 2 to obtain the first selectable reference frequency divider clock; the second (j=2) frequency divider generation unit divides the reference clock by 2... 2 =4 division, to obtain the second selectable reference frequency divider clock; and so on, the Kth (j=K) frequency divider generation unit is used to divide the reference clock by 2. K Frequency division is performed to obtain the Kth selectable reference frequency divider clock. Specifically, for example, when K=3, an 8-fold frequency division of the reference clock can be achieved by cascading three frequency divider generation units. The first frequency divider generation unit divides the reference clock by 2 to obtain the first selectable reference frequency divider clock; the second frequency divider generation unit divides the reference clock by 2... 2 =4 division, to obtain the second selectable reference frequency divider clock; the third frequency divider generation unit is used to divide the reference clock by 2. 3 =8 division, to obtain the third selectable reference frequency divider clock.

[0040] The first output selector 5 can be a combinational logic circuit composed of AND gates, OR gates, etc., used to select an output reference clock from the K selectable reference clocks output by the K frequency divider generation units 4. For example, the selectable reference clocks generated by the K frequency divider generation units 4 may include 2 times the reference clock. 1 Frequency division, 2 2 Frequency division, 2 3 Frequency division, up to 2 K Frequency division: the first output selector 5 can adaptively select one of these selectable reference frequency division clocks as the reference frequency division clock.

[0041] In one possible implementation, the compensation channel 2 may consist of at least a first decoder 6, a multiplex clock selector 7, K frequency division synchronization units 8, and a second output selector 9.

[0042] The first decoder 6 can be implemented by combinational logic circuits or field-programmable gate arrays (FPGAs), which can generate selection signals for the multi-channel clock selector 7 based on the phase selection signal and the frequency selection signal.

[0043] Among them, the multiplex clock selector 7, also known as a data selector or multiplexer, can select one of the multiple channels in the adjustment clock as the compensation clock under the indication of the selection signal.

[0044] The K frequency division synchronization units 8 may include the first to the Kth frequency division synchronization units. The j-th frequency division synchronization unit among the K frequency division synchronization units 8 is used to perform 2x frequency division synchronization on the compensation clock when it is simultaneously activated with the j-th frequency division generation unit among the K frequency division generation units 4. j Frequency division yields the j-th selectable compensated frequency-divided clock. The first to the k-th frequency-divided synchronization units can be cascaded. Each frequency-divided synchronization unit consists of a 2-dividend module (e.g., a 2-dividend module composed of D flip-flops and NOT gates), switches, transmission gates, and other digital circuits. The data input of the D flip-flops in the 2-dividend module is also the output of the corresponding D flip-flop in the frequency-dividend generation unit. This allows the frequency-dividend generation unit and the corresponding frequency-dividend synchronization unit to operate simultaneously, which is beneficial for synchronizing the operating frequency of reference channel 1. In this example, the K frequency-dividend synchronization units 8 can achieve a compensation clock M=2 through cascading. K Frequency division. The first (j=1) frequency division synchronization unit divides the compensation clock by 2 to obtain the first selectable compensation clock; the second (j=2) frequency division synchronization unit divides the compensation clock by 2... 2 =4 division, resulting in the second optional compensated frequency division clock; and so on, the Kth (j=K) frequency division synchronization unit is used to perform 2 division on the compensated clock. K Frequency division is performed to obtain the Kth optional compensated frequency-divided clock. Specifically, for example, when K=3, an 8-division compensation clock can be achieved by cascading three frequency division synchronization units. The first frequency division synchronization unit divides the compensation clock by 2 to obtain the first optional compensated frequency-divided clock; the second frequency division synchronization unit divides the compensation clock by 2... 2 =4 frequency division, resulting in the second optional compensated frequency division clock; the third frequency division synchronization unit is used to perform 2... 3 =8 division, resulting in the third optional compensated frequency division clock.

[0045] The second output selector 9 can be a combinational logic circuit composed of AND gates, OR gates, etc., used to determine the M=2 of the K frequency division synchronization units 8. K Frequency division allows selection of the output compensated frequency division clock. For example, the optional compensated frequency division clock generated by K frequency division synchronization units 8 can include 2 times the compensated clock. 1 Frequency division, 2 2 Frequency division, 2 3 Frequency division, up to 2 K With frequency division, the second output selector 9 can adaptively select one of these optional compensated frequency division clocks as the compensated frequency division clock.

[0046] The clock skew compensation circuit of this disclosure can adaptively output clock frequency, and its clock skew compensation range is constant.

[0047] Figure 2 A schematic diagram of a clock skew compensation circuit according to an embodiment of the present disclosure is shown. Figure 2 As shown, the reference channel 1 further includes a first logic gate circuit 01, and the compensation channel 2 further includes a second logic gate circuit 02; wherein, the output terminal of the input buffer 3 is connected to the first input terminal of the first logic gate circuit 01, the first output terminal of the first logic gate circuit 01 is connected to the first input terminal of the first frequency divider generation unit 4_1, the first output terminal of the i-th frequency divider generation unit 4_i is connected to the first input terminal of the (i+1)-th frequency divider generation unit 4_i+1, and the second output terminal of the first logic gate circuit 01, the first output terminal of each frequency divider generation unit among the first to the K-th frequency divider generation units 4_1, and the first input terminal of the (i+1)-th frequency divider generation unit 4_i+1 are connected to the first input terminal of the (i+1)-th frequency divider generation unit 4_i+1. The two output terminals are respectively connected to different input terminals of the first output selector 5 so that the first output selector 5 outputs a reference frequency divider clock, where the value of i ranges from 1 to K-1; wherein, the second output terminal of the first logic gate circuit 01 is connected to the first input terminal of the first output selector 5, the second output terminal of the first frequency divider generation unit 4_1 is connected to the second input terminal of the first output selector 5, the second output terminal of the second frequency divider generation unit 4_2 is connected to the third input terminal of the first output selector 5, and so on, with the second output terminal of the Kth frequency divider generation unit 4_K connected to the K+1th input terminal of the first output selector 5.

[0048] The first output of the first decoder 6 is connected to the second input of the multiplexer 7. The second output of the first decoder 6 is connected to the third input of each of the first to Kth frequency division synchronization units 8_1. The output of the multiplexer 7 is connected to the first input of the second logic gate 02. The first output of the second logic gate 02 is connected to the first input of the first frequency division synchronization unit 8_1. The first output of the i-th frequency division synchronization unit 8_i is connected to the first input of the (i+1)-th frequency division synchronization unit 8_i+1. The third output of the i-th frequency division generation unit 4_i is connected to the second input of the i-th frequency division synchronization unit 8_i. The second output terminal of logic gate circuit 02 and the second output terminal of each of the first to Kth frequency division synchronization units 8_1 are respectively connected to different input terminals of the second output selector 9 so that the second output selector 9 outputs a compensated frequency division clock. Specifically, the second output terminal of the second logic gate circuit 02 is connected to the first input terminal of the second output selector 9, the second output terminal of the first frequency division synchronization unit 8_1 is connected to the second input terminal of the second output selector 9, the second output terminal of the second frequency division synchronization unit 8_2 is connected to the third input terminal of the second output selector 9, and so on, with the second output terminal of the Kth frequency division synchronization unit 8_K connected to the (K+1)th input terminal of the second output selector 9.

[0049] The second input terminal of the first decoder 6, the second input terminal of the first logic gate circuit 01, the second input terminal of the second logic gate circuit 02, the second input terminal of each frequency division generation unit in the first frequency division generation unit 4_1 to the Kth frequency division generation unit 4_K, and the fourth input terminal of each frequency division synchronization unit in the first frequency division synchronization unit 8_1 to the Kth frequency division synchronization unit 8_K are used to receive the frequency selection level signal. The input terminal of the input buffer 3 is used to receive the reference clock. The first input terminal of the first decoder 6 is used to receive the phase selection level signal. The first input terminal of the multiplex clock selector 7 is used to receive the adjustment clock.

[0050] It should be understood that, Figure 2 In the diagram, ix represents the x-th input terminal, ox represents the x-th output terminal, and x is any positive integer. For example, i1 represents the first input terminal, i2 represents the second input terminal, i3 represents the third input terminal, and so on, i(K+1) represents the K+1-th input terminal; o1 represents the first output terminal, o2 represents the second output terminal, and o3 represents the third output terminal.

[0051] To more clearly illustrate the clock skew compensation circuit of the embodiments of this disclosure, a 3-bit 2-channel adaptive clock skew compensation circuit with an 8-division ratio is used as an example below (N=3, L=2, M=2).K =8), to illustrate the clock skew compensation circuit of this embodiment. Here, the number of bits N is determined by the bit width of the phase selection level signal; the number of channels L represents the total number of reference channel 1 and compensation channel 2 in the clock skew compensation circuit; for example, the number of channels L can be determined by adding 1 to the number of compensation channel 2; the frequency division number M=2 K K=2 P -1, the P value is determined by the bit width of the frequency selection gear signal.

[0052] Figure 3 A schematic diagram of another clock skew compensation circuit according to an embodiment of the present disclosure is shown. Figure 3 As shown, the clock skew compensation circuit is a 3-bit, 2-channel, 8-division adaptive clock skew compensation circuit. This clock skew compensation circuit includes a reference channel 1 and a compensation channel 2. The reference channel 1 includes an input buffer 3, a first logic gate circuit 01, three (K=3) frequency divider generation units 4 (e.g., the first frequency divider generation unit 4_1, the second frequency divider generation unit 4_2, and the third frequency divider generation unit 4_3), a first output selector 5, and a second decoder 03. The compensation channel 2 includes a first decoder 6, a multiplexer clock selector 7, three frequency divider synchronization units 8 (e.g., the first frequency divider synchronization unit 8_1, the second frequency divider synchronization unit 8_2, and the third frequency divider synchronization unit 8_3), and a second output selector 9.

[0053] In one possible implementation, the input buffer 3 includes a plurality of serially connected first NOT gates, the number of which is determined by the number of stages of the multiplexer 7.

[0054] like Figure 3 As shown, for the 3-bit 2-channel 8-division adaptive clock skew compensation circuit, the bit width of the adjustment clock CK_IN<7:1> input to the multiplexer 7 is 7, which means that the adjustment clock CK_IN<7:1> can include 7 different clock signals, i.e., CK_IN <1> ~ CK_IN <7> .

[0055] Figure 4 A schematic diagram of adjusting a clock according to an embodiment of the present disclosure is shown, such as Figure 4As shown, the reference clock CK_IN <0> The waveform is exactly the same as that of the adjustment clock CK_IN<7:1>, both of which can be generated by the same crystal oscillator. However, the reference clock CK_IN <0> The phase of the clock signal is different from that of any of the clock signals in the adjustment clock CK_IN<7:1>. For example, the CK_IN in the adjustment clock... <1> Relative reference clock CK_IN <0> Delayed by 1 / 8 phase, adjusting CK_IN in the clock. <2> Relative reference clock CK_IN <0> The phase was delayed by 2 / 8, and the CK_IN in the clock was adjusted. <3> Relative reference clock CK_IN <0> The phase was delayed by 3 / 8, and the CK_IN in the clock was adjusted. <4> Relative reference clock CK_IN <0> The phase was delayed by 4 / 8, and the CK_IN in the clock was adjusted. <5> Relative reference clock CK_IN <0> The phase was delayed by 5 / 8 seconds, and the CK_IN in the clock was adjusted. <6> Relative reference clock CK_IN <0> The phase was delayed by 6 / 8, and the CK_IN in the clock was adjusted. <7> Relative reference clock CK_IN <0> It was delayed by 7 / 8 phase.

[0056] The multiplexer 7 needs to select from the 7 clock signals CK_IN of the clock adjustment CK_IN<7:1>. <1> ~ CK_IN <7> Selecting one clock signal as the compensation clock (i.e., 7-to-1) requires at least four stages of delay time. The first stage requires four 2-to-1 data selectors to select four clock signals from the seven clock signals. The second stage requires two 2-to-1 data selectors to select two clock signals from the four clock signals. The third stage requires one 2-to-1 data selector to select one clock signal from the two clock signals. The fourth stage outputs the selected clock signal as the compensation clock. Therefore, in order to match the delay of the multiplex clock selector 7, the input buffer 3 needs to be equipped with four cascaded first NOT gates.

[0057] In this way, the moment when the reference clock arrives at the first frequency divider generation unit 4_1 is synchronized or aligned with the moment when the compensation clock arrives at the first frequency divider synchronization unit 8_1, which helps to improve the accuracy of the clock deviation compensation circuit.

[0058] In one possible implementation, such as Figure 3 As shown, in the clock skew compensation circuit, each frequency divider generation unit 4 (e.g., the first frequency divider generation unit 4_1, the second frequency divider generation unit 4_2, and the third frequency divider generation unit 4_3) contains a third logic gate circuit, and each frequency divider synchronization unit 8 (e.g., the first frequency divider synchronization unit 8_1, the second frequency divider synchronization unit 8_2, and the third frequency divider synchronization unit 8_3) contains a fourth logic gate circuit. The circuit structures of the third logic gate circuit, the fourth logic gate circuit, the first logic gate circuit 01, and the second logic gate circuit 02 are completely identical.

[0059] Figure 5 A schematic diagram of a logic gate circuit according to an embodiment of the present disclosure is shown, such as... Figure 5 As shown, the logic gate circuit includes an AND gate N1, a fifth NOT gate N5, and a first NAND gate NA1. The first input terminal of the AND gate N1 is connected to the second input terminal of the first NAND gate NA1 at a third node i1, and the third node i1 is the first input terminal of the logic gate circuit. The second input terminal of the AND gate N1 is connected to the output terminal of the fifth NOT gate N5. The input terminal of the fifth NOT gate N5 is connected to the first input terminal of the first NAND gate NA1 at a fourth node i2, and the fourth node i2 is the second input terminal of the logic gate circuit. The output terminal o1 of the AND gate N1 serves as the first output terminal of the logic gate circuit, and the output terminal o2 of the first NAND gate NA1 serves as the second output terminal of the logic gate circuit.

[0060] For example, suppose the signal input to the first input terminal i1 of the logic gate is A, the signal input to the second input terminal i2 is B, and the signal output from the first output terminal o1 of the logic gate is A& The signal output from the first output terminal O1 of the logic gate circuit is Thus, when B=0, the signal output from the first output terminal o1 of the logic gate circuit is A, and the signal output from the second output terminal o2 of the logic gate circuit is 1. When B=1, the signal output from the first output terminal o1 of the logic gate circuit is 0, and the signal output from the second output terminal o2 of the logic gate circuit is... Through logic gate circuits, under the control of signal B at the second input terminal i2, it is possible to select whether to output signal A input at the first input terminal i1 through the first output terminal o1 or through the second output terminal o2.

[0061] Figure 6 A circuit diagram of a frequency division generation unit according to an embodiment of the present disclosure is shown, such as... Figure 6 As shown, the frequency division generation unit 4 includes a first D flip-flop, a second NOT gate N2, and a third logic gate circuit 403 (see details). Figure 5The clock input terminal clk of the first D flip-flop serves as the first input terminal i1 of the frequency divider generation unit 4. The data input terminal D of the first D flip-flop is connected to the output terminal of the second NOT gate N2. The input terminal of the second NOT gate N2, the output terminal Q of the first D flip-flop, and the first input terminal of the third logic gate circuit 403 are connected to the first node o3. The first node o3 is the third output terminal of the frequency divider generation unit. The second input terminal i2 of the third logic gate circuit 403 serves as the second input terminal of the frequency divider generation unit 4. The first output terminal o1 of the third logic gate circuit 403 serves as the first output terminal of the frequency divider generation unit 4. The second output terminal o2 of the third logic gate circuit 403 serves as the second output terminal of the frequency divider generation unit.

[0062] In this way, each frequency divider generation unit 4 can divide the clock signal input at the first input terminal i1 by two, and select either the first output terminal o1 or the second output terminal o2 to output the divided clock signal according to the indication of the input signal at the second input terminal i2. Furthermore, the third output terminal o3 of the frequency divider generation unit 4 is also used to synchronize the corresponding frequency divider synchronization unit 8.

[0063] Figure 7 A circuit diagram of a frequency division synchronization unit according to an embodiment of the present disclosure is shown, as follows: Figure 7 As shown, the frequency division synchronization unit 8 includes a second D flip-flop, a first switch S, a third NOT gate N3, a fourth NOT gate N4, and a fourth logic gate circuit 804 (see details). Figure 5 The clock input terminal clk of the second D flip-flop serves as the first input terminal i1 of the frequency division synchronization unit 8, and the data input terminal D of the second D flip-flop serves as the second input terminal i2 of the frequency division synchronization unit 8. The output terminal Q of the second D flip-flop, the first terminal of the first switch S, and the input terminal of the fourth NOT gate N4 are connected. The second terminal of the first switch S, the output terminal of the fourth NOT gate N4, and the first input terminal of the fourth logic gate circuit 804 are connected. The input terminal of the third NOT gate N3, the first control terminal of the first switch S, and the control terminal of the fourth NOT gate N4 are connected to the second node i3. The second node i3 is the third input terminal of the frequency division synchronization unit 8. The output terminal of the third NOT gate N3 is connected to the second control terminal of the first switch S. The second input terminal of the fourth logic gate circuit 804 serves as the fourth input terminal i4 of the frequency division synchronization unit 8. The first output terminal o1 of the fourth logic gate circuit 804 serves as the first output terminal of the frequency division synchronization unit 8, and the second output terminal o2 of the fourth logic gate circuit 804 serves as the second output terminal of the frequency division synchronization unit 8.

[0064] In this way, the frequency division synchronization unit 8 can synchronize the operating frequency of the corresponding frequency division generation unit 4.

[0065] In one possible implementation, such as Figure 3 As shown, in the clock skew compensation circuit, the circuitry of the first output selector 5 and the second output selector 9 is identical. Each output selector includes a NOR gate and at least one second NAND gate, with the output of each second NAND gate connected to different inputs of the NOR gate. It should be understood that the number of second NAND gates is determined by the number of frequency division generation units 4 (or the number of frequency division synchronization units 8), and can be set according to the actual application scenario. The embodiments of this disclosure do not impose any limitations on this.

[0066] Figure 8 A circuit diagram of an output selector according to an embodiment of the present disclosure is shown, such as Figure 8 As shown, for a 3-bit, 2-channel, 8-division adaptive clock skew compensation circuit (see...), Figure 3 The output selector includes a NOR gate, a second NAND gate NA2_1, and a second NAND gate NA2_2. The output of the second NAND gate NA2_1 is connected to the first input of the NOR gate, and the output of the second NAND gate NA2_2 is connected to the second input of the NOR gate. The first input of the second NAND gate NA2_1 can serve as the first input of the output selector, the second input of the second NAND gate NA2_1 can serve as the second input of the output selector, the first input of the second NAND gate NA2_2 can serve as the third input of the output selector, the second input of the second NAND gate NA2_2 can serve as the fourth input of the output selector, and the output of the NOR gate serves as the output of the output selector.

[0067] like Figure 3 As shown, for the first output selector 5, the first input of the second NAND gate NA2_1 is connected to the second output of the first logic gate circuit 01 to receive the reference clock; the second input of the second NAND gate NA2_1 is connected to the second output of the first frequency divider generation unit 4_1 to receive the first selectable reference frequency divider clock (a 2-fold division of the reference clock); the first input of the second NAND gate NA2_2 is connected to the second output of the second frequency divider generation unit 4_2 to receive the second selectable reference frequency divider clock (a 4-fold division of the reference clock); the second input of the second NAND gate NA2_2 is connected to the second output of the third frequency divider generation unit 4_3 to receive the third selectable reference frequency divider clock (an 8-fold division of the reference clock). In this way, the first output selector 5 can select one of the following as the reference frequency divider clock: the reference clock, the first selectable reference frequency divider clock (a 2-fold division of the reference clock), the second selectable reference frequency divider clock (a 4-fold division of the reference clock), and the third selectable reference frequency divider clock (an 8-fold division of the reference clock).

[0068] like Figure 3 As shown, for the second output selector 9, the first input of the second NAND gate NA2_1 is connected to the second output of the second logic gate circuit 02 to receive the compensation clock; the second input of the second NAND gate NA2_1 is connected to the second output of the first frequency division synchronization unit 8_1 to receive the first optional compensation frequency division clock (compensation clock divided by 2); the first input of the second NAND gate NA2_2 is connected to the second output of the second frequency division synchronization unit 8_2 to receive the second optional compensation frequency division clock (compensation clock divided by 4); the second input of the second NAND gate NA2_2 is connected to the second output of the third frequency division synchronization unit 8_3 to receive the third optional compensation frequency division clock (compensation clock divided by 8). In this way, the second output selector 9 can select one of the compensation clocks (compensation clock, first optional compensation frequency division clock, compensation clock divided by 2, second optional compensation frequency division clock, compensation clock divided by 4, and third optional compensation frequency division clock) as the compensation frequency division clock.

[0069] The first output selector 5 can be used to select the output reference frequency divider clock based on each frequency divider generation unit 4; the second output selector 6 can be used to select the output compensation frequency divider clock based on each frequency divider synchronization unit 8.

[0070] In one possible implementation, the frequency selection gear signal includes 2 P The clock skew compensation circuit further includes a second decoder, which converts the input P-bit binary initial signal into a 2-bit binary signal. P The output signal serves as the frequency selection level signal.

[0071] For example, such as Figure 3 As shown, for a 3-bit, 2-channel, 8-division adaptive clock offset compensation circuit, the second decoder 03 can be a 2-to-4 decoder, which can convert the input 2-bit (P=2) binary initial signal DIV_SEL<1:0> into 4 output signals (e.g., 0, 1, 2, 3) as frequency selection gear signals.

[0072] In one possible implementation, such as Figure 3As shown, for a 3-bit, 2-channel, 8-division adaptive clock skew compensation circuit (N=3, L=2, M=2K=8), the first input of the first decoder 6 is used to receive the phase selection mode signal PHASE_SEL<2:0>, and the second input of the first decoder 6 is used to receive the frequency selection mode signal, that is, the signal after 2-4 decoding of DIV_SEL<1:0> (e.g., 0, 1, 2, 3). The first output of the first decoder 6 is used to generate the selection signal of the multiplexer 7. N=PHASE_SEL<2:0>=3, K=2DIV_SEL<1:0>-1=2²-1=3, M=2K=2³=8, N and M are independent of each other. The first decoder 6 represents the following function:

[0073]

[0074] It should be understood that the first decoder 6 can implement the above-mentioned functional relationship by combinational logic circuits or field-programmable gate arrays (FPGAs), and the embodiments of this disclosure do not impose specific limitations on this.

[0075] It should be understood that Figure 3 An adaptive clock skew compensation circuit with only 3 bits, 2 channels, and 8 divider (N=3, L=2, M=2) K =8) As an example, the multi-bit multi-channel multi-frequency division adaptive clock deviation compensation circuit provided in the embodiments of this disclosure can be set according to the actual application scenario. The embodiments of this disclosure do not limit the specific values ​​of the number of bits N, the number of channels L, and the number of frequency divisions M.

[0076] In summary, the N-bit L-channel M-division adaptive clock skew compensation circuit provided in this embodiment can adaptively output clock frequency, and its clock skew compensation range is constant.

[0077] In one possible implementation, embodiments of this disclosure also provide a chip including the clock skew compensation circuit described above.

[0078] In one possible implementation, embodiments of this disclosure also provide an electronic device including the clock skew compensation circuit described above.

[0079] For example, the electronic devices in this embodiment include, but are not limited to, desktop computers, televisions, mobile devices with large screens such as mobile phones and tablets, and other common electronic devices that require multiple chips to be cascaded together to achieve driving.

[0080] For example, electronic devices can also be user equipment (UE), mobile devices, user terminals, terminals, handheld devices, computing devices, or in-vehicle devices, etc. Examples of terminals include: displays, smartphones or portable devices, mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, a server can be a local server or a cloud server.

[0081] Figure 9 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. The electronic device includes the clock skew compensation circuit described above. For example, the electronic device 1900 may be provided as a server or terminal device. (Refer to...) Figure 9 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0082] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output interface 1958. Electronic device 1900 can operate on an operating system stored in memory 1932, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.

[0083] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0084] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the scope of protection of the present invention, which is determined by the appended claims.

[0085] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0086] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0087] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0088] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A clock skew compensation circuit, characterized in that, The clock skew compensation circuit includes a reference channel and at least one compensation channel. The reference channel includes an input buffer, K frequency divider generation units, and a first output selector. The compensation channel includes a first decoder, a multiplexed clock selector, K frequency divider synchronization units, and a second output selector, where K=2. P -1, where P is a positive integer; The input buffer is used to send the reference clock delayed to K frequency division generation units. Each frequency division generation unit performs frequency division processing on the reference clock to obtain K selectable reference frequency division clocks. The first output selector is used to output the reference frequency division clock according to the K selectable reference frequency division clocks. The first decoder is used to generate a selection signal for the multiplex clock selector, so that the multiplex clock selector generates a compensation clock based on the selection signal and the adjustment clock. When each frequency division synchronization unit and the frequency division generation unit at the corresponding position are turned on simultaneously, they perform frequency division processing on the compensation clock to obtain K selectable compensation frequency division clocks. The second output selector is used to output the compensation frequency division clock according to the K selectable compensation frequency division clocks.

2. The clock skew compensation circuit according to claim 1, characterized in that, The j-th frequency division generation unit among the K frequency division generation units is used to perform 2-division transformation on the reference clock. j Frequency division is performed to obtain the j-th selectable reference frequency division clock, where the value of j ranges from 1 to K; When the j-th frequency division synchronization unit among the K frequency division synchronization units and the j-th frequency division generation unit among the K frequency division generation units are simultaneously activated, the compensation clock is 2... j Frequency division yields the j-th optional compensated frequency division clock.

3. The clock skew compensation circuit according to claim 1, characterized in that, The reference channel further includes a first logic gate circuit, and the compensation channel further includes a second logic gate circuit; Wherein, the output terminal of the input buffer is connected to the first input terminal of the first logic gate circuit, the first output terminal of the first logic gate circuit is connected to the first input terminal of the first frequency divider generation unit, the first output terminal of the i-th frequency divider generation unit is connected to the first input terminal of the (i+1)-th frequency divider generation unit, and the second output terminal of the first logic gate circuit and the second output terminal of each frequency divider generation unit are respectively connected to different input terminals of the first output selector, so that the first output selector outputs a reference frequency divider clock, and the value of i ranges from 1 to K-1; The first output terminal of the first decoder is connected to the second input terminal of the multiplexer. The second output terminal of the first decoder is connected to the third input terminal of each frequency division synchronization unit. The output terminal of the multiplexer is connected to the first input terminal of the second logic gate circuit. The first output terminal of the second logic gate circuit is connected to the first input terminal of the first frequency division synchronization unit. The first output terminal of the i-th frequency division synchronization unit is connected to the first input terminal of the (i+1)-th frequency division synchronization unit. The third output terminal of the i-th frequency division generation unit is connected to the second input terminal of the i-th frequency division synchronization unit. The second output terminal of the second logic gate circuit and the second output terminal of each frequency division synchronization unit are connected to different input terminals of the second output selector, so that the second output selector outputs a compensated frequency division clock. The second input terminal of the first decoder, the second input terminal of the first logic gate circuit, the second input terminal of the second logic gate circuit, the second input terminal of each frequency divider generation unit, and the fourth input terminal of each frequency divider synchronization unit are used to receive frequency selection level signals. The input terminal of the input buffer is used to receive a reference clock. The first input terminal of the first decoder is used to receive a phase selection level signal. The first input terminal of the multiplex clock selector is used to receive an adjustment clock.

4. The clock skew compensation circuit according to claim 1, characterized in that, The input buffer includes a plurality of serially connected first NOT gates, the number of which is determined by the number of stages of the multiplexer.

5. The clock skew compensation circuit according to claim 1, characterized in that, The frequency divider generation unit includes a first D flip-flop, a second NOT gate, and a third logic gate circuit. The clock input terminal of the first D flip-flop serves as the first input terminal of the frequency divider generation unit. The data input terminal of the first D flip-flop is connected to the output terminal of the second NOT gate. The input terminals of the second NOT gate, the output terminal of the first D flip-flop, and the first input terminal of the third logic gate circuit are connected to a first node. The first node serves as the third output terminal of the frequency divider generation unit. The second input terminal of the third logic gate circuit serves as the second input terminal of the frequency divider generation unit. The first output terminal of the third logic gate circuit serves as the first output terminal of the frequency divider generation unit. The second output terminal of the third logic gate circuit serves as the second output terminal of the frequency divider generation unit.

6. The clock skew compensation circuit according to claim 1, characterized in that, The frequency division synchronization unit includes a second D flip-flop, a first switch, a third NOT gate, a fourth NOT gate, and a fourth logic gate circuit. The clock input terminal of the second D flip-flop serves as the first input terminal of the frequency division synchronization unit, and the data input terminal of the second D flip-flop serves as the second input terminal of the frequency division synchronization unit. The output terminal of the second D flip-flop, the first terminal of the first switch, and the input terminal of the fourth NOT gate are connected together. The second terminal of the first switch, the output terminal of the fourth NOT gate, and the first input terminal of the fourth logic gate circuit are connected together. The input terminal of the third NOT gate, the first control terminal of the first switch, and the control terminal of the fourth NOT gate are connected to a second node, which serves as the third input terminal of the frequency division synchronization unit. The output terminal of the third NOT gate is connected to the second control terminal of the first switch. The second input terminal of the fourth logic gate circuit serves as the fourth input terminal of the frequency division synchronization unit, the first output terminal of the fourth logic gate circuit serves as the first output terminal of the frequency division synchronization unit, and the second output terminal of the fourth logic gate circuit serves as the second output terminal of the frequency division synchronization unit.

7. The clock skew compensation circuit according to any one of claims 3, 5, and 6, characterized in that, The logic gate circuit includes an AND gate, a fifth NOT gate, and a first NAND gate. The first input terminal of the AND gate is connected to the second input terminal of the first NAND gate at a third node, and the third node is the first input terminal of the logic gate circuit. The second input terminal of the AND gate is connected to the output terminal of the fifth NOT gate. The input terminal of the fifth NOT gate is connected to the first input terminal of the first NAND gate at a fourth node, and the fourth node is the second input terminal of the logic gate circuit. The output terminal of the AND gate serves as the first output terminal of the logic gate circuit, and the output terminal of the first NAND gate serves as the second output terminal of the logic gate circuit.

8. The clock skew compensation circuit according to claim 1, characterized in that, The output selector includes a NOR gate and at least one second NAND gate, with the output of each second NAND gate connected to a different input of the NOR gate.

9. The clock skew compensation circuit according to claim 1, characterized in that, Frequency selection gear signal includes 2 P The clock skew compensation circuit further includes a second decoder, which converts the input P-bit binary initial signal into a 2-bit binary signal. P The output signal serves as the frequency selection level signal.

10. A chip, characterized in that, Includes a clock skew compensation circuit according to any one of claims 1 to 9.

11. An electronic device, characterized in that, Includes a clock skew compensation circuit according to any one of claims 1 to 9.

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