Control circuit of a feedforward equalizer with impedance correction function

Abstract

This invention discloses a control circuit for a feedforward equalizer and the feedforward equalizer thereof. The control circuit includes a feedforward equalizer controller and an impedance control loop. The feedforward equalizer has multiple voltage-mode drivers that are commonly coupled to an output terminal. The feedforward equalizer controller receives a base current from a current generator and includes a current-to-analog converter and a current mirror. The current-to-analog converter generates a reference current based on the base current. The current mirror mirrors the reference current to generate at least one first reference voltage and outputs the at least one first reference voltage to at least one first voltage-mode driver. The impedance control loop generates a second reference voltage based on the at least one first reference voltage and outputs the second reference voltage to at least one second voltage-mode driver.

Description

Technical Field

[0001] This invention relates to a feed-forward equalizer (FFE), and more particularly to a control circuit for a feed-forward equalizer with impedance correction function. Background Technology

[0002] The rapid development of cloud computing, 5G networks, and artificial intelligence has led to an explosive growth in the bandwidth demands of communication networks. With this increased bandwidth demand, signal transmission becomes more sensitive to inter-symbol interference (ISI). To address ISI, feed-forward equalizers (FFEs) with a sufficient number of slices can be incorporated into the transmitter. Therefore, managing the parameter control of the feed-forward equalizer while simultaneously ensuring impedance matching for high-speed transmission has become a major challenge in this field. Summary of the Invention

[0003] Therefore, the main objective of this invention is to propose a control circuit for a feed-forward equalizer (FFE) for application in voltage-mode transmitters of high-speed transmission systems.

[0004] One embodiment of the present invention discloses a control circuit for a feedforward equalizer having multiple voltage-mode drivers coupled to a common output. The control circuit includes a feedforward equalizer controller and an impedance control loop. The feedforward equalizer controller receives a base current from a current generator and includes a current digital-to-analog converter (current DAC) and a current mirror. The current DAC generates a reference current based on the base current. The current mirror, coupled to the current DAC, mirrors the reference current to generate at least one first reference voltage and outputs the at least one first reference voltage to at least one of the multiple voltage-mode drivers. The impedance control loop, coupled to the feedforward equalizer controller, generates a second reference voltage based on the at least one first reference voltage and outputs the second reference voltage to at least one of the multiple voltage-mode drivers.

[0005] Another embodiment of the present invention discloses a feedforward equalizer, comprising an output circuit and a control circuit. The output circuit includes a plurality of voltage-mode drivers, which are collectively coupled to an output terminal. The control circuit is coupled to the output circuit and includes a feedforward equalizer controller and an impedance control loop. The feedforward equalizer controller receives a base current from a current generator and includes a current-to-analog converter and a current mirror. The current-to-analog converter generates a reference current based on the base current. The current mirror is coupled to the current-to-analog converter and mirrors the reference current to generate at least one first reference voltage, and outputs the at least one first reference voltage to at least one of the plurality of voltage-mode drivers. The impedance control loop is coupled to the feedforward equalizer controller and generates a second reference voltage based on the at least one first reference voltage, and outputs the second reference voltage to at least one of the plurality of voltage-mode drivers. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the feedforward equalizer in Embodiment 1 of the present invention.

[0007] Figure 2 This is a schematic diagram of a high-speed transmission system according to Embodiment 1 of the present invention.

[0008] Figure 3 The impedance matching of a transmitter is shown from the perspective of impedance.

[0009] Figure 4 The impedance matching of a transmitter is shown from the perspective of current.

[0010] Figure 5 A detailed embodiment of the control circuit of this invention is shown.

[0011] Figure 6 A detailed embodiment of the current digital-to-analog converter of the present invention is shown.

[0012] Figure 7 A detailed embodiment of the control circuit of this invention is shown.

[0013] The reference numerals in the attached figures are explained as follows:

[0014] 10 Feedforward Equalizer

[0015] 100 Output Circuit

[0016] 110 Control Circuit

[0017] 120 Feedforward Equalizer Controller

[0018] 130 Impedance Control Circuit

[0019] 150 Current Generator

[0020] 122, 122_1, 122_2 Current-to-Digital Converter

[0021] 124, 124_1, 124_2 Current mirrors

[0022] T_1~T_X Voltage Mode Drivers

[0023] Vout, Voutp, Voutn output signals

[0024] IB Base Current

[0025] IDAC, IDACpre, IDACpost reference current

[0026] Vref1 First reference voltage

[0027] Vref2 Second reference voltage

[0028] 20 High-speed transmission system

[0029] 210 Transmitter

[0030] 220 receiver

[0031] 200 transmission channels

[0032] P_DRV, N_DRV output drivers

[0033] MP1, MP2 P-type metal-oxide-semiconductor transistors

[0034] MN1, MN2 N-type metal-oxide-semiconductor transistors

[0035] resistors R1 and R2

[0036] Vrefp, Vrefn, Vrefp_main, Reference Voltage

[0037] Vrefn_main, Vrefp_pre, Vrefn_pre,

[0038] Vrefp_post, Vrefn_post CP1 pre-weight controller CP2 post-weighted controller Dpre pre-emphasis data Dpost-emphasized data CH1 Input Channel

[0039] CH2 Mirror Channel

[0040] CH3 Replication Channel

[0041] VCC power supply voltage

[0042] GND grounding voltage

[0043] 132, 134, 154 operational amplifiers

[0044] External resistors Rextn and Rextp

[0045] DRVn N-type copy drive

[0046] DRVp P-type copy drive

[0047] R is the voltage divider resistor.

[0048] Vy and Vx nodes

[0049] 152 Selection Device

[0050] Rref reference resistor

[0051] VBG bandgap voltage Detailed Implementation

[0052] Figure 1 This is a schematic diagram of a feed-forward equalizer (FFE) 10 according to an embodiment of the present invention. The feed-forward equalizer 10 can be implemented in a voltage-mode transmitter of a high-speed transmission system to perform pre-emphasis or de-emphasis on the output signal to reduce or eliminate the influence of noise or line loss that may interfere with the signal, thereby improving signal quality.

[0053] like Figure 1As shown, the feedforward equalizer 10 includes an output circuit 100 and a control circuit 110. The output circuit 100 serves as the output driver for a voltage-mode transmitter, comprising multiple voltage-mode drivers T_1 to T_X, which are collectively coupled to an output terminal of the transmitter. The outputs of each voltage-mode driver T_1 to T_X can be combined to generate an output signal Vout. Each voltage-mode driver T_1 to T_X can be a drive channel, or it can be considered a circuit slice. Generally, the voltage-mode drivers T_1 to T_X include one or more main-tap drivers, one or more pre-tap drivers, and one or more post-tap drivers. The main-tap drivers are used to output the main signal. The pre-tap and post-tap drivers are used to provide pre-emphasis or de-emphasis to improve signal quality. Generally, pre-voltage mode drivers and post-voltage mode drivers are essential components in the architecture of feedforward equalizers. They can increase the high-frequency components of the signal to resist high-frequency attenuation in the transmission channel, resulting in a more ideal signal quality measured at the receiver.

[0054] Control circuit 110 can be used to control the operation of feedforward equalizer 10, integrating coefficient control and impedance control of the feedforward equalizer. Specifically, control circuit 110 includes a feedforward equalizer controller 120 and an impedance control loop 130. Feedforward equalizer controller 120 can be used to control the coefficients of the feedforward equalizer, and impedance control loop 130 can be used to control impedance matching with the transmission channel. For ease of explanation, Figure 1 A current generator 150 is also shown, which may or may not be included in the feedforward equalizer 10. The current generator 150 can provide a base current IB to the feedforward equalizer controller 120.

[0055] The feedforward equalizer controller 120 may include a current digital-to-analog converter (Current DAC) 122 and a current mirror 124. After receiving a base current IB from a current generator 150, the current DAC 122 generates a reference current IDAC based on the base current IB. The current mirror 124 then mirrors the reference current IDAC to generate at least one first reference voltage Vref1, and outputs the first reference voltage Vref1 to at least one of the voltage mode drivers T_1 to T_X. In some embodiments, the first reference voltage Vref1 may be output to a pre-voltage mode driver and a post-voltage mode driver among the voltage mode drivers T_1 to T_X. Based on the pre-emphasis data and the post-emphasis data, the feedforward equalizer controller 120 can generate a suitable reference voltage for the pre-voltage mode driver and the post-voltage mode driver to achieve the desired pre-emphasis or de-emphasis effect.

[0056] The first reference voltage Vref1 can also be provided to the impedance control circuit 130 for impedance matching. After receiving the first reference voltage Vref1, the impedance control circuit 130 can generate at least one second reference voltage Vref2 based on the first reference voltage Vref1, and output the second reference voltage Vref2 to at least one of the voltage mode drivers T_1 to T_X. In some embodiments, the second reference voltage Vref2 can be output to the main voltage mode driver among the voltage mode drivers T_1 to T_X.

[0057] Figure 2 This is a schematic diagram of a high-speed transmission system 20 according to an embodiment of the present invention. The high-speed transmission system 20 includes a transmitter 210, a receiver 220, and a transmission channel 200 connected between the transmitter 210 and the receiver 220. The transmission channel 200 can be implemented using a twisted-pair cable, and its characteristic impedance is equal to 50 ohms (Ω). The transmission channel 200 can be any type of wired channel with high-speed transmission capability, including, but not limited to, High Definition Multimedia Interface (HDMI) and DisplayPort (DP).

[0058] In this example, transmitter 210 can be a differential transmitter with a pair of output drivers P_DRV and N_DRV, used to output output signals Voutp and Voutn, respectively. Each output driver P_DRV and N_DRV can be an output circuit of a feedforward equalizer (e.g., ...). Figure 1The output circuit 100 shown includes multiple voltage-mode drivers, including one or more pre-voltage-mode drivers, one or more post-voltage-mode drivers, and one or more main voltage-mode drivers. Since the output drivers are differentially configured, the differential impedance faced by transmitter 210 is equal to 100Ω, which is equivalent to output drivers P_DRV and N_DRV being coupled to the two ends of a 100Ω resistive load, as shown below. Figure 3 As shown. To achieve impedance matching, the output drivers P_DRV and N_DRV should be well designed so that the output impedance of P_DRV is substantially equal to 50Ω and the output impedance of N_DRV is substantially equal to 50Ω.

[0059] It is worth noting that impedance matching is a fundamental requirement in high-speed transmission systems. The output impedance of the transmitter is required to be substantially equal to 50Ω, or close to 50Ω within the allowable error range; otherwise, the output signal will produce unnecessary reflections, leading to a degraded signal quality.

[0060] like Figure 2 As shown, in the output drivers P_DRV and N_DRV, each voltage-mode driver can be composed of two P-type metal-oxide-semiconductor transistors (PMOS transistors) MP1 and MP2, two N-type metal-oxide-semiconductor transistors (NMOS transistors) MN1 and MN2, and two resistors R1 and R2. Transistors MP1 and MN1 receive reference voltages Vrefp and Vrefn, respectively, to generate the desired output impedance to match the characteristic impedance of the transmission channel 200. Based on the feedforward equalizer structure of transmitter 210, each output driver P_DRV and N_DRV is composed of multiple voltage-mode drivers; therefore, the output impedance of each output driver P_DRV or N_DRV is generated by the combination of the output impedances of these parallel voltage-mode drivers. In other words, the output impedance of each voltage-mode driver should be well designed so that, when these voltage-mode drivers are connected in parallel, both output drivers P_DRV and N_DRV can achieve the target impedance of 50Ω.

[0061] Unlike the impedance perspectives mentioned above, this invention uses a current perspective to address impedance matching issues, such as... Figure 4As shown, when the output impedances of output drivers P_DRV and N_DRV are perfectly matched and have a resistance of 50Ω, the overall impedance from the power supply terminal of one output driver (e.g., P_DRV) to the ground terminal of the other output driver (e.g., N_DRV) is equal to 200Ω. Assuming the power supply voltage VCC supplied to output drivers P_DRV and N_DRV is 1V, the total current through the channel formed by output drivers P_DRV and N_DRV and the 100Ω resistive load is equal to 5 milliamperes (mA). This 5mA current is distributed to each voltage-mode driver in output drivers P_DRV and N_DRV. In this case, the pre-emphasis / deemphasis intensity can be adjusted by regulating the current flowing through the pre-voltage-mode driver and the post-voltage-mode driver, while the current used for the main voltage-mode driver can be further controlled so that the sum of the currents for all voltage-mode drivers equals 5mA.

[0062] Please refer to Figure 2 Matching Figure 4 As shown, the current flowing through the voltage-mode driver can be controlled by adjusting the reference voltage Vrefp or Vrefn. For both the pre-voltage-mode and post-voltage-mode drivers, the reference voltages Vrefp or Vrefn can be designed with appropriate values ​​to achieve the desired pre-emphasis / de-emphasis effect. The reference voltages Vrefp or Vrefn used for the main voltage-mode driver can be further designed so that the total current through each output driver P_DRV and N_DRV is equal to 5mA.

[0063] In existing technologies, impedance matching is performed from a reference impedance perspective. Based on pre-emphasis and post-emphasis data, the feedforward equalizer control circuit selects the desired output impedance from a resistor array to provide to the pre-voltage mode driver and post-voltage mode driver. This allows the use of operational amplifiers to generate reference voltages Vrefp and Vrefn for the pre-voltage mode driver and post-voltage mode driver, thereby locking the output impedance to a target level. Based on the output impedances of the pre-voltage mode driver and post-voltage mode driver, the control circuit also determines the output impedance of the main voltage mode driver to control the overall output impedance to reach 50Ω. Subsequently, the control circuit determines the reference voltages Vrefp and Vrefn for the main voltage mode driver to ensure that the overall output impedance of the output circuit (i.e., the parallel impedance of the voltage mode driver) equals 50Ω. It should be noted that existing feedforward equalizer control circuits are equipped with a resistor array that can be switched according to the pre-emphasis or post-emphasis data. This resistor array has a considerable area to achieve the necessary pre-emphasis / de-emphasis function. In addition, the feedforward equalizer control circuit uses many operational amplifiers to lock the reference voltages Vrefp and Vrefn, and operational amplifiers usually require a lot of power.

[0064] Therefore, this invention proposes a novel control circuit that can be used in feedforward equalizers and high-speed transmitters, wherein the control circuit controls impedance matching from a current perspective. For example, such as Figure 1 As shown, the feedforward equalizer controller 120 can be implemented using a current-to-digital converter 122 and a current mirror 124 to generate the desired current for the voltage-mode driver. Therefore, the feedforward equalizer does not require a large resistor array, and the number of operational amplifiers can be reduced, thereby reducing circuit area and power consumption.

[0065] Figure 5 A detailed embodiment of the control circuit 110 of this invention is shown. The control circuit 110 is used to output a reference voltage to an output circuit (such as...). Figure 1 The output circuit 100 shown is omitted. Figure 5For simplification. In one embodiment, the output circuit includes three main voltage-mode drivers, one pre-voltage-mode driver, and one post-voltage-mode driver. Control circuit 110 provides reference voltages Vrefp_main and Vrefn_main to the main voltage-mode drivers, reference voltages Vrefp_pre and Vrefn_pre to the pre-voltage-mode drivers, and reference voltages Vrefp_post and Vrefn_post to the post-voltage-mode drivers. P-type reference voltages Vrefp_main, Vrefp_pre, and Vrefp_post are provided to the P-type metal-oxide-semiconductor transistors in the respective voltage-mode drivers, which can serve as… Figure 2 The reference voltage Vrefp is output to transistor MP1. The N-type reference voltages Vrefn_main, Vrefn_pre, and Vrefn_post are provided to the N-type metal-oxide-semiconductor transistors in the corresponding voltage-mode drivers, which can be used as… Figure 2 The reference voltage Vrefn is output to transistor MN1.

[0066] It is worth noting that, in another embodiment, the output circuit may also include multiple pre-voltage mode drivers and / or multiple post-voltage mode drivers, and / or any number of main voltage mode drivers. For example, to achieve higher transmission speeds, the output circuit may include a greater number of main voltage mode drivers, and the number (or slices) of various types of voltage mode drivers included in the output circuit should not be used to limit the scope of the invention.

[0067] The feedforward equalizer controller 120 in the control circuit 110 is configured to generate reference voltages Vrefp_pre and Vrefn_pre for the pre-voltage mode driver, and reference voltages Vrefp_post and Vrefn_post for the post-voltage mode driver. To achieve the desired pre-emphasis / de-emphasis effect on the output signal, the feedforward equalizer controller 120 can control the values ​​of these reference voltages.

[0068] Based on the values ​​of reference voltages Vrefp_pre, Vrefn_pre, Vrefp_post, and Vrefn_post, the impedance control loop 130 in control circuit 110 is configured to generate reference voltages Vrefp_main and Vrefn_main for the main voltage-mode driver. The values ​​of reference voltages Vrefp_main and Vrefn_main can be well adjusted to control the total current flowing through the voltage-mode driver, thereby meeting impedance matching requirements.

[0069] In detail, the feedforward equalizer controller 120 includes a pre-emphasis controller CP1 and a post-emphasis controller CP2. The pre-emphasis controller CP1 includes a current-to-analog converter 122_1 and a current mirror 124_1, while the post-emphasis controller CP2 includes a current-to-analog converter 122_2 and a current mirror 124_2. Generally, the pre-emphasis controller CP1 and the post-emphasis controller CP2 have the same structure; the following detailed explanation uses the pre-emphasis controller CP1 as an example.

[0070] In the pre-weighting controller CP1, the current digital-to-analog converter 122_1 receives the base current IB and is controlled by a pre-weighting data Dpre, which specifies the required pre-weighting or de-weighting intensity. The pre-weighting data Dpre is used to determine the value of the reference current IDACpre output by the current digital-to-analog converter 122_1.

[0071] Figure 6 A detailed embodiment of the current digital-to-analog converter 122_1 according to an embodiment of the present invention is shown. For example... Figure 6 As shown, the current digital-to-analog converter 122_1 includes N output channels with different current weights. The pre-emphasis data Dpre can be N-bit control data, output to the switches of the N output channels respectively, to control whether each output channel is turned on or off. The currents of the turned-on channels are then summed to generate the reference current IDACpre output by the current digital-to-analog converter 122_1. In this example, the reference current IDACpre is k times the base current IB, where k can be determined by the pre-emphasis data Dpre, and the relevant formula is as follows:

[0072] IDACpre = k × IB.

[0073] The current mirror 124_1 includes an input channel CH1, a mirror channel CH2, and a replication channel CH3. The replication channel CH3 can be a copy of the corresponding voltage-mode driver; therefore, it includes two P-type MOSFETs MP1 and MP2, two N-type MOSFETs MN1 and MN2, and two resistors R1 and R2, using the same notation as the corresponding components in the voltage-mode driver. To simulate the voltage-mode driver environment for impedance matching, both the high-side P-type MOSFET and the low-side N-type MOSFET in the replication channel CH3 are fully turned on. Therefore, the gate of the N-type MOSFET MN2 receives a supply voltage VCC, and the gate of the P-type MOSFET MP2 receives a ground voltage GND. The input channel CH1 is coupled to the replication channel CH3 through the gate of the N-type MOSFET MN1, which is the node that generates the reference voltage Vrefn_pre. Based on the reference current IDACpre (which has a target value expected to flow through the pre-voltage mode driver), the reference voltage Vrefn_pre supplied to transistor MN1 in the pre-voltage mode driver is exactly at its target value. The mirror channel CH2 is coupled to the replication channel CH3 via the gate of the P-type MOSFET MP1, which is the node that generates the reference voltage Vrefp_pre. Similarly, based on the reference current IDACpre (which has a target value expected to flow through the pre-voltage mode driver), the reference voltage Vrefp_pre supplied to transistor MP1 in the pre-voltage mode driver is exactly at its target value.

[0074] Similarly, the current digital-to-analog converter 122_2 and the current mirror 124_2 of the post-emphasis controller CP2 can work together to generate reference voltages Vrefp_post and Vrefn_post for the post-voltage mode driver. More specifically, the current digital-to-analog converter 122_2 can generate a reference current IDACpost, the value of which can be controlled by receiving a post-emphasis data Dpost. The current digital-to-analog converter 122_2 can also have, for example,... Figure 6 The circuit structure shown is used to generate the required reference current IDACpost. The current mirror 124_2 can also have the same structure as the current mirror 124_1. By mirroring the reference current IDACpost, the current mirror 124_2 can generate reference voltages Vrefp_post and Vrefn_post.

[0075] The reference voltages Vrefp_pre, Vrefn_pre, Vrefp_post, and Vrefn_post generated by the feedforward equalizer controller 120 are then provided to the impedance control loop 130, enabling the impedance control loop 130 to perform impedance matching and generate reference voltages Vrefp_main and Vrefn_main for the main voltage mode driver. In some embodiments, the impedance control loop 130 can determine the values ​​of the reference voltages Vrefp_main and Vrefn_main based on the values ​​of the reference voltages Vrefp_pre, Vrefn_pre, Vrefp_post, and Vrefn_post. As described above, the feedforward equalizer controller 120 can determine the reference voltages Vrefp_pre, Vrefn_pre, Vrefp_post, and Vrefn_post for the pre-voltage mode driver and the post-voltage mode driver, thereby determining the current flowing through the pre-voltage mode driver and the post-voltage mode driver. From the viewpoint of impedance matching current, the impedance control loop 130 can control the current flowing through the main voltage mode driver so that the total current of the output circuit reaches a level corresponding to the characteristic impedance of 50Ω. For example, if the power supply voltage VCC equals 1V, the total current will be 5mA. The impedance control loop 130 can then generate the reference voltages Vrefp_main and Vrefn_main to be output to the main voltage mode driver, thus achieving the required total current.

[0076] In detail, the impedance control circuit 130 includes a replication path of an N-type metal-oxide-semiconductor (hereinafter referred to as the N-type replication path) and a replication path of a P-type metal-oxide-semiconductor (hereinafter referred to as the P-type replication path), wherein, Figure 5 The structure of an N-type replication path is shown. For example... Figure 5As shown, the N-type replication path includes an operational amplifier 132, an external resistor Rextn, and multiple N-type metal-oxide-semiconductor (MOS) replication drivers DRVn (hereinafter referred to as N-type replication drivers). The N-type replication drivers DRVn can be used to simulate the N-type MOS path of the voltage-mode driver included in the output circuit. More specifically, each N-type replication driver DRVn can be a replica of the N-type MOS path of a voltage-mode driver, which includes two N-type MOS transistors MN1 and MN2 and a resistor R2. Furthermore, since the output circuit includes three main voltage-mode drivers, one pre-voltage-mode driver, and one post-voltage-mode driver, the N-type replication path can include three N-type replication drivers DRVn to simulate the main voltage-mode drivers, one N-type replication driver DRVn to simulate the pre-voltage-mode drivers, and one N-type replication driver DRVn to simulate the post-voltage-mode drivers. The N-type replica driver DRVn used to simulate the pre-voltage mode driver and the post-voltage mode driver can receive and obtain reference voltages Vrefn_pre and Vrefn_post from the feedforward equalizer controller 120, respectively. The reference voltage Vrefn_main used to generate the required output current can be obtained in the N-type replica driver DRVn corresponding to the master voltage mode driver through an appropriate replication structure in the N-type replication path; that is, the reference voltage Vrefn_main is obtained from the gate terminal of transistor MN1 in these N-type replica drivers DRVn.

[0077] On the N-type replication path, in addition to configuring the same number of N-type replication drivers DRVn as the voltage-mode drivers, these N-type replication drivers DRVn, external resistors Rextn, and operational amplifier 132 can be designed appropriately to simulate the environment of the output circuit under N-type MOSFET path conduction. Specifically, the transistor MN2 in each N-type replication driver DRVn can receive the supply voltage VCC to ensure the N-type MOSFET path conduction. The value of the external resistor Rextn and the input voltage of the operational amplifier 132 should be well designed to achieve the desired output impedance of 50Ω. In an exemplary embodiment, the operational amplifier 132 can receive a voltage of 0.25VCC, and the external resistor Rextn is equal to 150Ω, thereby achieving an output impedance of 50Ω. The voltage of 0.25VCC can be easily obtained by setting several voltage divider resistors R between the power supply terminal and the ground terminal, such as... Figure 5 As shown.

[0078] The operating principle of the N-type replication path is explained below. One input of operational amplifier 132 receives a voltage of 0.25VCC. Due to the virtual short-circuit characteristic of operational amplifier 132, its other input (node ​​Vy) also reaches 0.25VCC. A current path is thus formed on the N-type replication path. The current from the power supply can flow to node Vy through the external resistor Rextn, and then through multiple parallel N-type replication drivers DRVn to reach ground. The power supply voltage is VCC, and the voltage at node Vy is equal to 0.25VCC. Under this voltage relationship, since the external resistor Rextn is set to 150Ω, the impedance between node Vy and ground is 50Ω, meaning the total impedance of the parallel N-type replication drivers DRVn is equal to 50Ω.

[0079] From a current perspective, in the current path formed by the N-type replication path, the current equals the voltage across the external resistor Rextn divided by its resistance value, i.e., (VCC - 0.25VCC) / Rextn. If the power supply voltage VCC is 1V and the external resistor Rextn is 150Ω, then the current is 5mA, which satisfies the requirement. Figure 4 The impedance matching requirements are shown.

[0080] Therefore, impedance matching of the N-type metal-oxide-semiconductor path can be achieved with circuit balance on the N-type replica path of impedance control loop 130. The input voltage and external resistor Rextn of operational amplifier 132 can be preset to suitable values ​​to achieve matched output impedance and current. The reference voltages Vrefn_pre and Vrefn_post of the N-type replica driver DRVn corresponding to the pre-voltage mode driver and the post-voltage mode driver are known values ​​obtained through feedforward equalizer controller 120. In this way, the reference voltage Vrefn_main for the main voltage mode driver can be obtained in the N-type replica driver DRVn corresponding to the main voltage mode driver.

[0081] Figure 7 A detailed embodiment of the control circuit 110 of this invention is also shown, illustrating an implementation of the P-type replication path in the impedance control loop 130. For example... Figure 7As shown, the P-type replication path includes an operational amplifier 134, an external resistor Rextp, and multiple P-type MOSFET replication drivers DRVp (hereinafter referred to as P-type replication drivers). The P-type replication drivers DRVp can be used to simulate the P-type MOSFET path of the voltage-mode driver included in the output circuit. More specifically, each P-type replication driver DRVp can be a replica of a voltage-mode driver's P-type MOSFET path, which includes two P-type MOSFETs MP1 and MP2 and a resistor R1. Similarly, since the output circuit includes three main voltage-mode drivers, one pre-voltage-mode driver, and one post-voltage-mode driver, the P-type replication path can include three P-type replication drivers DRVp to simulate the main voltage-mode drivers, one P-type replication driver DRVp to simulate the pre-voltage-mode drivers, and one P-type replication driver DRVp to simulate the post-voltage-mode drivers. The P-type replica driver DRVp used to simulate the pre-voltage mode driver and the post-voltage mode driver can receive and obtain reference voltages Vrefp_pre and Vrefp_post from the feedforward equalizer controller 120, respectively. The reference voltage Vrefp_main used to generate the required output current can be obtained in the P-type replica driver DRVp corresponding to the main voltage mode driver through an appropriate replication structure in the P-type replication path; that is, the reference voltage Vrefp_main is obtained from the gate terminal of transistor MP1 in these P-type replica drivers DRVp.

[0082] On the P-type replication path, in addition to configuring the same number of P-type replication drivers DRVp as the voltage-mode drivers, these P-type replication drivers DRVp, external resistors Rextp, and operational amplifier 134 can be designed appropriately to simulate the environment of the output circuit under P-type MOSFET path conduction. Specifically, the transistor MP2 in each P-type replication driver DRVp can receive ground voltage GND to ensure P-type MOSFET path conduction. The value of the external resistor Rextp and the input voltage of the operational amplifier 134 should be well designed to achieve the desired output impedance of 50Ω. In an exemplary embodiment, the operational amplifier 134 can receive a voltage of 0.75VCC, and the external resistor Rextp is equal to 150Ω, thereby achieving an output impedance of 50Ω. The voltage of 0.75VCC can also be easily obtained by using a voltage divider resistor R placed between the power supply terminal and the ground terminal, such as... Figure 7 As shown.

[0083] The operating principle of the P-type replication path is explained below. One input of operational amplifier 134 receives a voltage of 0.75VCC. Due to the virtual short-circuit characteristic of operational amplifier 134, its other input (node ​​Vx) also reaches 0.75VCC. A current path is thus formed on the P-type replication path. Current from the power supply flows to node Vx through multiple parallel P-type replication drivers DRVp, and then reaches ground through the external resistor Rextp. The power supply voltage is VCC, and the voltage at node Vx is equal to 0.75VCC. Under these voltage relationships, since the external resistor Rextp is set to 150Ω, the impedance between the power supply and node Vx is 50Ω, meaning the total impedance of the parallel P-type replication drivers DRVp is 50Ω.

[0084] From a current perspective, in the current path formed by the P-type replication path, the current equals the voltage across the external resistor Rextp divided by its resistance value, i.e., 0.75VCC / Rextp. If the power supply voltage VCC is 1V and the external resistor Rextp is 150Ω, then the current is 5mA, which satisfies the requirement. Figure 4 The impedance matching requirements are shown.

[0085] Therefore, impedance matching of the P-type metal-oxide-semiconductor path can be achieved with circuit balance on the P-type replica path of impedance control loop 130. The input voltage and external resistor Rextp of operational amplifier 134 can be preset to suitable values ​​to achieve matched output impedance and current. The reference voltages Vrefp_pre and Vrefp_post of the P-type replica driver DRVp corresponding to the pre-voltage mode driver and the post-voltage mode driver are known values ​​obtained through feedforward equalizer controller 120. In this way, the reference voltage Vrefp_main for the main voltage mode driver can be obtained in the P-type replica driver DRVp corresponding to the main voltage mode driver.

[0086] It is worth noting that the values ​​of the external resistors Rextn or Rextp included in the impedance control loop 130 are merely examples. As long as the replication path achieves the desired output impedance of 50Ω, the external resistors Rextn or Rextp can be designed with any suitable value. For example, in another embodiment, the input voltage received by operational amplifiers 132 or 134 is equal to 0.5VCC; in this case, the external resistors Rextn or Rextp can be set to 50Ω.

[0087] Figure 5 and Figure 7An exemplary embodiment of the current generator 150 is also shown, which includes a selection device 152, an operational amplifier 154, and a reference resistor Rref. The current generator 150 can be used to generate a base current IB, which is required to have high accuracy. Through the structure of the current generator 150, the base current IB is equal to the input voltage divided by the reference resistor Rref. In one embodiment, the reference resistor Rref can be an external resistor with an accurate resistance value.

[0088] The input voltage of the current generator 150 can be selected from a bandgap voltage VBG or a voltage divider (e.g., via selection device 152). The bandgap voltage VBG is a constant voltage unaffected by process, voltage, and temperature (PVT) variations. Therefore, by receiving the bandgap voltage VBG, the base current IB generated by the current generator 150 has an accurate value, unaffected by environmental changes. The voltage divider can be generated using the power supply voltage VCC in conjunction with a voltage divider resistor R. More specifically, the voltage divider is equal to the power supply voltage VCC divided by a specific ratio, which is determined by the division of the voltage divider resistor R, such as... Figure 5 and Figure 7 As shown. For example, current generator 150 can receive a voltage of 0.25VCC, and then use the voltage of 0.25VCC and a reference resistor Rref to generate a base current IB. By receiving a voltage divider, the base current IB will vary with the supply voltage VCC. That is, the base current IB and the supply voltage VCC change to the same extent. This synchronous change ensures that the control circuit can generate the current required for impedance matching regardless of how the supply voltage VCC changes.

[0089] The control circuit structure for a feedforward equalizer proposed in this invention achieves multiple benefits. In one embodiment, the control circuit continuously performs equalization and correction. Continuous correction ensures that the feedforward equalizer is constantly protected from interference from process, voltage, and temperature variations. Consequently, the pre-emphasis / de-emphasis intensity of the feedforward equalizer controller is less affected by these variations, allowing for a fixed number of voltage-mode drivers (i.e., slices) under different environmental conditions. Furthermore, because the feedforward equalizer controller of this invention uses a current-to-digital converter and a current mirror to replace the large-area resistor array and high-power operational amplifiers found in the prior art, both circuit area and power consumption performance are improved.

[0090] It is worth noting that the purpose of this invention is to provide a control circuit for a feedforward equalizer that can be used in a voltage-mode transmitter. Those skilled in the art will be able to modify or vary this circuit, and it is not limited thereto. For example, the control circuit of this invention can employ any signal modulation technique, including non-return-to-zero (NRZ) and fourth-level pulse amplitude modulation (PAM4), but is not limited thereto. In the above embodiments, the structure of the control circuit can be applied to non-return-to-zero. In another embodiment, more current digital-to-analog converters and more current mirrors with the same structure can also be used to implement feedforward equalizer control in a fourth-level pulse amplitude modulation signal system.

[0091] besides, Figures 5-7 The illustrated control circuit implementation is merely an exemplary embodiment of the invention. For example, in the feedforward equalizer controller 120, the current digital-to-analog converter 122 is configured to generate a controllable current based on pre-emphasis data or post-emphasis data. In another embodiment, the current digital-to-analog converter 122 can be replaced by a variable current source, which can be used to generate a variable and controllable output current. It should also be noted that the external resistors Rextn / Rextp for the impedance control loop 130 and / or the reference resistor Rref for the current generator 150 are preferably off-chip resistors, which typically have accurate resistance values, thus enabling accurate correction results for pre-emphasis / deemphasis and impedance matching. In another embodiment, if an on-chip resistor (or internal resistor) with sufficient accuracy or precision is available, this on-chip resistor can be used to replace the off-chip resistor, thereby reducing circuit cost. It should also be noted that the structure of each voltage-mode driver is merely exemplary. In another embodiment, the voltage-mode driver may also include more or fewer transistors and / or more or fewer resistors, and / or these circuit components may be connected in other ways. In this case, the replication channel and replication path implemented in the control circuit should be modified accordingly.

[0092] In summary, this invention proposes a novel control circuit for use in the feedforward equalizer of a voltage-mode transmitter in a high-speed transmission system. The output circuit of the voltage-mode transmitter may include multiple voltage-mode drivers, including one or more pre-voltage-mode drivers, one or more post-voltage-mode drivers, and one or more main voltage-mode drivers. The main voltage-mode drivers are the primary driving units of the transmitter. The pre-voltage-mode drivers and post-voltage-mode drivers are configured to perform pre-emphasis or de-emphasis of the feedforward equalizer. The control circuit also provides feedforward equalizer coefficient control and impedance matching functions. In some embodiments, the control circuit consists of a feedforward equalizer controller and an impedance control loop. The feedforward equalizer controller includes a current-to-analog converter and a current mirror, which applies a reference current to the replication channel to determine the reference current for the pre-voltage-mode drivers and post-voltage-mode drivers, thereby generating reference voltages for the pre-voltage-mode drivers and post-voltage-mode drivers. Based on the reference voltages used for the pre-voltage mode driver and the post-voltage mode driver, the impedance control loop can simulate the N-type and P-type MOSFET paths of the output circuit to achieve a total current corresponding to the characteristic impedance of the transmission line, thereby generating a reference voltage for the main voltage mode driver. All of these reference voltages can be provided to the voltage mode driver to achieve pre-emphasis / de-emphasis effects while simultaneously achieving impedance matching.

[0093] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A control circuit for a feedforward equalizer, characterized in that, The feedforward equalizer has multiple voltage-mode drivers that are coupled to a common output. The control circuit includes: A feedforward equalizer controller for receiving a base current from a current generator, the feedforward equalizer controller comprising: A current-to-digital converter is used to generate a reference current based on the base current; and A current mirror, coupled to the current-to-analog converter, is used to mirror the reference current to generate at least one first reference voltage, and output the at least one first reference voltage to at least one of the plurality of voltage-mode drivers; and An impedance control loop, coupled to the feedforward equalizer controller, is used to generate a second reference voltage based on the at least one first reference voltage, and output the second reference voltage to at least one of the plurality of voltage mode drivers.

2. The control circuit as described in claim 1, characterized in that, The current generator uses a bandgap voltage or a power supply voltage combined with a voltage divider resistor to generate the base current.

3. The control circuit as described in claim 1, characterized in that, The current mirror includes: One copy channel; An input channel coupled to the replicated channel via a first node having one of the at least one first reference voltage; and A mirror channel is coupled to the replicated channel via a second node having another of the at least one first reference voltage.

4. The control circuit as described in claim 3, characterized in that, The replicated channel is a copy of one of the at least one first voltage mode driver.

5. The control circuit as described in claim 1, characterized in that, The current digital-to-analog converter receives control data that is used to determine the value of the reference current.

6. The control circuit as described in claim 1, characterized in that, The plurality of voltage-mode drivers includes a pre-voltage-mode driver, a post-voltage-mode driver, and a main voltage-mode driver.

7. The control circuit as described in claim 6, characterized in that, The at least one first voltage mode driver includes the pre-voltage mode driver and the post-voltage mode driver, and the at least one second voltage mode driver includes the main voltage mode driver.

8. The control circuit as described in claim 1, characterized in that, The feedforward equalizer controller is used to determine the at least one first reference voltage for pre-emphasis or de-emphasis of the feedforward equalizer.

9. The control circuit as described in claim 1, characterized in that, The impedance control loop determines the at least one second reference voltage based on the at least one first reference voltage, in order to control the plurality of voltage mode drivers to generate a current corresponding to a characteristic impedance.

10. A feedforward equalizer, characterized in that, include: An output circuit includes multiple voltage-mode drivers that are coupled to a common output terminal. as well as A control circuit, coupled to the output circuit, the control circuit comprising: A feedforward equalizer controller for receiving a base current from a current generator, the feedforward equalizer controller comprising: A current-to-digital converter is used to generate a reference current based on the base current; and A current mirror, coupled to the current-to-analog converter, is used to mirror the reference current to generate at least one first reference voltage, and output the at least one first reference voltage to at least one of the plurality of voltage-mode drivers; and An impedance control loop, coupled to the feedforward equalizer controller, is used to generate a second reference voltage based on the at least one first reference voltage, and output the second reference voltage to at least one of the plurality of voltage mode drivers.

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