Inverse Ferroelectric Capacitor Memory Based on Lateral Window Readout and Its Fabrication Method

Abstract

A method for fabricating an inverse ferroelectric capacitor memory based on lateral window readout is disclosed. The device includes a substrate, a TiO2 interlayer, a superlattice HZO ferroelectric layer, a top electrode, and a bottom electrode. The substrate includes P-type doped regions and N-type doped regions. The TiO2 interlayer is disposed on the substrate and covers at least one interface between the P-type and N-type doped regions. The superlattice HZO ferroelectric layer is disposed on the TiO2 interlayer. The top electrode is disposed on the superlattice HZO ferroelectric layer, and the bottom electrode is disposed on the substrate and covers the N-type doped region. This invention introduces a TiO2 interlayer-superlattice HZO synergistic structure into the inverse ferroelectric capacitor, increasing the lateral window from less than 1 V to 2.5 V, thereby achieving 3-bit multi-value based on the lateral window readout method. Simultaneously, it retains the high speed and high durability advantages of ferroelectric technology while avoiding the defects of millisecond programming and low reliability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to an inverse ferroelectric capacitor memory based on lateral window reading and its fabrication method. Background Technology

[0002] Memristors with in-memory computing capabilities have become a key technology for achieving in-memory computing because they can perform analog calculations directly through the device's conductance state, significantly reducing redundant data transfer between memory and processor. However, the inherent read current or leakage current of memristors leads to unavoidable static power consumption, severely limiting their energy efficiency and becoming a core obstacle restricting their large-scale integrated application.

[0003] Capacitive memory, based on the charge storage mechanism of capacitors, theoretically has no DC current path when not in read / write state, thus essentially eliminating static power consumption and making it possible to achieve ultra-low power storage and computing. Therefore, it can theoretically serve as an alternative to memristors.

[0004] Among them, existing capacitive memories, primarily ferroelectric capacitive memories that utilize vertical window readouts due to their high switching speed and reliability, are mainly ferroelectric capacitive memories. However, these devices generally suffer from key drawbacks such as low vertical window switching ratio, narrow horizontal storage window, small readout charge, low noise margin, and weak multi-level storage capability, severely limiting their further development and application. Although charge-trapping capacitive memories based on horizontal window readouts can compensate for the aforementioned shortcomings of ferroelectric capacitive memories to some extent, their reliability is extremely low and their programming speed is slow (on the order of milliseconds), making it difficult to meet the application requirements of high-speed, high-density in-memory computing chips. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, the present invention aims to provide an inverse ferroelectric capacitor memory based on horizontal window reading and its preparation method, so as to solve the problems of slow programming speed and low reliability of traditional charge trap memory based on horizontal window reading, as well as the problems of low switching ratio and weak multi-level storage capability of traditional ferroelectric capacitor memory based on vertical window reading.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An inverse ferroelectric capacitor memory based on lateral window readout includes a substrate, a TiO2 interlayer, a superlattice HZO ferroelectric layer, a top electrode, and a bottom electrode; the substrate includes a P-type doped region and an N-type doped region; The TiO2 interlayer is disposed on the substrate and covers at least one interface between the P-type doped region and the N-type doped region; the superlattice HZO ferroelectric layer is disposed on the TiO2 interlayer; The top electrode is disposed on the superlattice HZO ferroelectric layer, and the bottom electrode is disposed on the substrate and covers the N-type doped region.

[0007] In one embodiment, the substrate is a silicon wafer, the P-type doped region is lightly P-type doped, and the N-type doped region is heavily N-type doped.

[0008] In one embodiment, the lightly doped p-type has a doping concentration ranging from 1E14 to 1E15 cm⁻¹. -3 The N-type heavy doping concentration ranges from 1E18 to 1E20 cm⁻¹. -3 .

[0009] In one embodiment, the TiO2 interlayer material is pure TiO2 with a thickness of 0.5 nm to 3 nm. If it is too thin, it will be difficult to deposit and the growth will be discontinuous. If it is too thick, it will be difficult to achieve sufficient ferroelectric layer voltage and the polarization will not be able to reverse normally. The thickness of the superlattice HZO ferroelectric layer is 3 nm to 10 nm. If it is too thin, it will be difficult to achieve poor ferroelectricity. If it is too thick, it will be difficult to achieve uneven polarization.

[0010] In one embodiment, the lateral window is 2.5V @4.5 fF / μm. 2 .

[0011] The present invention also provides a method for fabricating the inverse ferroelectric capacitor memory based on lateral window reading, comprising the following steps: Step 1: Clean the P-type doped substrate to remove surface organic matter and oxide layer; Step 2: On the substrate, the TiO2 interlayer, the superlattice HZO ferroelectric layer and the top electrode are deposited sequentially. Step 3: Etch the top electrode, the superlattice HZO ferroelectric layer, and the TiO2 interlayer; Step 4: Ion implantation is performed below the area of ​​the substrate not covered after etching to achieve N-type doping and obtain the N-type doped region of the substrate. Step 5: Deposit the bottom electrode on the N-type doped region.

[0012] In one embodiment, step 2 involves growing the TiO2 interlayer on the substrate using atomic layer deposition; growing the superlattice HZO ferroelectric layer on the TiO2 interlayer using atomic layer deposition; and depositing the top electrode on the superlattice HZO ferroelectric layer using magnetron sputtering.

[0013] In one embodiment, the TiO2 interlayer is grown using atomic layer deposition, as follows: Set the chamber temperature to 250 ℃~300 ℃, turn on the precursor TiCl4 as the titanium source and H2O as the oxygen source in sequence, and introduce N2 to purge the chamber to remove unreacted precursors and reaction byproducts. The superlattice HZO ferroelectric layer is grown using atomic layer deposition, as follows: The cavity temperature is set to 250℃~300℃. The precursor TEMAHf is introduced as the Hf source, TDMAZr as the Zr source, and H2O as the oxygen source. The cavity is then purged with N2. The superlattice HZO ferroelectric layer is grown by repeating N HfO2 sub-cycles and N ZrO2 sub-cycles multiple times.

[0014] In one embodiment, step 4, ion implantation is performed at room temperature with a doping dose of 1E13 cm⁻¹. -2 ~1E15cm -2 The injection energy was 20 keV ~ 30 keV, and the injection tilt angle remained unchanged at 7°.

[0015] In one embodiment, after step 5 is completed, rapid thermal annealing is performed in an inert atmosphere, wherein the rapid thermal annealing is performed in an N2 atmosphere, and the heating rate is set to ≥ 50 °C s. - ¹, peak temperature 500 ~ 600 °C, peak duration 200 ~ 300 s, followed by a decrease of ≥ 30 °C s - ¹ Cooled to room temperature at a rate of .

[0016] Compared with the prior art, the beneficial effects of the present invention are: Compared to the limitations of existing longitudinal read ferroelectric capacitors, such as narrow window size, low switching ratio, weak multi-stage capability, and slow programming and poor reliability of lateral charge-trapping memories, this invention introduces a TiO2 sandwich-superlattice HZO synergistic structure into the inverted ferroelectric capacitor, increasing the lateral window size from less than 1 V to 2.5 V. This allows for 3-bit multi-value processing based on the reading method of the lateral window. At the same time, it retains the advantages of high speed and high durability of ferroelectric capacitors, avoiding the defects of millisecond programming and low reliability. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the inverse ferroelectric capacitor type memory based on horizontal window reading of the present invention.

[0018] Figure 2 This is a PV test diagram of the inverse ferroelectric capacitor memory based on horizontal window reading according to the present invention.

[0019] Figure 3 This is a CV test diagram of the inverse ferroelectric capacitor memory based on horizontal window reading according to the present invention.

[0020] Figure 4 This is a schematic diagram of the reading method of the inverse ferroelectric capacitor type memory based on horizontal window reading according to the present invention.

[0021] Figure 5 This is a schematic diagram illustrating the weight definition of the inverse ferroelectric capacitor type memory based on horizontal window reading according to the present invention.

[0022] Figure 6 This is a flowchart illustrating the fabrication process of the inverse ferroelectric capacitor memory based on horizontal window reading according to the present invention. Detailed Implementation

[0023] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings and examples.

[0024] Inverse ferroelectric capacitor (IFC) memory relies on the offset of the ferroelectric polarization on the CV curve to read the vertical window at 0 V to obtain high and low capacitance states. However, this mode is limited by the small vertical read charge, low noise margin due to the low on / off ratio, and weak multi-stage capability, making it difficult to meet the requirements of high-density, high-precision in-memory computing. In contrast, lateral window readout, by scanning the inversion-depletion transition of the semiconductor channel with the gate voltage, can release more charge and significantly improve signal strength and noise immunity; however, the narrow lateral window of traditional ferroelectric capacitors (~1 V) limits the application of this readout strategy. To widen the lateral window, the industry has turned to charge-trapping memory with a wide storage window, but this comes at the cost of millisecond-level programming speed and only 1E3 cycles of endurance, becoming the core bottleneck of high-speed, high-reliability CIM.

[0025] To address this, the present invention provides an inverse ferroelectric capacitive memory based on lateral window readout, by innovatively introducing a superlattice ferroelectric layer structure with TiO2 interlayers into the inverse ferroelectric capacitive memory. This design enables the fabricated device to maintain the high speed and high reliability advantages of inverse ferroelectric capacitive memory while achieving an innovatively high lateral window, thus providing a new technical path and device foundation for constructing high-precision, high-density, and ultra-low-power in-memory computing chips.

[0026] like Figure 1 As shown, the inverse ferroelectric capacitor memory based on lateral window reading of the present invention mainly includes a substrate 100, a TiO2 interlayer 101, a superlattice HZO ferroelectric layer 102, a top electrode 103, and a bottom electrode 104, etc., wherein the substrate 100 includes a P-type doped region 1001 and an N-type doped region 1002, which have an interface and the interface extends to one surface of the substrate 100. In the present invention, the substrate 100 is a silicon wafer.

[0027] Compared with the prior art, the present invention introduces a TiO2 interlayer 101, which is specifically disposed on a substrate 100 and covers at least one interface between the P-type doped region 1001 and the N-type doped region 1002. Obviously, it is disposed on the surface of the substrate 100 where the interface extends.

[0028] A superlattice HZO ferroelectric layer 102 is disposed on a TiO2 interlayer 101, and a top electrode 103 is disposed on the superlattice HZO ferroelectric layer 102. A bottom electrode 104 is directly disposed on the substrate 100 and covers the N-type doped region 1002. In this invention, the P-type doped region 1001 is preferably lightly doped with a doping concentration ranging from 1E14 to 1E15 cm⁻¹. -3 The N-type doped region 1002 is preferably heavily N-type doped, with a doping concentration ranging from 1E18 to 1E20 cm⁻¹. -3 .

[0029] Memory devices utilize the inversion and depletion states of the semiconductor channel to output high and low capacitances, and rely on ferroelectric polarization to shift the CV curve. Simultaneously, band-to-band tunneling caused by heavily doped depletion regions provides charge carriers, enabling high-speed write operations. Lateral window reads release more charge by scanning the inversion-depletion transition of the semiconductor channel with the gate voltage. Therefore, to improve the multi-level storage capability of these devices, a wider memory window (MW) is required; according to the definition, MW ≤ 2E. c T FE E c For the coercive electric field of ferroelectric materials, T FE Let be the thickness of the ferroelectric material. When 2E c T FE When there is no limit on the maximum value of MW, MW=P eff / C FE C FE P represents the ferroelectric multilayer capacitance. eff This represents the effective polarization after compensation by channel charge injection, with a compensation ratio α = P. eff / P r Less than 10%. Therefore, there are two ways to increase MW: one is to increase the remanent polarization intensity P of the ferroelectric layer. r Secondly, it reduces the charge trapping effect of the channel, thereby improving the compensation ratio α. This invention innovatively proposes introducing a TiO2 interlayer 101 in an inverted ferroelectric capacitor memory. Firstly, because the ferroelectric design of the superlattice HZO ferroelectric layer 102 can obtain more t phases than conventional HZO ferroelectric layers, it transforms into the ferroelectric o phase during annealing, achieving a larger P phase. r Secondly, the introduction of the TiO2 interlayer 101 can reduce the depolarization field and interface defects, thereby reducing charge trapping and further increasing P.r , making P eff The increased size allows the fabricated device to achieve a significantly higher lateral window.

[0030] Figure 2 and Figure 3 The results of simultaneous polarization-voltage (P–V) and capacitance-voltage (C–V) tests for the device are presented. PV shows the residual polarization 2P of the device under 10 kHz, 6 V programming conditions. r Reaching 71 μC / cm 2 Compared to traditional HZO ferroelectric (≈30 μC / cm) 2 This achieved a more than 2-fold improvement, directly verifying the significant enhancement effect of the superlattice stacked structure with the TiO2 interlayer 101 on polarization intensity. CV shows that as the programming voltage increases, the residual polarization P... r As the voltage increases, the lateral storage window widens accordingly; when the voltage increases to 4V, the MW reaches 2.5V, which is the largest lateral window publicly reported for inverse ferroelectric capacitors to date.

[0031] Figure 4 and Figure 5 This demonstrates a complete multi-value readout scheme of "pre-polarization - step programming - charge integration": first with A 4V, 100μs pulse uniformly flips the ferroelectric polarization to the upward direction, and then scans the C-V curve as State 0. Subsequently, programming pulses start at 3.5V, 1μs, with the amplitude increasing by 0.2V in each step, causing the polarization components to gradually flip downward, and the C-V curve shifts to the left accordingly. A total of 8 reproducible C-V curves are obtained, meeting the 3-bit storage requirement. The weights of each state are directly quantized by the charge Q=∫C dV of the curve in a fixed interval, providing a reliable electrical basis for high-precision multiply-accumulate operations.

[0032] In summary, the inverse ferroelectric capacitor memory of this invention employs a TiO2 sandwich-superlattice ferroelectric synergistic design, which widens the lateral window from <1 V to 2.5 V@4.5 fF / μm. 2 While retaining the high speed and high endurance (>10) of ferroelectric capacitor memory 6 With its advantages, it overcomes the shortcomings of low vertical window read-to-switch ratio in ferroelectric memory and avoids the drawbacks of millisecond-level programming and low reliability in charge-trapping memory. This enables a 3-bit multi-value, low-power, fast programming speed and CMOS-compatible capacitive memory, providing a general technical path for CMOS integration of low-power, high-density and high-precision capacitive memory chips.

[0033] Figure 6 The overall fabrication process of the inverse ferroelectric capacitor memory with a wide horizontal window of the present invention is shown in a continuous cross-sectional view: 1) As Figure 6 As shown in (a), 1E15 cm is selected. -3 A lightly p-type doped silicon wafer was used as substrate 100. The wafer was ultrasonically cleaned for 5 minutes by sequentially immersing it in acetone and isopropanol solutions to remove organic matter from its surface. Substrate 100 was then inorganically cleaned by immersing it in a 1:20 BOE solution to remove the naturally formed silicon oxide film on the wafer surface; 2) such as Figure 6 As shown in (b), a TiO2 interlayer 101 is grown on the substrate 100 using atomic layer deposition. The thickness of the TiO2 interlayer 101 is generally in the range of 0.5 nm to 3 nm, and preferably about 1 nm in the embodiment. Specifically, the chamber temperature is set to 250°C, and the precursor TiCl4 is turned on as the titanium source, H2O is turned on as the oxygen source, and N2 is introduced to purge the chamber to remove unreacted precursors and reaction byproducts; 3) as Figure 6 As shown in (c), a superlattice HZO ferroelectric layer 102 is grown on the TiO2 interlayer 101 by atomic layer deposition. The thickness of the superlattice HZO ferroelectric layer 102 is generally in the range of 3 nm to 10 nm, and is preferably around 10 nm in the embodiment. Specifically, the cavity temperature is set to 300°C, and the precursor TEMAHf as Hf source, TDMAZr as Zr source, and H2O as oxygen source are introduced sequentially. The cavity is then purged with N2. The 10 nm superlattice HZO ferroelectric layer 102 is formed by 5 HfO2 sub-cycles and 5 ZrO2 sub-cycles, repeated 10 times; 4) as Figure 6 As shown in (d), a 30nm layer of tungsten metal is deposited on the superlattice HZO ferroelectric layer 102 by magnetron sputtering as the top electrode 103. Specifically, the substrate temperature is kept at room temperature, and sputtering is performed on the substrate using W as the target material under a high-purity argon atmosphere. Subsequently, the top electrode 103 and the superlattice HZO ferroelectric layer 102 below it are patterned using photolithography and dry etching, retaining only the predetermined area on the left and completely removing the rest, thereby defining the geometric contour of the top electrode of the device; 5) as Figure 6 As shown in (e), N-type doping was achieved by implanting P ions under a substrate 100 not covered by the top electrode at room temperature, with a doping dose of 1E15 cm⁻¹. -2 The implantation energy was 20 keV, the implantation tilt angle was 7°, and an N-type doped region 1002 was constructed; 6) as Figure 6As shown in (f), a 30 nm layer of metallic tungsten was deposited again on the exposed substrate 101 on the right side as the bottom electrode 104 using a sputtering process. Finally, rapid thermal annealing was performed in an inert atmosphere. This annealing induced crystallization of the ferroelectric layer and, since most of the ions were in interstitial positions after high-energy ion implantation and had low electrical activity, the rapid thermal annealing caused impurity atoms to move into substitution sites, increasing electrical activity and significantly reducing contact resistance. This completed the fabrication of an inverse ferroelectric capacitor with a wide lateral window.

[0034] In more embodiments, the cavity temperature range during atomic layer deposition growth in step 2) is 250 °C to 300 °C. In step 3), the cavity temperature range during atomic layer deposition growth is 250 °C to 300 °C, and the number of HfO2 sub-cycles and ZrO2 sub-cycles during the growth of the superlattice HZO ferroelectric layer 102 can be set as needed. In step 4), the doping dose range for achieving N-type heavy doping is 1E13 cm⁻¹. -2 ~1E15 cm -2 The injection energy range is 20 keV ~ 30 keV. The final rapid thermal annealing can be performed in a N2 atmosphere with a heating rate ≥ 50 °C s. - ¹, peak temperature 500 ~ 600 °C, peak duration 200 ~ 300 s, followed by a decrease of ≥ 30 °C s - ¹ Cooled to room temperature at a rate of .

Claims

1. An inverse ferroelectric capacitor memory based on horizontal window reading, characterized in that, It includes a substrate (100), a TiO2 interlayer (101), a superlattice HZO ferroelectric layer (102), a top electrode (103), and a bottom electrode (104); the substrate (100) includes a P-type doped region (1001) and an N-type doped region (1002). The TiO2 interlayer (101) is disposed on the substrate (100) and covers at least one interface between the P-type doped region (1001) and the N-type doped region (1002); the superlattice HZO ferroelectric layer (102) is disposed on the TiO2 interlayer (101); The top electrode (103) is disposed on the superlattice HZO ferroelectric layer (102), and the bottom electrode (104) is disposed on the substrate (100) and covers the N-type doped region (1002).

2. The inverse ferroelectric capacitor memory based on horizontal window reading according to claim 1, characterized in that, The substrate (100) is a silicon wafer, the P-type doped region (1001) is lightly doped P-type, and the N-type doped region (1002) is heavily doped N-type.

3. The inverse ferroelectric capacitor memory based on horizontal window reading according to claim 2, characterized in that, The p-type light doping concentration ranges from 1E14 to 1E15 cm⁻¹. -3 The N-type heavy doping concentration ranges from 1E18 to 1E20 cm⁻¹. -3 .

4. The inverse ferroelectric capacitor memory based on horizontal window reading according to claim 1, characterized in that, The thickness of the TiO2 interlayer (101) is 0.5 nm to 3 nm; the thickness of the superlattice HZO ferroelectric layer (102) is 3 nm to 10 nm.

5. The inverse ferroelectric capacitor memory based on horizontal window reading according to claim 1, characterized in that, The lateral window is 2.5V @4.5 fF / μm. 2 .

6. A method for preparing the inverse ferroelectric capacitor type memory based on lateral window reading as described in claim 1, characterized in that, Includes the following steps: Step 1: Clean the P-type doped substrate (100) to remove surface organic matter and oxide layer; Step 2: On the substrate (100), the TiO2 interlayer (101), the superlattice HZO ferroelectric layer (102) and the top electrode (103) are deposited sequentially. Step 3: Etch the top electrode (103), the superlattice HZO ferroelectric layer (102), and the TiO2 interlayer (101); Step 4: Ion implantation is performed below the area of ​​the substrate (100) that is not covered after etching to achieve N-type doping and obtain the N-type doped region (1002) of the substrate (100). Step 5: Deposit the bottom electrode (104) on the N-type doped region (1002).

7. The method for preparing an inverse ferroelectric capacitor memory based on lateral window reading according to claim 6, characterized in that, In step 2, the TiO2 interlayer (101) is grown on the substrate (100) by atomic layer deposition; the superlattice HZO ferroelectric layer (102) is grown on the TiO2 interlayer (101) by atomic layer deposition; and the top electrode (103) is deposited on the superlattice HZO ferroelectric layer (102) by magnetron sputtering.

8. The method for preparing an inverse ferroelectric capacitor memory based on lateral window reading according to claim 7, characterized in that, In one embodiment, the TiO2 interlayer is grown using atomic layer deposition, as follows: Set the chamber temperature to 250 ℃~300 ℃, turn on the precursor TiCl4 as the titanium source and H2O as the oxygen source in sequence, and introduce N2 to purge the chamber to remove unreacted precursors and reaction byproducts. The superlattice HZO ferroelectric layer is grown using atomic layer deposition, as follows: The cavity temperature is set to 250℃~300℃. The precursor TEMAHf is introduced as the Hf source, TDMAZr as the Zr source, and H2O as the oxygen source. The cavity is then purged with N2. The superlattice HZO ferroelectric layer (102) is grown by repeating N HfO2 sub-cycles and N ZrO2 sub-cycles multiple times.

9. The method for preparing an inverse ferroelectric capacitor memory based on lateral window reading according to claim 6, characterized in that, In step 4, ion implantation is performed at room temperature with a doping dose of 1E13 cm⁻¹. -2 ~1E15 cm -2 The injection energy was 20 keV ~ 30 keV, and the injection tilt angle remained unchanged at 7°.

10. The method for preparing an inverse ferroelectric capacitor memory based on lateral window reading according to claim 6, characterized in that, After step 5 is completed, rapid thermal annealing is performed in an inert atmosphere. This rapid thermal annealing is conducted in a N2 atmosphere with a heating rate ≥ 50 °C s. - ¹, peak temperature 500 ~ 600 °C, peak duration 200 ~ 300 s, followed by a decrease of ≥ 30 °C s - ¹ Cooled to room temperature at a rate of .

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