Active interconnect die and semiconductor package including the active interconnect die

Abstract

A semiconductor package includes: an active interconnect die including a modulator and at least one first metal line; a processor die on the active interconnect die; a first memory die stacked on top of each other on the active interconnect die and spaced apart from the processor die by a first lateral distance; and a second memory die stacked on top of each other on the active interconnect die and spaced apart from the processor die by a second lateral distance greater than the first lateral distance, wherein the at least one first metal line is configured for data communication between the second memory die and the processor die.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0175632, filed on November 29, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to an active interconnect die and a semiconductor package including the active interconnect die. Background Technology

[0003] Modern electronic devices demand high performance and high energy efficiency. To meet these requirements, semiconductor integrated circuit (IC) technology continues to evolve. In particular, the rapid development of high-performance computing devices, artificial intelligence (AI) processors, graphics processing units (GPUs), data centers, and mobile devices necessitates faster processing speeds and greater data processing capabilities.

[0004] This enables multi-die or system-on-a-chip (SoC) technology. This technology allows multiple processors, memories, and various functional blocks to operate within a single package, thus contributing to improved space efficiency and performance. In high-performance systems, maintaining reliability while optimizing data transfer speeds between the processor and multiple memories is crucial, thus requiring new packaging methods and power management solutions.

[0005] The information disclosed in this Background section was already known to or derived by the inventors before or during the implementation of embodiments of this application, or is technical information obtained during the implementation of embodiments. Therefore, this section may contain information that does not constitute prior art already known to the public. Summary of the Invention

[0006] This summary is provided to describe in simplified form the selection of concepts further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help define the scope of the claimed subject matter.

[0007] According to one aspect of this disclosure, a semiconductor package may include: an active interconnect die including a modulator and at least one first metal line; a processor die on the active interconnect die; a first memory die stacked on top of each other on the active interconnect die and spaced apart from the processor die by a first lateral distance; and a second memory die stacked on top of each other on the active interconnect die and spaced apart from the processor die by a second lateral distance greater than the first lateral distance, wherein at least one first metal line is configured for data communication between the second memory die and the processor die.

[0008] The active interconnect die may include at least one second metal line configured for data communication between the first memory die and the processor die, and the at least one first metal line may be thicker than the at least one second metal line.

[0009] The symbol rate of data communication between the second memory die and the processor die can be greater than the symbol rate of data communication between the first memory die and the processor die.

[0010] The SerDes ratio for data communication between the second memory die and the processor die can be less than the SerDes ratio for data communication between the first memory die and the processor die.

[0011] An active interconnect die may include at least one second metal line configured for data communication between a first memory die and a processor die, and the number of at least one first metal line may be different from the number of at least one second metal line.

[0012] The processor die may include multiple pins, and the first number of pins of the processor die that are connected to the second memory die may be greater than the second number of pins of the processor die that are connected to the first memory die.

[0013] The first memory die may be in a first high-bandwidth memory (HBM), and the second memory die may be in a second HBM, or the first memory die and the second memory die may be in the same HBM.

[0014] The modulation type of data communication between the second memory die and the processor die can be controlled based on the loss of the signal transmitted from the second memory die through at least one first metal line.

[0015] The signal gain for data communication between the second memory die and the processor die can be controlled based on the strength of the signal transmitted from the second memory die through at least one first metal line.

[0016] The frequency of the clock signal supplied to at least one of the first and second memory dies via a through-silicon via (TSV) may be lower than the frequency of the clock signal supplied to the modulator.

[0017] According to one aspect of this disclosure, an active interconnect die may include: a serializer configured to convert parallel data received from memory dies stacked on the active interconnect die into serial data based on a SerDes ratio; a modulator configured to modulate the serial data and transmit the modulated serial data to at least one metal line; and a three-dimensional input / output (3DIO) configured to demodulate the modulated serial data received through at least one metal line and transmit the demodulated serial data to a processor die on the active interconnect die.

[0018] At least one of the SerDes ratio or modulation type of serial data can be determined based on the lateral distance between the memory die and the processor die.

[0019] The number of at least one metal line or the thickness of at least one metal line can be determined based on the lateral distance between the memory die and the processor die.

[0020] The processor die can have multiple pins, and the number of pins on the processor die that are connected to 3DIO can be determined based on the lateral distance between the memory die and the processor die.

[0021] The memory die can be in HBM.

[0022] The modulation type of serial data can be controlled based on the loss of the signal received by 3DIO through at least one metal line.

[0023] The signal gain transmitted through at least one metal line can be controlled based on the strength of the signal received by 3DIO through at least one metal line.

[0024] The frequency of the clock signal supplied to the through-silicon via (TSV) of the memory die can be lower than the frequency of the modulator's clock signal.

[0025] According to one aspect of this disclosure, a semiconductor package may include: an interposer; a logic die, on the interposer, the logic die including a modulator; a memory die, stacked on the logic die and connected to the logic die via a through electrode; a processor die, on the interposer; and a redistribution layer (RDL), below the interposer, the RDL including at least one metal line, wherein the modulator and the at least one metal line may be configured for data communication between the memory die and the processor die.

[0026] The modulator can be configured to modulate data received from the memory die, and the modulated data can be transmitted to the processor die by sequentially passing through the interposer, at least one metal line in the RDL, and the interposer. Attached Figure Description

[0027] The above and other aspects, features, and advantages of some embodiments of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 This is a diagram illustrating the arrangement of a processor die and memory stack according to one or more embodiments.

[0029] Figure 2 It is a perspective view of a semiconductor package structure according to one or more embodiments.

[0030] Figure 3 This is a cross-sectional view of a semiconductor package illustrating data movement in a semiconductor package according to one or more embodiments.

[0031] Figure 4 This is a conceptual diagram of a semiconductor package structure according to one or more embodiments.

[0032] Figure 5 This is a diagram illustrating the operation of an active interconnect die included in a semiconductor package according to one or more embodiments.

[0033] Figure 6 This is a graph illustrating the total data rates of short-distance and long-distance memory dies according to one or more embodiments.

[0034] Figure 7 This is a diagram illustrating adaptive control applied to a transceiver (TRX) according to one or more embodiments.

[0035] Figure 8 This is a diagram illustrating an active interconnect die with face-to-face connections according to one or more embodiments.

[0036] Figure 9 This is a diagram illustrating a semiconductor package structure with a redistribution layer (RDL) applied according to one or more embodiments. Detailed Implementation

[0037] Referring now to the embodiments, examples of which are shown in the accompanying drawings, wherein similar reference numerals throughout the drawings denote similar elements. In this respect, the presented embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only with reference to the accompanying drawings to explain various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. Expressions such as “at least one of…” modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the expression “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0038] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings. The embodiments described below are merely exemplary, and various modifications can be made to these embodiments.

[0039] Throughout the accompanying drawings and detailed description, unless otherwise described or specified, the same reference numerals shall be understood to refer to the same elements, features, and structures. The drawings may be drawn not to scale, and for clarity, illustration, and convenience, the relative dimensions, scale, and depiction of elements in the drawings may be enlarged.

[0040] Although terms such as first and second are used to describe various components, components are not limited to these terms. These terms should only be used to distinguish one component from another. For example, the first component can be called the second component, and similarly, the second component can be called the first component.

[0041] It should be noted that if a component is described as "connected", "coupled", or "joined" to another component, a third component can be "connected", "coupled", and "joined" between the first and second components, but the first component can be directly connected, coupled, or joined to the second component.

[0042] It will be understood that when an element or layer is referred to as being "above," "on top of," "below," "under," "connected to," or "coupled to" another element or layer, it may be directly above, above, below, under, or directly connected to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly above," "on top of," "below," "under," "under," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers.

[0043] Unless the context clearly indicates otherwise, the singular form also includes the plural form. It will also be understood that the terms “comprising” and / or “including” as used herein mean the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having meaning consistent with their meaning in the context of the relevant art, and not as having an ideal or overly formal meaning, unless expressly defined herein.

[0045] Unless explicitly described in terms of order, the operations of the method may be performed in the appropriate order. Furthermore, the use of all illustrative terms (e.g., "etc.") is solely for the purpose of describing the technical concept in detail, and the scope is not limited by these illustrative or exemplary terms unless restricted by the claims.

[0046] Figure 1 This is a diagram illustrating the arrangement of a processor die and memory stack according to one or more embodiments.

[0047] refer to Figure 1 The semiconductor package 100 may include one or more processors 110 and multiple memories 120 and 130.

[0048] One or more processors 110 can process data or perform given operations and / or tasks, and may include various processors such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), and a digital signal processor (DSP). This enables efficient execution of high-performance computing tasks, more specifically, machine learning tasks such as artificial intelligence (AI) and deep neural networks (DNNs). The computing system including the semiconductor package 100 can perform a variety of high-performance computing tasks, including machine learning. Machine learning can be used in various application areas, such as data analysis, image processing, and natural language processing, including AI and DNNs.

[0049] Multiple memories 120 and 130 can store data processed by one or more processors 110, and may include, for example, high-bandwidth memory (HBM). Since transferring large amounts of data processed at high speed by one or more processors 110 from multiple memories 120 and 130 to one or more processors 110 can have a significant impact on the performance of the semiconductor package 100, the multiple memories 120 and 130 can be located near one or more processors 110. Due to physical size limitations, only the near memory 120 of the multiple memories 120 and 130 can be located near the edge of the processor, while the far memory 130 can be located further away from the processor than the near memory 120. That is, memory 120 can be closer to processor 110 than memory 130, thus positioning processor 110, memory 120 adjacent to processor 110, and memory 130 adjacent to memory 120.

[0050] Remote memory 130 can be used to connect multiple memories to a single processor to improve performance, but increasing the number of memories may be effective while keeping memory bandwidth and performance constant. In other words, it is important to keep the transfer rate and bandwidth between remote memory 130 and the processor at a predetermined level.

[0051] The method for high-speed data transfer to the processor from both the near memory 120 and the far memory 130 is further described below with reference to the accompanying drawings.

[0052] Figure 2 It is a perspective view of a semiconductor package structure according to one or more embodiments.

[0053] refer to Figure 2 The semiconductor package 200 may include a substrate 210, an active interconnect die 220, a processor die 230, a first memory die 240, and a second memory die 250. The active interconnect die 220 may be disposed on the substrate 210. The first memory die 240, the second memory die 250, and the processor die 230 may be disposed on the active interconnect die 220. Although Figure 2 Two memory die stacks and one processor die are shown, but the embodiment is not limited thereto. The number of memory dies and processor dies disposed on the active interconnect die 220 is not limited thereto.

[0054] The active interconnect die 220 may be a layer providing electrical connections between the processor die 230 and the first memory die 240 and the second memory die 250, and may include active circuitry. The processor die 230 may be spaced apart from the first memory die 240 by a first lateral distance, and the processor die 230 may be spaced apart from the second memory die 250 by a second lateral distance greater than the first lateral distance, such that the distance between the second memory die 250 and the processor die 230 is greater than the distance between the first memory die 240 and the processor die 230. The second memory die 250 may be referred to as "located at a distance" or "far distance" relative to each other and to the processor die 230, while the first memory die 240 may be referred to as "located nearby" or "short distance". Data transmission between the processor die 230 and the remotely located second memory die 250 can be rapidly performed via the active circuitry included in the active interconnect die 220. The active interconnect die 220 can improve the performance of the second memory die 250, while also serving as a logic die and passive interposer included in the 2.5" high-bandwidth memory (HBM) die structure. The active interconnect die 220 can manage and optimize data transfer between the processor die 230 and the first memory die 240 and the second memory die 250. (Reference) Figures 3 to 8 Further description of the active interconnect die 220.

[0055] Processor die 230 plays a central role in processing data transferred from memory dies 240 / 250 and can include various processors such as CPUs, GPUs, and NPUs. Processor die 230 can be designed to efficiently perform high-performance computing tasks and smoothly handle data transfers with memory dies.

[0056] The first memory die 240 and the second memory die 250 may have a structure in which memory dies for storing data are stacked in multiple layers. For example, the first memory die 240 and the second memory die 250 may be implemented as individual HBMs and can provide high data transfer rates and high bandwidth. However, the first memory die 240 and the second memory die 250 are not limited thereto. Each of the first memory die 240 and the second memory die 250 may be implemented not only as an HBM device, but also as a Low Power Double Data Rate (LPDDR) device, a Graphics Double Data Rate (GDDR) device, or a Double Data Rate (DDR) device. The first memory die 240 may be a short-distance memory die disposed at the edge of the processor die 230, and the second memory die 250 may be a long-distance memory die disposed relatively far from the processor die 230. Multiple memory dies may be referred to as a memory stack. For example, the first memory die 240 and the second memory die 250, which respectively include multiple memory dies, may be referred to as memory stack 240 and memory stack 250, respectively.

[0057] Semiconductor package 200 can be a physical structure in which a semiconductor chip is attached to a substrate 210 and connected to an external circuit. Semiconductor package 200 can be referred to as a semiconductor structure or a semiconductor device.

[0058] According to one or more embodiments, the semiconductor package 200 can be advantageously applied to applications requiring high-bandwidth data transmission. For example... Figure 2 As shown, when multiple memory stacks 240 / 250 are connected to a single processor die 230, each memory stack can communicate efficiently with the processor die 230 via an active interconnect die 220. This maximizes system performance and scalability, and in particular, provides significant benefits for parallel data processing and high-performance computing tasks.

[0059] Figure 3 This is a cross-sectional view of a semiconductor package illustrating data movement in a semiconductor package according to one or more embodiments.

[0060] refer to Figure 3 Because the second memory die 350 is positioned further away from the processor die 330 on the active interconnect die 320 than the first memory die 340, electrical losses may occur during signal transmission. To compensate for this, the active interconnect die 320 may include transceivers (TRXs) 341 and 351, as well as active circuitry such as three-dimensional input / output (3DIO) 331. For example, the 3DIO 331 may be in the form of an array comprising multiple 3DIOs. References below... Figure 3The data transfer between processor die 330 and first memory die 340 and second memory die 350 is further described.

[0061] The first memory die 340 and the active interconnect die 320 can be physically connected via a through-electrode 343. The through-electrode 343 can transmit electrical signals by vertically penetrating the interior of the first memory die 340, enabling data transmission from the first memory die 340 to the active interconnect die 320, or efficiently transmitting data from the active interconnect die 320 to the first memory die 340. Using the through-electrode 343, data lines from the first memory die 340 can extend to and connect to the active interconnect die 320. The through-electrode 343 can be a through-silicon via (TSV) penetrating the silicon substrate. The TSV provides a high-speed path for quickly and losslessly transmitting data generated by the first memory die 340 to the active interconnect die 320 while maintaining signal integrity within the package. Multiple data lines connecting the first memory die 340 to the active interconnect die 320 can be formed via the TSV, allowing for rapid parallel data transmission across these multiple data lines. Similarly, the second memory die 350 and the active interconnect die 320 can be physically connected via through electrode 353 to transmit data.

[0062] In the semiconductor package 300 employing the active interconnect die 320, the active interconnect die 320 includes active circuitry, thus eliminating the need for a conventionally implemented PHY circuit. This allows data lines to be directly connected to the TRX 341 and 351 of the active interconnect die 320, thereby simplifying the data transmission path and minimizing signal delay and loss. By directly connecting the data lines provided by the first memory die 340 and the second memory die 350 to the active interconnect die 320, data transmission rates and system performance can be improved.

[0063] The active interconnect die 320 may include a silicon layer 321 and a metal layer 323. The silicon layer 321 may include TRX 341 and 351, as well as active circuitry such as 3DIO 331. The metal layer 323 may include metal lines 325, including a first metal line 326 connecting 3DIO 331 to TRX 341 and the first memory die 340, and a second metal line 327 connecting 3DIO 331 to TRX 351 and the second memory die 350. The metal layer 323 may correspond to a back-to-end (BEOL) region.

[0064] Although described further below, TRX 341 can convert parallel data received from the first memory die 340 into serial data according to the SerDes ratio, and can modulate the serial data, transmitting the modulated serial data to metal line 326. Similarly, TRX 351 can convert parallel data received from the second memory die 350 into serial data according to the SerDes ratio, and can modulate the serial data, transmitting the modulated serial data to metal line 327. Since metal channel losses may vary with transmission distance, the SerDes ratio and / or modulation type applied to TRX 341 and 351 can differ from each other. Furthermore, the thickness and / or number of metal lines 325 connected to TRX 341 and 351 can differ from each other.

[0065] The 3DIO 331, located beneath the processor die 330, can receive modulated serial data transmitted via metal line 325. The 3DIO 331 can demodulate the modulated serial data received via metal line 325 and convert the demodulated serial data into parallel data. The 3DIO 331 can transmit the parallel data to the 3DIO 333 within the processor die 330 via through electrode 335.

[0066] Figure 4 This is a conceptual diagram of a semiconductor package structure according to one or more embodiments.

[0067] refer to Figure 4 Data can be transferred between the processor die 430 and the first memory die 440 and the second memory die 450 via the active interconnect die 420. Through electrodes between the first memory die 440 and the second memory die 450 and their respective TRX441 and 451 can include multiple data lines for transmitting data at relatively low speeds. Since the metal lines connecting each of the TRX441 and 451 to the 3DIO 431 are used as channels, signal attenuation may increase with increasing data transmission distance. To compensate for metal channel losses, adaptive control of the modulation type, SerDes ratio, and gain can be applied to the TRX 441 and 451 based on the loss or strength of the signal received by the 3DIO 431. (Reference) Figure 7 and Figure 8 Further description of adaptive control.

[0068] 3DIO 431 can perform equalization to compensate for metal channel losses. The through electrode between 3DIO 431 and 3DIO 433 in the processor die 430 can transfer data at a relatively high speed.

[0069] Figure 5This is a diagram illustrating the operation of an active interconnect die included in a semiconductor package according to one or more embodiments.

[0070] refer to Figure 5 The various components included in the active interconnect die 520 are shown as examples. Figure 5 The number of memory dies, processor dies, TRX and data lines shown is for illustrative purposes only and is not limited thereto.

[0071] TRX 541, which receives parallel data (e.g., TSV_DQ) from a short-range first memory die 540 via TSV, can convert the parallel data into serial data according to a first SerDes ratio, and after modulating the serial data into non-return-to-zero (NRZ) code, can transmit the modulated data to the metal line. For example, TRX 541 can convert data and transmit data at a frequency higher than TSV IO.

[0072] The TRX 551, which receives parallel data (e.g., TSV_DQ) from a remotely located second memory die 550 via TSV, can convert the parallel data into serial data according to a second SerDes ratio, and after modulating the serial data into Pulse Amplitude Modulation 4 (PAM4), can transmit the modulated data to the metal line. For example, the TRX 551 can convert and transmit data at a frequency higher than TSV IO.

[0073] Because the channel loss differs depending on the distance of the metal lines transmitting data from TRX 541 and 551, the SerDes ratio or modulation type applied to TRX 541 and 551 can be different from each other. For example, the signal frequency can be determined by considering the signal attenuation of the metal line channels in the interconnect connecting the two memory dies 540 and 550 to the processor die 530, where the two memory dies 540 / 550 have different data transmission distances. For example, as a characteristic of the metal line channels, PAM4 with a low Nyquist frequency can be applied to data transmission over the distant second memory die 550, while NRZ can be applied to data transmission over the short distance first memory die 540. For example, the PAM4 modulation type can be selected because significant signal attenuation can occur when the signal frequency increases over long distances greater than or equal to 8000 micrometers.

[0074] Furthermore, the thickness and / or number of metal lines connected to TRX 541 and 551 can differ from each other. Typically, as the thickness of the metal lines increases, the resistance value may decrease, thereby potentially reducing losses during data transmission. Due to these characteristics, metal lines 561 / 562 connected to TRX 551, which requires data transmission over longer distances, can be thicker than metal lines 563 / 564 connected to TRX 541. In other words, the thickness of the metal lines disposed within the layer can increase as it moves from metal layer 523 upwards to silicon layer 521. However, the thickness of the metal lines is not limited to this. Since the thickness only needs to satisfy the condition that the losses occurring in the metal lines need to be below a predetermined level, according to an embodiment, metal lines 563 / 564 connected to TRX 541 for data transmission over short distances can be designed to be as thick as metal lines 561 / 562 connected to TRX 551 to minimize data loss. Reference Figure 6 Further describe the differences between TRX 541 and 551. For example, the thickness of metal wires 561 / 562 / 563 / 564 can refer to the width and / or height of the corresponding metal wire, such as "lateral thickness".

[0075] The 3DIO 531 can demodulate data transmitted from the TRX 541 and 551. The 3DIO 531 can convert the demodulated data into parallel data and can transmit the parallel data to the processor die 530 via TSV as needed. Figure 5 As shown in the example, when data is transmitted from two metal lines to two TSV data lines, the operation of converting demodulated data to parallel data in 3DIO 531 can be omitted. When data is transmitted to more TSV data lines than the number of metal lines, the operation of converting demodulated data to parallel data in 3DIO 531 can be performed.

[0076] The data lines 570 connecting the 3DIO 531 to the TSV of the processor die 530 can be divided into a first line 571 (or a set of first lines) for transmitting data to the first memory die 540 and a second line 572 (or a set of second lines) for transmitting data to the second memory die 550. For semiconductor package architecture design, the ratio of the first line 571 to the second line 572 in the TSV data lines 570 connecting the 3DIO 531 to the processor die 530 can be considered. For example, data loss may occur frequently over the relatively long distance of the second memory die 550, and data movement time may be longer; the TSV data lines can be designed such that the number of second lines 572 is greater than the number of first lines 571. However, the embodiments are not limited to this. Figure 5 In, N C1 It can indicate the number of pins of the processor die 530 that receive data from the first memory die 540, and NC2 It can indicate the number of pins on the processor die 530 that receive data from the second memory die 550.

[0077] It may be necessary to transmit data from multiple memory dies simultaneously to increase the data rate or the amount of data transmitted to the processor die 530, and when the number of pins connected to the processor die 530 is the same, the data rate of each pin can be increased to expand the bandwidth.

[0078] For example, when the amount of data transferred from the second memory die 550 to the TSV IO is A × B Gbps and requires C pins of the processor die 530, each pin of the processor die 530 can transfer (A × B) / C Gbps of data, and the SerDes ratio can be determined as A / C (e.g., when the deserializer operation is not performed in the 3DIO 531).

[0079] Additionally, for example, when the TSV data rate of both the first memory die 540 and the second memory die 550 is D H And the number of TSV IOs is N. H At that time, each pin of the processor die 530 that receives data from the first memory die 540 can transmit D S1 =D H N H / N C1 The data, and each pin of the processor die 530 that receives data from the second memory die 550 can transmit D S2 =D H N H / N C2 The data.

[0080] Figure 6 This is a graph illustrating the total data rates of short-distance and long-distance memory dies according to one or more embodiments.

[0081] refer to Figure 6 The example illustrates serialization and modulation performed by the TRX 610 and deserialization and demodulation performed by the 3DIO 620 to describe the total data rate for short-distance and long-distance memory dies. Figure 6 In this context, short-range HBM (SR-HBM) can represent short-range memory dies, and long-range HBM (LR-HBM) can represent long-range memory dies. As an example... Figure 6 The specific values ​​shown are for illustrative purposes only, and the values ​​applied to actual semiconductor packaging are not limited to these.

[0082] The total data rate of short-range memory dies and long-range memory dies can be expressed as the following equation (1).

[0083] Total data rate = (1)

[0084] In equation (1), D HS S can represent the data rate of a short-range memory die's TSV. RS N can represent the SerDes ratio applied to TRX connected to short-distance memory dies. WS This can represent the number of metal wires used to transmit data in a short-distance memory die, and S PAMS This can represent the modulation type applied to TRX connected to short-range memory dies; in other words, the symbol rate. D HL S can represent the data rate (TSV) of a long-distance memory die. RL N can represent the SerDes ratio applied to TRX connected to long-distance memory dies. WL This can represent the number of metal wires used to transmit data over long distances in a memory die, and S PAML This can represent the modulation type applied to TRX connected to long-distance memory dies; in other words, the symbol rate.

[0085] exist Figure 6 In the example, the SerDes ratio applied to the TRX 610 connected to the long-distance memory die can be 2:1, and the modulation type applied to the TRX 610 can be PAM4, with a symbol rate corresponding to 2. In other words, the TRX 610 can convert every two parallel data lines transmitted from the long-distance memory die into one serial data line. Figure 6 As shown, the serializer in the TRX 610 can receive four parallel data streams, output two serial data streams, and transmit this serial data to the modulator within the TRX 610. The modulator can modulate the two serial data streams into PAM4 and output one modulated data stream. The above description aims to illustrate the ratio between parallel data, serial data, and modulated data. The actual number of parallel data streams input to the TRX 610 can be greater than four, and the number of serial and modulated data streams can be determined proportionally to the number of parallel data streams. The modulated data can be transmitted to the 3DIO 620 via 512 metal lines. The 3DIO 620 can demodulate the modulated data received via the metal lines and convert the demodulated data back into parallel data. The symbol rate indicates the degree of modulation of the signal and is also called the modulation index.

[0086] The SerDes ratio applied to a TRX connected to a short-range memory die can be 8:1, and the modulation type applied to the TRX connected to the short-range memory die can be NRZ, with a symbol rate corresponding to 1. In other words, a TRX connected to a short-range memory die can convert every eight parallel data lines transmitted from the short-range memory die into one serial data line, can modulate the serial data into NRZ, and can transmit the modulated data to 256 metal lines. The corresponding 3DIO can demodulate the data received through the metal lines and can convert the demodulated data back into parallel data.

[0087] As described above, the number of metal lines used for transmitting data from a long-distance memory die can differ from the number of metal lines used for transmitting data from a short-distance memory die. For example, the number of metal lines used for transmitting data from a long-distance memory die can be greater than the number of metal lines used for transmitting data from a short-distance memory die.

[0088] The signal attenuation of a metal wire channel over data transmission distance can be determined by the Nyquist frequency of the signal, and the modulation type can be determined based on the channel characteristics at the Nyquist frequency. The effective data rate at the Nyquist frequency can be determined based on the signal attenuation of the metal wire channel, and as the transmission distance increases, modulation types with higher symbol rates can be applied. For example, with increasing transmission distance, modulation types with higher symbol rates, such as PAM4 or PAM8, can be used.

[0089] When transmitting data, data in long-distance memory dies may need to travel farther than data in short-distance memory dies. For this purpose, high-speed data conversion SerDes can be used.

[0090] SerDes can be a combined approach that includes a serializer that converts parallel data into serial data and a deserializer that restores serial data to parallel data. Semiconductor packages can use SerDes circuits (i.e., serializers and deserializers) to maintain high data transfer rates while reducing the number of data lines. SerDes circuits can minimize signal distortion or loss and maximize data transfer efficiency. As mentioned above, memory dies and processor dies can achieve efficient bidirectional data transfer using SerDes circuits.

[0091] The SerDes circuitry and modulator included in the TRX 610 can be used to increase the data rate of each pin of the processor die, and the data rate can be converted according to the SerDes ratio.

[0092] The SerDes ratio can be determined as shown in equation (2).

[0093]

[0094] When the number of metal wires N W The number of pins N of the processor die C When the operation of the deserializer in the 3DIO 620 is not required, the SerDes ratio can also be determined as in equation (3).

[0095]

[0096] When designing semiconductor packages, the data rate in the TSV from the memory die to the TRX 610, the data rate in the metal line from the TRX 610 to the 3DIO 620, and the data rate in the TSV from the 3DIO 620 to the processor die can be set to the same value.

[0097] By placing the TRX 610, which includes the SerDes circuit, near the memory die and the 3DIO 620, which includes the equalizer, near the processor die in the active interconnect die, the loss of the metal line channel can be effectively compensated, and the stability and accuracy of the signal can be ensured.

[0098] According to one or more embodiments, since a metal wire is used as the transmission channel, signal attenuation may be greater in longer metal wires. Therefore, the transmission speed can vary according to distance to stably transmit data signals. For example, data from a long-distance memory die can be transmitted at a relatively low speed, and data from a short-distance memory die can be transmitted at a relatively high speed. Furthermore, to maintain the same bandwidth for two memory dies with different data transmission speeds and to optimize bandwidth, the number of pins on the processor die used to receive data from the two memory dies can differ. For example, the number of pins on the processor die for receiving data from the long-distance memory die can be greater than the number of pins on the processor die for receiving data from the short-distance memory die.

[0099] Figure 7 This is a diagram illustrating adaptive control applied to TRX according to one or more embodiments.

[0100] refer to Figure 7An embodiment is shown in which the aforementioned short-distance memory die and long-distance memory die are implemented as the same memory die 740. As the size of the memory die 740 increases, there may be a near-field adjacent to the processor die 730 and a far-field not adjacent to the processor die 730 within the memory die 740. A single TRX 741 can also be implemented to receive data from the memory die 740 via TSV. The TRX 741 can transmit data received from the near-field to a short metal line 765 and can transmit data received from the far-field to a long metal line 775. The TRX 741 can apply a SerDes ratio and / or modulation type suitable for the data received from the near-field and the data received from the far-field, respectively, based on the signal attenuation characteristics of each metal line channel. Furthermore, the thickness / length and / or number of metal lines can be determined based on the signal attenuation characteristics of each metal line channel.

[0101] According to one or more embodiments, since a metal line is used as a channel, signal attenuation may occur as data moves along the metal line. Adaptive control can be performed in the 3DIO 731 to compensate for signal attenuation. The 3DIO 731 can adaptively control the modulation type, SerDes ratio, and gain performed by the TRX 741 based on the loss or strength of the received signal. For example, when signal loss is significant due to substantial signal attenuation in the metal line, the 3DIO 731 can instruct the TRX 741 to change to a modulation type with a higher symbol rate than before (e.g., from NRZ to PAM4). When signal loss is significant, the 3DIO 731 can instruct the TRX 741 to increase the SerDes ratio compared to before. When the strength of the received signal is low due to substantial signal attenuation in the metal line, the 3DIO 731 can instruct the TRX 741 to increase the gain compared to before. When the signal strength is sufficient compared to the predetermined standard and the attenuation is small, the 3DIO 731 can instruct the TRX 741 to change to a modulation type with a reduced symbol rate, a lower SerDes ratio, or a lower gain.

[0102] The phase-locked loop (PLL) 760 can provide a clock signal to the active circuitry in the active interconnect die 720. The frequency of the clock signal output by the PLL 760 can be divided by a predetermined number N and can be provided to the TRX 741, and can also be additionally divided by the predetermined number N. TSVThis clock signal can be provided to the TSV. In other words, the frequency of the clock signal provided to the TSV can be lower than the frequency of the clock signal provided to the SerDes circuitry and modulator included in the TRX741. Since the TRX741 may need to convert parallel data transmitted from the TSV IO into serial data according to the SerDes ratio and transmit that data, the operating speed of the TRX741 may be faster than that of the TSV. Furthermore, the frequency of the clock signal output from the PLL 760 can be divided by a predetermined number N and can be provided to the processor die 730. Figure 7 The frequency of the clock signal output by the PLL 760 is shown divided by the same number N and provided to the TRX 741 and the processor die 730, but according to one or more embodiments, the frequency may also be divided by a different number.

[0103] The above description of the adaptive control applied to the TRX 741 and the operation of the PLL 760 can be applied to examples using a large-capacity memory die 740, as well as examples where short-range and long-range memory dies are respectively provided. Adaptive control can be applied to the TRX corresponding to the short-range memory die and the TRX corresponding to the long-range memory die. Furthermore, the frequency of the clock signal output by the PLL 760 can be divided by predetermined amounts N1 and N2, and can be provided to the TRX corresponding to the short-range memory die and the TRX corresponding to the long-range memory die, respectively. In this case, depending on the embodiment, N1 and N2 can be the same or different from each other.

[0104] According to one or more embodiments, the electrical connection between the memory die 740 and the active interconnect die 720 can vary depending on the orientation of the wiring layer of the active interconnect die 720. The active region of the active interconnect die 720 can be formed beneath a wafer surface where active elements (e.g., transistors) for performing data operations and processing are disposed. The wiring layer region formed thereon (i.e., the BEOL region) can include multiple layers of metal wiring and can be used to transmit signals generated in the active region.

[0105] like Figure 7 As shown, when the wiring layer of the active interconnect die 720 is located at the bottom (i.e., front-to-back connection), the wiring layer region of the active interconnect die 720 can be located at the bottom and may not be directly connected to the memory die 740. In this case, the through-hole electrode (TSV) in the silicon layer 721 can penetrate the active interconnect die 720 and can connect to the upper memory die 740. Signals generated in the memory die 740 can be transmitted to the wiring layer below the active interconnect die 720. This wiring layer can be referred to as the metal layer 723 or the BEOL region.

[0106] Figure 8This is a diagram illustrating an active interconnect die with face-to-face connections according to one or more embodiments.

[0107] refer to Figure 8 When the wiring layer of the active interconnect die 820 is located on top (i.e., face-to-face connection), the wiring layer region of the active interconnect die 820 can be located on the upper part and can directly contact and connect to the wiring layer region of the memory die 840. The TRX 841 in the active interconnect die 820 can be connected to the memory die 840 via a metal line (e.g., line 870) without a TSV, and the 3DIO 831 can also be connected to the processor die 830 via a metal line (e.g., line 880) without a TSV. In this case, the active interconnect die 820 can form a through electrode on the bottom for connection to the outside and can be connected to external circuitry. The above description applies to the connections between the active interconnect die 820, the processor die 830, and the memory die 840.

[0108] Figure 9 This is a diagram illustrating a semiconductor package structure with a redistribution layer (RDL) applied according to one or more embodiments.

[0109] refer to Figure 9 The semiconductor package 900 may include an RDL 910, a passive interposer 920, a processor die 930, a first logic die 940, a first memory die 950, a second logic die 960, and a second memory die 970. The passive interposer 920 may be disposed on the RDL 910, and the processor die 930, the first logic die 940, and the second logic die 960 may be disposed on the passive interposer 920. The first memory die 950 may be disposed on the first logic die 940, and the second memory die 970 may be disposed on the second logic die 960. The first memory die 950 may be disposed at a short distance close to the processor die 930, and the second memory die 970 may be disposed at a long distance away from the processor die 930. That is, the first memory die 950 may be closer to the processor die 930 than the second memory die 970.

[0110] The passive interposer 920 can be a passive component for providing electrical connections and can provide a physical wiring path for communication between the first memory die 950 and the processor die 930. In this case, the passive interposer 920 can be used to transmit only electrical signals and may not include any active circuitry.

[0111] The first logic die 940 plays a crucial role in relaying data between the first memory die 950 and the processor die 930. Data stored in the first memory die 950 may not be directly transmitted to the processor die 930; instead, it can be transmitted via the first logic die 940. During this process, the first logic die 940 can temporarily store data signals and can transmit signals by regenerating them, thereby improving signal stability and accuracy. Furthermore, the first logic die 940 can improve the overall system's data processing speed by minimizing potential delays and signal distortion during data transmission.

[0112] The presence of the first logic die 940 can be particularly important in high-speed data transmission environments because signal loss and latency can increase as the physical distance between the first memory die 950 and the processor die 930 increases. The first logic die 940 can mitigate this problem and may facilitate smooth communication between the memory and the processor.

[0113] The description of the first logic die 940 can also be applied to the second logic die 960. Logic dies can also be called buffer dies or base dies.

[0114] The first logic die 940 can convert parallel data received from the first memory die 950 via TSV into serial data according to a predetermined SerDes ratio, and can transmit the data to the processor die 930 based on NRZ modulation through the data path included in the passive interposer layer 920.

[0115] Because the second memory die 970 is located at a considerable distance from the processor die 930, data transfer between the second memory die 970 and the processor die 930 may be difficult to achieve through the data path included in the passive interposer 920, as is the case with the first memory die 950. Data from the second memory die 970 can be transmitted to the second logic die 960 via TSV, and the second logic die 960 can convert the received parallel data into serial data according to a predetermined SerDes ratio, and can modulate the serial data into PAM4. The modulated data can be transmitted via the metal lines included in the RDL 910 through the passive interposer 920. The processor die 930 can then receive data transmitted via the metal lines included in the RDL 910 through the passive interposer 920. The received data can be demodulated by a demodulator included in the processor die 930. For example, the demodulator included in the processor die 930 can be controlled by a controller.

[0116] Since the above description applies to the operation of processing data from the remote memory die 970 via the SerDes circuitry and modulator of the logic die 960 and transmitting the data to the processor die 930 via the metal lines in the RDL 910, its detailed description is omitted.

[0117] exist Figure 9 In the example, microbumps can be provided between RDL 910 and passive interposer 920, between passive interposer 920 and processor die 930, between passive interposer 920 and first logic die 940 and second logic die 960, and between first logic die 940 and second logic die 960 and first memory die 950 and second memory die 970 for electrical connection to each other. Microbumps can provide contact between the two layers and can ensure stable transmission of data signals. For example, microbumps can serve as an example of data pins, or other types of data pins can be used. For example, other types of bumps, such as copper (Cu) bumps or solder bumps, can be used as data transmission pins. Alternatively, hybrid bonding can be used to achieve direct die-to-die connections.

[0118] For ease of description, data movement from the memory die to the processor die is described. However, the embodiments are not limited thereto, and the above description can be applied to data movement from the processor die to the memory die. Furthermore, the above references... Figures 1 to 9 The description can be applied to various die-to-die data movements, except for data movement between memory dies and processor dies.

[0119] The semiconductor packages described herein can be incorporated into a wide variety of electronic devices. For example, electronic devices can include: various computing devices such as mobile phones, smartphones, tablet PCs, e-book devices, laptops, PCs, desktop computers, workstations, or servers; various wearable devices such as smartwatches, smart glasses, head-mounted displays (HMDs), or smart clothing; various home appliances such as smart speakers, smart TVs (TVs), or smart refrigerators; and smart cars, smart self-service terminals, Internet of Things (IoT) devices, walking aids (WADs), drones, or robots.

[0120] The embodiments described herein can be implemented using hardware components, software components, and / or combinations thereof. The processing device can be implemented using one or more general-purpose or special-purpose computers, such as processors, controllers and arithmetic logic units (ALUs), DSPs, microcomputers, FPGAs, programmable logic units (PLUs), microprocessors, or any other device capable of responding to and executing instructions in a defined manner. The processing device can run an operating system (OS) and one or more software applications running on the OS. The processing device can also access, store, manipulate, process, and create data in response to the execution of software. For simplicity, the description of the processing device is used as the singular; however, those skilled in the art will understand that the processing device can include multiple processing elements and various types of processing elements. For example, the processing device can include multiple processors, or a single processor and a single controller. Furthermore, different processing configurations are also possible, such as parallel processors.

[0121] Software can include computer programs, code segments, instructions, or some combination thereof, to independently or uniformly instruct or configure a processing device to operate as needed. Software and data can be stored in any type of machine, component, physical or virtual device, or computer storage medium or device capable of providing instructions or data to or being interpreted by the processing device. Software can also be distributed across network-coupled computer systems, enabling it to be stored and executed in a distributed manner. Software and data can be stored on one or more non-transitory computer-readable recording media.

[0122] The methods according to the above embodiments can be recorded in a non-transitory computer-readable medium, including program instructions for implementing the various operations of the above embodiments. The medium may also include data files, data structures, etc., alone or in combination with the program instructions. The program instructions recorded on the medium may be specifically designed and constructed for the purposes of the exemplary embodiments, or they may be well-known and available to those skilled in the art of computer software. Examples of non-transitory computer-readable media include: magnetic media, such as hard disks, floppy disks, and magnetic tapes; optical media, such as CD-ROMs, DVDs, and / or Blu-ray discs; magneto-optical media, such as optical discs; and hardware devices specifically configured to store and execute program instructions, such as ROMs, random access memory (RAM), flash memory (e.g., Universal Serial Bus (USB) flash drives, memory cards, memory sticks, etc.). Examples of program instructions include both machine code generated by a compiler and files containing high-level code that can be executed by a computer using an interpreter.

[0123] The aforementioned hardware device can be configured to act as one or more software modules to perform the operations described in the examples above, or vice versa.

[0124] Each embodiment described above is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with this disclosure.

[0125] It should be understood that the embodiments described herein should be considered in a descriptive sense and not for limiting purposes only. The description of features or aspects in each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope defined by the appended claims.

Claims

1. A semiconductor package, comprising: An active interconnect die includes a modulator and at least one first metal line; Processor die, on the active interconnect die; First memory dies are stacked on top of each other on the active interconnect dies and spaced apart from the processor die by a first lateral distance; as well as The second memory dies are stacked on top of each other on the active interconnect dies and spaced apart from the processor die by a second lateral distance greater than the first lateral distance; The at least one first metal line is configured for data communication between the second memory die and the processor die.

2. The semiconductor package according to claim 1, wherein, The active interconnect die includes at least one second metal line configured for data communication between the first memory die and the processor die. Wherein, the at least one first metal wire is thicker than the at least one second metal wire.

3. The semiconductor package according to claim 1, wherein, The symbol rate of data communication between the second memory die and the processor die is greater than the symbol rate of data communication between the first memory die and the processor die.

4. The semiconductor package according to claim 1, wherein, The SerDes ratio of data communication between the second memory die and the processor die is less than the SerDes ratio of data communication between the first memory die and the processor die.

5. The semiconductor package according to claim 1, wherein, The active interconnect die includes at least one second metal line configured for data communication between the first memory die and the processor die. The number of the at least one first metal wire is different from the number of the at least one second metal wire.

6. The semiconductor package according to claim 1, wherein, The processor die includes multiple pins, and Wherein, the first number of pins of the processor die connected to the second memory die is greater than the second number of pins of the processor die connected to the first memory die.

7. The semiconductor package according to claim 1, wherein, The first memory die is included in a first high-bandwidth memory (HBM), and the second memory die is included in a second HBM, or the first memory die and the second memory die are included in the same HBM.

8. The semiconductor package according to claim 1, wherein, The modulation type of the data communication between the second memory die and the processor die is controlled based on the signal loss transmitted from the second memory die through the at least one first metal line.

9. The semiconductor package according to claim 1, wherein, The signal gain of the data communication between the second memory die and the processor die is controlled based on the strength of the signal transmitted from the second memory die through the at least one first metal line.

10. The semiconductor package according to claim 1, wherein, The frequency of the clock signal supplied to the through-silicon via (TSV) of at least one of the first memory die and the second memory die is lower than the frequency of the clock signal supplied to the modulator.

11. An active interconnect die, comprising: The serializer is configured to convert parallel data received from memory dies stacked on the active interconnect die into serial data based on the SerDes ratio. A modulator is configured to modulate the serial data and transmit the modulated serial data to at least one metal line; as well as The 3D I / O is configured to demodulate the modulated serial data received through the at least one metal line and transmit the demodulated serial data to the processor die on the active interconnect die.

12. The active interconnect die according to claim 11, wherein, At least one of the SerDes ratio or modulation type of the serial data is determined based on the lateral distance between the memory die and the processor die.

13. The active interconnect die according to claim 11, wherein, The number of at least one metal line or the thickness of at least one metal line is determined based on the lateral distance between the memory die and the processor die.

14. The active interconnect die according to claim 11, wherein, The processor die includes multiple pins, and The number of pins of the processor die connected to the 3DIO is determined based on the lateral distance between the memory die and the processor die.

15. The active interconnect die according to claim 11, wherein, The memory die is included in the high-bandwidth memory (HBM).

16. The active interconnect die according to claim 11, wherein, The modulation type of the serial data is controlled based on the loss of the signal received by the 3DIO through the at least one metal line.

17. The active interconnect die according to claim 11, wherein, The signal gain transmitted through the at least one metal line is controlled based on the strength of the signal received by the 3DIO through the at least one metal line.

18. The active interconnect die according to claim 11, wherein, The frequency of the clock signal supplied to the through-silicon via (TSV) of the memory die is lower than the frequency of the clock signal of the modulator.

19. A semiconductor package, comprising: Intermediate layer; A logic die, on the interposer layer, the logic die includes a modulator; A memory die, stacked on the logic die and connected to the logic die via a through electrode; The processor die is located on the interposer layer. as well as The redistribution layer RDL, located beneath the interposer layer, includes at least one metal line. The modulator and the at least one metal line are configured for data communication between the memory die and the processor die.

20. The semiconductor package of claim 19, wherein, The modulator is configured to modulate data received from the memory die, and The modulated data is transmitted to the processor die by sequentially passing through the interposer, the at least one metal line in the RDL, and the interposer.

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