Semiconductor power device and method of manufacturing the same

Abstract

This application provides a semiconductor power device and its fabrication method. The semiconductor power device includes a semiconductor substrate, a drift layer, and a well region. The drift layer is located on one side of the semiconductor substrate along a first direction. The well region is located in the drift layer and includes a channel region. The channel region includes a first channel region and a second channel region, wherein the first channel region and the well region have the same doping type, and the second channel region has the opposite doping type. This reduces the channel resistance and improves the channel mobility.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor power device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in high-power fields such as new energy vehicles, power systems, and energy storage converters due to their high voltage resistance, high temperature stability, and excellent switching characteristics. Summary of the Invention

[0003] The technical problem addressed in this application includes how to reduce the channel resistance of semiconductor power devices and improve channel mobility.

[0004] The present invention provides a semiconductor power device, comprising: a semiconductor substrate layer; a drift layer located on one side of the semiconductor substrate layer along a first direction; a well region located in the drift layer, the well region including a channel region; wherein the channel region includes a first channel region and a second channel region, the first channel region and the well region having the same doping type and the opposite doping type to the second channel region.

[0005] Optionally, the doping concentration in the second channel region is 5E16 atom / cm³. 3 -1E18atom / cm 3 The doping concentration in the first channel region is 1E17 atom / cm³. 3 -5E17atom / cm 3 .

[0006] Optionally, the semiconductor power device further includes a JFET region located on one side of the well region along the second direction; wherein the second channel region is a strip extending along a third direction; wherein the third direction, the second direction, and the first direction intersect each other.

[0007] Optionally, one of the channel regions includes a plurality of second channel regions spaced apart in the second direction.

[0008] Optionally, the size of the second channel region in the second direction is 0.01 micrometer to 0.1 micrometer; the size of the first channel region between adjacent second channel regions in the second direction is 0.3 micrometer to 0.5 micrometer.

[0009] Optionally, one of the channel regions includes a second channel region.

[0010] Optionally, the size of the second channel region in the second direction is 0.01 micrometer to 0.1 micrometer; for the first channel region located on one side of the second channel region in the second direction, the size of the first channel region in the second direction is 0.1 micrometer to 0.5 micrometer.

[0011] Optionally, the semiconductor power device further includes a JFET region located on one side of the well region along the second direction; wherein the second channel region is a strip extending along the second direction; or, the cross-sectional shape of the second channel region perpendicular to the first direction is square, rectangular, circular, triangular or W-sided, where W is an integer greater than or equal to 5.

[0012] Optionally, multiple second channel regions are arranged at intervals along a third direction, and the third direction, the second direction, and the first direction intersect each other.

[0013] Optionally, for the channel region, two adjacent second channel regions in the third direction are spaced apart in the second direction, wherein the third direction, the second direction, and the first direction intersect each other.

[0014] Optionally, the size of the second channel region in the third direction is 0.01 micrometers to 5 micrometers; the spacing between adjacent second channel regions in the third direction is 0.05 micrometers to 50 micrometers.

[0015] Optionally, the size of the second channel region in the first direction is less than or equal to the size of the first channel region in the first direction.

[0016] Optionally, the semiconductor power device further includes a gate dielectric layer covering the channel region and the JFET region located on one side of the well region along the second direction; wherein the dimension of the gate dielectric layer in the first direction is greater than or equal to 50 nm.

[0017] Optionally, the gate dielectric layer has a size of 50 nm to 100 nm in the first direction.

[0018] This application also provides a method for fabricating a semiconductor power device, comprising: forming a drift layer on one side of a semiconductor substrate along a first direction; forming a well region in the drift layer, the well region including an initial channel region; and doping a portion of the initial channel region to form a channel region, wherein the channel region includes a first channel region and a second channel region, the first channel region and the well region having the same doping type and the doping type opposite to that of the second channel region.

[0019] The technical solution of this invention has the following technical effects: The semiconductor power device provided by this invention includes a first channel region and a second channel region. The first channel region and the well region have the same doping type, while the doping type of the second channel region is opposite. In thermal equilibrium without an applied operating voltage, a transverse electric field exists in both the first and second channel regions, causing space charge regions to form and resulting in a local depletion effect. Based on this local depletion effect, the channel region can achieve inversion at a lower gate voltage to form an inversion layer, enabling forward conduction. In other words, the channel region can achieve a degree of inversion comparable to conventional structures at a lower gate voltage. The lower gate voltage reduces the electric field strength in the first direction on the channel region, preventing electrons in the inversion layer from being excessively confined near the interface between the channel region and the gate dielectric layer. Electrons in the inversion layer are distributed over a wider area, thus increasing the size of the inversion layer in the first direction, improving the channel mobility, and reducing the channel resistance.

[0020] Secondly, the channel region can achieve inversion at a lower gate voltage to form an inversion layer, and the lower gate voltage can be matched with a gate dielectric layer with a larger size in the first direction. By increasing the size of the gate dielectric layer in the first direction, the influence of the second channel region on the threshold voltage can be compensated. The gate dielectric layer with increased size in the first direction can reduce the electric field strength in the gate dielectric layer and improve the long-term reliability of semiconductor power devices. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a three-dimensional schematic diagram of a semiconductor power device; Figure 2 for Figure 1 Top view of the central area; Figure 3 This is a three-dimensional schematic diagram of a semiconductor power device according to an embodiment of this application; Figure 4 for Figure 3 A top view of the central area; Figure 5 for Figure 3 Another top view of the central area; Figure 6 for Figure 3 Another top view of the central area; Figure 7 for Figure 3Another top view of the central area; Figure 8 for Figure 3 Another top view of the central area; Figures 9 to 12 This is a schematic diagram illustrating the fabrication process of a semiconductor power device in one embodiment of this application. Detailed Implementation

[0023] A semiconductor power device, reference Figure 1 and Figure 2 , Figure 2 for Figure 1 A top view of a portion of the semiconductor power device shows that the device includes: a semiconductor substrate 100, a drift layer 101, a well region 102, a first active region 103 and a second active region 104, a gate dielectric layer 111, and a gate electrode layer 112. The drift layer 101 is located on one side of the semiconductor substrate 100 along the first direction Z. The well region 102 is located in the drift layer 101 and includes a channel region F. The gate dielectric layer 111 covers a portion of the first active region 103, the channel region F, and the JFET region 130. The gate electrode layer 112 is located on the side of the gate dielectric layer 111 opposite to the drift layer 101 along the first direction Z.

[0024] In the above structure, the channel resistance accounts for a relatively high proportion of the on-resistance of the semiconductor power device. Research has found that the reason is as follows: The interface defect density and roughness between the channel region F and the gate dielectric layer 111 are high. When an operating voltage is applied to the gate electrode layer 112 to conduct the channel region F, an inversion layer forms in the region of the channel region near the gate dielectric layer 111. The size of the inversion layer in the first direction Z is approximately tens of nanometers or a few nanometers. The electron mobility of the inversion layer is significantly affected by the scattering at the interface between the channel region F and the gate dielectric layer 111. Furthermore, the higher the operating voltage, the closer the electrons in the inversion layer are to the interface between the channel region F and the gate dielectric layer 111, meaning the size of the inversion layer in the first direction Z is smaller. This results in a low carrier mobility in the channel region F. For example, when the drift layer 101 is made of N-type SiC, the carrier mobility in the channel region F is much lower than the intrinsic mobility of SiC. Consequently, the channel resistance accounts for a high proportion of the on-resistance of the semiconductor power device.

[0025] Based on this, this application proposes a new semiconductor power device and its fabrication method, which reduces channel resistance and improves channel mobility.

[0026] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] One embodiment of this application discloses a semiconductor power device, referencing... Figures 3 to 8 Semiconductor power devices include: Semiconductor substrate layer 200; A drift layer 201 is located on one side of the semiconductor substrate layer 200 along the first direction Z; A well region 202 is located in the drift layer 201, and the well region 202 includes a channel region F1; The channel region F1 includes a first channel region F11 and a second channel region F12. The first channel region F11 and the well region 202 have the same doping type and the opposite doping type to the second channel region F12.

[0031] The semiconductor power device provided in this embodiment includes a channel region F1 comprising a first channel region F11 and a second channel region F12. The first channel region F11 and the well region 202 have the same doping type, while the doping type of the second channel region F12 is opposite. In a thermal equilibrium state without an applied operating voltage, a transverse electric field exists in the first channel region F11 and the second channel region F12, causing space charge regions to form in both regions, resulting in a local depletion effect. Based on this local depletion effect, the channel region F1 can achieve inversion at a lower gate voltage to form an inversion layer, enabling forward conduction of the channel region. In other words, the channel region F1 can achieve an inversion degree comparable to that of conventional structures at a lower gate voltage. The lower gate voltage reduces the electric field strength in the channel region F1 in the first direction Z, so that the electrons in the inversion layer are not excessively bound near the interface between the channel region F1 and the gate dielectric layer 211. The electrons in the inversion layer are distributed in a wider area. That is, the size of the inversion layer in the first direction Z is increased, the mobility of the channel region F1 is improved, and the channel resistance is reduced.

[0032] Secondly, the channel region F1 can achieve inversion at a lower gate voltage to form an inversion layer. The lower gate voltage can be matched with a gate dielectric layer 211 with a larger dimension in the first direction Z. By increasing the dimension of the gate dielectric layer 211 in the first direction Z, the influence of the second channel region F12 on the threshold voltage can be compensated. The gate dielectric layer 211 with an increased dimension in the first direction Z can reduce the electric field strength in the gate dielectric layer 211, thereby improving the long-term reliability of the semiconductor power device. For example, the dimension of the gate dielectric layer 211 in the first direction Z is greater than or equal to 50 nm. Further, the dimension of the gate dielectric layer 211 in the first direction Z is 50 nm to 100 nm, for example, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm.

[0033] It should be noted that this application does not impose any limitation on the size of the gate dielectric layer 211 in the first direction Z.

[0034] In this embodiment, the semiconductor power device is a MOSFET semiconductor power device.

[0035] In this embodiment, a SiC-based semiconductor power device is used as an example for illustration. Accordingly, the semiconductor substrate 200 is silicon carbide (SiC) doped with conductive ions. New-generation semiconductor power devices based on SiC exhibit higher reverse breakdown voltage, lower forward conduction loss, faster switching frequency, and stronger environmental tolerance. It should be noted that the material of the semiconductor substrate is not limited in this embodiment.

[0036] In one embodiment, the semiconductor substrate 200 is N-type doped.

[0037] In one embodiment, the doping type of the drift layer 201 is the same as that of the semiconductor substrate layer 200. The doping concentration of the drift layer 201 is lower than that of the semiconductor substrate layer 200.

[0038] In one embodiment, the drift layer 201 is N-type doped, and further, the material of the drift layer 201 is silicon carbide doped with N-type conductive ions. It should be noted that in other embodiments, the material of the drift layer can also be other materials. The N-type conductive ions can be phosphorus ions or nitrogen ions.

[0039] In one embodiment, the doping type of the well region 202 is opposite to that of the drift layer 201. For example, the well region 202 is doped with P-type and the drift layer 201 is doped with N-type.

[0040] In one embodiment, the semiconductor power device further includes a first active region 203 and a second active region 204 located in the well region 202. The doping type of the first active region 203 is opposite to that of the well region 202, and the doping concentration of the first active region 203 is greater than that of the drift layer 201. The doping type of the second active region 204 is opposite to that of the first active region 203, and the doping concentration of the second active region 204 is greater than that of the well region 202. For example, the first active region 203 is N-type doped, and the second active region 204 is P-type doped.

[0041] In one embodiment, the semiconductor power device further includes a JFET region 230, which is located on one side of the well region 202 along the second direction X, and the JFET region 230 is located between adjacent well regions 202 along the second direction X. The second direction X intersects the first direction Z, for example, the second direction X is perpendicular to the first direction.

[0042] In one embodiment, the semiconductor power device further includes a gate dielectric layer 211 and a gate electrode layer 212. The gate dielectric layer 211 covers a portion of the first active region 203, the channel region F1, and the JFET region 230, and the gate electrode layer 212 is located on the side of the gate dielectric layer 211 facing away from the drift layer 201 along a first direction Z. The material of the gate dielectric layer 211 is, for example, silicon oxide. The material of the gate electrode layer 212 includes polysilicon.

[0043] In one embodiment, the gate electrode layer 212 extends along a third direction Y. Specifically, the dimension of the gate electrode layer 212 along the third direction Y is larger than the dimension of the gate electrode layer 212 along the second direction X, and the dimension of the gate electrode layer 212 along the third direction Y is larger than the dimension of the gate electrode layer 212 along the first direction Z. In other embodiments, the dimension of the gate electrode layer 212 is not limited.

[0044] In one embodiment, the well region 202 extends along a third direction Y. Specifically, the size of the well region 202 along the third direction Y is larger than the size of the well region 202 along the second direction X, and the size of the well region 202 along the third direction Y is larger than the size of the well region 202 along the first direction Z. In other embodiments, the size of the well region 202 is not limited.

[0045] In one embodiment, the channel region F1 extends along a third direction Y. Specifically, the dimension of the channel region F1 along the third direction Y is greater than the dimension of the channel region F1 along the second direction X, and the dimension of the channel region F1 along the third direction Y is greater than the dimension of the channel region F1 along the first direction Z. In other embodiments, the dimension of the channel region F1 is not limited.

[0046] Specifically, the third direction Y intersects the first direction Z and the second direction X. For example, the third direction Y is perpendicular to the first direction Z and the second direction X.

[0047] In one embodiment, the doping concentration of F12 in the second channel region is 5E16 atom / cm². 3 -1E18atom / cm 3 The doping concentration of F11 in the first channel region is 1E17 atom / cm³. 3 -5E17atom / cm 3 The doping concentration of the second channel region F12 can be greater than the doping concentration of the first channel region F11, or the doping concentration of the second channel region F12 can be equal to the doping concentration of the first channel region F11, or the doping concentration of the second channel region F12 can be less than the doping concentration of the first channel region F11. When the doping concentration of the second channel region F12 and the volume occupied by the second channel region F12 are matched, the second channel region F12 is completely depleted while the first channel region F11 is partially depleted when no gate voltage is applied.

[0048] The doping concentration of the first channel region F11 is less than the doping concentration of the well region 202. For example, the doping concentration of the first channel region F11 is less than the doping concentration of the well region 202 located on the side of the first channel region F11 facing the semiconductor substrate layer 200.

[0049] The first channel region F11 has a dimension of 0.1 micrometer to 0.2 micrometers, for example, 0.15 micrometers, in the first direction Z. The second channel region F12 has a dimension of 0.1 micrometer to 0.2 micrometers, for example, 0.15 micrometers, in the first direction Z.

[0050] In one embodiment, reference Figure 4 The second channel region F12 is a strip extending along the second direction X, and the size of the second channel region F12 in the second direction X is larger than the size of the second channel region F12 in the third direction Y.

[0051] In one embodiment, reference Figure 5 and Figure 6 The second channel region F12 is a strip extending along the third direction Y, and its dimension along the third direction Y is larger than its dimension along the second direction X. The continuous extension of the second channel region F12 along the third direction Y provides continuous electrostatic modulation in that direction, resulting in a more uniform pre-depletion distribution within the first channel region F11 without a gate voltage applied. This improves the consistency and repeatability of semiconductor power devices. The continuous strip geometry is simple, more user-friendly for mask design and ion implantation window definition, and relatively easy to control the process, making it suitable for large-scale manufacturing.

[0052] refer to Figure 5 A channel region F1 includes a second channel region F12. Further, the size of the second channel region F12 in the second direction X is 0.01 micrometers to 0.1 micrometers, for example, 0.01 micrometers, 0.03 micrometers, 0.05 micrometers, 0.08 micrometers or 0.1 micrometers; for a first channel region F11 located on one side of the second channel region F12 in the second direction X, the size of the first channel region F11 in the second direction X is 0.1 micrometers to 0.5 micrometers, for example, 0.1 micrometers, 0.2 micrometers, 0.3 micrometers, 0.4 micrometers or 0.5 micrometers.

[0053] refer to Figure 6 A channel region F1 includes a plurality of second channel regions F12 spaced apart in a second direction X. Further, the size of the second channel regions F12 in the second direction X is 0.01 micrometers to 0.1 micrometers, for example, 0.01 micrometers, 0.03 micrometers, 0.05 micrometers, 0.08 micrometers, or 0.1 micrometers; the size of the first channel region F11 between adjacent second channel regions F12 in the second direction X is 0.3 micrometers to 0.5 micrometers, for example, 0.3 micrometers, 0.4 micrometers, or 0.5 micrometers.

[0054] In one embodiment, the cross-sectional shape of the second channel region F12 perpendicular to the first direction Z is square, rectangular, circular, triangular, or W-sided, where W is an integer greater than or equal to 5. (See reference) Figure 7 and Figure 8 Taking a square cross-sectional shape of the second channel region F12 perpendicular to the first direction Z as an example, multiple second channel regions F12 are arranged in a discrete island pattern, reducing the continuous coverage ratio of the second channel regions F12 in the plane perpendicular to the first direction Z. Therefore, while achieving pre-depletion modulation of the first channel region F11 without applying a gate voltage, the space charge region will not excessively compress the space of the first channel region F11 in the third direction Y when no gate voltage is applied. The discrete island structure makes the transverse electric field periodically distributed in space, which can alleviate the overall barrier reduction caused by continuous strong coupling and is beneficial to maintaining the channel opening capability.

[0055] refer to Figure 4 and Figure 7 Multiple second channel zones F12 are arranged at intervals along the third direction Y.

[0056] refer to Figure 4 Since multiple second channel regions F12 are arranged in segments along the third direction Y, rather than being laid out continuously, a lateral built-in electric field can be introduced locally, which can drive the pre-depletion of the adjacent first channel region F11 without applying a gate voltage. Furthermore, without applying a gate voltage, the space charge region will not excessively compress the space of the first channel region F11 in the third direction Y, thus reducing the impact of setting the second channel region F12 on the threshold voltage.

[0057] refer to Figure 8 For the channel region, the two adjacent second channel regions F12 in the third direction Y are spaced apart in the second direction X.

[0058] refer to Figure 7 and Figure 8 The size of the second channel region F12 in the third direction Y is 0.01 micrometers to 5 micrometers, for example, 0.01 micrometers, 0.05 micrometers, 0.1 micrometers, 1 micrometer, 3 micrometers or 5 micrometers; the spacing between adjacent second channel regions F12 in the third direction F12 is 0.05 micrometers to 50 micrometers, for example, 0.01 micrometers, 0.05 micrometers, 0.1 micrometers, 1 micrometer, 3 micrometers, 5 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, 30 micrometers, 40 micrometers or 50 micrometers.

[0059] In one embodiment, the size of the second channel region F12 in the first direction Z is less than or equal to the size of the first channel region F11 in the first direction Z. This is beneficial for the second channel region F12 to be fully depleted without applying a gate voltage.

[0060] It should be noted that under thermal equilibrium conditions without applied operating voltage, space charge regions are formed in the first channel region F11 and the second channel region F12, resulting in a local depletion effect. The second channel region F12 is completely depleted, while the first channel region F11 is partially depleted. The doping concentration and volume occupied by the second channel region F12 can be adjusted to achieve complete depletion of the second channel region F12.

[0061] In one embodiment, the semiconductor power device further includes a front electrode (not shown) that contacts the first active region 203. The semiconductor power device also includes (not shown) a drain metal layer located on a side surface of the semiconductor substrate layer 200 opposite to the drift layer 201. The semiconductor power device further includes an isolation dielectric layer that surrounds the side and top surfaces of the gate electrode layer 212. The front electrode covers the gate electrode layer 212, and the isolation dielectric layer isolates the front electrode and the gate electrode layer 212. The material of the isolation dielectric layer includes silicon oxide.

[0062] Another embodiment of this application also provides a method for fabricating a semiconductor power device, comprising: forming a drift layer on one side of a semiconductor substrate along a first direction; forming a well region in the drift layer, the well region including an initial channel region; and doping a portion of the initial channel region to form a channel region, wherein the channel region includes a first channel region and a second channel region, the first channel region and the well region having the same doping type and the opposite doping type to the second channel region.

[0063] The following is for reference. Figures 9 to 12 This document provides a detailed introduction to the fabrication methods of semiconductor power devices.

[0064] refer to Figure 9 A drift layer 201 is formed on one side of the semiconductor substrate layer 200 along the first direction Z.

[0065] The process for forming the drift layer 201 includes epitaxial processes.

[0066] The semiconductor substrate layer 200 and the drift layer 201 are described with reference to the foregoing embodiments.

[0067] refer to Figure 9 A trap region 202 is formed in the drift layer 201.

[0068] The description of the trap region 202 refers to the description of the foregoing embodiments.

[0069] The process for forming the trap region 202 includes ion implantation.

[0070] The method for fabricating a semiconductor power device further includes: implanting ions into a drift layer 201 between adjacent well regions 202 in the second direction X, thereby forming a JFET region 230 between adjacent well regions 202 in the second direction X. The doping type of the JFET region 230 is the same as that of the drift layer 201. The doping concentration of the JFET region 230 is greater than the doping concentration of the drift layer 201 between the JFET region 230 and the semiconductor substrate layer 200.

[0071] refer to Figure 10 and Figure 11 , Figure 10 In order to be in Figure 9 A basic diagram. Figure 11 for Figure 10 A top view of the central region shows that a first active region 203 is formed in the well region 202; a second active region 204 is formed in the well region 202.

[0072] The process for forming the first active region 203 includes an ion implantation process, and the process for forming the second active region 204 includes an ion implantation process.

[0073] The description of the first active region 203 and the second active region 204 is the same as that of the foregoing embodiments and will not be described in detail again.

[0074] The method for fabricating a semiconductor power device further includes: implanting ions into a well region 202 between the first active region 203 and the JFET region 230 to form an initial channel region F0 between the first active region 203 and the JFET region 230. The doping type of the initial channel region F0 is the same as that of the well region 202. The doping concentration of the initial channel region F0 is lower than the doping concentration of the well region 202 on the side of the initial channel region F0 facing the semiconductor substrate layer 200.

[0075] refer to Figure 12 , Figure 12 In order to be in Figure 11 Based on the schematic diagram, a portion of the initial channel region F0 is doped to form a channel region F1. The channel region F1 includes a first channel region F11 and a second channel region F12. The first channel region F11 and the well region 202 have the same doping type, while the doping type of the second channel region F12 is opposite.

[0076] The process of doping a portion of the initial channel region F0 includes ion implantation.

[0077] refer to Figure 12 The second channel region F12 is a strip extending along the second direction X, and the size of the second channel region F12 in the second direction X is larger than the size of the second channel region F12 in the third direction Y.

[0078] refer to Figure 12 Multiple second channel zones F12 are arranged at intervals along the third direction Y.

[0079] The method for fabricating a semiconductor power device further includes forming a gate dielectric layer 211 and a gate electrode layer 212. The gate dielectric layer 211 covers a portion of the first active region 203, the channel region F1, and the JFET region 230. The gate electrode layer 212 is located on the side of the gate dielectric layer 211 facing away from the drift layer 201 along a first direction Z. The material of the gate dielectric layer 211 is, for example, silicon oxide. The material of the gate electrode layer 212 includes polysilicon.

[0080] The method for fabricating a semiconductor power device further includes: forming an isolation dielectric layer that surrounds the side surface and top surface of the gate electrode layer 212; forming a front electrode (not shown) that contacts the first active region 203; and the isolation dielectric layer isolating the front electrode and the gate electrode layer 212. The material of the isolation dielectric layer includes silicon oxide.

[0081] The method for fabricating a semiconductor power device further includes: forming a drain metal layer, wherein the drain metal layer is located on the side surface of the semiconductor substrate layer 200 away from the drift layer 201.

[0082] It should be noted that in the fabrication method of semiconductor power devices, the formation of Figure 12 The channel region F1 shown is an example. The fabrication method of semiconductor power devices can also form... Figures 5 to 8 The channel region F1 is shown. The description of channel region F1 is the same as in the previous embodiment and will not be repeated here.

[0083] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A semiconductor power device, characterized in that, include: Semiconductor substrate layer; A drift layer is located on one side of the semiconductor substrate layer along the first direction; A trap region, located in the drift layer, the trap region including a channel region; The channel region includes a first channel region and a second channel region, wherein the first channel region and the well region have the same doping type and the doping type is opposite to that of the second channel region.

2. The semiconductor power device according to claim 1, characterized in that, The doping concentration of the second channel region is 5E16 atom / cm 3 -1E18atom / cm 3 The doping concentration in the first channel region is 1E17 atom / cm³. 3 -5E17atom / cm 3 .

3. The semiconductor power device according to claim 1, characterized in that, The semiconductor power device further includes a JFET region located on one side of the well region along the second direction; The second channel area is a strip extending in a third direction; Wherein, the third direction, the second direction, and the first direction intersect each other.

4. The semiconductor power device according to claim 3, characterized in that, A channel region includes a plurality of second channel regions spaced apart in the second direction.

5. The semiconductor power device according to claim 4, characterized in that, The second channel region has a size of 0.01 micrometers to 0.1 micrometers in the second direction; the first channel region between adjacent second channel regions has a size of 0.3 micrometers to 0.5 micrometers in the second direction.

6. The semiconductor power device according to claim 3, characterized in that, One of the trench areas includes a second trench area.

7. The semiconductor power device according to claim 6, characterized in that, The second channel region has a size of 0.01 micrometers to 0.1 micrometers in the second direction; for the first channel region located on one side of the second channel region in the second direction, the size of the first channel region in the second direction is 0.1 micrometers to 0.5 micrometers.

8. The semiconductor power device according to claim 1, characterized in that, The semiconductor power device further includes a JFET region located on one side of the well region along the second direction; The second channel region is a strip extending along the second direction; or, the cross-sectional shape of the second channel region perpendicular to the first direction is square, rectangular, circular, triangular, or W-sided, where W is an integer greater than or equal to 5.

9. The semiconductor power device according to claim 8, characterized in that, Multiple second channel zones are arranged at intervals along a third direction; Wherein, the third direction, the second direction, and the first direction intersect each other.

10. The semiconductor power device according to claim 8, characterized in that, For the trench region, two adjacent second trench regions in the third direction are spaced apart in the second direction; Wherein, the third direction, the second direction, and the first direction intersect each other.

11. The semiconductor power device according to claim 9 or 10, characterized in that, The second channel region has a size of 0.01 micrometers to 5 micrometers in the third direction; the spacing between adjacent second channel regions in the third direction is 0.05 micrometers to 50 micrometers.

12. The semiconductor power device according to claim 1, characterized in that, The size of the second channel region in the first direction is less than or equal to the size of the first channel region in the first direction.

13. The semiconductor power device according to claim 1, characterized in that, The semiconductor power device further includes a gate dielectric layer that covers the channel region and the JFET region located on one side of the well region along the second direction; Wherein, the dimension of the gate dielectric layer in the first direction is greater than or equal to 50 nm.

14. The semiconductor power device according to claim 13, characterized in that, The gate dielectric layer has a size of 50nm to 100nm in the first direction.

15. A method for fabricating a semiconductor power device as described in any one of claims 1 to 14, characterized in that, include: A drift layer is formed on one side of the semiconductor substrate along the first direction; A well region is formed in the drift layer, the well region including an initial channel region; as well as A portion of the initial channel region is doped to form a channel region, wherein the channel region includes a first channel region and a second channel region, the first channel region and the well region having the same doping type and the opposite doping type to the second channel region.

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