Semiconductor structure and step-down converter

Abstract

This invention provides a semiconductor structure and a buck converter. The semiconductor structure includes a substrate, a body region, a drift region, a first deep well region, a gate structure, a source region, and a drain region. The body region and the adjacent drift region are located in the substrate. The body region has a first conductivity type. The drift region has a second conductivity type different from the first conductivity type. The first deep well region is located below the body region and the drift region and has the first conductivity type. The gate structure is located on the drift region and adjacent to the body region. The source region is located on the body region. The drain region is located adjacent to the drift region and contacts the first deep well region. The source and drain regions have the second conductivity type. The buck converter includes a buck controller, a low-voltage device, and a high-voltage device.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a buck converter, and more particularly, to a semiconductor structure and a buck converter having a controlled breakdown path. Background Technology

[0002] Recently, with the increasing demand for high-voltage devices such as power semiconductor devices, people have shown growing interest in high-voltage metal-oxide-semiconductor field-effect transistors (HV MOSFETs) used in high-voltage devices.

[0003] Among various types of high-voltage metal-oxide-semiconductor field-effect transistors (HV MOSFETs), semiconductor devices such as lateral double diffused metal-oxide-semiconductor (LDMOS) devices are frequently used.

[0004] However, with advancements in semiconductor manufacturing technology, the breakdown voltage of high-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) used in high-voltage devices needs to be carefully controlled to prevent it from exceeding the operating voltage. Therefore, a reliable high-voltage MOSFET with a controlled breakdown path is required for high-voltage devices to meet performance requirements due to the ongoing demand for high-voltage devices in semiconductor manufacturing. Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a substrate, a body region, a drift region, a first deep well region, a gate structure, a source region, and a drain region. The body region is located in the substrate. The body region has a first conductivity type. The drift region is located in the substrate and adjacent to the body region. The drift region has a second conductivity type different from the first conductivity type. The first deep well region is located in the substrate and below the body region and the drift region. The first deep well region has the first conductivity type. The gate structure is located on the drift region and adjacent to the body region. The source region is located on the body region. The source region has the second conductivity type. The drain region is located adjacent to the drift region and in contact with the first deep well region. The drain region has the second conductivity type.

[0006] One embodiment of the present invention provides a buck converter. The buck converter includes a buck controller, a low-voltage (LS) device, and a high-voltage (HS) device. The low-voltage (LS) device is connected to the buck controller. The high-voltage (HS) device is connected to the buck controller. The high-voltage (HS) device comprises a first semiconductor structure including a substrate, a body region, a drift region, a first deep-well region, a gate structure, a source region, and a drain region. The body region is located on the first deep-well region. The body region has a first conductivity type. The drift region is located on the first deep-well region and adjacent to the body region. The drift region has a second conductivity type different from the first conductivity type. The first deep-well region is located in the substrate and below the body region and the drift region. The first deep-well region has the first conductivity type. The gate structure is located on the drift region and adjacent to the body region. The source region is located on the body region. The source region has the second conductivity type. The leak region is located adjacent to the drift region and in contact with the first deep well region. The leak region has the second conductivity type.

[0007] In some embodiments, the low-voltage device comprises a second semiconductor structure identical to the first semiconductor structure. Attached Figure Description

[0008] A more complete understanding of the invention can be obtained by reading the following detailed description and referring to the accompanying drawings, wherein:

[0009] Figure 1 This is a schematic top view of a semiconductor structure according to some embodiments of the present invention;

[0010] Figure 2 According to some embodiments of the present invention, along Figure 1 A schematic cross-sectional view of the semiconductor structure along line A-A';

[0011] Figure 3 According to some embodiments of the present invention, along Figure 1 A schematic cross-sectional view of the semiconductor structure along line A-A';

[0012] Figure 4 According to some embodiments of the present invention, it includes Figure 1 , 2 Circuit diagram of a step-down device with a semiconductor structure of 3. Detailed Implementation

[0013] The following description is intended to illustrate the general principles of the invention and should not be considered as limiting. The scope of the invention is best determined by referring to the claims.

[0014] The inventive concept will now be described in detail with reference to the accompanying drawings, which illustrate exemplary embodiments of the inventive concept. The advantages and features of the inventive concept, as well as methods for achieving these advantages and features, will become apparent from the following exemplary embodiments, which will be described in more detail with reference to the accompanying drawings. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments and can be implemented in various forms. Therefore, exemplary embodiments are provided only to disclose the inventive concept and to allow those skilled in the art to understand the category of the inventive concept. Furthermore, the drawings shown are merely illustrative and not restrictive. In the drawings, the dimensions of certain elements may be exaggerated for illustrative purposes and are not drawn to scale. Dimensions and relative dimensions do not correspond to actual dimensions in the practice of the invention.

[0015] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. The same numbers refer to the same elements throughout this description. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items.

[0016] High-voltage metal-oxide-semiconductor field-effect transistors (HV MOSFETs), such as power MOSFETs, have been used as switching devices in buck converters. However, in conventional buck converters, the buck power stage MOSFETs (composed of a high-side (HS) MOSFET and a low-side (LS) MOSFET in a half-bridge configuration) can be damaged during operation when input voltage (Vin) fluctuations occur and exceed the device's safe operating area (SOA) due to undesirable breakdown paths in the MOSFETs. Therefore, a reliable high-voltage MOSFET with a controlled breakdown path is needed for high-voltage devices to meet device performance requirements, as the demand for semiconductor manufacturing of high-voltage devices continues to increase.

[0017] Figure 1 It is a semiconductor structure 500 (including Figure 2 and Figure 3 The schematic top view of semiconductor structures 500A and 500B shown in the figure is based on some embodiments of the present invention. Figure 2 It is along Figure 1A schematic cross-sectional view of the semiconductor structure 500A along line A-A', according to some embodiments of the present invention. In some embodiments, the semiconductor structure 500A includes a transistor, such as a laterally diffused MOS (LDMOS) transistor, which includes a substrate 200, a body region PB, a drift region ND, a first deep well region DPW, a gate structure 250, a source region N1, and a drain region N2A. Figure 1 The leak region N2 includes Figure 2 and Figure 3 The leak areas N2A and N2B are shown in the image. Figure 2 In the following cross-sectional views, direction D100 is defined as the transverse direction parallel to the top surface 200T of substrate 200, and direction D120 is defined as the vertical direction perpendicular to the top surface 200T of substrate 200.

[0018] In some embodiments, substrate 200 includes a central active region AC surrounded by peripheral active regions AP1, AP2, and AP3. The central active region AC and the peripheral active regions AP1, AP2, and AP3 are defined by isolation features 201 (including isolation features 201-1, 201-2, 201-3, and 201-4), such as shallow trench isolations (STIs). For example, the central active region AC is defined by isolation feature 201-1. The peripheral active region AP1 surrounding the central active region AC is defined by isolation features 201-1 and 201-2. The peripheral active region AP2 surrounding the peripheral active region AP1 is defined by isolation features 201-2 and 201-3. The peripheral active region AP3 surrounding the peripheral active region AP2 is defined by isolation features 201-3 and 201-4. A body region PB, a drift region ND, a first deep well region DPW, a gate structure 250, a source region N1, and a drain region N2A are formed in the central active region AC. The semiconductor structure 500A is basically symmetrical in terms of the bulk region PB.

[0019] In some embodiments, the isolation feature 201 includes silicon dioxide, silicon nitride, silicon oxynitride (SiON), other suitable insulating materials, or combinations thereof. In some embodiments, the isolation feature 201 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0020] The substrate 200 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP). The substrate 200 may be doped with dopants having P-type or N-type conductivity. In some embodiments, the substrate 200 is P-type.

[0021] The body region PB and the drift region ND are located in the substrate 200. The body region PB and the drift region ND may be adjacent to each other. In some embodiments, the drift region ND surrounds and contacts the opposite sidewall PS of the body region PB. Therefore, the sidewall PS of the body region PB may also serve as the interface PS between the body region PB and the drift region ND. In some embodiments, the body region PB has a first conductivity type. For example, when the first conductivity type is P-type, the body region PB is a P-type body region PB. In some embodiments, the drift region ND has a second conductivity type different from the first conductivity type. For example, when the first conductivity type is P-type, the second conductivity type is N-type, and the drift region ND is an N-type drift region ND.

[0022] The first deep well region DPW is located in the substrate 200. Furthermore, the first deep well region DPW is located below the body region PB and the drift region ND. Additionally, the bottom B1 of the body region PB and the bottom B2 of the drift region ND are in contact with different portions of the first deep well region DPW. In some embodiments, the interface between the body region PB and the first deep well region DPW (i.e., the bottom B1 of the body region PB) and the interface between the drift region ND and the first deep well region DPW (i.e., the bottom B2 of the drift region ND) are substantially at the same level. Figure 2 As shown, the interface PS between the body region PB and the drift region ND is located directly above the first deep well region DPW.

[0023] like Figure 2 As shown, the bottom 201-1B of the isolation feature 201-1 surrounding the body region PB and the drift region ND is located below the interface between the body region PB and the first deep well region DPW (i.e., the bottom B1 of the body region PB) and the interface between the drift region ND and the first deep well region DPW (i.e., the bottom B2 of the drift region ND).

[0024] In some embodiments, the first deep well DPW has a first conductivity type. For example, when the first conductivity type is P-type, the first deep well DPW is a P-type deep well DPW.

[0025] A gate structure 250 is formed on a substrate 200. Furthermore, the gate structure 250 is located on the drift region ND and adjacent to the body region PD. In some embodiments, the gate structure 250 includes a gate dielectric layer 252 and a gate electrode layer 254 formed on the gate dielectric layer 252. A pair of gate spacer layers 256 are formed on opposite sidewall surfaces of the gate structure 250. The gate electrode layer 254 is separated from the drift region ND by the gate dielectric layer 252. A channel region 251 is located directly beneath the gate structure 250 and between the source region N1 and the drain region N2A.

[0026] In some embodiments, the dielectric constant of the gate dielectric layer 252 is greater than the dielectric constant of the gate spacer layer 256. In some embodiments, the gate dielectric layer 252 comprises one or more dielectric materials, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide alloy (HfO2-Al2O3), other suitable high dielectric constant materials, or combinations thereof. In some embodiments, the gate dielectric layer 252 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0027] In some embodiments, the gate spacer layer 256 comprises a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), or a combination thereof. In some embodiments, the gate spacer layer 256 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0028] In some embodiments, the gate electrode layer 254 comprises one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride, tungsten nitride, titanium-aluminum alloy, titanium-aluminum nitride, tantalum carbonitride, tantalum carbide, silicon tantalum nitride, metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate electrode layer 254 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, other suitable methods, or combinations thereof.

[0029] Other conductive layers, such as work function metal layers, may also be formed in the gate structure 250, although they are not shown in the figure. In some embodiments, the n-type work function layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), silicon tantalum nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. In some embodiments, the p-type work function layer includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), molybdenum nitride (MoN), tungsten nitride (WN), ruthenium (Ru), or combinations thereof.

[0030] Source region N1 is located on body region PB and close to gate structure 250. In some embodiments, source region N1 has a second conductivity type. For example, when the first conductivity type is P-type, the second conductivity type is N-type, and source region N1 is N-type source region N1. Furthermore, semiconductor structure 500A may also include a pickup region P1 formed on body region PB and adjacent to source region N1. Pickup region P1 is in direct contact with source region N1. In some embodiments, pickup region P1 has a first conductivity type. For example, when the first conductivity type is P-type, pickup region P1 is P-type pickup region P1.

[0031] In some embodiments, the doping concentration of the pickup region P1 is greater than the doping concentration of the body region PB. In some embodiments, the doping concentration of the body region PB ranges from about 10¹³ / cm² to about 10¹⁴ / cm², while the doping concentration of the pickup region P1 ranges from 10¹⁴ / cm² to about 10¹⁵ / cm².

[0032] The drain region N2A is located adjacent to the drift region ND and opposite the body region PB. The opposite sidewalls of the drain region N2A are in contact with the drift region ND and the isolation feature 201-1 surrounding the drift region ND, body region PB, and drain region N2A. The bottom B3 of the drain region N2A is in contact with the first deep well region DPW. In some embodiments, the bottom B3 of the drain region N2A, the bottom B1 of the body region PB, and the bottom B2 of the drift region ND are in contact with different portions of the first deep well region DPW. In some embodiments, the interface between the drain region N2A and the first deep well region DPW (i.e., the bottom B3 of the drain region N2A), the interface between the body region PB and the first deep well region DPW (i.e., the bottom B1 of the body region PB), and the interface between the drift region ND and the first deep well region DPW (i.e., the bottom B2 of the drift region ND) are at the same level.

[0033] In some embodiments, the depth D-N2A of the drain region N2A is greater than the depth D-N1 of the source region N1. In some embodiments, the depth D-N2A of the drain region N2A may be the same as the depth of the body region PB and the drift region ND.

[0034] like Figure 1 and Figure 2 As shown, the bottom 201-1B of the isolation feature 201-1 surrounding the leak zone N2A is located below the interface between the leak zone N2A and the first deep well zone DPW (i.e., the bottom B3 of the leak zone N2A). Furthermore, the side surface 201-1S of the isolation feature 201-1 is adjacent to both the first deep well zone DPW and the leak zone N2A.

[0035] In some embodiments, the drain region N2A has a second conductivity type. For example, when the first conductivity type is P-type, the second conductivity type is N-type, and the drain region N2A is an N-type drain region N2A.

[0036] In some embodiments, the doping concentration of the drain region N2A is greater than the doping concentration of the drift region ND. In some embodiments, the doping concentration of the drift region ND is in the range of about 3*10¹² / cm² to about 6*10¹² / cm², while the doping concentration of the drain region N2A is in the range of 10¹⁴ / cm² to about 10¹⁵ / cm².

[0037] In some embodiments, the doping concentration of the drain region N2A is greater than or equal to the doping concentration of the source region N1.

[0038] The semiconductor structure 500A may further include a portion of the gate structure 250 and a portion of the gate spacer layer 256, as well as a silicide barrier layer 260 formed on the substrate 200. More specifically, the silicide barrier layer 260 covers the top surface of the gate electrode layer 254 of the gate structure 250 and the sidewall surface of the gate spacer layer 256. In some embodiments, the silicide barrier layer 260 is configured to block the deposition of a silicide layer.

[0039] In some embodiments, the silicide barrier layer 260 comprises an oxide or nitride, such as silicon dioxide, silicon oxynitride, silicon nitride, or other suitable materials. In some embodiments, the silicide barrier layer 260 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0040] like Figure 1 and Figure 2 As shown, the semiconductor structure 500A may further include guard rings GR1, GR2, and GR3 located in the peripheral active regions AP1, AP2, and AP3 of the substrate 200, respectively. The body region PB, drift region ND, first deep well region DPW, gate structure 250, source region N1, and drain region N2A are surrounded by guard ring GR1. Guard ring GR1 is surrounded by guard ring GR2. Furthermore, guard ring GR2 is surrounded by guard ring GR3. It should be noted that the number of guard rings is not limited to the disclosed embodiment.

[0041] In some embodiments, the guard ring GR1 includes a well zone PW1 and a pickup zone P2. The well zone PW1 is located adjacent to the first deep well zone DPW. In some embodiments, the interface between the leak zone N2A and the first deep well zone DPW (i.e., the bottom B3 of the leak zone N2A) is located above the bottom 201-1B of the isolation feature 201-1. Therefore, the well zone PW1 is separated from the leak zone N2A by the isolation feature 201-1 and the first deep well zone DPW. The pickup zone P2 is located on the well zone PW. Furthermore, the pickup zone P2 is separated from the leak zone N2A by the isolation feature 201-1.

[0042] In some embodiments, both well region PW1 and pickup region P2 have a first conductivity type. For example, when the first conductivity type is P-type, well region PW1 is a P-type well region PW1, and pickup region P2 is a P-type pickup region P2. In some embodiments, the doping concentration of pickup region P2 is greater than the doping concentration of well region PW1. In some embodiments, the doping concentration of body region PB is greater than the doping concentration of well region PW1. In some embodiments, the doping concentration of pickup region P1 is equal to the doping concentration of pickup region P2. In some embodiments, the doping concentration of pickup region P2 is in the range of 10¹⁴ / cm² to about 10¹⁵ / cm². In some embodiments, the doping concentration of well region PW1 is in the range of about 1*10¹² / cm² to about 2*10¹² / cm².

[0043] In some embodiments, the guard ring GR2 includes a well zone NW1 and a pickup zone N3. The well zone NW1 may surround a well zone PW1. The well zone NW1 is separated from the well zone PW1. The pickup zone N3 is located on the well zone NW. Furthermore, the pickup zone N3 is separated from the leak zone N2A by isolation feature 201-2.

[0044] In some embodiments, both well region NW1 and pickup region N3 have a second conductivity type. For example, when the first conductivity type is P-type, the second conductivity type is N-type, well region NW1 is an N-type well region NW1, and pickup region N3 is an N-type pickup region N3. In some embodiments, the doping concentration of pickup region N3 is greater than the doping concentration of well region NW1. In some embodiments, the doping concentration of drift region ND is greater than the doping concentration of well region NW1. In some embodiments, the doping concentration of source region N1 is equal to the doping concentration of pickup region N3. In some embodiments, the doping concentration of pickup region N3 ranges from 10¹⁴ / cm² to about 10¹⁵ / cm². In some embodiments, the doping concentration of well region NW1 ranges from about 1*10¹² / cm² to about 2*10¹² / cm².

[0045] like Figure 2 As shown, the semiconductor structure 500A may further include a second deep well region DNW. The second deep well region DNW is located in the substrate 200 and below the first deep well region DPW and guard rings GR1 and GR2. The second deep well region DNW is configured to connect to well region NW1 of guard ring GR2.

[0046] In some embodiments, the bottom B4 of the first deep well zone DPW, the bottom B5 of the well zone PW1 of the guard ring GR1, and the bottom B6 of the well zone NW1 of the guard ring GR2 are in contact with different portions of the second deep well zone DNW. In some embodiments, the interface between the first deep well zone DPW and the second deep well zone DNW (i.e., the bottom B4 of the first deep well zone DPW), the interface between well zone PW1 and the second deep well zone DNW (i.e., the bottom B5 of well zone PW1), and the interface between well zone NW1 and the second deep well zone DNW (i.e., the bottom B6 of well zone NW1) are substantially at the same level. Figure 2 As shown, the interface PS1 between the first deep well zone DPW and well zone PW1 is directly located above the second deep well zone DNW.

[0047] In some embodiments, the second deep well zone DNW has a second conductivity type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the second deep well zone DNW is an N-type deep well zone DNW.

[0048] like Figure 2 As shown, the semiconductor structure 500A may further include an intrinsically doped region NTN-1. The intrinsically doped region NTN-1 is a region of the substrate 200, surrounded by guard rings GR1 and GR2, isolation feature 201-2, and a second deep well region DNW. The upper portion of well region NW1 is separated from the upper portion of well region PW1 by isolation feature 201-2. Furthermore, the lower portion of well region NW1 is separated from the lower portion of well region PW1 by the intrinsically doped region NTN-1. In some embodiments, the intrinsically doped region NTN-1 and the substrate 200 have the same conductivity type and doping concentration.

[0049] In some embodiments, the well region PW1 of the guard ring GR1, the intrinsic doped region NTN-1, and the well region NW1 of the guard ring GR2 can together form a parasitic PiN diode with reduced junction capacitance (i.e., depletion capacitance), increased junction resistance, and high breakdown voltage due to the large depletion region of the P-type intrinsic doped region NTN-1.

[0050] In some embodiments, the guard ring GR3 includes a well zone PW2 and a pickup zone P3. Well zone PW2 is located adjacent to the first deep well zone DPW. Furthermore, well zone PW2 is separated from well zone NW1. Pickup zone P3 is located on well zone PW2. Furthermore, pickup zone P3 is separated from pickup zone N3 by isolation features 201-3 surrounding the guard ring GR2.

[0051] In some embodiments, both well region PW2 and pickup region P3 have a first conductivity type. For example, when the first conductivity type is P-type, well region PW2 is a P-type well region PW2, and pickup region P3 is a P-type pickup region P3. In some embodiments, the doping concentration of pickup region P3 is greater than the doping concentration of well region PW2. In some embodiments, the doping concentration of body region PB is greater than the doping concentration of well region PW2. In some embodiments, the doping concentration of pickup region P1 is equal to the doping concentration of pickup region P3.

[0052] In some embodiments, the doping concentration of well region PW1 is equal to the doping concentration of well region PW2. The doping concentration of pickup region P2 is equal to the doping concentration of pickup region P3.

[0053] In some embodiments, the doping concentration of the pickup region P3 ranges from 10¹⁴ / cm² to about 10¹⁵ / cm². In some embodiments, the doping concentration of the well region PW2 ranges from about 1*10¹² / cm² to about 2*10¹² / cm².

[0054] In some embodiments, guard rings GR1, GR2 and GR3 may be connected to a ground (GND) terminal (not shown).

[0055] like Figure 2 As shown, the region in substrate 200 located between well region NW1 of guard ring GR2 and well region PW2 of guard ring GR3 can also be considered as intrinsic doped region NTN-2. In other words, the upper part of well region NW1 is separated from the upper part of well region PW2 by isolation feature 201-3. Furthermore, the lower part of well region NW1 is separated from the lower part of well region PW2 by intrinsic doped region NTN-2. Since intrinsic doped region NTN-2 is a region of substrate 200, intrinsic doped region NTN-2 and substrate 200 have the same conductivity type and doping concentration.

[0056] In some embodiments, the well region NW1 of the guard ring GR2, the intrinsic doped region NTN-2, and the well region PW2 of the guard ring GR3 can together form a parasitic PiN diode with reduced junction capacitance (i.e., depletion capacitance), increased junction resistance, and high breakdown voltage due to the large depletion region of the P-type intrinsic doped region NTN-2.

[0057] In semiconductor structure 500A, the drain region N2A, having a second conductivity type, can extend downwards to the first deep well region DPW, having a first conductivity type, to form a PN junction. Furthermore, the doping concentration of the drain region N2A is higher than that of the drift region ND, which has a second conductivity type. The breakdown voltage of the PN junction between the drain region N2A and the first deep well region DPW is lower than that between the drift region ND and the first deep well region DPW. When semiconductor structure 500A operates at high voltage, the PN junction between the drain region N2A and the first deep well region DPW is more prone to breakdown, thus forming a current path (breakdown path) PH1 through the drain region N2A and the first deep well region DPW, and releasing the high current from the gate dielectric layer 252 through the guard ring GR1. Therefore, the design of the drain region N2A protects the gate structure 250 of the transistor in the central active region AC. When semiconductor structure 500A operates at high voltage, damage to the gate dielectric layer 252 of the transistor in the central active region AC can be prevented.

[0058] Figure 3 According to some embodiments of the present invention, along Figure 1 A schematic cross-sectional view of semiconductor structure 500B along the midline A-A'. For simplicity, [the following is omitted as it is not part of the original text]. Figure 1 and Figure 2 Elements of the same or similar embodiments described herein will not be repeated here. Figures 1 to 2 As shown, the difference between semiconductor structure 500A and semiconductor structure 500B includes at least the fact that the drain region N2B of semiconductor structure 500B comprises multiple sub-parts SB1 and SB2. It should be noted that the number of sub-parts of the drain region N2B is not limited to the disclosed embodiments.

[0059] like Figure 3 As shown, sub-parts SB1 and SB2 are arranged side-by-side along direction D120 (also known as the vertical direction), which is perpendicular to the top surface 200T of substrate 200. Sub-part SB1 may contact sub-part SB2. More specifically, the bottom B4-1 of sub-part SB1 may contact the top T4-2 of sub-part SB2. Furthermore, the bottom B4-2 of sub-part SB2 may contact the first deep well region DPW.

[0060] Sub-parts SB1 and SB2 of the leak region N2B are located adjacent to the drift region ND and opposite the body region PB. The opposing sidewalls of each sub-part SB1 and SB2 are in contact with the drift region ND and the isolation feature 201-1 surrounding the drift region ND, the body region PB, and the leak region N2B. In some embodiments, the bottom B4-2 of sub-part SB2, the bottom B1 of the body region PB, and the bottom B2 of the drift region ND are in contact with different portions of the first deep well region DPW. In some embodiments, the interface between the leak region N2B and the first deep well region DPW (i.e., the bottom B4-2 of sub-part SB2), the interface between the body region PB and the first deep well region DPW (i.e., the bottom B1 of the body region PB), and the interface between the drift region ND and the first deep well region DPW (i.e., the bottom B2 of the drift region ND) are at the same level.

[0061] In direction D120, depending on the design of the device's electrical performance (e.g., breakdown voltage), the depth D-SB1 of sub-section SB1 may be the same as or different from the depth D-SB2 of sub-section SB2. In some embodiments, the depth of drain region N2B (i.e., the sum of depths D-SB1 and D-SB2) is greater than the depth D-N1 of source region N1. In some embodiments, the depth D-N2B of drain region N2B may be the same as the depth of body region PB and the depth of drift region ND.

[0062] like Figure 1 and Figure 3 As shown, the bottom 201-1B of the isolation feature 201-1 surrounding the drain region N2B is located below the interface between the drain region N2B and the first deep well region DPW (i.e., the bottom B4-2 of the drain region N2B). Furthermore, the side surface 201-1S of the isolation feature 201-1 is adjacent to both the first deep well region DPW and the drain region N2B.

[0063] In some embodiments, sub-parts SB1 and SB2 of the drain region N2B have a second conductivity type. For example, when the first conductivity type is P-type and the second conductivity type is N-type, the sub-parts SB1 and SB2 of the drain region N2B are N-type sub-parts SB1 and SB2.

[0064] In some embodiments, the doping concentration of sub-regions SB1 and SB2 of the drain region N2B is greater than the doping concentration of the drift region ND. In some embodiments, the doping concentration of the drift region ND ranges from approximately 3*10¹² / cm² to approximately 6*10¹² / cm², while the doping concentration of the drain region N2B ranges from 10¹⁴ / cm² to approximately 10¹⁵ / cm².

[0065] In some embodiments, the sub-regions SB1 and SB2 of the drain region N2B can have different doping concentrations depending on the design of the device's electrical properties (e.g., breakdown voltage). For example, the doping concentration of sub-regions SB1 and SB2 can gradually decrease towards the first deep well region DPW.

[0066] In some embodiments, the doping concentration of at least one sub-region SB1 and SB2 of the drain region N2B is greater than or equal to the doping concentration of the source region N1.

[0067] In semiconductor structure 500B, sub-parts SB1 and SB2 of the drain region N2B having a second conductivity type can extend downward to the first deep well region DPW having a first conductivity type to form a PN junction. Furthermore, the doping concentration of the sub-parts SB1 and SB2 of the drain region N2B is higher than that of the drift region ND having a second conductivity type. The breakdown voltage of the PN junction between the sub-parts SB1 and SB2 of the drain region N2B and the first deep well region DPW is lower than the breakdown voltage of the PN junction between the drift region ND and the first deep well region DPW. When semiconductor structure 500B operates at high voltage, the PN junction between the sub-parts SB1 and SB2 of the drain region N2B and the first deep well region DPW is more prone to breakdown, thereby forming a current path (breakdown path) PH2 through the sub-parts SB1 and SB2 of the drain region N2B and the first deep well region DPW, and guiding the high current out from the gate dielectric layer 252 (and the PN junction between the drift region ND and the first deep well region DPW) through the guard ring GR1. Therefore, the design of sub-parts SB1 and SB2 of the drain region N2B protects the gate structure 250 of the transistor in the central active region AC. When the semiconductor structure 500B operates at high voltage, damage to the gate dielectric layer 252 of the transistor in the central active region AC can be prevented.

[0068] In some embodiments, the semiconductor structure 500 can be used as a switching device for a buck converter.

[0069] Figure 4 This is a circuit diagram of a buck converter 600, which includes some embodiments according to the present invention. Figure 1 , Figure 2 and Figure 3 Semiconductor structures 500A and 500B are shown in the figures. In some embodiments, the buck converter 600 includes a buck controller 610, a low-voltage side (LS) device 620, a high-voltage side (HS) device 630, an inductor 640, resistors 650 and 660, and a capacitor 670. In some embodiments, the buck controller 610, the low-voltage side (LS) device 620, the high-voltage side (HS) device 630, the inductor 640, the resistors 650 and 660, and the capacitor 670 are integrated on a single integrated circuit semiconductor substrate, for example... Figure 2 and Figure 3 The substrate 200 shown.

[0070] The buck controller 610 is connected (coupled) between the input terminal Vin and the ground terminal GND. The low-voltage side (LS) device 620 and the high-voltage side (HS) device 630 are connected (coupled) to the buck controller 610. The low-voltage side (LS) device 620 and the high-voltage side (HS) device 630 are connected in series. Furthermore, the low-voltage side (LS) device 620 and the high-voltage side (HS) device 630 are connected (coupled) between the input terminal Vin and the ground terminal GND.

[0071] In some embodiments, the high-voltage side (HS) device 630 comprises transistors of semiconductor structure 500 (including semiconductor structures 500A and 500B). The transistors of semiconductor structure 500 include a gate structure 250, a drain region N2A (or drain region N2B), and a source region N1.

[0072] In some embodiments, the drain region N2A (or drain region N2B) of the high-voltage-side (HS) device 630 is connected (coupled) to the input terminal Vin. The gate structure 250 of the high-voltage-side (HS) device 630 is connected (coupled) to the buck controller 610. The source region N1 of the high-voltage-side (HS) device 630 is connected (coupled) to the low-voltage-side (LS) device 620 and the inductor 640.

[0073] Inductor 640 is connected (coupled) to the output terminal Vout and connected to ground GND via capacitor 670. Furthermore, inductor 640 is connected (coupled) to ground GND via resistors 650 and 660 connected in series (also referred to as feedback resistors 650 and 660). Additionally, resistor 650 is connected (coupled) between the output terminal Vout and the feedback terminal VFB of the buck controller 610. Resistor 660 is connected (coupled) between the feedback terminal VFB of the buck controller 610 and ground GND.

[0074] When a high input voltage is applied to the input terminal Vin, the PN junction between the drain region N2A (or the sub-parts SB1 and SB2 of the drain region N2B) and the first deep well region DPW is more prone to breakdown, thus forming a PN junction between the drain region N2A (or the sub-parts SB1 and SB2 of the drain region N2B) and the first deep well region DPW. Figure 2 The current path PH1 (or Figure 3 The high current is guided out of the gate dielectric layer 252 via the current path PH2 and the guard ring GR1. Therefore, the gate structure 250 of the high-voltage side (HS) device 630 is protected by the design of the drain region N2A (or sub-parts SB1 and SB2 of the drain region N2B). When the high-voltage side (HS) device 630 receives a high voltage from the input terminal Vin, damage to the gate dielectric layer 252 of the high-voltage side (HS) device 630 can be prevented.

[0075] In some embodiments, the low-voltage side (LS) device 620 is also composed of transistors of semiconductor structure 500 (including semiconductor structures 500A and 500B). The transistors of semiconductor structure 500 include gate structure 250, drain region N2A (or drain region N2B) and source region N1.

[0076] In some embodiments, the drain region N2A (or drain region N2B) of the low-voltage side (LS) device 620 is connected (coupled) to the source region N1 of the high-voltage side (HS) device 630. The gate structure 250 of the low-voltage side (LS) device 620 is connected (coupled) to the buck controller 610. The source region N1 of the low-voltage side (LS) device 620 is connected (coupled) to ground GND.

[0077] When the low-voltage (LS) device 620 operates at a high voltage, the PN junction between the drain region N2A (or sub-regions SB1 and SB2 of the drain region N2B) and the first deep-well region DPW is more prone to breakdown, forming a PN junction through the drain region N2A (or sub-regions SB1 and SB2 of the drain region N2B) and the first deep-well region DPW. Figure 2 The current path PH1 (or Figure 3 The high current is released from the gate dielectric layer 252 through the protection ring GR1 via the current path PH2. Therefore, the gate structure 250 of the low-voltage (LS) device 620 is protected by the design of the drain region N2A (or sub-parts SB1 and SB2 of the drain region N2B). This prevents damage to the gate dielectric layer 252 of the low-voltage (LS) device 620 when it operates at a high voltage.

[0078] Embodiments of the present invention provide a semiconductor structure (e.g., an LDMOS transistor). The semiconductor structure includes a substrate, a body region, a drift region, a first deep well region, a gate structure, a source region, and a drain region. The body region is located in the substrate. The body region has a first conductivity type. The drift region is located in the substrate and adjacent to the body region. The drift region has a second conductivity type different from the first conductivity type. The first deep well region is located in the substrate and below the body region and the drift region. The first deep well region has a first conductivity type. The gate structure is located on the drift region and adjacent to the body region. The source region is located on the body region. The source region has a second conductivity type. The drain region is located adjacent to the drift region and in contact with the first deep well region. The drain region has a second conductivity type. By optimizing the injection and layout of the drain region (e.g., drain N2), drift region (e.g., drift ND), and first deep well region (e.g., first deep well region DPW), the breakdown path through the vertical PN junction (from (e.g., drain N2) to the first deep well region (e.g., first deep well region DPW)) can be effectively controlled, thereby preventing damage to semiconductor structures (e.g., semiconductor structures 500A and 500B).

[0079] In some embodiments, the drift region, body region, and leak region are in contact with different portions of the first deep well region.

[0080] In some embodiments, the first interface between the leak zone and the first deep well zone and the second interface between the drift zone and the first deep well zone are at the same level.

[0081] In some embodiments, the first interface between the leak zone and the first deep well zone and the third interface between the body zone and the first deep well zone are at the same level.

[0082] In some embodiments, the drain region includes sub-regions arranged side-by-side along a direction perpendicular to the top surface of the substrate. The sub-regions have different doping concentrations.

[0083] In some embodiments, the doping concentration of the sub-parts gradually decreases toward the first deep well region.

[0084] In some embodiments, the semiconductor structure further includes a first isolation feature surrounding the drift region, the body region, and the drain region. The bottom of the first isolation feature is located below a second interface between the drift region and the first deep well region.

[0085] In some embodiments, the side surface of the first isolation feature is adjacent to the first deep well area and the leak area.

[0086] In some embodiments, the first depth of the drain region is greater than the second depth of the source region.

[0087] In some embodiments, the semiconductor structure further includes a first guard ring and a second guard ring. The first guard ring is located in the substrate and surrounds a first deep well region, a drift region, a body region, and a drain region. The first guard ring includes a first well region and a first pickup region. The first well region has a first conductivity type. The first pickup region is located on the first well region. The first pickup region has a first conductivity type. The second guard ring is located in the semiconductor substrate and surrounds the first guard ring. The second guard ring includes a second well region and a second pickup region. The second well region has a second conductivity type. The second pickup region is located on the second well region, wherein the second pickup region has a second conductivity type.

[0088] In some embodiments, the first pickup area is separated from the leak area by a first isolation feature.

[0089] In some embodiments, the semiconductor structure further includes a second isolation feature, a second deep well region, and a first intrinsically doped region. The second isolation feature surrounds a first guard ring. A first pickup region is separated from a second pickup region by the second isolation feature. The second deep well region is located in the substrate and below the first deep well region, the first guard ring, and the second guard ring. The second deep well region has a second conductivity type. The first intrinsically doped region is surrounded by the first guard ring, the second guard ring, the second isolation feature, and the second deep well region. The first intrinsically doped region and the substrate have the same conductivity type and doping concentration.

[0090] In some embodiments, the semiconductor structure further includes a third guard ring and a third isolation feature. The third guard ring is located in the substrate and surrounds the second guard ring. The third guard ring includes a third well region and a third pickup region. The third well region is separated from the second well region and has a first conductivity type. The third pickup region is located on the third well region. The third pickup region has a first conductivity type. The third isolation feature surrounds the second guard ring. The second pickup region is separated from the third pickup region by the third isolation feature.

[0091] Embodiments of the present invention provide a buck converter. The buck converter includes a buck controller, a low-voltage (LS) device, and a high-voltage (HS) device. The low-voltage (LS) device is connected to the buck controller. The high-voltage (HS) device is connected to the buck controller. The high-voltage (HS) device comprises a first semiconductor structure including a substrate, a body region, a drift region, a first deep-well region, a gate structure, a source region, and a drain region. The body region is located in the substrate. The body region has a first conductivity type. The drift region is located in the substrate and adjacent to the body region. The drift region has a second conductivity type different from the first conductivity type. The first deep-well region is located in the substrate and below the body region and the drift region. The first deep-well region has a first conductivity type. The gate structure is located on the drift region and adjacent to the body region. The source region is located on the body region. The source region has a second conductivity type. The drain region is located adjacent to the drift region and in contact with the first deep-well region. The drain region has a second conductivity type.

[0092] In some embodiments, the low-voltage (LS) device consists of a second semiconductor structure identical to the first semiconductor structure.

[0093] In some embodiments, the drain region of the high-voltage (HS) device is connected to the input.

[0094] In some embodiments, the gate structure of the high-voltage (HS) device is connected to a buck controller.

[0095] In some embodiments, the source region of the high-voltage (HS) device is connected to the low-voltage (LS) device and an inductor. In some embodiments, the inductor is connected to the output (Vout) and to ground via a capacitor. In some embodiments, the inductor is connected to ground via a resistor. In some embodiments, the high-voltage (HS) device and the low-voltage (LS) device are connected in series between the input and ground. In some embodiments, the buck controller is connected between the input and ground.

[0096] While the invention has been described by way of examples and preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements. Therefore, the scope of the claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor structure, comprising: A substrate; A bulk region located in the substrate, wherein the bulk region has a first conductivity type; A drift region located in the substrate and adjacent to the bulk region, wherein the drift region has a second conductivity type different from the first conductivity type; A first deep well region located in the substrate and below the bulk region and the drift region, wherein the first deep well region has the first conductivity type; A gate structure located on and adjacent to the body region in the drift region; A source region located on the body region, wherein the source region has the second conductivity type; And a drain region located adjacent to the drift region and in contact with the first deep well region, wherein the drain region has the second conductivity type.

2. The semiconductor structure of claim 1, wherein the drift region, the body region, and the drain region are in contact with different portions of the first deep well region.

3. The semiconductor structure of claim 2, wherein the first interface between the drain region and the first deep well region and the second interface between the drift region and the first deep well region are at the same level.

4. The semiconductor structure of claim 2, wherein the first interface between the drain region and the first deep well region and the third interface between the body region and the first deep well region are at the same level.

5. The semiconductor structure of claim 2, wherein the drain region comprises sub-parts arranged side-by-side along a direction perpendicular to the top surface of the substrate, and the sub-parts have different doping concentrations.

6. The semiconductor structure of claim 5, wherein the doping concentration of the sub-part gradually decreases toward the first deep well region.

7. The semiconductor structure of claim 2, further comprising: A first isolation feature surrounds the drift region, the body region, and the leak region, wherein the bottom of the first isolation feature is located below a second interface between the drift region and the first deep well region.

8. The semiconductor structure of claim 7, wherein the side surface of the first isolation feature is adjacent to the first deep well region and the drain region.

9. The semiconductor structure of claim 1, wherein the first depth of the drain region is greater than the second depth of the source region.

10. The semiconductor structure of claim 7, further comprising: A first protective ring located in the substrate and surrounding the first deep well region, the drift region, the body region, and the drain region, wherein the first protective ring comprises: A first well region, wherein the first well region has the first conductivity type; And a first pickup area located on the first well area, wherein the first pickup area has the first conductivity type; And a second protective ring located in the semiconductor substrate and surrounding the first protective ring, wherein the second protective ring comprises: A second well region, wherein the second well region has the second conductivity type; And a second pickup area located on the second well area, wherein the second pickup area has the second conductivity type.

11. The semiconductor structure of claim 10, wherein the first pickup region is separated from the drain region by the first isolation feature.

12. The semiconductor structure of claim 10, further comprising: A second isolation feature surrounding the first protective ring, wherein the first pickup area is separated from the second pickup area by the second isolation feature; A second deep well region located in the substrate and below the first deep well region, the first guard ring, and the second guard ring, wherein the second deep well region has the second conductivity type; And a first intrinsically doped region surrounded by the first guard ring, the second guard ring, the second isolation feature and the second deep well region, wherein the first intrinsically doped region and the substrate have the same conductivity type and doping concentration.

13. The semiconductor structure of claim 12, further comprising: The third protective ring is located in the substrate and surrounds the second protective ring, wherein the third protective ring includes: A third well region, distinct from the second well, wherein the third well region has the first conductivity type; and A third pickup region located on the third well region, wherein the third pickup region has the first conductivity type; and A third isolation feature surrounding the second protection ring, wherein the second pickup area is separated from the third pickup area by the third isolation feature.

14. A buck converter, comprising: Step-down controller; Low-voltage devices connected to the buck controller; and A high-voltage device connected to the buck controller, wherein the high-voltage device comprises a first semiconductor structure including the following: substrate; A body region located in the substrate, wherein the body region has a first conductivity type; A drift region located in the substrate and adjacent to the body region, wherein the drift region has a second conductivity type different from the first conductivity type; A first deep well region located in the substrate and below the body region and the drift region, wherein the first deep well region has the first conductivity type; The gate structure located on and adjacent to the body region in the drift region; A source region located on the body region, wherein the source region has the second conductivity type; as well as A drain region located adjacent to the drift region and in contact with the first deep well region, wherein the drain region has the second conductivity type.

15. The buck converter of claim 14, wherein the low-voltage device comprises a second semiconductor structure identical to the first semiconductor structure.

16. The buck converter of claim 14, wherein the drain region of the high-voltage device is connected to the input, the gate structure of the high-voltage device is connected to the buck controller, and the source region of the high-voltage device is connected to the low-voltage device and an inductor.

17. The buck converter of claim 16, wherein the inductor is connected to the output terminal and connected to ground via a capacitor.

18. The buck converter of claim 16, wherein the inductor is connected to the ground terminal via a resistor.

19. The buck converter of claim 14, wherein the high-voltage device and the low-voltage device are connected in series between the input terminal and ground.

20. The buck converter of claim 14, wherein the buck controller is connected between the input terminal and ground.

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