Lateral double-diffused field-effect transistor, fabrication method, chip and circuit

Abstract

This invention provides a lateral double-diffused field-effect transistor, its fabrication method, chip, and circuit, relating to the field of semiconductor technology. The transistor includes: a base substrate; a first transistor and a second transistor having the same carrier type, the first transistor being formed downwards on the back side of the base substrate, and the second transistor being formed upwards on the front side of the base substrate; and an intermediate sandwich structure formed laterally between a first body region and a first drift region and vertically between the first transistor and the second transistor. The intermediate sandwich structure, from bottom to top, includes a first oxide layer, an intermediate polysilicon layer, and a second oxide layer. The intermediate sandwich structure includes a first sandwich structure formed between the two body regions and part of the drift region, and a second sandwich structure formed between the remaining drift regions. The second sandwich structure serves as a third field plate for the first transistor and a fourth field plate for the second transistor. This invention can improve the transistor's operating current, reduce the transistor area, and improve the breakdown voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a lateral double-diffused field-effect transistor, a method for fabricating a lateral double-diffused field-effect transistor, a chip, and a circuit. Background Technology

[0002] Lateral double-diffused MOSFETs (LDMOS) are a type of lateral power device whose electrodes are all located on the device surface. They are easy to integrate with low-voltage signal circuits and other devices through internal connections. At the same time, they have advantages such as high voltage withstand capability, high gain, good linearity, high efficiency, and good broadband matching performance. They are now widely used in power integrated circuits, especially power management chips.

[0003] In the prior art, the lateral double-diffused field-effect transistor provides a small operating current under high operating voltage, resulting in low power output per unit device area. To meet the same operating current requirement, a larger device area is needed, leading to high production costs. Summary of the Invention

[0004] To address the technical problems of existing lateral double-diffused field-effect transistors (LDFETs) such as low operating current, low power output per unit area, and the need for larger device areas and high production costs for the same operating current, this invention provides a lateral double-diffused field-effect transistor, a method for fabricating a lateral double-diffused field-effect transistor, a chip, and a circuit. Using this lateral double-diffused field-effect transistor can increase the transistor's operating current, increase the power output per unit area, improve power density, enhance driving capability, thereby better driving loads, enhancing signal transmission capability, increasing transistor switching speed, reducing transistor area, increasing integration density, increasing breakdown voltage, and improving device stability and reliability for the same operating current requirements.

[0005] To achieve the above objectives, a first aspect of the present invention provides a lateral double-diffused field-effect transistor, comprising: a base substrate; a first transistor and a second transistor having the same carrier type, wherein a first gate and a first field plate of the first transistor are formed downward on the back side of the base substrate, and a second gate and a second field plate of the second transistor are formed upward on the front side of the base substrate; wherein the first transistor comprises: a first body region, a first drift region, a first source, a first drain, a first gate, and a first field plate, the first gate is formed on the lower surface of the first body region and a portion of the first drift region, and the first field plate is formed on the lower surface of the remaining portion of the first drift region; the second transistor comprises: a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate. The second gate is formed on the upper surface of the second body region and a portion of the second drift region, and the second field plate is formed on the upper surface of the remaining second drift region; an intermediate sandwich structure is formed laterally in the intermediate region between the first body region and the first drift region and longitudinally between the first transistor and the second transistor, the intermediate sandwich structure being composed of a first oxide layer, an intermediate polysilicon layer and a second oxide layer from bottom to top, the intermediate sandwich structure including a first sandwich structure formed between the first body region and the second body region and between a portion of the first drift region and a portion of the second drift region and a second sandwich structure formed between the remaining portion of the first drift region and the remaining portion of the second drift region, the second sandwich structure serving as the third field plate of the first transistor and the fourth field plate of the second transistor.

[0006] Furthermore, the first body region of the first transistor and the second body region of the second transistor are located on the same side of the base substrate, and the first drift region of the first transistor and the second drift region of the second transistor are located on the same side of the base substrate.

[0007] Furthermore, the thickness of the intermediate polysilicon layer in the first sandwich structure is greater than the thickness of the intermediate polysilicon layer in the second sandwich structure, and the first sandwich structure serves as the third gate of the first transistor and the fourth gate of the second transistor.

[0008] Furthermore, the first source electrode is formed on the side of the first body region away from the first drift region, the first drain electrode is formed on the side of the first drift region away from the first body region, the second source electrode is formed on the side of the second body region away from the second drift region, and the second drain electrode is formed on the side of the second drift region away from the second body region.

[0009] Furthermore, the lateral double-diffused field-effect transistor further includes: a first metal electrode extending upward from the first source to the upper surface of the base substrate; a second metal electrode extending upward from the first drain to the upper surface of the base substrate; a third metal electrode extending downward from the first gate to the lower surface of the base substrate; a fourth metal electrode extending upward from the second source to the upper surface of the base substrate; a fifth metal electrode extending upward from the second drain to the upper surface of the base substrate; a sixth metal electrode extending upward from the second gate to the upper surface of the base substrate; and a dielectric layer formed between the first metal electrode and the fourth metal electrode, between the fourth metal electrode and the sixth metal electrode, between the sixth metal electrode and the fifth metal electrode, and between the fifth metal electrode and the second metal electrode.

[0010] Furthermore, the lateral double-diffused field-effect transistor also includes a seventh metal electrode, which is led upward from the middle polysilicon layer of the first sandwich structure to the upper surface of the base substrate.

[0011] Furthermore, the first body region is arranged adjacent to the first drift region, and the second body region is arranged adjacent to the second drift region.

[0012] A second aspect of the present invention provides a method for fabricating a lateral double-diffused field-effect transistor (LDFET). The method includes: forming a base substrate; forming a first transistor and a second transistor having the same carrier type within the base substrate; and forming an intermediate sandwich structure laterally formed between a first body region and a first drift region of the first transistor and longitudinally formed between the first transistor and the second transistor; wherein the first gate and a first field plate of the first transistor are formed downwards on the back side of the base substrate, the second gate and the second field plate of the second transistor are formed upwards on the front side of the base substrate, and the first body region of the first transistor and the second body region of the second transistor are located on the same side of the base substrate, and the first drift region of the first transistor and the second drift region of the second transistor are located on the same side of the base substrate; wherein the first transistor includes: a first body region, a first drift region, a first source, and a second drift region. The transistor comprises a drain, a first gate, and a first field plate. The first gate is formed on the lower surface of the first body region and a portion of the first drift region, and the first field plate is formed on the lower surface of the remaining portion of the first drift region. The second transistor comprises a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate. The second gate is formed on the upper surface of the second body region and a portion of the second drift region, and the second field plate is formed on the upper surface of the remaining portion of the second drift region. The intermediate sandwich structure consists of a first oxide layer, an intermediate polysilicon layer, and a second oxide layer from bottom to top. The intermediate sandwich structure includes a first sandwich structure formed between the first body region and the second body region and between a portion of the first drift region and a portion of the second drift region, and a second sandwich structure formed between the remaining portion of the first drift region and the remaining portion of the second drift region. The second sandwich structure serves as the third field plate of the first transistor and the fourth field plate of the second transistor.

[0013] Furthermore, the first body region of the first transistor and the second body region of the second transistor are located on the same side of the base substrate, and the first drift region of the first transistor and the second drift region of the second transistor are located on the same side of the base substrate.

[0014] Furthermore, the thickness of the intermediate polysilicon layer in the first sandwich structure is greater than the thickness of the intermediate polysilicon layer in the second sandwich structure, and the first sandwich structure serves as the third gate of the first transistor and the fourth gate of the second transistor.

[0015] Furthermore, the first source electrode is formed on the side of the first body region away from the first drift region, the first drain electrode is formed on the side of the first drift region away from the first body region, the second source electrode is formed on the side of the second body region away from the second drift region, and the second drain electrode is formed on the side of the second drift region away from the second body region.

[0016] Further, the step of forming a base substrate and forming a first transistor and a second transistor having a carrier type within the base substrate, as well as an intermediate sandwich structure laterally formed between the first body region and the first drift region and longitudinally formed between the first transistor and the second transistor, includes: forming a first substrate and forming a first body region, a first drift region, a first source, and a first drain of the first transistor on the first substrate; forming the intermediate sandwich structure on the upper surface of the first body region and the first drift region; forming a second substrate on the upper surface of the intermediate sandwich structure and forming the second transistor within the second substrate; wherein the base substrate includes the first substrate and the second substrate; and forming a first gate and a first field plate of the first transistor.

[0017] Further, the step of forming a first substrate and forming a first body region, a first drift region, a first source, and a first drain of the first transistor on the first substrate includes: providing a first sub-substrate and forming a stepped etch surface on the upper surface of the first sub-substrate; wherein the stepped etch surface includes a high-order etch surface and a low-order etch surface; forming a first silicon dioxide layer on the stepped etch surface, using the first silicon dioxide layer on the high-order etch surface as a first gate oxide layer, and using the first silicon dioxide layer on the low-order etch surface as a first field plate oxide layer; forming a second sub-substrate on the upper surface of the first silicon dioxide layer, and forming the first body region, the first drift region, the first source, and the first drain on the second sub-substrate; wherein the first substrate includes the first sub-substrate and the second sub-substrate.

[0018] Further, forming the intermediate sandwich structure on the upper surfaces of the first body region and the first drift region includes: forming a second silicon dioxide layer on the upper surfaces of the first body region and the first drift region; thinning a portion of the second silicon dioxide layer to form the first oxide layer; forming a first polysilicon layer on the upper surface of the first oxide layer; thinning a portion of the first polysilicon layer to form the intermediate polysilicon layer; wherein the thinned region of the first polysilicon layer is far from the thinned region of the second silicon dioxide layer; and forming the second oxide layer on the upper surface of the intermediate polysilicon layer.

[0019] Further, the formation of the first gate and the first field plate of the first transistor includes: thinning the first sub-substrate; heavily doping the thinned first sub-substrate to obtain a heavily doped silicon layer; using the heavily doped silicon layer and the first gate oxide layer as the first gate, and using the heavily doped silicon layer and the first field plate oxide layer as the first field plate.

[0020] Further, after forming the second transistor within the second substrate, the method further includes: forming a dielectric layer on the second substrate, the exposed intermediate sandwich structure, and the first substrate; forming contact holes within the dielectric layer, the contact holes contacting the first source, the first drain, the second source, the second drain, and the second gate, respectively; forming a first metal electrode, a second metal electrode, a fourth metal electrode, a fifth metal electrode, and a sixth metal electrode within the contact holes, respectively; wherein the first metal electrode extends upward from the first source to the upper surface of the base substrate; the second metal electrode extends upward from the first drain to the upper surface of the base substrate; the fourth metal electrode extends upward from the second source to the upper surface of the base substrate; the fifth metal electrode extends upward from the second drain to the upper surface of the base substrate; the sixth metal electrode extends upward from the second gate to the upper surface of the base substrate; and forming a third metal electrode on the lower surface of the first gate and the first field plate.

[0021] Furthermore, the contact hole is also connected to the intermediate polysilicon layer of the first sandwich structure; the method further includes: forming a seventh metal electrode in the contact hole that contacts the intermediate polysilicon layer of the first sandwich structure, the seventh metal electrode being led upward from the intermediate polysilicon layer of the first sandwich structure to the upper surface of the base substrate.

[0022] A third aspect of the present invention provides a chip comprising the lateral double-diffused field-effect transistor described above.

[0023] A fourth aspect of the present invention provides a circuit comprising the lateral double-diffused field-effect transistor described above.

[0024] The present invention has at least the following technical effects through the technical solution provided by the present invention: The lateral double-diffused field-effect transistor of the present invention includes a base substrate. A first gate and a first field plate of a first transistor are formed downward on the back side of the base substrate, and a second gate and a second field plate of a second transistor are formed upward on the front side of the base substrate. Two transistors are stacked on the base substrate, which can increase the overall operating current of the transistors, increase the power output per unit area, and reduce the transistor area and increase integration density under the same operating current requirements. The first transistor includes: a first body region, a first drift region, a first source, a first drain, a first gate, and a first field plate. The first gate is formed on the lower surface of the first body region and a portion of the first drift region, and the first field plate is formed on the lower surface of the remaining first drift region. The second transistor includes: a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate. The second gate is formed on the upper surface of the second body region and a portion of the second drift region, and the second field plate is formed on the upper surface of the remaining second drift region. An intermediate sandwich structure is formed between the first transistor and the second transistor, and the intermediate sandwich structure is formed in the longitudinal direction in the intermediate region between the first body region and the first drift region. The intermediate sandwich structure includes a first sandwich structure formed between the first body region and the second body region, and between a portion of the first drift region and a portion of the second drift region, and a second sandwich structure formed between the remaining first drift region and the remaining second drift region. The second sandwich structure serves as the third field plate of the first transistor and the fourth field plate of the second transistor, adding field plates to both transistors. This allows for better control of the electric field distribution within the two transistors, improving the transistor's breakdown voltage, reducing the influence of surface charge, improving charge transport characteristics, and enhancing the stability and reliability of the device. Therefore, the lateral double-diffused field-effect transistor provided by this invention can increase the transistor's operating current, increase the power output per unit area, increase power density, enhance driving capability, thereby better driving the load, enhancing signal transmission capability, increasing the transistor's switching speed, reducing the transistor area under the same operating current requirements, increasing integration density, increasing breakdown voltage, and improving the stability and reliability of the device.

[0025] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the structure of the first sub-substrate formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention. Figure 2This is a schematic diagram of the stepped etching surface formed after etching the first sub-substrate in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of the first gate oxide layer and the first field plate oxide layer formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 4 This is a schematic diagram of the structure of the second sub-substrate formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention. Figure 5 A schematic diagram of the structure of the first bulk region and the first drift region formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the first source and the second drain formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 7 A schematic diagram of the structure of the first oxide layer formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of the first polysilicon layer formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention. Figure 9 A schematic diagram of the structure of the intermediate polysilicon layer and the second oxide layer formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 10 A schematic diagram of the structure of the second substrate formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention; Figure 11 A schematic diagram of the structure of the initial second body region and the initial second drift region formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 12 A schematic diagram of the structure of the second body region and the second drift region formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 13 This is a schematic diagram of the structure of the second field plate oxide layer formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 14 This is a schematic diagram of the structure of the second gate oxide layer, the second polysilicon layer, the second source, and the second drain formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 15 A schematic diagram of the structure of the dielectric layer formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of the heavily doped silicon layer formed in the lateral double-diffusion field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 17 A schematic diagram of the contact hole formed in the method for fabricating a lateral double-diffused field-effect transistor according to an embodiment of the present invention; Figure 18 This is a schematic diagram of the structure of the lateral double-diffused field-effect transistor formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiments of the present invention.

[0027] Explanation of reference numerals in the attached figures 1-First sub-substrate; 2-First gate oxide layer; 3-First field plate oxide layer; 4-Second sub-substrate; 5-First body region; 6-First drift region; 7-First source; 8-First drain; 9-First oxide layer; 10-Intermediate polysilicon layer; 11-Second oxide layer; 12-Second substrate; 13-Initial second body region; 14-Initial second drift region; 15-Second body region; 16-Second drift region; 17-Second field plate oxide layer; 18-Second gate oxide layer; 19-Second polysilicon layer; 20-Second source; 21-Second drain; 22-Dielectric layer; 23-Heavily doped silicon layer; 24-Contact hole; 25-First metal electrode; 26-Second metal electrode; 27-Fourth metal electrode; 28-Fifth metal electrode; 29-Sixth metal electrode; 30-Seventh metal electrode; 31-Third metal electrode. Detailed Implementation

[0028] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0030] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used to describe the relative positions of components in relation to the directions shown in the accompanying drawings or in relation to the vertical, perpendicular, or gravitational directions.

[0031] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Please refer to Figure 18The first aspect of this invention provides a lateral double-diffused field-effect transistor, comprising: a base substrate; a first transistor and a second transistor having the same carrier type, wherein the first transistor's first gate and first field plate are formed downward on the back side of the base substrate, and the second transistor's second gate and second field plate are formed upward on the front side of the base substrate; wherein the first transistor comprises: a first body region 5, a first drift region 6, a first source 7, a first drain 8, a first gate, and a first field plate, wherein the first gate is formed on the lower surface of the first body region 5 and a portion of the first drift region 6, and the first field plate is formed on the lower surface of the remaining portion of the first drift region 6; the second transistor comprises: a second body region 15, a second drift region 16, a second source 20, a second drain 21, a second gate, and a second field plate. The second gate is formed on the upper surface of the second body region 15 and a portion of the second drift region 16, and the second field plate is formed on the upper surface of the remaining second drift region 16; an intermediate sandwich structure is formed laterally in the intermediate region between the first body region 5 and the first drift region 6 and longitudinally between the first transistor and the second transistor, the intermediate sandwich structure being composed of a first oxide layer 9, an intermediate polysilicon layer 10 and a second oxide layer 11 from bottom to top, the intermediate sandwich structure including a first sandwich structure formed between the first body region 5 and the second body region 15 and between a portion of the first drift region 6 and a portion of the second drift region 16 and a second sandwich structure formed between the remaining portion of the first drift region 6 and the remaining portion of the second drift region 16, the second sandwich structure serving as the third field plate of the first transistor and the fourth field plate of the second transistor.

[0033] Specifically, in this embodiment of the invention, the lateral double-diffused field-effect transistor includes a base substrate on which a first transistor and a second transistor of the same carrier type are formed, such as both being PLDMOS or both being NLDMOS. The first and second transistors are arranged vertically, with the first gate and first field plate of the first transistor formed downwards on the back side of the base substrate, and the second gate and second field plate of the second transistor formed upwards on the front side of the base substrate. Stacking two transistors on the base substrate increases the overall operating current of the transistor, increases the power output per unit area, improves power density, enhances driving capability, thereby better driving the load, enhances signal transmission capability, improves the switching speed of the transistor, and reduces the transistor area and increases integration density under the same operating current requirements.

[0034] The first transistor includes: a first body region 5, a first drift region 6, a first source 7, a first drain 8, a first gate, and a first field plate. The first gate is formed on the lower surface of the first body region 5 and the first drift region 6, and the first field plate is formed on the lower surface of the remaining first drift region 6. The second transistor includes: a second body region 15, a second drift region 16, a second source 20, a second drain 21, a second gate, and a second field plate. The second gate is formed on the upper surface of the second body region 15 and a portion of the second drift region 16, and the second field plate is formed on the upper surface of the remaining second drift region 16.

[0035] An intermediate sandwich structure is formed between the first transistor and the second transistor. The intermediate sandwich structure is formed laterally in the intermediate region between the first body region 5 and the first drift region 6, and vertically between the first transistor and the second transistor. The intermediate sandwich structure consists of a first oxide layer 9, an intermediate polysilicon layer 10, and a second oxide layer 11 from bottom to top. It includes a first sandwich structure and a second sandwich structure arranged laterally. The first sandwich structure is formed between the first body region 5 and the second body region 15 and between a portion of the first drift region 6 and a portion of the second drift region 16. The second sandwich structure is formed between the remaining portion of the first drift region 6 and the remaining portion of the second drift region 16. The second sandwich structure, serving as the third field plate of the first transistor and the fourth field plate of the second transistor, adds new field plate structures to both transistors. This reduces the electric field intensity in the drift or depletion regions of both transistors, optimizes the electric field distribution, prevents electric field breakdown, increases the breakdown voltage, reduces the influence of surface charge, improves the stability and reliability of the device, and improves charge transport in the transistor, making the movement of electrons or holes in the transistor more uniform. This improves the switching characteristics of the transistor, increases energy efficiency, and reduces the decrease in charge mobility caused by electric field concentration, thereby optimizing the performance of the transistor.

[0036] The lateral double-diffused field-effect transistor provided by this invention can increase the transistor's operating current, increase the power output per unit area, increase power density, enhance driving capability, thereby better driving the load, enhancing signal transmission capability, increasing the transistor's switching speed, reducing the transistor area under the same operating current requirements, increasing integration density, increasing breakdown voltage, and improving the stability and reliability of the device.

[0037] Furthermore, the lateral double-diffused field-effect transistor further includes: a first metal electrode 25, extending upward from the first source 7 to the upper surface of the base substrate; a second metal electrode 26, extending upward from the first drain 8 to the upper surface of the base substrate; a third metal electrode 31, extending downward from the first gate to the lower surface of the base substrate; a fourth metal electrode 27, extending upward from the second source 20 to the upper surface of the base substrate; a fifth metal electrode 28, extending upward from the second drain 21 to the upper surface of the base substrate; a sixth metal electrode 29, extending upward from the second gate to the upper surface of the base substrate; and a dielectric layer 22 formed between the first metal electrode 25 and the fourth metal electrode 27, between the fourth metal electrode 27 and the sixth metal electrode 29, between the sixth metal electrode 29 and the fifth metal electrode 28, and between the fifth metal electrode 28 and the second metal electrode 26.

[0038] Specifically, in this embodiment of the invention, a first metal electrode 25, a second metal electrode 26, a third metal electrode 31, a fourth metal electrode 27, a fifth metal electrode 28, and a sixth metal electrode 29 are respectively disposed on the first source 7, the first drain 8, the first gate, the second source 20, the second drain 21, and the second gate. The first metal electrode 25, the second metal electrode 26, the fourth metal electrode 27, the fifth metal electrode 28, and the fourth metal electrode 27 are led upwards to the upper surface of the base substrate, and the third metal electrode 31 is led downwards from the first gate to the lower surface of the base substrate. The first metal electrode 25 and the fourth metal electrode 27, as well as the second metal electrode 26 and the fifth metal electrode 28, can be interconnected or independently connected. The second sandwich structure serves as the third field plate of the first transistor and the fourth field plate of the second transistor, and can be connected to the metal electrodes led to the upper surface of the base substrate or not connected to the metal electrodes.

[0039] Furthermore, the first body region 5 of the first transistor and the second body region 15 of the second transistor are located on the same side of the base substrate, and the first drift region 6 of the first transistor and the second drift region 16 of the second transistor are located on the same side of the base substrate.

[0040] Specifically, in the embodiments of the present invention, the first body region 5 of the first transistor and the second body region 15 of the second transistor are located on the same side of the base substrate, and the first drift region 6 of the first transistor and the second drift region 16 of the second transistor are located on the same side of the base substrate. This facilitates the fabrication of transistors and improves fabrication efficiency.

[0041] Furthermore, the thickness of the intermediate polysilicon layer 10 in the first sandwich structure is greater than the thickness of the intermediate polysilicon layer 10 in the second sandwich structure, and the first sandwich structure serves as the third gate of the first transistor and the fourth gate of the second transistor.

[0042] Specifically, in this embodiment of the invention, the thickness of the intermediate polysilicon layer 10 of the first sandwich structure is greater than the thickness of the intermediate polysilicon layer 10 of the second sandwich structure. The first sandwich structure serves as both the third gate of the first transistor and the fourth gate of the second transistor. This is equivalent to adding a third gate-controlled transistor to the original first gate-controlled transistor, and adding a fourth gate-controlled transistor to the original second gate-controlled transistor. In other words, two transistors are added overall, which increases the overall operating current of the transistors, increases the power output per unit area, improves power density, enhances driving capability, thereby better driving the load, enhances signal transmission capability, improves transistor switching speed, and reduces transistor area and increases integration density under the same operating current requirements.

[0043] Furthermore, the first source electrode 7 is formed on the side of the first body region 5 away from the first drift region 6, the first drain electrode 8 is formed on the side of the first drift region 6 away from the first body region 5, the second source electrode 20 is formed on the side of the second body region 15 away from the second drift region 16, and the second drain electrode 21 is formed on the side of the second drift region 16 away from the second body region 15.

[0044] Specifically, in this embodiment of the invention, the first source 7 and the first drain 8 are formed on both sides of the first body region 5 and the first drift region 6, respectively. This increases the area between the first source 7 and the first drain 8. When a second transistor of the same area is required, the overall area of ​​the transistor can be reduced, the effective utilization rate of the transistor area between the first source 7 and the first drain 8 can be improved, the drift region width can be increased, the breakdown voltage can be increased, and the power output per unit device area can be increased.

[0045] The second source 20 is formed on the side of the second body region 15 away from the second drift region 16, so that the second source 20 can be connected to the middle fourth gate, adding a transistor controlled by the fourth gate to the second crystal. The second drain 21 is formed on the side of the second drift region 16 away from the second body region 15. The second drain 21 can be fabricated simultaneously with the second source 20 in the fabrication process, simplifying the process, reducing fabrication steps, and reducing manufacturing costs.

[0046] Furthermore, the lateral double-diffused field-effect transistor also includes a seventh metal electrode 30, which is led upward from the middle polysilicon layer 10 of the first sandwich structure to the upper surface of the base substrate.

[0047] Specifically, in this embodiment of the invention, a seventh metal electrode 30 is disposed on the intermediate polysilicon layer 10 of the first sandwich structure. The seventh metal electrode 30 is led upward from the intermediate polysilicon layer 10 of the first sandwich structure to the upper surface of the base substrate. This enables precise control of the current flowing through the transistors, controlling the switching of the transistors corresponding to the third and fourth gates, and achieving high impedance control.

[0048] Furthermore, the first body region 5 is arranged adjacent to the first drift region 6, and the second body region 15 is arranged adjacent to the second drift region 16.

[0049] Specifically, in this embodiment of the invention, the first body region 5 and the first drift region 6 are arranged adjacent to each other, and the second body region 15 and the second drift region 16 are arranged adjacent to each other. This can better control the charge in the channel region, reduce the short-channel effect, improve the switching characteristics of the device, simplify the manufacturing process, reduce the process steps, reduce the manufacturing cost, distribute heat more evenly, reduce thermal stress, improve the thermal stability of the device, reduce the size of the device, and help improve the integration density of integrated circuits.

[0050] A second aspect of the present invention provides a method for fabricating a lateral double-diffused field-effect transistor (LDFET). The method includes: forming a base substrate; forming a first transistor and a second transistor having the same carrier type within the base substrate; and an intermediate sandwich structure formed laterally between a first body region 5 and a first drift region 6 of the first transistor and longitudinally between the first transistor and the second transistor; wherein the first gate and a first field plate of the first transistor are formed downwards on the back side of the base substrate, the second gate and the second field plate of the second transistor are formed upwards on the front side of the base substrate, and the first body region 5 of the first transistor and the second body region 15 of the second transistor are located on the same side of the base substrate, and the first drift region 6 of the first transistor and the second drift region 16 of the second transistor are located on the same side of the base substrate; wherein the first transistor includes: a first body region 5, a first drift region 6, a first source 7, a first drain 8, and a first gate. The first gate is formed on the lower surface of the first body region 5 and a portion of the first drift region 6, and the first field plate is formed on the lower surface of the remaining portion of the first drift region 6; the second transistor includes: a second body region 15, a second drift region 16, a second source 20, a second drain 21, a second gate, and a second field plate, the second gate being formed on the upper surface of the second body region 15 and a portion of the second drift region 16, and the second field plate being formed on the upper surface of the remaining portion of the second drift region 16; the intermediate sandwich structure is composed of a first oxide layer 9, an intermediate polysilicon layer 10, and a second oxide layer 11 from bottom to top, the intermediate sandwich structure including a first sandwich structure formed between the first body region 5 and the second body region 15 and between a portion of the first drift region 6 and a portion of the second drift region 16, and a second sandwich structure formed between the remaining portion of the first drift region 6 and the remaining portion of the second drift region 16, the second sandwich structure serving as the third field plate of the first transistor and the fourth field plate of the second transistor.

[0051] Furthermore, the first body region 5 of the first transistor and the second body region 15 of the second transistor are located on the same side of the base substrate, and the first drift region 6 of the first transistor and the second drift region 16 of the second transistor are located on the same side of the base substrate.

[0052] Furthermore, the thickness of the intermediate polysilicon layer 10 in the first sandwich structure is greater than the thickness of the intermediate polysilicon layer 10 in the second sandwich structure, and the first sandwich structure serves as the third gate of the first transistor and the fourth gate of the second transistor.

[0053] Furthermore, the first source electrode 7 is formed on the side of the first body region 5 away from the first drift region 6, the first drain electrode 8 is formed on the side of the first drift region 6 away from the first body region 5, the second source electrode 20 is formed on the side of the second body region 15 away from the second drift region 16, and the second drain electrode 21 is formed on the side of the second drift region 16 away from the second body region 15.

[0054] Further, the step of forming a base substrate and forming a first transistor and a second transistor having the same carrier type within the base substrate, and an intermediate sandwich structure formed laterally between the first body region 5 and the first drift region 6 of the first transistor and longitudinally between the first transistor and the second transistor, includes: forming a first substrate and forming the first body region 5, the first drift region 6, the first source 7, and the first drain 8 of the first transistor on the first substrate; forming the intermediate sandwich structure on the upper surface of the first body region 5 and the first drift region 6; forming a second substrate 12 on the upper surface of the intermediate sandwich structure and forming the second transistor within the second substrate 12; wherein the base substrate includes the first substrate and the second substrate 12; and forming the first gate and the first field plate of the first transistor.

[0055] Further, the step of forming a first substrate and forming a first body region 5, a first drift region 6, a first source 7, and a first drain 8 of the first transistor on the first substrate includes: providing a first sub-substrate 1 and forming a stepped etched surface on the upper surface of the first sub-substrate 1; wherein the stepped etched surface includes a high-order etched surface and a low-order etched surface; forming a first silicon dioxide layer on the stepped etched surface, using the first silicon dioxide layer on the high-order etched surface as a first gate oxide layer 2, and using the first silicon dioxide layer on the low-order etched surface as a first field plate oxide layer 3; forming a second sub-substrate 4 on the upper surface of the first silicon dioxide layer, and forming the first body region 5, the first drift region 6, the first source 7, and the first drain 8 on the second sub-substrate 4; wherein the first substrate includes the first sub-substrate 1 and the second sub-substrate 4.

[0056] Specifically, in the embodiments of the present invention, the provided lateral double-diffused field-effect transistor can be either an N-type lateral double-diffused field-effect transistor or a P-type lateral double-diffused field-effect transistor. The present invention does not limit this; the following embodiments will only use an N-type lateral double-diffused field-effect transistor as an example for illustration.

[0057] In this embodiment of the invention, the base substrate is composed of multiple sub-substrates, first provided Figure 1The first sub-substrate 1 of the P-type silicon shown has a thin oxide layer thermally oxidized on its surface. Photoresist is formed on the oxide layer surface, and etching windows are formed on the photoresist. The oxide layer and the first sub-substrate 1 are etched through the etching windows to form... Figure 2 The stepped etching surface shown includes a high-order etching surface and a low-order etching surface. After removing the photoresist, the surface of the first sub-substrate 1 is thermally oxidized to form a thick oxide layer. Excess oxide layer is removed by chemical mechanical polishing to form... Figure 3 The first silicon dioxide layer shown is used as the first gate oxide layer 2 on the high-order etched surface and as the first field plate oxide layer 3 on the low-order etched surface.

[0058] A P-type silicon substrate with a thin layer of silicon dioxide on its surface is attached to the upper surface of the first silicon dioxide layer. The P-type silicon substrate is then thinned to the required thickness to form... Figure 4 The second sub-substrate 4 is shown. A thin layer of silicon dioxide is thermally oxidized on the surface of the second sub-substrate 4, and photoresist is formed on the silicon dioxide surface. Ion implantation windows are formed on the photoresist through exposure and development. N-type ion implantation is performed on the second sub-substrate 4 through the ion input windows, and the photoresist is removed. Photoresist is formed again, and ion implantation windows are formed on the photoresist through exposure and development. P-type ion implantation is performed on the second sub-substrate 4 through the ion input windows, and the photoresist is removed. High-temperature propagation is then performed to form the substrate as shown. Figure 5 The first drift region 6 and the first body region 5 are shown. Next, N-type heavily doped ions are implanted into the first body region 5 and the first drift region 6 to form... Figure 6 The first source 7 and the first drain 8 are shown.

[0059] Further, forming the intermediate sandwich structure on the upper surfaces of the first body region 5 and the first drift region 6 includes: forming a second silicon dioxide layer on the upper surfaces of the first body region 5 and the first drift region 6; thinning a portion of the second silicon dioxide layer to form the first oxide layer 9; forming a first polysilicon layer on the upper surface of the first oxide layer 9; thinning a portion of the first polysilicon layer to form the intermediate polysilicon layer 10; wherein the thinned region of the first polysilicon layer is far from the thinned region of the second silicon dioxide layer; and forming the second oxide layer 11 on the upper surface of the intermediate polysilicon layer 10.

[0060] Specifically, in this embodiment of the invention, a second silicon dioxide layer is formed on the surface of the second sub-substrate 4 by chemical vapor deposition, and a portion of the second silicon dioxide layer is thinned by wet etching to form... Figure 7 The first oxide layer 9 is shown. A layer of heavily doped N-type silicon is deposited on the upper surface of the first oxide layer 9 using low-pressure chemical vapor deposition, forming... Figure 8The first polysilicon layer is shown. The thinned portion of the first polysilicon layer has thinned regions that are opposite to the thinned regions of the second silicon dioxide layer in the lateral direction, forming... Figure 9 The intermediate polysilicon layer 10 is shown. Then, a layer of silicon dioxide is chemically vapor-deposited on the surface of the intermediate polysilicon layer 10, and excess silicon dioxide is chemically mechanically polished to form... Figure 9 The second oxide layer 11 shown gives an intermediate sandwich structure.

[0061] In another possible implementation, if the intermediate sandwich structure serves only as the field plate for the first transistor and the second transistor, it is not necessary to fabricate the first oxide layer 9, the intermediate polysilicon layer 10, and the second oxide layer 11 of different thicknesses. Instead, a flat first oxide layer 9, intermediate polysilicon layer 10, and second oxide layer 11 can be formed directly on the upper surface of the second sub-substrate 4.

[0062] Next, P-type silicon is adhered to the surface of the second oxide layer 11, and the P-type silicon is thinned to the required thickness to form... Figure 10 The second substrate 12 is shown. A thin layer of silicon dioxide is thermally oxidized on the surface of the second substrate 12, and photoresist is formed on the silicon dioxide surface. An ion implantation window is formed on the photoresist through exposure and development. N-type ion implantation is performed on the second substrate 12 through the ion input window, and the photoresist is removed. Photoresist is formed again, and an ion implantation window is formed on the photoresist through exposure and development. P-type ion implantation is performed on the second substrate 12 through the ion input window, and the photoresist is removed. High-temperature propagation is then performed to form the substrate 12 shown. Figure 11 The initial second drift region 14 and initial second body region 13 are shown. A thin layer of silicon dioxide is oxidized on the surface of the second substrate 12. Part of the initial second drift region 14 and initial second body region 13, as well as part of the underlying intermediate sandwich structure, are removed using dry etching, exposing the first source 7 and the first drain 8. Then, part of the initial second body region 13 is etched away, exposing the underlying intermediate sandwich structure, resulting in... Figure 12 The second body region 15 and the second drift region 16 are shown.

[0063] A thick silicon dioxide layer is chemically vapor-deposited on the surface of the second substrate 12. The surface of the silicon dioxide layer is planarized using chemical mechanical polishing, while retaining a silicon dioxide layer of the same thickness as the second field plate oxide layer 17. Part of the silicon dioxide layer is removed using wet etching, forming a layer on the surface of the second drift region 16. Figure 13 The second field plate oxide layer 17 is shown. The exposed surface of the second substrate 12 is thermally oxidized to form a thin silicon dioxide layer. The silicon dioxide layer on the second body region 15 and part of the second drift region 16 serves as the second gate oxide layer 18, as shown. Figure 14 As shown, N-type heavily doped polysilicon is deposited on the transistor surface using low-pressure chemical vapor deposition. Part of the N-type heavily doped polysilicon is then removed using dry etching to form... Figure 14The second polysilicon layer 19 shown forms a second gate with the second gate oxide layer 18, and a second field plate oxide layer 17 forms a second field plate. Next, N-type heavily doped ions are implanted into the second body region 15 and the second drift region 16 to form... Figure 14 The second source 20 and the second drain 21 are shown.

[0064] Further, the formation of the first gate and the first field plate of the first transistor includes: thinning the first sub-substrate 1; heavily doping the thinned first sub-substrate 1 to obtain a heavily doped silicon layer 23; using the heavily doped silicon layer 23 and the first gate oxide layer 2 as the first gate, and using the heavily doped silicon layer 23 and the first field plate oxide layer 3 as the first field plate.

[0065] Further, after forming the second transistor within the second substrate 12, the method further includes: forming a dielectric layer 22 on the second substrate 12, the exposed intermediate sandwich structure, and the first substrate; forming a contact hole 24 within the dielectric layer 22, the contact hole 24 contacting the first source 7, the first drain 8, the second source 20, the second drain 21, and the second gate, respectively; and forming a first metal electrode 25, a second metal electrode 26, a fourth metal electrode 27, a fifth metal electrode 28, and a sixth metal electrode, respectively, within the contact hole 24. 29; wherein, the first metal electrode 25 is led upward from the first source electrode 7 to the upper surface of the base substrate; the second metal electrode 26 is led upward from the first drain electrode 8 to the upper surface of the base substrate; the fourth metal electrode 27 is led upward from the second source electrode 20 to the upper surface of the base substrate; the fifth metal electrode 28 is led upward from the second drain electrode 21 to the upper surface of the base substrate; the sixth metal electrode 29 is led upward from the second gate electrode to the upper surface of the base substrate; and a third metal electrode 31 is formed on the lower surface of the first gate electrode and the first field plate.

[0066] Furthermore, the contact hole 24 is also in contact with the intermediate polysilicon layer 10 of the first sandwich structure; the method further includes: forming a seventh metal electrode 30 in the contact hole 24 that is in contact with the intermediate polysilicon layer 20 of the first sandwich structure, the seventh metal electrode 30 being led upward from the intermediate polysilicon layer 10 of the first sandwich structure to the upper surface of the base substrate.

[0067] Specifically, in this embodiment of the invention, chemical vapor deposition is used to form on the transistor surface. Figure 15 The dielectric layer 22 is shown. The thickness of the first sub-substrate 1 at the bottom is reduced, and then N-type heavily doped ions are implanted into the thinned first sub-substrate 1 to form... Figure 16The heavily doped silicon layer 23 is shown. The heavily doped silicon layer 23 and the first gate oxide layer 2 constitute the first gate, and the heavily doped silicon layer 23 and the first field plate oxide layer 3 constitute the first field plate.

[0068] Dry etching is performed on the dielectric layer 22 on the front side to form Figure 17 The plurality of contact holes 24 shown are respectively in contact with the first source 7, the first drain 8, the second source 20, the second drain 21, and the second gate. Metallic material is physically vapor-deposited within the contact holes 24 to form... Figure 18 The first metal electrode 25, the second metal electrode 26, the fourth metal electrode 27, the fifth metal electrode 28, and the sixth metal electrode 29 are shown. Then, a metal material is physically vapor-deposited under the heavily doped silicon layer 23 on the back side to form... Figure 18 The third metal electrode 31 shown is used to obtain the final lateral double-diffused field-effect transistor.

[0069] The first source 7 and the first drain 8 are formed on both sides of the first body region 5 and the first drift region 6, respectively. This increases the area between the first source 7 and the first drain 8. When a second transistor of the same area is required, the overall area of ​​the transistor can be reduced, the effective utilization rate of the transistor area between the first source 7 and the first drain 8 can be improved, the drift region width can be increased, the breakdown voltage can be increased, and the power output per unit device area can be increased.

[0070] The second source 20 is formed on the side of the second body region 15 away from the second drift region 16, so that the second source 20 can be connected to the middle fourth gate, adding a transistor controlled by the fourth gate to the second crystal. The second drain 21 is formed on the side of the second drift region 16 away from the second body region 15. The second drain 21 can be fabricated simultaneously with the second source 20 in the fabrication process, simplifying the process, reducing fabrication steps, and reducing manufacturing costs.

[0071] The intermediate sandwich structure includes a first sandwich structure and a second sandwich structure arranged laterally. The first sandwich structure is formed between the first body region 5 and the second body region 15, and between a portion of the first drift region 6 and a portion of the second drift region 16. The second sandwich structure is formed between the remaining first drift region 6 and the remaining second drift region 16. The thickness of the intermediate polysilicon layer 10 in the first sandwich structure is greater than the thickness of the intermediate polysilicon layer 10 in the second sandwich structure. The first sandwich structure serves as both the third gate of the first transistor and the fourth gate of the second transistor. Essentially, the first transistor adds a third gate-controlled transistor to the original first gate-controlled transistor, and the second transistor adds a fourth gate-controlled transistor to the original second gate-controlled transistor. This results in two additional transistors, increasing the overall operating current, increasing the power output per unit area, improving power density, enhancing driving capability, thus better driving the load, enhancing signal transmission capability, increasing transistor switching speed, and reducing transistor area while increasing integration density under the same operating current requirements.

[0072] The first sandwich structure serves as the third gate shared by the first and second transistors. A channel is added to the surface of the first body region 5 near the first sandwich structure, and another channel is added to the surface of the second body region 15 near the first sandwich structure. This improves the current carrying capacity of the first and second transistors, making them more suitable for applications requiring high current. Each channel can share a portion of the total current, thus reducing channel current density, decreasing on-resistance, and improving device efficiency. It also enhances the transistor's power handling capability, disperses heat, reduces thermal stress in each channel, reduces local hot spots, lowers the risk of thermal runaway, and improves the overall device reliability and lifespan. Even if one channel fails, the other channels can still operate, providing redundancy and increasing transistor reliability.

[0073] A third aspect of the present invention provides a chip comprising the lateral double-diffused field-effect transistor described above.

[0074] A fourth aspect of the present invention provides a circuit comprising the lateral double-diffused field-effect transistor described above.

[0075] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0076] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0077] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A lateral double-diffused field-effect transistor, characterized in that, The lateral double-diffused field-effect transistor includes: Basic substrate; A first transistor and a second transistor having the same carrier type, wherein the first transistor has a first gate and a first field plate formed downward on the back side of the base substrate, and the second transistor has a second gate and a second field plate formed upward on the front side of the base substrate; wherein the first transistor includes: a first body region, a first drift region, a first source, a first drain, a first gate, and a first field plate, the first gate being formed on the lower surface of the first body region and a portion of the first drift region, and the first field plate being formed on the lower surface of the remaining portion of the first drift region; the second transistor includes: a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate, the second gate being formed on the upper surface of the second body region and a portion of the second drift region, and the second field plate being formed on the upper surface of the remaining portion of the second drift region; An intermediate sandwich structure is formed laterally in the intermediate region between the first body region and the first drift region and longitudinally between the first transistor and the second transistor. The intermediate sandwich structure is composed of a first oxide layer, an intermediate polysilicon layer and a second oxide layer from bottom to top. The intermediate sandwich structure includes a first sandwich structure formed between the first body region and the second body region and between a portion of the first drift region and a portion of the second drift region, and a second sandwich structure formed between the remaining portion of the first drift region and the remaining portion of the second drift region. The second sandwich structure serves as the third field plate of the first transistor and the fourth field plate of the second transistor.

2. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The first body region of the first transistor and the second body region of the second transistor are located on the same side of the base substrate, and the first drift region of the first transistor and the second drift region of the second transistor are located on the same side of the base substrate.

3. The lateral double-diffused field-effect transistor according to claim 2, characterized in that, The thickness of the intermediate polysilicon layer in the first sandwich structure is greater than the thickness of the intermediate polysilicon layer in the second sandwich structure, and the first sandwich structure serves as the third gate of the first transistor and the fourth gate of the second transistor.

4. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The first source is formed on the side of the first body region away from the first drift region, the first drain is formed on the side of the first drift region away from the first body region, the second source is formed on the side of the second body region away from the second drift region, and the second drain is formed on the side of the second drift region away from the second body region.

5. The lateral double-diffused field-effect transistor according to claim 4, characterized in that, The lateral double-diffused field-effect transistor further includes: A first metal electrode is led upward from the first source electrode to the upper surface of the base substrate; The second metal electrode is led upward from the first drain electrode to the upper surface of the base substrate; The third metal electrode is led down from the first gate to the lower surface of the base substrate; A fourth metal electrode is led upward from the second source electrode to the upper surface of the base substrate; The fifth metal electrode extends upward from the second drain electrode to the upper surface of the base substrate; The sixth metal electrode is led upward from the second gate to the upper surface of the base substrate; A dielectric layer is formed between the first metal electrode and the fourth metal electrode, between the fourth metal electrode and the sixth metal electrode, between the sixth metal electrode and the fifth metal electrode, and between the fifth metal electrode and the second metal electrode.

6. The lateral double-diffused field-effect transistor according to claim 3, characterized in that, Lateral double-diffused field-effect transistors also include: The seventh metal electrode is led upward from the middle polycrystalline silicon layer of the first sandwich structure to the upper surface of the base substrate.

7. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The first body region is arranged adjacent to the first drift region, and the second body region is arranged adjacent to the second drift region.

8. A method for fabricating a lateral double-diffused field-effect transistor, characterized in that, The method for fabricating the lateral double-diffused field-effect transistor includes: A base substrate is formed, and a first transistor and a second transistor having the same carrier type are formed within the base substrate, as well as an intermediate region formed laterally between a first body region and a first drift region of the first transistor and an intermediate sandwich structure formed longitudinally between the first transistor and the second transistor. The first transistor has its first gate and first field plate formed downwards on the back side of the base substrate, and the second transistor has its second gate and second field plate formed upwards on the front side of the base substrate. The first transistor includes a first body region, a first drift region, a first source, a first drain, a first gate, and a first field plate. The first gate is formed on the lower surface of the first body region and a portion of the first drift region, and the first field plate is formed on the lower surface of the remaining portion of the first drift region. The second transistor includes a second body region, a second drift region, a second source, a second drain, a second gate, and a second field plate. The second gate is formed on the upper surface of the second body region and a portion of the second drift region, and the second field plate is formed on the upper surface of the remaining portion of the second drift region. The intermediate sandwich structure is composed of a first oxide layer, an intermediate polysilicon layer and a second oxide layer from bottom to top. The intermediate sandwich structure includes a first sandwich structure formed between the first body region and the second body region and between a portion of the first drift region and a portion of the second drift region, and a second sandwich structure formed between the remaining portion of the first drift region and the remaining portion of the second drift region. The second sandwich structure serves as the third field plate of the first transistor and the fourth field plate of the second transistor.

9. The method for fabricating a lateral double-diffused field-effect transistor according to claim 8, characterized in that, The first body region of the first transistor and the second body region of the second transistor are located on the same side of the base substrate, and the first drift region of the first transistor and the second drift region of the second transistor are located on the same side of the base substrate.

10. The method for fabricating a lateral double-diffused field-effect transistor according to claim 9, characterized in that, The thickness of the intermediate polysilicon layer in the first sandwich structure is greater than the thickness of the intermediate polysilicon layer in the second sandwich structure, and the first sandwich structure serves as the third gate of the first transistor and the fourth gate of the second transistor.

11. The method for fabricating a lateral double-diffused field-effect transistor according to claim 10, characterized in that, The first source is formed on the side of the first body region away from the first drift region, the first drain is formed on the side of the first drift region away from the first body region, the second source is formed on the side of the second body region away from the second drift region, and the second drain is formed on the side of the second drift region away from the second body region.

12. The method for fabricating a lateral double-diffused field-effect transistor according to claim 11, characterized in that, The formation of a base substrate, and the formation of a first transistor and a second transistor having the same carrier type within the base substrate, and an intermediate sandwich structure formed laterally between a first body region and a first drift region of the first transistor and longitudinally between the first transistor and the second transistor, includes: A first substrate is formed, and a first body region, a first drift region, a first source, and a first drain of the first transistor are formed on the first substrate; The intermediate sandwich structure is formed on the upper surfaces of the first body region and the first drift region; A second substrate is formed on the upper surface of the intermediate sandwich structure, and the second transistor is formed within the second substrate; wherein the base substrate includes the first substrate and the second substrate; The first gate and the first field plate of the first transistor are formed.

13. The method for fabricating a lateral double-diffused field-effect transistor according to claim 12, characterized in that, The process of forming a first substrate and forming a first body region, a first drift region, a first source, and a first drain of the first transistor on the first substrate includes: A first sub-substrate is provided, and a stepped etched surface is formed on the upper surface of the first sub-substrate; wherein the stepped etched surface includes a high-order etched surface and a low-order etched surface; A first silicon dioxide layer is formed on the stepped etching surface, and the first silicon dioxide layer on the higher-order etching surface is used as the first gate oxide layer, and the first silicon dioxide layer on the lower-order etching surface is used as the first field plate oxide layer. A second sub-substrate is formed on the upper surface of the first silicon dioxide layer, and the first body region, the first drift region, the first source, and the first drain are formed on the second sub-substrate; wherein, the first substrate includes the first sub-substrate and the second sub-substrate.

14. The method for fabricating a lateral double-diffused field-effect transistor according to claim 13, characterized in that, The formation of the intermediate sandwich structure on the upper surfaces of the first body region and the first drift region includes: A second silicon dioxide layer is formed on the upper surface of the first body region and the first drift region; The second silicon dioxide layer is partially thinned to form the first oxide layer; A first polycrystalline silicon layer is formed on the upper surface of the first oxide layer; The first polysilicon layer is thinned to form the intermediate polysilicon layer; wherein the thinned region of the first polysilicon layer is far from the thinned region of the second silicon dioxide layer. A second oxide layer is formed on the upper surface of the intermediate polycrystalline silicon layer.

15. The method for fabricating a lateral double-diffused field-effect transistor according to claim 14, characterized in that, The first gate and first field plate forming the first transistor include: Thinning of the first sub-substrate; The thinned first sub-substrate was heavily doped to obtain a heavily doped silicon layer. The heavily doped silicon layer and the first gate oxide layer are used as the first gate, and the heavily doped silicon layer and the first field plate oxide layer are used as the first field plate.

16. The method for fabricating a lateral double-diffused field-effect transistor according to claim 15, characterized in that, After forming the second transistor within the second substrate, the method further includes: A dielectric layer is formed on the second substrate, the exposed intermediate sandwich structure, and the first substrate; Contact holes are formed within the dielectric layer, and the contact holes are respectively in contact with the first source, the first drain, the second source, the second drain, and the second gate; A first metal electrode, a second metal electrode, a fourth metal electrode, a fifth metal electrode, and a sixth metal electrode are formed within the contact hole, respectively; wherein, the first metal electrode extends upward from the first source electrode to the upper surface of the base substrate; the second metal electrode extends upward from the first drain electrode to the upper surface of the base substrate; the fourth metal electrode extends upward from the second source electrode to the upper surface of the base substrate; the fifth metal electrode extends upward from the second drain electrode to the upper surface of the base substrate; and the sixth metal electrode extends upward from the second gate electrode to the upper surface of the base substrate. A third metal electrode is formed on the lower surface of the first gate and the first field plate.

17. The method for fabricating a lateral double-diffused field-effect transistor according to claim 16, characterized in that, The contact hole also contacts the intermediate polysilicon layer of the first sandwich structure; The method further includes: forming a seventh metal electrode in a contact hole that contacts the intermediate polysilicon layer of the first sandwich structure, the seventh metal electrode being led upward from the intermediate polysilicon layer of the first sandwich structure to the upper surface of the base substrate.

18. A chip, characterized in that, The chip includes a lateral double-diffused field-effect transistor as described in any one of claims 1-7.

19. A circuit, characterized in that, The circuit includes a lateral double-diffused field-effect transistor as described in any one of claims 1-7.

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