Lateral double diffused field effect transistor, preparation method thereof, chip and circuit
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2026-02-09
- Publication Date
- 2026-06-02
Smart Images
Figure CN122138461A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, specifically to a lateral double-diffused field-effect transistor, a method for fabricating a lateral double-diffused field-effect transistor, a chip, and a circuit. Background Technology
[0002] Lateral double-diffused MOSFETs (LDMOS) are a type of lateral power device whose electrodes are all located on the device surface. They are easy to integrate with low-voltage signal circuits and other devices through internal connections. At the same time, they have advantages such as high voltage withstand capability, high gain, good linearity, high efficiency, and good broadband matching performance. They are now widely used in power integrated circuits, especially power management chips.
[0003] In the prior art, the operating current provided by the lateral double-diffused field-effect transistor is relatively small, and the transistor area is relatively large. Summary of the Invention
[0004] To address the technical problems of low operating current and large transistor area in existing lateral double-diffused field-effect transistors, this invention provides a lateral double-diffused field-effect transistor, a method for fabricating a lateral double-diffused field-effect transistor, a chip, and a circuit. Using this lateral double-diffused field-effect transistor can improve the breakdown voltage, increase the total operating current of the lateral double-diffused field-effect transistor, reduce the on-resistance, enhance the power amplification capability of radio frequency signals, improve signal fidelity, and reduce the device area.
[0005] To achieve the above objectives, a first aspect of the present invention provides a lateral double-diffused field-effect transistor, comprising: a base substrate; wherein the base substrate has an intermediate isolation structure that divides the base substrate into a top substrate and a bottom substrate; a first body region and a second body region, a first drift region and a second drift region, a first gate and a second gate, and a first field plate and a second field plate symmetrically disposed on both sides of the base substrate with the intermediate isolation structure as the axis of symmetry; the first gate and the first field plate being formed downward on the back side of the bottom substrate, the second gate and the second field plate being formed upward on the front side of the top substrate, the first body region and the first drift region being formed on the front side of the bottom substrate, and the second body region and the second drift region being formed on the back side of the top substrate; a source electrode being formed on one side of the first body region and the second body region; and a drain electrode being formed on one side of the first drift region and the second drift region; the source electrode, the drain electrode, the first body region, the first drift region, the first gate electrode, and the first field plate constituting a first transistor; and the source electrode, the drain electrode, the second body region, the second drift region, the second gate electrode, and the second field plate constituting a second transistor.
[0006] Furthermore, the intermediate isolation structure is a single-layer isolation structure.
[0007] Furthermore, the single-layer isolation structure includes a silicon oxide isolation structure or a silicon carbide isolation structure.
[0008] Furthermore, the intermediate isolation structure is a sandwich isolation structure, which includes an intermediate sandwich layer and an isolation layer wrapped around the intermediate sandwich layer.
[0009] Furthermore, the intermediate interlayer includes a polycrystalline silicon interlayer or a metal interlayer.
[0010] Furthermore, the lateral double-diffused field-effect transistor further includes: a first dielectric layer formed on the lower surface of the bottom substrate; a second dielectric layer formed on the upper surface of the top substrate; a first metal electrode led downward from the source to the lower surface of the first dielectric layer; a second metal electrode led downward from the first gate to the lower surface of the first dielectric layer; a third metal electrode led downward from the drain to the lower surface of the first dielectric layer; a fourth metal electrode led upward from the source to the upper surface of the second dielectric layer; a fifth metal electrode led upward from the second gate to the upper surface of the second dielectric layer; and a sixth metal electrode led upward from the drain to the upper surface of the second dielectric layer.
[0011] A second aspect of the present invention provides a method for fabricating a lateral double-diffused field-effect transistor (LDFET), the method comprising: providing a base substrate; wherein the base substrate has an intermediate isolation structure that divides the base substrate into a top substrate and a bottom substrate; forming a first body region, a first drift region, a first gate, a first field plate, a second body region, a second drift region, a second gate, a second field plate, a source, and a drain on the base substrate; wherein the first body region and the second body region, the first drift region and the second drift region, the first gate and the second gate, and the first field plate and the second field plate are all symmetrically disposed on both sides of the base substrate with the intermediate isolation structure as the axis of symmetry, the first body region and the second drift region, the first drift region and the second drift region, the first gate and the second gate, and the first field plate and the second field plate are all symmetrically disposed on both sides of the base substrate with the intermediate isolation structure as the axis of symmetry, the second body region and the second drift region being formed in the base substrate. A gate and a first field plate are formed downward on the back side of the bottom substrate, and a second gate and a second field plate are formed upward on the front side of the top substrate. A first body region and a first drift region are formed on the front side of the bottom substrate, and a second body region and a second drift region are formed on the back side of the top substrate. A source is formed on one side of the first body region and the second body region, and a drain is formed on one side of the first drift region and the second drift region. The source, the drain, the first body region, the first drift region, the first gate, and the first field plate constitute a first transistor, and the source, the drain, the second body region, the second drift region, the second gate, and the second field plate constitute a second transistor.
[0012] Further, the step of forming a first body region, a first drift region, a first gate, a first field plate, a second body region, a second drift region, a second gate, a second field plate, a source, and a drain on the base substrate includes: forming a second body region, a second drift region, a second gate, a second field plate, a first initial source, and a first initial drain on the top layer substrate; wherein the first initial source is formed on the side of the second body region away from the second drift region, and the first initial drain is formed on the side of the second drift region away from the second body region; forming an initial first body region and an initial first drift region on the bottom layer substrate; removing the initial first body region and the intermediate isolation structure at the bottom of the first initial source, and the initial first drift region and the intermediate isolation structure at the bottom of the first initial drain, using an etching process to form the first body region and the first drift region; forming a second initial source at the bottom of the first initial source to form the source; forming a second initial drain at the bottom of the first initial drain to form the drain; and forming the first gate and the first field plate on the bottom layer substrate.
[0013] Furthermore, the intermediate isolation structure is a single-layer isolation structure.
[0014] Furthermore, the single-layer isolation structure includes a silicon oxide isolation structure or a silicon carbide isolation structure.
[0015] Furthermore, the intermediate isolation structure is a sandwich isolation structure, which includes an intermediate sandwich layer and an isolation layer wrapped around the intermediate sandwich layer.
[0016] Furthermore, the intermediate interlayer includes a polycrystalline silicon interlayer or a metal interlayer.
[0017] Further, after forming the first transistor and the second transistor, the method further includes: forming a first dielectric layer on the lower surface of the bottom substrate and forming a second dielectric layer on the upper surface of the top substrate; forming a first contact hole in the first dielectric layer and forming a second contact hole in the second dielectric layer; wherein the first contact hole contacts the source, the drain, and the first gate, respectively, and the second contact hole contacts the source, the drain, and the second gate, respectively; forming a first metal electrode, a second metal electrode, and a third metal electrode in the first contact hole; wherein the first metal electrode extends downward from the source to the lower surface of the first dielectric layer, the second metal electrode extends downward from the first gate to the lower surface of the first dielectric layer, and the third metal electrode extends downward from the drain to the lower surface of the first dielectric layer; forming a fourth metal electrode, a fifth metal electrode, and a sixth metal electrode in the second contact hole; wherein the fourth metal electrode extends upward from the source to the upper surface of the second dielectric layer, the fifth metal electrode extends upward from the second gate to the upper surface of the second dielectric layer, and the sixth metal electrode extends upward from the drain to the upper surface of the second dielectric layer.
[0018] A third aspect of the present invention provides a chip comprising the lateral double-diffused field-effect transistor described above.
[0019] A fourth aspect of the present invention provides a circuit comprising the lateral double-diffused field-effect transistor described above.
[0020] The present invention has at least the following technical effects through the technical solution provided by the present invention: The lateral double-diffused field-effect transistor of the present invention includes a base substrate having an intermediate isolation structure that divides the base substrate into a top substrate and a bottom substrate. A first gate and a first field plate are formed on the back side of the bottom substrate, and a first body region and a first drift region are formed on the front side. A second gate and a second field plate are formed on the front side of the top substrate, and a second body region and a second drift region are formed on the back side. The first and second body regions, the first and second drift regions, the first and second gates, the first and second field plates are symmetrically arranged on both sides of the base substrate with the intermediate isolation structure as the axis of symmetry. A source is formed on one side of the first and second body regions, and a drain is formed on one side of the first and second drift regions. The source, drain, first body region, first drift region, first gate, and first field plate constitute a first transistor, and the source, drain, second body region, second drift region, second gate, and second field plate constitute a second transistor. The lateral double-diffused field-effect transistor provided by this invention increases the total operating current of the lateral double-diffused field-effect transistor, reduces the on-resistance, enhances the power amplification capability of radio frequency signals, improves signal fidelity, and reduces the device area.
[0021] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description
[0022] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings: Figure 1 A schematic diagram of the structure of the base substrate formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention; Figure 2 A schematic diagram of the structure of the second body region and the second drift region formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 3 A schematic diagram of the structure of the first initial source and the first initial drain formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the second field plate oxide layer, the second gate oxide layer, and the second polysilicon layer formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 5 This is a schematic diagram of the structure of the base substrate formed in the lateral double-diffusion field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 6 A schematic diagram of the initial first bulk region and the initial first drift region formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 7 A schematic diagram of the structure of the first bulk region and the first drift region formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention; Figure 8 This is a schematic diagram of the source and drain structures formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of the structure of the first field plate oxide layer and the first gate oxide layer formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 10 This is a schematic diagram of the structure of the first polycrystalline silicon layer formed in the lateral double-diffused field-effect transistor fabrication method provided in an embodiment of the present invention. Figure 11 This is a schematic diagram of the structure of the first dielectric layer, the second dielectric layer, the first contact hole, and the second contact hole formed in the lateral double-diffused field-effect transistor fabrication method provided in the embodiment of the present invention. Figure 12 This is a schematic diagram of the structure of the lateral double-diffused field-effect transistor formed in the fabrication method of the lateral double-diffused field-effect transistor provided in the embodiment of the present invention. Figure 13 A schematic diagram of the structure of a lateral double-diffused field-effect transistor formed in a method for fabricating a lateral double-diffused field-effect transistor according to another embodiment of the present invention; Figure 14 A flowchart illustrating a method for fabricating a lateral double-diffused field-effect transistor according to an embodiment of the present invention.
[0023] Explanation of reference numerals in the attached figures 1-Top substrate; 2-Bottom substrate; 3-Intermediate isolation structure; 4-Second body region; 5-Second drift region; 6-First initial source; 7-First initial drain; 8-Second field plate oxide layer; 9-Second gate oxide layer; 10-Second polysilicon layer; 11-Base substrate; 12-Initial first body region; 13-Initial first drift region; 14-First body region; 15-First drift region; 16-Source; 17-Drain; 18-First field plate oxide layer; 19-First gate oxide layer; 20-First polysilicon layer; 21-First dielectric layer; 22-Second dielectric layer; 23-First contact hole; 24-Second contact hole; 25-First metal electrode; 26-Second metal electrode; 27-Third metal electrode; 28-Fourth metal electrode; 29-Fifth metal electrode; 30-Sixth metal electrode; 31-Intermediate sandwich layer; 32-Isolation layer. Detailed Implementation
[0024] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.
[0025] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0026] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used to describe the relative positions of components in relation to the directions shown in the accompanying drawings or in relation to the vertical, perpendicular, or gravitational directions.
[0027] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0028] Please refer to Figure 12 The first aspect of this invention provides a lateral double-diffused field-effect transistor (LDFET), comprising: a base substrate; wherein the base substrate has an intermediate isolation structure 3, the intermediate isolation structure 3 dividing the base substrate into a top substrate 1 and a bottom substrate 2; a first body region 14 and a second body region 4, a first drift region 15 and a second drift region 5, a first gate and a second gate, and a first field plate and a second field plate are symmetrically disposed on both sides of the base substrate with the intermediate isolation structure 3 as the axis of symmetry; the first gate and the first field plate are formed downward on the back surface of the bottom substrate 2, and the second gate and the second field plate are formed upward on the top substrate 1. On the front side, the first body region 14 and the first drift region 15 are formed on the front side of the bottom substrate 2, and the second body region 4 and the second drift region 5 are formed on the back side of the top substrate 1; the source 16 is formed on one side of the first body region 14 and the second body region 4; the drain 17 is formed on one side of the first drift region 15 and the second drift region 5; the source 16, the drain 17, the first body region 14, the first drift region 15, the first gate and the first field plate constitute a first transistor; the source 16, the drain 17, the second body region 4, the second drift region 5, the second gate and the second field plate constitute a second transistor.
[0029] Specifically, in this embodiment of the invention, the lateral double-diffused field-effect transistor includes a base substrate having an intermediate isolation structure 3, which divides the base substrate into a top substrate 1 and a bottom substrate 2. A first body region 14 and a first drift region 15 are formed on the front side of the bottom substrate 2 (in this embodiment, with the substrate placed horizontally as shown in the figure, the upper side of the substrate is defined as the front side and the lower side as the back side), and a first gate and a first field plate are formed downwards on the back side of the bottom substrate 2. A second body region 4 and a second drift region 5 are formed on the back side of the top substrate 1, and a second gate and a second field plate are formed upwards on the front side of the top substrate 1. The first body region 14 and the second body region 4, the first drift region 15 and the second drift region 5, the first gate and the second gate, and the first field plate and the second field plate are symmetrically arranged on both sides of the base substrate with the intermediate isolation structure 3 as the axis of symmetry.
[0030] A source electrode 16 is formed on one side of the first body region 14 and the second body region 4, and a drain electrode 17 is formed on one side of the first drift region 15 and the second drift region 5. The source electrode 16, drain electrode 17, first body region 14, first drift region 15, first gate, and first field plate constitute an independent first transistor, and the source electrode 16, drain electrode 17, second body region 4, second drift region 5, second gate, and second field plate constitute another independent second transistor. Two mutually symmetrical independent transistors can be formed on the base substrate, and the current of the two transistors can be controlled by the first gate and the second gate respectively. This increases the overall operating current of the lateral double-diffused field-effect transistor, which can improve the power amplification capability of RF signals, improve signal fidelity, improve linearity, reduce on-resistance, and reduce the device area while requiring the same operating current.
[0031] The lateral double-diffused field-effect transistor provided by the present invention can increase the overall operating current of the lateral double-diffused field-effect transistor, reduce the on-resistance, enhance the power amplification capability of radio frequency signals, improve signal fidelity, and reduce the device area.
[0032] Furthermore, the intermediate isolation structure 3 is a single-layer isolation structure.
[0033] Furthermore, the single-layer isolation structure includes a silicon oxide isolation structure or a silicon carbide isolation structure.
[0034] Specifically, in this embodiment of the invention, the intermediate isolation structure 3 can be a single-layer isolation structure. This single-layer isolation structure can isolate the transistors in the top substrate 1 from the transistors in the bottom substrate 2, preventing breakdown of the two transistors and improving device reliability. The single-layer isolation structure includes a silicon oxide isolation structure or a silicon carbide isolation structure. The silicon carbide isolation structure can better dissipate heat, increase power density, reduce thermal resistance, and delay device aging.
[0035] Furthermore, the intermediate isolation structure 3 is a sandwich isolation structure, which includes an intermediate sandwich 31 and an isolation layer 32 wrapped around the intermediate sandwich 31.
[0036] Furthermore, the intermediate interlayer 31 includes a polycrystalline silicon interlayer or a metal interlayer.
[0037] Specifically, in the embodiments of the present invention, please refer to Figure 13 The intermediate isolation structure 3 can be a sandwich isolation structure, comprising an intermediate sandwich layer 31 and an isolation layer 32 surrounding the intermediate sandwich layer 31. The intermediate sandwich layer 31 can serve as a floating field plate for the first transistor and the second transistor, respectively, optimizing the electric field distribution, improving the breakdown voltage, reducing the surface electric field, and improving the reliability of the transistor. The intermediate sandwich layer 31 includes a polycrystalline silicon sandwich layer or a metal sandwich layer. The metal sandwich layer includes a high-temperature resistant, refractory metal, such as titanium nitride or titanium.
[0038] Furthermore, the lateral double-diffused field-effect transistor further includes: a first dielectric layer 21 formed on the lower surface of the bottom substrate 2; a second dielectric layer 22 formed on the upper surface of the top substrate 1; a first metal electrode 25 led downward from the source electrode 16 to the lower surface of the first dielectric layer 21; a second metal electrode 26 led downward from the first gate electrode to the lower surface of the first dielectric layer 21; a third metal electrode 27 led downward from the drain electrode 17 to the lower surface of the first dielectric layer 21; a fourth metal electrode 28 led upward from the source electrode 16 to the upper surface of the second dielectric layer 22; a fifth metal electrode 29 led upward from the second gate electrode to the upper surface of the second dielectric layer 22; and a sixth metal electrode 30 led upward from the drain electrode 17 to the upper surface of the second dielectric layer 22.
[0039] Specifically, in this embodiment of the invention, a first dielectric layer 21 is formed on the lower surface of the substrate 2, and a first metal electrode 25, a second metal electrode 26, and a third metal electrode 27 are formed on the first dielectric layer 21. The first metal electrode 25 is led downward from the source electrode 16 to the lower surface of the first dielectric layer 21, the second metal electrode 26 is led downward from the first gate electrode to the lower surface of the first dielectric layer 21, and the third metal electrode 27 is led downward from the drain electrode 17 to the lower surface of the first dielectric layer 21.
[0040] A second dielectric layer 22 is formed on the upper surface of the top substrate 1, and a fourth metal electrode 28, a fifth metal electrode 29, and a sixth metal electrode 30 are formed on the second dielectric layer 22. The fourth metal electrode 28 is led upward from the source electrode 16 to the upper surface of the second dielectric layer 22, the fifth metal electrode 29 is led upward from the second gate electrode to the upper surface of the second dielectric layer 22, and the sixth metal electrode 30 is led upward from the drain electrode 17 to the upper surface of the second dielectric layer 22.
[0041] The second metal electrode 26 and the fifth metal electrode 29 are connected independently to form two independent transistors. The first metal electrode 25 and the fourth metal electrode 28, and the third metal electrode 27 and the sixth metal electrode 30 can be connected independently or interconnected.
[0042] Please refer to Figure 14 The second aspect of the present invention provides a method for fabricating a lateral double-diffused field-effect transistor, the method comprising: S101: providing a base substrate; wherein the base substrate has an intermediate isolation structure 3, the intermediate isolation structure 3 dividing the base substrate into a top substrate 1 and a bottom substrate 2; S102: forming a first body region 14, a first drift region 15, a first gate, a first field plate, a second body region 4, a second drift region 5, a second gate, a second field plate, a source 16, and a drain 17 on the base substrate; wherein the first body region 14 and the second body region 4, the first drift region 15 and the second drift region 5, the first gate and the second gate, and the first field plate and the second field plate are all symmetrically disposed on both sides of the base substrate with the intermediate isolation structure 3 as the axis of symmetry. The gate and the first field plate are formed downward on the back side of the bottom substrate 2, and the second gate and the second field plate are formed upward on the front side of the top substrate 1. The first body region 14 and the first drift region 15 are formed on the front side of the bottom substrate 2, and the second body region 4 and the second drift region 5 are formed on the back side of the top substrate 1. The source 16 is formed on one side of the first body region 14 and the second body region 4, and the drain 17 is formed on one side of the first drift region 15 and the second drift region 5. The source 16, the drain 17, the first body region 14, the first drift region 15, the first gate and the first field plate constitute a first transistor, and the source 16, the drain 17, the second body region 4, the second drift region 5, the second gate and the second field plate constitute a second transistor.
[0043] Further, the formation of a first body region 14, a first drift region 15, a first gate, a first field plate, a second body region 4, a second drift region 5, a second gate, a second field plate, a source 16, and a drain 17 on the base substrate includes: forming a second body region 4, a second drift region 5, a second gate, a second field plate, a first initial source 6, and a first initial drain 7 on the top layer substrate 1; wherein the first initial source 6 is formed on the side of the second body region 4 away from the second drift region 5, and the first initial drain 7 is formed on the side of the second drift region 5 away from the second body region 4; on the bottom layer substrate... The bottom substrate 2 forms an initial first body region 12 and an initial first drift region 13; the initial first body region 12 and the intermediate isolation structure 3 at the bottom of the first initial source electrode 6, and the initial first drift region 13 and the intermediate isolation structure 3 at the bottom of the first initial drain electrode 7 are removed by etching process to form the first body region 14 and the first drift region 15; a second initial source electrode is formed at the bottom of the first initial source electrode 6 to form the source electrode 16; a second initial drain electrode is formed at the bottom of the first initial drain electrode 7 to form the drain electrode 17; the first gate electrode and the first field plate are formed on the bottom substrate 2.
[0044] Further, after forming the first transistor and the second transistor, the method further includes: forming a first dielectric layer 21 on the lower surface of the bottom substrate 2 and forming a second dielectric layer 22 on the upper surface of the top substrate 1; forming a first contact hole 23 in the first dielectric layer 21 and forming a second contact hole 24 in the second dielectric layer 22; wherein the first contact hole 23 contacts the source 16, the drain 17 and the first gate respectively, and the second contact hole 24 contacts the source 16, the drain 17 and the second gate respectively; forming a first metal electrode 25, a second metal electrode 26 and a third metal electrode 27 in the first contact hole 23 respectively; wherein the first metal electrode 25 is formed by the... The source electrode 16 is led downward to the lower surface of the first dielectric layer 21, the second metal electrode 26 is led downward from the first gate electrode to the lower surface of the first dielectric layer 21, and the third metal electrode 27 is led downward from the drain electrode 17 to the lower surface of the first dielectric layer 21; a fourth metal electrode 28, a fifth metal electrode 29, and a sixth metal electrode 30 are formed in the second contact hole 24, respectively; wherein, the fourth metal electrode 28 is led upward from the source electrode 16 to the upper surface of the second dielectric layer 22, the fifth metal electrode 29 is led upward from the second gate electrode to the upper surface of the second dielectric layer 22, and the sixth metal electrode 30 is led upward from the drain electrode 17 to the upper surface of the second dielectric layer 22.
[0045] Specifically, in the embodiments of the present invention, the provided lateral double-diffused field-effect transistor can be either an N-type lateral double-diffused field-effect transistor or a P-type lateral double-diffused field-effect transistor. The present invention does not limit this; the following embodiments will only use an N-type lateral double-diffused field-effect transistor as an example for illustration.
[0046] First provide Figure 1 The base substrate shown comprises, from top to bottom, a P-type top substrate 1, an intermediate isolation structure 3, and a P-type bottom substrate 2. A thin layer of silicon dioxide is thermally oxidized on the surface of the top substrate 1, and photoresist is formed on the silicon dioxide surface. Ion implantation windows are formed on the photoresist through exposure and development. N-type lightly doped ions are implanted into the top substrate 1 through the ion input windows, and the photoresist is removed. Photoresist is formed again, and ion implantation windows are formed on the photoresist through exposure and development. P-type lightly doped ions are implanted into the top substrate 1 through the ion input windows, and the photoresist is removed. High-temperature propagation is then performed to form the substrate as shown. Figure 2 The second body region 4 and the second drift region 5 are shown.
[0047] Photoresist is formed on the upper surface of the top substrate 1. Ion implantation windows are formed on the photoresist through exposure and development. N-type heavily doped ions are implanted into the second bulk region 4 and the second drift region 5 through the ion input windows. The photoresist is then removed, and high-temperature propagation is performed to form a structure in the second bulk region 4. Figure 3 The first initial source 6 is shown, and the first initial drain 7 is formed in the second drift region 5. The first initial source 6 is formed on the side of the second body region 4 away from the second drift region 5, and the first initial drain 7 is formed on the side of the second drift region 5 away from the second body region 4.
[0048] A thick silicon dioxide layer is chemically vapor-deposited on the surface of the top substrate 1. The silicon dioxide layer is then dry-etched, retaining the silicon dioxide layers on the first initial source 6, the first initial drain 7, and part of the second drift region 5. A relatively thick silicon dioxide layer is then thermally oxidized, and part of the silicon dioxide layer is wet-etched, retaining part of the silicon dioxide layer on the second drift region 5, forming... Figure 4 The second field plate oxide layer 8 is shown.
[0049] Then, thermal oxidation is performed on the transistor surface to form a thin oxide layer, and the oxide layer on the second body region 4 is used as the second gate oxide layer 9. A layer of heavily N-type doped polysilicon is deposited by low-pressure chemical vapor deposition, excess polysilicon on the surface is chemically mechanically polished, and planarization is performed to obtain… Figure 4 The second polysilicon layer 10 is shown. The second polysilicon layer 10 and the second gate oxide layer 9 constitute the second gate, and the second polysilicon layer 10 and the second field plate oxide layer 8 constitute the second field plate.
[0050] A thin layer of silicon dioxide is thermally oxidized on the upper surface of the top substrate 1, and then bonded to a base substrate 11 with a thin layer of silicon dioxide to form a... Figure 5 The structure is shown. The entire transistor is flipped over to fabricate the bottom substrate 2. For easy correspondence with the previous images, the following images are still presented from the perspective of the top substrate 1 on top and the bottom substrate 2 on the bottom.
[0051] A thin layer of silicon dioxide is thermally oxidized on the surface of the bottom substrate 2. Photoresist is then formed on the silicon dioxide surface. Ion implantation windows are formed on the photoresist through exposure and development. N-type lightly doped ions are implanted into the bottom substrate 2 through the ion input windows, and the photoresist is removed. Photoresist is formed again, and ion implantation windows are formed on the photoresist through exposure and development. P-type lightly doped ions are implanted into the bottom substrate 2 through the ion input windows, and the photoresist is removed. High-temperature propagation is then performed to form a layer... Figure 6 The initial first body region 12 and the initial first drift region 13 are shown.
[0052] A thick silicon dioxide layer is chemically vapor deposited on the surface of the bottom substrate 2. The initial first body region 12 and intermediate isolation structure 3 at the bottom of the first initial source 6 and the initial first drift region 13 and intermediate isolation structure 3 at the bottom of the first initial drain 7 are dry etched to form... Figure 7 The first body region 14 and the first drift region 15 are shown. N-type heavily doped silicon is selectively epitaxially grown at the bottom of the first initial source 6 and the first initial drain 7 to form... Figure 8 The source 16 and drain 17 are shown.
[0053] A photoresist is formed on the silicon dioxide surface, and dry etching is performed on the photoresist, retaining a portion of the silicon dioxide on the surface of the first drift region 15, forming a structure as shown in the image. Figure 9 The first field plate oxide layer 18 is shown. The photoresist is removed, and then the surface of the bottom substrate 2 is thermally oxidized to form a thin oxide layer. The oxide layer on the surface of the first body region 14 serves as the first gate oxide layer 19. A layer of heavily doped N-type polysilicon is deposited using low-pressure chemical vapor deposition. Photoresist is formed on the polysilicon, and etching is performed on the photoresist to form an etching window. The polysilicon is etched through the etching window, retaining the first gate oxide layer 19 and part of the polysilicon on the surface of the first field plate oxide layer 18, forming the first polysilicon layer 20. The first polysilicon layer 20 and the first gate oxide layer 19 constitute the first gate, and the first polysilicon layer 20 and the first field plate oxide layer 18 constitute the first field plate. The base substrate 11 and oxide layer on the surface of the top substrate 1 are removed, and the upper surface is polished flat to obtain... Figure 10 The structure shown.
[0054] A first dielectric layer 21 is formed on the lower surface of the bottom substrate 2 using chemical vapor deposition, and a second dielectric layer 22 is formed on the upper surface of the top substrate 1. The upper surface of the second dielectric layer 22 and the lower surface of the first dielectric layer 21 are planarized using chemical mechanical polishing. Figure 11 As shown, a first contact hole 23 is formed in the first dielectric layer 21 using an etching process, and a second contact hole 24 is formed in the second dielectric layer 22. Metal material is then physically vapor-deposited within the first contact hole 23 and the second contact hole 24 to form... Figure 12 The six metal electrodes shown are as follows: the first metal electrode 25 is led down from the source 16 to the lower surface of the first dielectric layer 21; the second metal electrode 26 is led down from the first gate to the lower surface of the first dielectric layer 21; the third metal electrode 27 is led down from the drain 17 to the lower surface of the first dielectric layer 21; the fourth metal electrode 28 is led up from the source 16 to the upper surface of the second dielectric layer 22; the fifth metal electrode 29 is led up from the second gate to the upper surface of the second dielectric layer 22; and the sixth metal electrode 30 is led up from the drain 17 to the upper surface of the second dielectric layer 22.
[0055] Furthermore, the intermediate isolation structure 3 is a single-layer isolation structure.
[0056] Furthermore, the single-layer isolation structure includes a silicon oxide isolation structure or a silicon carbide isolation structure.
[0057] Furthermore, the intermediate isolation structure 3 is a sandwich isolation structure, which includes an intermediate sandwich 31 and an isolation layer 32 wrapped around the intermediate sandwich 31.
[0058] Furthermore, the intermediate interlayer 31 includes a polycrystalline silicon interlayer or a metal interlayer.
[0059] Specifically, in this embodiment of the invention, the intermediate isolation structure 3 can be a single-layer isolation structure. This single-layer isolation structure isolates the transistors in the top substrate 1 from the transistors in the bottom substrate 2, preventing breakdown of the two transistors and improving device reliability. The single-layer isolation structure includes a silicon oxide isolation structure or a silicon carbide isolation structure. The silicon carbide isolation structure can better dissipate heat, increase power density, reduce thermal resistance, and delay device aging. When the single-layer isolation structure includes a silicon oxide isolation structure, the base substrate can be directly an SOI (Silicon On Insulator) substrate.
[0060] Please refer to Figure 13The intermediate isolation structure 3 can be a sandwich isolation structure, comprising an intermediate sandwich layer 31 and an isolation layer 32 surrounding the intermediate sandwich layer 31. The intermediate sandwich layer 31 can be pre-fabricated within the base substrate and includes a polycrystalline silicon sandwich layer or a metal sandwich layer. The isolation layer 32 is made of silicon oxide or silicon carbide. The intermediate sandwich layer 31 can serve as a floating field plate for the first transistor and the second transistor, respectively, optimizing the electric field distribution, improving the breakdown voltage, reducing the surface electric field, and improving the reliability of the transistor.
[0061] A third aspect of the present invention provides a chip comprising the lateral double-diffused field-effect transistor described above.
[0062] A fourth aspect of the present invention provides a circuit comprising the lateral double-diffused field-effect transistor described above.
[0063] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.
[0064] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.
[0065] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.
Claims
1. A lateral double-diffused field-effect transistor, characterized in that, The lateral double-diffused field-effect transistor includes: A base substrate; wherein the base substrate has an intermediate isolation structure that divides the base substrate into a top layer substrate and a bottom layer substrate; With the intermediate isolation structure as the axis of symmetry, a first body region and a second body region, a first drift region and a second drift region, a first gate and a second gate, a first field plate and a second field plate are symmetrically arranged on both sides of the base substrate. The first gate and the first field plate are formed downward on the back side of the bottom substrate, and the second gate and the second field plate are formed upward on the front side of the top substrate. The first body region and the first drift region are formed on the front side of the bottom substrate, and the second body region and the second drift region are formed on the back side of the top substrate. The source electrode is formed on one side of the first body region and the second body region; The drain electrode is formed on one side of the first drift region and the second drift region; The source, the drain, the first body region, the first drift region, the first gate, and the first field plate constitute a first transistor; the source, the drain, the second body region, the second drift region, the second gate, and the second field plate constitute a second transistor.
2. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The intermediate isolation structure is a single-layer isolation structure.
3. The lateral double-diffused field-effect transistor according to claim 2, characterized in that, The single-layer isolation structure includes a silicon oxide isolation structure or a silicon carbide isolation structure.
4. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The intermediate isolation structure is a sandwich isolation structure, which includes an intermediate sandwich layer and an isolation layer wrapped around the intermediate sandwich layer.
5. The lateral double-diffused field-effect transistor according to claim 4, characterized in that, The intermediate interlayer includes a polycrystalline silicon interlayer or a metal interlayer.
6. The lateral double-diffused field-effect transistor according to claim 1, characterized in that, The lateral double-diffused field-effect transistor further includes: A first dielectric layer is formed on the lower surface of the underlying substrate; A second dielectric layer is formed on the upper surface of the top substrate; The first metal electrode is led downward from the source electrode to the lower surface of the first dielectric layer; The second metal electrode is led downward from the first gate to the lower surface of the first dielectric layer; The third metal electrode is led downward from the drain electrode to the lower surface of the first dielectric layer; The fourth metal electrode is led upward from the source electrode to the upper surface of the second dielectric layer; The fifth metal electrode is led upward from the second gate to the upper surface of the second dielectric layer; The sixth metal electrode is led upward from the drain electrode to the upper surface of the second dielectric layer.
7. A method for fabricating a lateral double-diffused field-effect transistor, characterized in that, The method for fabricating the lateral double-diffused field-effect transistor includes: A base substrate is provided; wherein the base substrate has an intermediate isolation structure that divides the base substrate into a top substrate and a bottom substrate; A first body region, a first drift region, a first gate, a first field plate, a second body region, a second drift region, a second gate, a second field plate, a source, and a drain are formed on the base substrate. The first body region and the second body region, the first drift region and the second drift region, the first gate and the second gate, and the first field plate and the second field plate are symmetrically arranged on both sides of the base substrate with the intermediate isolation structure as the axis of symmetry. The first gate and the first field plate are formed downwards on the back side of the bottom substrate, and the second gate and the second field plate are formed upwards on the front side of the top substrate. The first body region and the first drift region are formed on the front side of the bottom substrate, and the second body region and the second drift region are formed on the back side of the top substrate. The source is formed on one side of the first body region and the second body region, and the drain is formed on one side of the first drift region and the second drift region. The source, the drain, the first body region, the first drift region, the first gate, and the first field plate constitute a first transistor, and the source, the drain, the second body region, the second drift region, the second gate, and the second field plate constitute a second transistor.
8. The method for fabricating a lateral double-diffused field-effect transistor according to claim 7, characterized in that, The process of forming a first body region, a first drift region, a first gate, a first field plate, a second body region, a second drift region, a second gate, a second field plate, a source, and a drain on the base substrate includes: A second body region, a second drift region, a second gate, a second field plate, a first initial source, and a first initial drain are formed in the top substrate; wherein the first initial source is formed on the side of the second body region away from the second drift region, and the first initial drain is formed on the side of the second drift region away from the second body region; An initial first bulk region and an initial first drift region are formed on the bottom substrate; The initial first body region and intermediate isolation structure at the bottom of the first initial source electrode, as well as the initial first drift region and intermediate isolation structure at the bottom of the first initial drain electrode, are removed by etching process to form the first body region and the first drift region. A second initial source is formed at the bottom of the first initial source to form the source. A second initial drain is formed at the bottom of the first initial drain to form the drain. The first gate and the first field plate are formed on the underlying substrate.
9. The method for fabricating a lateral double-diffused field-effect transistor according to claim 7, characterized in that, The intermediate isolation structure is a single-layer isolation structure.
10. The method for fabricating a lateral double-diffused field-effect transistor according to claim 9, characterized in that, The single-layer isolation structure includes a silicon oxide isolation structure or a silicon carbide isolation structure.
11. The method for fabricating a lateral double-diffused field-effect transistor according to claim 7, characterized in that, The intermediate isolation structure is a sandwich isolation structure, which includes an intermediate sandwich layer and an isolation layer wrapped around the intermediate sandwich layer.
12. The method for fabricating a lateral double-diffused field-effect transistor according to claim 11, characterized in that, The intermediate interlayer includes a polycrystalline silicon interlayer or a metal interlayer.
13. The method for fabricating a lateral double-diffused field-effect transistor according to claim 7, characterized in that, After forming the first transistor and the second transistor, the method further includes: A first dielectric layer is formed on the lower surface of the bottom substrate, and a second dielectric layer is formed on the upper surface of the top substrate; A first contact hole is formed in the first dielectric layer, and a second contact hole is formed in the second dielectric layer; wherein the first contact hole contacts the source, the drain and the first gate respectively, and the second contact hole contacts the source, the drain and the second gate respectively; A first metal electrode, a second metal electrode, and a third metal electrode are formed in the first contact hole, respectively; wherein, the first metal electrode is led down from the source to the lower surface of the first dielectric layer, the second metal electrode is led down from the first gate to the lower surface of the first dielectric layer, and the third metal electrode is led down from the drain to the lower surface of the first dielectric layer. A fourth metal electrode, a fifth metal electrode, and a sixth metal electrode are formed in the second contact hole, respectively; wherein, the fourth metal electrode is led upward from the source to the upper surface of the second dielectric layer, the fifth metal electrode is led upward from the second gate to the upper surface of the second dielectric layer, and the sixth metal electrode is led upward from the drain to the upper surface of the second dielectric layer.
14. A chip, characterized in that, The chip includes a lateral double-diffused field-effect transistor as described in any one of claims 1-7.
15. A circuit, characterized in that, The circuit includes a lateral double-diffused field-effect transistor as described in any one of claims 1-7.