Fluorine ion implantation process for high-voltage, low-leakage-current GaN Schottky diodes

Abstract

This invention discloses a fluorine ion implantation process for high-voltage, low-leakage-current GaN Schottky diodes, relating to the field of semiconductor device fabrication technology. The specific steps of this process are: using a specific doping concentration of n... + -GaN bulk substrate, n-type substrate grown using hydride vapor phase epitaxy. ‑ - GaN drift layer; deposition of hard mask and self-aligned fluorine ion implantation to form a distribution region; removal of mask and deposition of polarization matching layer; electrode fabrication and annealing; finally, the fabricated diode is subjected to characteristic testing, and the process parameters of polarization matching layer and fluorine ion implantation are adjusted according to the results; this invention adopts a self-aligned implantation process to achieve simultaneous patterning of mesa isolation and fluorine ion implantation region, improving device withstand voltage and reducing leakage current; it also systematically optimizes the entire device fabrication process, improves bonding quality, reduces lattice defects, optimizes interface and contact effects, enhances fabrication repeatability and stability, simplifies the process, and improves efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, specifically to the fluorine ion implantation process for high-voltage, low-leakage-current GaN Schottky diodes. Background Technology

[0002] GaN, as a third-generation wide-bandgap semiconductor material, has become a core material for fabricating high-frequency, high-voltage, and high-temperature power semiconductor devices due to its high breakdown field strength, high electron saturation drift velocity, excellent high-temperature stability, and radiation resistance. GaN Schottky diodes, as typical power semiconductor devices, are increasingly demonstrating their application value in the field of power electronics. With the rapid development of power electronics technology towards miniaturization, high efficiency, and integration, the performance bottlenecks of traditional silicon-based power devices are becoming increasingly apparent, making it difficult to meet the requirements of high-frequency and high-voltage application scenarios. GaN-based power devices have become an important direction to replace traditional silicon-based devices. The withstand voltage and leakage current of Schottky diodes are the core parameters for measuring their operating performance. Fluorine ion implantation is a key means to regulate the electrical properties of GaN materials and optimize the performance of Schottky diodes. Therefore, developing fluorine ion implantation processes adapted to GaN Schottky diodes to improve the withstand voltage level and reduce leakage current has become a research focus and development trend in the industry.

[0003] Traditional fluorine ion implantation processes for GaN Schottky diodes suffer from numerous technical defects. Firstly, in the patterning stage, the definition of the mesa isolation etching and fluorine ion implantation regions often employs multiple photolithography processes, increasing the complexity of the fabrication process and increasing the risk of positioning errors. This results in insufficient spatial distribution accuracy of the fluorine ion implantation region, leading to electric field concentration at the Schottky contact edges and subsequent edge breakdown, significantly reducing the device's breakdown voltage. Secondly, traditional processes lack targeted polarization structure design after fluorine ion implantation, resulting in poor compatibility with the implantation region's structure and performance. This leads to undesirable device interface characteristics, difficulty in effectively suppressing carrier tunneling behavior, and persistent challenges in optimizing leakage current. Furthermore, the lack of systematic synergistic optimization across various process stages, such as substrate pretreatment, epitaxial growth, and electrode fabrication, results in poor material crystal quality, numerous lattice defects, poor contact between the electrode and semiconductor material, high contact resistance, and inappropriate hard mask selection and processing, further impacting the etching and implantation process accuracy. Ultimately, this leads to poor consistency in the device's electrical performance and compromises long-term reliability. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a fluoride ion implantation process for high-voltage, low-leakage-current GaN Schottky diodes. The entire process design and improvement revolves around optimizing the performance of GaN Schottky diodes. The core technology employs a self-aligned implantation process to simultaneously define the mesa isolation etching region and the fluoride ion implantation region, achieving precise and selective fluoride ion implantation. A polarization matching layer deposition process is also specifically designed. Furthermore, systematic process optimizations are performed on each step, including substrate pretreatment, epitaxial layer growth, hard mask fabrication, electrode deposition, and annealing. This process effectively controls the electric field distribution at the Schottky contact edge, suppresses edge breakdown, reduces device leakage current, and improves voltage withstand performance. Simultaneously, it optimizes the device interface and electrode contact characteristics, enhancing electrical performance consistency and operational reliability, and simplifying the fabrication process. This provides an efficient and feasible process solution for the fabrication of high-performance GaN Schottky diodes.

[0005] To solve the above-mentioned technical problems, this invention provides the following technical solution: a fluorine ion implantation process for high-voltage, low-leakage-current GaN Schottky diodes, the specific steps of which are as follows:

[0006] Epitaxial layer fabrication: with Ge doping concentration of 10 18 cm -3 n + Using a GaN bulk substrate as the base, hydride vapor phase epitaxy was employed to grow Si doped to a concentration of 10 on the substrate surface. 17 cm -3 n with a thickness of 8.4μm - -GaN drift layer;

[0007] Self-aligned injection: in n - - A Ni / SiO2 dual-layer hard mask is deposited on the GaN drift layer surface. A single photolithography process simultaneously defines the mesa isolation etching region and the fluorine ion implantation region. After completing the 1μm deep mesa isolation etching, the patterned dual-layer hard mask is used as the implantation mask. fluorine ion selective implantation is performed sequentially at energies of 40keV, 80keV, and 140keV, forming a 300-350nm deep GaN region with a concentration of 2×10⁻⁶ ions at the Schottky contact edge. 18 -10 19 cm -3 The fluoride ion distribution region is controlled such that the lateral distance between the fluoride ion implantation region and the Schottky contact edge is 0.1-0.3 μm.

[0008] Polarization layer deposition: Remove the Ni / SiO2 double hard mask and deposit a polarization matching layer with a thickness of 50-100nm above the fluorine ion implantation region. The polarization matching layer is a gradient AlGaN layer with an Al composition that linearly changes from 0.1 to 0.3, or an AlGaN / GaN superlattice structure with a single-period thickness of 5-10nm and a period number of 10-20.

[0009] Electrode fabrication annealing: A 100 nm thick SiO2 dielectric layer was deposited on the surface of the polarization matching layer. A circular Schottky contact window with a diameter of 100 μm was opened by photolithography and BOE wet etching. After immersion in HCl solution, the Pt / Au Schottky electrode and Ti / Pt / Au ohmic electrode were deposited and formed in sequence. The sample was placed in a N2 atmosphere for rapid thermal annealing at 400 °C for 10 minutes.

[0010] Calibration of detection parameters: The forward IV, reverse IV and CV characteristics of the fabricated GaN-based Schottky barrier diodes were tested. The electric field distribution and peak value at the Schottky contact edge were detected. The composition parameters of the polarization matching layer and the process parameters of fluorine ion implantation were adjusted based on the test results.

[0011] Furthermore, in the epitaxial layer preparation step, n is first... + - The GaN bulk substrate is pretreated as follows: the substrate is ultrasonically cleaned in acetone solution for 10-15 min, then ultrasonically cleaned in isopropanol solution for 10-15 min, then immersed in a 1:3 mixture of hydrofluoric acid and deionized water for 30-60 s, and finally rinsed 3-5 times with ultrapure water with a resistivity ≥18.2 MΩ·cm and dried with high-purity nitrogen.

[0012] Furthermore, in the epitaxial layer preparation step, n is grown using a hydride vapor phase epitaxy process. - Before the GaN drift layer, a 200 nm thick GaN buffer layer is grown at 1080 °C and 100 Torr. Then, the reaction conditions are adjusted to 1050 °C and 50 Torr to grow a 200 nm thick GaN buffer layer. - - For the GaN drift layer, the flow rate of hydrogen chloride gas during growth is 50 sccm, the flow rate of ammonia gas is 3000 sccm, the flow rate of trimethylgallium gas is 20 sccm, and the fluctuation range of silane flow rate is controlled within ±2%.

[0013] Furthermore, in the self-aligned implantation step, the deposition process of the Ni / SiO2 double-layer hard mask is as follows: a 50-100 nm thick SiO2 layer is deposited using plasma-enhanced chemical vapor deposition (PECVD), with silane and nitrous oxide as the reactant gases at a flow rate ratio of 1:10, a deposition temperature of 200 °C, a deposition pressure of 1 Torr, and a deposition rate of 10 nm / min; then, a 20-50 nm thick Ni layer is deposited using electron beam evaporation (EBBE), with a vacuum degree ≤2 × 10⁻⁶ during the deposition process. -4 Pa, deposition rate of 0.05 nm / s, and vacuum baking at 120℃ for 10 min after deposition.

[0014] Furthermore, in the self-aligned injection step, the photolithography process is as follows: AZ5214 photoresist is spin-coated onto the surface of a double-layer hard mask at a spin speed of 3000 r / min for 30 s, with the photoresist thickness controlled at 1.4 μm; after spin-coating, it is pre-baked on a 110℃ hot plate for 90 s, followed by UV contact exposure with an exposure dose of 80-100 mJ / cm². 2 After exposure, develop in AZ300MIF developer for 45-60 seconds, rinse with deionized water, and then bake on a hot plate at 120°C for 120 seconds.

[0015] Furthermore, in the self-aligned injection step, the mesa isolation etching adopts inductively coupled plasma etching process. During the etching process, the ICP source power is 500W, the bias power is 100W, the etching gas Cl2 flow rate is 30sccm, the BCl3 flow rate is 10sccm, the cavity pressure is 5mTorr, the etching rate is controlled at 100nm / min, and a 30s pause is taken every 100nm of etching. The etching depth uniformity deviation is controlled within ±3%.

[0016] Furthermore, in the self-aligned implantation step, the cavity vacuum degree during the selective implantation of fluoride ions is ≤5×10⁻⁶. -6 Pa, with an injection angle of 7°, and single-stage injection doses corresponding to injection energies of 40keV, 80keV, and 140keV are respectively 4×10 Pa. 14 cm -2 5×10 14 cm -2 6×10 14 cm -2 The total injected dose was 1.5 × 10⁻⁶. 15 cm -2 .

[0017] Furthermore, in the polarization layer deposition step, the removal process of the Ni / SiO2 double-layer hard mask is as follows: First, the sample is placed in a nickel etching solution with a volume ratio of nitric acid to glacial acetic acid of 3:1 and immersed in a water bath at 40°C for 10-15 minutes, followed by rinsing with ultrapure water three times; then, the SiO2 layer is removed by inductively coupled plasma dry etching, with the etching gas being carbon tetrafluoride and oxygen at a flow ratio of 9:1, the ICP source power being 300W, the bias power being 50W, and the chamber pressure being 10mTorr. The etching endpoint is monitored in real time by an optical emission spectrometer.

[0018] Furthermore, in the polarization layer deposition step, the polarization matching layer is deposited using a metal-organic chemical vapor deposition process at a growth temperature of 900-1000℃ and a growth pressure of 100-200 Torr. N2 is used as the carrier gas, trimethylaluminum and trimethylgallium are used as metal sources, and ammonia is used as the nitrogen source. The deposition area of ​​the polarization matching layer completely covers the fluorine ion implantation area and extends outward by 0.5 μm along the lateral edge of the fluorine ion implantation area.

[0019] Furthermore, in the electrode fabrication annealing step, the deposition process of the Pt / Au Schottky electrode is as follows: under a vacuum degree ≤ 5 × 10⁻⁶. -5 Under a Pa environment, a 40 nm thick Pt layer and a 250 nm thick Au layer were sequentially deposited using electron beam evaporation. The Pt layer deposition rate was 0.05 nm / s, and the Au layer deposition rate was 0.1 nm / s. The sample stage temperature was maintained at 25 °C during the deposition process. The deposition process of the Ti / Pt / Au ohmic electrode was as follows: for n + - After performing inductively coupled plasma etching to a depth of 500 nm on the back side of the GaN bulk substrate, a 50 nm thick Ti layer, a 100 nm thick Pt layer, and a 50 nm thick Au layer were sequentially deposited using electron beam evaporation.

[0020] Compared with existing technologies, the fluorine ion implantation process for this high-voltage, low-leakage-current GaN Schottky diode has the following advantages:

[0021] I. This invention employs a self-aligned implantation process to achieve simultaneous patterning definition of the mesa isolation etching region and the fluorine ion implantation region, eliminating the tedious steps of multiple photolithography processes. This enables precise positioning of the fluorine ion implantation region, allowing fluorine ions to form a uniform ion distribution region at the Schottky contact edge. Combined with a suitable polarization matching layer, the electric field distribution at the contact edge can be effectively controlled, suppressing edge breakdown and structurally improving the device's breakdown voltage performance. Simultaneously, the selective implantation of fluorine ions optimizes the Schottky barrier characteristics, reduces carrier tunneling behavior, and fundamentally reduces device leakage current. The rational selection and processing of the hard mask ensures the patterning accuracy of the etching and implantation processes, resulting in a more uniform spatial distribution of the ion implantation region and further improving the consistency of the device's electrical performance.

[0022] II. This invention systematically optimizes the entire device fabrication process, starting with the refined pretreatment of the substrate to improve the bonding quality between the epitaxial layer and the substrate. The layered construction mode in the epitaxial growth stage optimizes the crystallization characteristics of the material, reduces the generation of lattice defects, and lays a good material foundation for the device. The targeted deposition design of the polarization matching layer can form a structural and performance fit with the fluorine ion implantation region, improving the interface characteristics of the device. The surface treatment, layered deposition, and subsequent annealing processes in the electrode fabrication process optimize the contact effect between the electrode and the semiconductor material, reducing contact resistance. The coordinated control of each process step in the entire process not only improves the overall electrical performance of the device, but also enhances the repeatability and stability of the fabrication process, improves the reliability of the device in long-term operation, and simplifies the core process steps, thereby improving the overall fabrication efficiency.

[0023] Other advantages, objectives and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from the practice of the invention. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0025] Figure 1 This is a flowchart of the fluorine ion implantation process for a high-voltage, low-leakage-current GaN Schottky diode. Detailed Implementation

[0026] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0027] Example 1:

[0028] Fluorine ion implantation process for high-voltage, low-leakage-current GaN Schottky diodes

[0029] This embodiment fully implements the fluorine ion implantation process for high-voltage, low-leakage-current GaN Schottky diodes, sequentially performing the entire process of epitaxial layer fabrication, self-aligned implantation, polarization layer deposition, and electrode fabrication and annealing. Each step strictly controls process operation details and parameters to ensure the accuracy and stability of the process implementation. Specific operations are as follows: Figure 1 As shown:

[0030] Epitaxial layer preparation:

[0031] Select a Ge doping concentration of 10 18 cm -3 n + Using a GaN bulk substrate as the base, the substrate underwent pretreatment. The substrate was ultrasonically cleaned in acetone solution for 12 minutes. After cleaning, the substrate was removed and the acetone solution drained. It was then ultrasonically cleaned again in isopropanol solution for 12 minutes. After this, the substrate was removed and rinsed with ultrapure water to remove any residual isopropanol. The substrate was then immersed in a 1:3 mixture of hydrofluoric acid and deionized water for 45 seconds, keeping the solution still without stirring. After immersion, the substrate was quickly removed and rinsed four times with ultrapure water with a resistivity ≥18.2 MΩ·cm. Each rinse completely submerged the substrate and gently agitated it. Finally, the substrate was dried in a continuous and uniform flow of high-purity nitrogen, avoiding watermarks on the substrate surface during the drying process.

[0032] After substrate pretreatment, epitaxial layer growth was performed using hydride vapor phase epitaxy. First, the pretreated substrate was placed in an epitaxial reaction chamber, with the chamber temperature controlled at 1080℃ and the pressure at 100 Torr. A GaN buffer layer with a thickness of 200 nm was grown on the substrate surface. After growth, the internal conditions of the reaction chamber were adjusted, with the temperature reduced to 1050℃ and the pressure adjusted to 50 Torr. Then, n nm was grown on the surface of the GaN buffer layer. - -GaN drift layer. During the growth of the drift layer, hydrogen chloride gas, ammonia gas, trimethylgallium gas, and silane were continuously introduced. The flow rate of hydrogen chloride gas was controlled at 50 sccm, the flow rate of ammonia gas at 3000 sccm, the flow rate of trimethylgallium gas at 20 sccm, and the flow rate of silane was kept stable. Finally, a Si doping concentration of 10 was obtained. 17 cm -3 n with a thickness of 8.4μm - -GaN drift layer.

[0033] Self-aligned injection:

[0034] In n - A Ni / SiO2 dual-layer hard mask was deposited on the surface of the GaN drift layer. First, a SiO2 layer with a thickness of 80 nm was deposited using plasma-enhanced chemical vapor deposition (PECVD). During deposition, silane and nitrous oxide were introduced as reactant gases at a flow rate ratio of 1:10. The deposition temperature was controlled at 200℃, the deposition pressure at 1 Torr, and the deposition rate at 10 nm / min. After the SiO2 layer was deposited, a Ni layer with a thickness of 35 nm was deposited using electron beam evaporation (EBBE). During deposition, the vacuum level in the cavity was controlled at 1 × 10⁻⁶. -4Pa, deposition rate of 0.05 nm / s. After the Ni layer was deposited, the sample was placed in a vacuum environment at 120°C for baking for 10 minutes.

[0035] A photolithography process was performed on the surface of a double-layer hard mask. First, photoresist was spin-coated onto the mask surface at a spin speed of 3000 r / min for 30 seconds, ensuring uniform coverage of the mask surface with a thickness of 1.4 μm. After spin-coating, the sample was pre-baked at 110℃ for 90 seconds. Following pre-baking, ultraviolet contact exposure was performed at a dose of 90 mJ / cm². 2 After exposure, the sample is placed in the developer for development for 50 seconds. After development, the sample surface is rinsed with deionized water to remove any remaining developer. Finally, the sample is placed on a hot plate at 120°C for post-baking for 120 seconds. This photolithography process simultaneously defines the tabletop isolation etching area and the fluorine ion implantation area.

[0036] Mesa isolation etching was performed using inductively coupled plasma etching (ICP) technology. During the etching process, the ICP source power was controlled at 500W and the bias power at 100W. Cl2 and BCl3 were introduced as etching gases, with a Cl2 flow rate of 30 sccm and a BCl3 flow rate of 10 sccm. The pressure inside the chamber was maintained at 5 mTorr, and the etching rate was controlled at 100 nm / min. The etching process was paused for 30 seconds after every 100 nm of etching to release the stress generated during the etching process. Finally, mesa isolation etching with a depth of 1 μm was completed, and the etching process ensured the uniformity of the etching depth.

[0037] Selective fluoride ion implantation was performed using a graphical double-layer hard mask as the implantation mask. During the implantation process, the vacuum level within the cavity was controlled at 3 × 10⁻⁶. -6 Pa, with the injection angle adjusted to 7°, fluoride ion implantation was performed sequentially using energies of 40keV, 80keV, and 140keV, corresponding to single-stage implantation doses of 4×10⁻⁶ Pa. 14 cm -2 5×10 14 cm -2 6×10 14 cm -2 The total injected dose was 1.5 × 10⁻⁶. 15 cm -2 By precisely controlling the injection parameters, a 320nm deep GaN region with a concentration of 5×10⁻⁶ was formed in the GaN region at the edge of the Schottky contact. 18 cm -3 The fluoride ion distribution region, the lateral distance between the fluoride ion implantation region and the Schottky contact edge is controlled to be 0.2 μm.

[0038] Polarization layer deposition:

[0039] After fluorine ion implantation, the Ni / SiO2 double-layer hard mask was removed. The sample was first immersed in a nickel etching solution containing nitric acid and glacial acetic acid at a volume ratio of 3:1, and then in a 40°C water bath for 12 minutes. After immersion, the sample was removed and rinsed three times with ultrapure water to remove any residual etching solution. Subsequently, an inductively coupled plasma (ICP) dry etching process was used to remove the SiO2 layer. The etching gases were carbon tetrafluoride and oxygen at a flow ratio of 9:1. The ICP source power was controlled at 300W, the bias power at 50W, and the chamber pressure at 10mTorr. During the etching process, the etching status was monitored in real-time using an optical emission spectrometer to determine the etching endpoint and ensure complete removal of the SiO2 layer without any residue.

[0040] A polarization matching layer was deposited above the fluorine ion implantation region using metal-organic chemical vapor deposition. In this embodiment, a gradient AlGaN layer with an Al composition linearly varying from 0.1 to 0.3 was selected as the polarization matching layer, with a thickness of 75 nm. During the deposition process, the growth temperature was controlled at 950 °C and the growth pressure at 150 Torr. N2 was used as the carrier gas, trimethylaluminum and trimethylgallium were used as the metal sources, and ammonia was used as the nitrogen source. The deposition range was precisely controlled during the deposition process to ensure that the polarization matching layer completely covered the fluorine ion implantation region and extended outward by 0.5 μm along the lateral edge of the fluorine ion implantation region.

[0041] Electrode preparation annealing:

[0042] A 100 nm thick SiO2 dielectric layer was deposited on the surface of the polarization matching layer. After deposition, a circular Schottky contact window with a diameter of 100 μm was formed on the surface of the dielectric layer using photolithography and BOE wet etching. The sample with the window formed was then immersed in an HCl solution to remove impurities and oxide layers from the window surface. After immersion, the sample was removed and dried, and Pt / Au Schottky electrodes and Ti / Pt / Au ohmic electrodes were deposited sequentially.

[0043] The Pt / Au Schottky electrode was deposited using an electron beam evaporation process, with the sample placed under a vacuum of 3 × 10⁻⁶. -5 In the Pa deposition chamber, a Pt layer with a thickness of 40 nm and a deposition rate of 0.05 nm / s is deposited first. After the Pt layer is deposited, an Au layer with a thickness of 250 nm and a deposition rate of 0.1 nm / s is deposited. Throughout the deposition process, the sample stage temperature is maintained at 25 °C to ensure the uniformity of the electrode layer deposition.

[0044] The Ti / Pt / Au ohmic electrode is also deposited using an electron beam evaporation process, first by depositing n +- Inductively coupled plasma etching was performed on the back side of the GaN bulk substrate to a depth of 500 nm. After etching, the back side of the substrate was cleaned, and then Ti, Pt and Au layers were deposited sequentially. The thickness of the Ti layer was 50 nm, the thickness of the Pt layer was 100 nm, and the thickness of the Au layer was 50 nm. The deposition process of each layer ensured uniform thickness and no pinholes.

[0045] After electrode deposition, the sample was placed in an N2 atmosphere for rapid thermal annealing. The annealing temperature was controlled at 400℃ and the annealing time was 10 minutes. After annealing, the sample was allowed to cool naturally to room temperature, thus completing the entire fluorine ion implantation process for the GaN Schottky diode.

[0046] Example 2:

[0047] Performance testing of epitaxial layer fabrication process.

[0048] This embodiment conducts comprehensive performance testing on the epitaxial layer fabrication process, focusing on the surface cleanliness of the substrate after pretreatment, the thickness and doping concentration uniformity of the epitaxial layer after growth, and the crystal quality of the epitaxial layer. By setting different pretreatment process parameters, the influence of parameter changes on the overall epitaxial layer fabrication performance is explored, providing experimental basis for the selection of parameters in the epitaxial layer fabrication process. The specific test operations are as follows:

[0049] Substrate pretreatment surface cleanliness test:

[0050] Three Ge-doped n-type wafers of the same specifications were selected. + For GaN bulk substrates, three different pretreatment parameters were set for each substrate to carry out pretreatment operations. All three parameters controlled the ultrasonic, immersion, and rinsing operations according to process requirements, with only the duration and number of cycles adjusted. After pretreatment, X-ray photoelectron spectroscopy was used to perform elemental analysis on the surfaces of the three substrates, accurately determining the content of surface impurities such as C and O to determine whether the surface cleanliness met the requirements for epitaxial layer growth.

[0051] Epitaxial layer thickness and doping concentration uniformity test:

[0052] Based on the epitaxial layer growth process of Example 1, GaN buffer layers and n-type epitaxial layers were grown on three pretreated substrates. - -GaN drift layer: After growth, the thickness of the epitaxial layer of each sample was measured using an ellipsometry. Five test points were selected on the sample surface, including the center and surrounding areas. The thickness of the buffer layer and drift layer at each test point was recorded, and the thickness deviation was calculated to determine the thickness uniformity. Simultaneously, a secondary ion mass spectrometer was used to analyze the n... - - The Si doping concentration of the GaN drift layer was tested. Multiple test points were selected along the depth direction of the drift layer, the doping concentration at each point was recorded, the concentration deviation value was calculated, and the uniformity of the doping concentration was judged.

[0053] Epitaxial layer crystal quality test:

[0054] For the three samples with completed epitaxial layers, high-resolution X-ray diffraction was used to test the GaN buffer layer and n... - The crystal quality of the GaN drift layer is mainly tested by measuring the half-width at half-maximum (WHM) of the rocking curve. The smaller the WHM value, the better the crystal orientation of the epitaxial layer, the fewer the lattice defects, and the better the crystal quality. This indicator can be used to intuitively evaluate the crystal performance of the epitaxial layer.

[0055] Comparison of epitaxial layer fabrication performance with different pretreatment parameters.

[0056] Preprocessing scheme Acetone ultrasound duration Isopropanol ultrasound duration Soaking time in hydrofluoric acid mixture Number of ultrapure water rinses Surface C impurity content Surface O impurity content Drift layer thickness deviation Drift layer doping concentration deviation Buffer layer rocking curve half-width Option 1 10 minutes 10 minutes 30 seconds 3 times 0.48at.% 0.29at.% 0.95% 1.90% 198arcsec Option 2 12 minutes 12 minutes 45 seconds 4 times 0.42at.% 0.25at.% 0.80% 1.50% 185arcsec Option 3 15 minutes 15 minutes 60 seconds 5 times 0.40at.% 0.24at.% 0.85% 1.60% 188arcsec

[0057] The test data above shows that under all three pretreatment schemes, the C and O impurity content on the substrate surface is at an extremely low level. This indicates that within the pretreatment parameter range of this process, regardless of the adjustment of time and number of cycles, organic contaminants and the natural oxide layer on the substrate surface can be effectively removed, achieving a good surface cleaning effect. The impurity content of Scheme 3 is slightly lower than that of Schemes 1 and 2, but the difference is minimal. Scheme 2 has the smallest drift layer thickness deviation and doping concentration deviation among the three groups, and the half-width at half-maximum (WHM) of the buffer layer rocking curve is also at a low level, indicating that the epitaxial layer prepared under these parameters has the best uniformity in thickness and doping concentration, and the crystal quality is also superior. The deviation values ​​of Scheme 1 are slightly higher, and its overall performance is slightly inferior to Schemes 2 and 3. Although Scheme 3 has the lowest impurity content, the thickness and doping uniformity of the epitaxial layer are slightly worse than those of Scheme 2. In summary, all three pretreatment parameters can meet the process requirements for epitaxial layer preparation. Among them, the parameter combination of 12 minutes of acetone ultrasound, 12 minutes of isopropanol ultrasound, 45 seconds of hydrofluoric acid mixture immersion, and 4 rinses with ultrapure water can achieve the best overall performance in epitaxial layer preparation.

[0058] Example 3:

[0059] Performance testing of the self-aligned injection process.

[0060] This embodiment conducts comprehensive performance testing on the self-aligned implantation process, focusing on the surface integrity and etching resistance of the Ni / SiO2 double-layer hard mask, the depth uniformity and surface smoothness of the mesa isolation etching, and the distribution characteristics after fluorine ion implantation. By setting different Ni layer thickness parameters, the influence of these parameters on the overall performance of the self-aligned implantation process is explored, and the correlation between mask thickness and process performance is verified. The specific test operations are as follows:

[0061] Ni / SiO2 dual-layer hard mask performance test:

[0062] Keeping the SiO2 layer thickness of 80nm and the deposition process parameters unchanged, only the Ni layer deposition thickness was adjusted to prepare three double-layer hard mask samples with Ni layer thicknesses of 20nm, 35nm, and 50nm, respectively. The three samples were processed according to the mesa isolation etching and fluorine ion implantation process in Example 1. After processing, the mask morphology on the sample surface was observed using a scanning electron microscope to determine whether there was any peeling, cracking, or damage to the mask, and to evaluate the surface integrity and etching resistance of the mask.

[0063] Tabletop isolation etching effect test:

[0064] For the three samples that underwent etching and implantation treatments, a profilometer was used to test the depth of the etched area on the mesa. Multiple test points were selected in the etched area, and the etching depth at each point was recorded. The depth deviation value was calculated to evaluate the uniformity of the etching depth. At the same time, the surface and edge morphology of the etched area were observed using a scanning electron microscope to determine whether there were problems such as edge chipping, over-etching, or surface roughness, and to evaluate the smoothness of the etched surface.

[0065] Fluorine ion implantation distribution characteristics test:

[0066] The fluoride ion implantation region of three samples was tested using a secondary ion mass spectrometer. Test points were selected along the depth and lateral directions of the GaN material, and the distribution depth and concentration of fluoride ions at each point were recorded. At the same time, the lateral distance between the fluoride ion implantation region and the Schottky contact edge was measured to determine whether fluoride ions formed the distribution region designed for the process and to evaluate the distribution characteristics of fluoride ion implantation.

[0067] Comparison table of self-aligned implantation process effects with different Ni layer thicknesses.

[0068] Ni layer thickness Mask surface condition Mask etch resistance Etching depth deviation Surface smoothness of etching Fluoride ion distribution depth Fluoride ion concentration Lateral distance of injection zone 20nm Minor localized peeling generally 2.80% Slight edge chipping 310nm <![CDATA[4.2×10 18 cm -3 ]]> 0.22μm 35nm intact and undamaged Excellent 1.20% Smooth and defect-free surface 320nm <![CDATA[5.0×10 18 cm -3 ]]> 0.20μm 50nm intact and undamaged Excellent 1.30% Smooth and defect-free surface 325nm <![CDATA[5.1×10 18 cm -3 ]]> 0.19μm

[0069] The test data above clearly shows that the Ni layer thickness has a significant impact on the self-aligned implantation process. For samples with a 20nm Ni layer thickness, the mask exhibits slight localized peeling, moderate etching resistance, and a large etching depth deviation, along with slight edge chipping. This is because the thinner Ni layer cannot effectively resist the impact of etching gas and fluorine ion implantation, leading to a decrease in mask protection and consequently affecting the subsequent etching and implantation processes. Samples with 35nm and 50nm Ni layer thicknesses, however, maintain an intact and undamaged mask, exhibiting excellent etching resistance, a smooth and defect-free etched surface, and a low etching depth deviation. Fluorine ions also form a uniform distribution area consistent with the process design, indicating that these two Ni layer thicknesses provide good mask protection for the etching and implantation processes. Among the three groups, the sample with a 35nm Ni layer thickness exhibited the smallest etching depth deviation, and the lateral distance between the fluorine ion implantation region and the Schottky contact edge was precisely controlled at 0.2μm, demonstrating the best process precision. While the 50nm Ni layer thickness sample showed good performance across the board, it did not offer a significant performance improvement compared to the 35nm thickness and increased the deposition cost and subsequent removal difficulty of the Ni layer. Considering both process performance and cost factors, a 35nm Ni layer thickness is the optimal choice for the self-aligned implantation process.

[0070] Example 4

[0071] Performance testing of polarization layer deposition process.

[0072] This embodiment focuses on system performance testing of the polarization layer deposition process, specifically testing the deposition coverage integrity, polarization intensity, and interfacial compatibility with the GaN substrate of the polarization matching layer. Two types of polarization matching layers were prepared: a gradient AlGaN layer and an AlGaN / GaN superlattice structure. For each structure, three different sets of deposition thickness parameters were set to explore the influence of structure type and thickness parameters on the polarization layer deposition performance. The specific test procedures are as follows:

[0073] Polarization layer deposition coverage integrity test:

[0074] Following the polarization layer deposition process of Example 1, gradient AlGaN layers and AlGaN / GaN superlattice structure polarization layer samples of different thicknesses were prepared. The morphology of the polarization layer of each sample was observed using a scanning electron microscope. The focus was on observing the coverage of the polarization layer over the fluorine ion implantation region to determine whether it completely covered the implantation region and whether the extension distance along the lateral edge met the process requirements. At the same time, the presence of defects such as pinholes and voids on the surface of the polarization layer was observed to evaluate the integrity of the coverage.

[0075] Polarization intensity test of polarization layer:

[0076] The polarization intensity of each polarization layer sample was tested using a ferroelectric tester. The test conditions were kept consistent during the test. The polarization intensity values ​​of each sample's polarization layer were obtained through precise measurement. The higher the polarization intensity value, the better the polarization characteristics of the polarization layer and the better the polarization improvement effect on the fluorine ion implantation region.

[0077] Polarization layer interface compatibility test:

[0078] High-resolution X-ray diffraction was used to perform interface tests on each sample, focusing on the analysis of the interfacial lattice structure between the polarization layer and the GaN substrate. The lattice mismatch rate was calculated; a lower lattice mismatch rate indicates a higher lattice matching degree between the polarization layer and the GaN substrate, better interfacial compatibility, and can effectively reduce interface defects, ensuring the electrical performance of the device. Simultaneously, scanning electron microscopy was used to observe the interface morphology to determine the presence of problems such as diffusion layers and delamination.

[0079] Comparison table of polarization layer deposition performance with different structures and thicknesses.

[0080] Polarization matching layer structure Deposition thickness parameters Coverage integrity polarization intensity Lattice mismatch Interface appearance status Gradient AlGaN layer 50nm Basic coverage, with localized micro-pinholes <![CDATA[1.0C / m 2 ]]> 0.45% The interface is clear and there is no obvious diffusion. Gradient AlGaN layer 75nm Complete coverage, no surface defects <![CDATA[1.2C / m 2 ]]> 0.40% The interface is clear, without any blurring or layering. Gradient AlGaN layer 100nm Complete coverage, no surface defects <![CDATA[1.1C / m 2 ]]> 0.42% The interface is clear, without any blurring or layering. AlGaN / GaN superlattice structure Single cycle 5nm - Number of cycles 10 Complete coverage, no surface defects <![CDATA[1.3C / m 2 ]]> 0.38% The interface is clear and there is no obvious diffusion. AlGaN / GaN superlattice structure Single cycle 8nm - Number of cycles 15 Complete coverage, no surface defects <![CDATA[1.5C / m 2 ]]> 0.35% The interface is clear, without any blurring or layering. AlGaN / GaN superlattice structure 10nm per cycle - 20 cycles Complete coverage, no surface defects <![CDATA[1.4C / m 2 ]]> 0.36% The interface is clear, without any blurring or layering.

[0081] The test data above show that both the structure type and deposition thickness of the polarization matching layer have a significant impact on deposition performance. For the gradient AlGaN layer, the 50nm thick sample exhibits localized micro-pinholes, slightly poor coverage integrity, and the lowest polarization intensity among the three groups. The 75nm thick sample reaches a peak polarization intensity of 1.2C / m. 2 The lattice mismatch rate was also the lowest among the three groups. Although the 100nm thick sample had complete coverage, the polarization intensity decreased slightly, indicating that there is an optimal deposition thickness for the gradient AlGaN layer; both excessively thick and thin layers will affect the polarization performance. For the AlGaN / GaN superlattice structure, samples under all three thickness parameters achieved complete coverage, and the overall polarization intensity was higher than that of the gradient AlGaN layer, with a lower lattice mismatch rate. Among them, the samples with a single period of 8nm to 15 periods achieved a polarization intensity of 1.5C / m. 2 The lattice mismatch rate was as low as 0.35%, the best among all samples, indicating that the polarization characteristics and interfacial compatibility of this structure are superior to those of the gradient AlGaN layer. Comparing the two structures, the preparation process of the gradient AlGaN layer is relatively simple, and it can achieve good overall performance at a thickness of 75 nm. Although the preparation process of the AlGaN / GaN superlattice structure is relatively complex, its polarization performance and interfacial compatibility are superior. The parameter combination of 8 nm per period to 15 periods is the optimal deposition parameter for this structure.

[0082] Example 5:

[0083] Performance testing of electrode preparation annealing process.

[0084] This embodiment focuses on specific performance tests for the electrode preparation annealing process, specifically testing the Schottky barrier height and uniformity of the Pt / Au Schottky electrode, the ohmic contact resistivity of the Ti / Pt / Au ohmic electrode, and the surface adhesion of the two electrodes. Different n values ​​were used to test these properties. + The back-side etching depth parameter of the GaN bulk substrate was investigated to explore its impact on the overall process performance of electrode fabrication and annealing, and to verify the correlation between the back-side etching depth and electrode contact performance. The specific test procedures are as follows:

[0085] Schottky electrode contact characteristic test:

[0086] Keeping the deposition and annealing process parameters of the Pt / Au Schottky electrode unchanged, only adjusting the etching depth on the back side of the substrate during the fabrication of the Ti / Pt / Au ohmic electrode, three complete electrode samples with etching depths of 450 nm, 500 nm, and 550 nm were prepared. The Pt / Au Schottky electrodes of the three samples were tested using a semiconductor parameter analyzer. Multiple test points were selected in the Schottky contact area of ​​the samples, and the Schottky barrier height at each point was recorded. The barrier height deviation value was calculated to evaluate the contact characteristics and uniformity of the Schottky electrode.

[0087] Ohmic electrode contact characteristic test:

[0088] The contact resistivity of Ti / Pt / Au ohmic electrodes on three samples was tested using the four-probe method. Multiple test points were selected on the surface of the ohmic electrodes, and the ohmic contact resistivity at each point was obtained through precise measurement and calculation. The lower the resistivity value, the better the contact performance of the ohmic electrode, which can effectively reduce the contact resistance of the device.

[0089] Electrode surface adhesion test:

[0090] The adhesion of Schottky and Ohmic electrodes on three samples was tested using a scratch tester. During the test, the scratching force was increased uniformly, and the critical load at which the electrode detached or peeled was recorded. The higher the critical load value, the stronger the adhesion between the electrode and the substrate or dielectric layer, and the better the mechanical properties of the electrode. This can effectively prevent the electrode from detaching during subsequent use of the device.

[0091] Comparison of annealing process performance for electrodes with different back-side etching depths.

[0092] Substrate backside etching depth Schottky Barrier Height Schottky barrier height deviation Ohmic contact resistivity Schottky electrode adhesion Ohmic electrode adhesion 450nm 0.78eV 4.20% <![CDATA[7.8×10 -6 Ohm cm 2 ]]> 30N 28N 500nm 0.85eV 2.80% <![CDATA[5.0×10 -6 Ohm cm 2 ]]> 35N 33N 550nm 0.84eV 3.00% <![CDATA[6.5×10 -6 Ohm cm 2 ]]> 34N 32N

[0093] The test data clearly show that the etching depth on the back side of the substrate has a direct and significant impact on the performance of the electrode fabrication annealing process. The sample with an etching depth of 450 nm exhibits the lowest Schottky barrier height among the three groups, along with the largest barrier height deviation, and an ohmic contact resistivity reaching 7.8 × 10⁻⁶. -6 Ω·cm2 The electrode adhesion was also at a low level. This was due to insufficient etching depth, resulting in incomplete removal of the natural oxide layer on the back side of the substrate. This led to insufficient contact between the ohmic electrode and the substrate, thus affecting the overall contact and mechanical properties of the electrode. The sample with a 500 nm etching depth achieved a Schottky barrier height of 0.85 eV, the highest among the three groups, with a barrier height deviation of only 2.80%. This indicates that the Schottky electrode exhibited the best contact characteristics and uniformity, while the ohmic contact resistivity decreased to 5.0 × 10⁻⁶. -6 Ω·cm 2 The electrode adhesion was also the highest among the three groups. This is because this etching depth can completely remove the natural oxide layer on the back side of the substrate, and the substrate surface roughness is moderate, providing a good contact substrate for ohmic electrode deposition, thereby improving the overall contact performance and mechanical properties of the electrode. While the 550nm etching depth sample outperformed the 450nm etching depth sample in various aspects, compared to the 500nm etching depth, the Schottky barrier height was slightly lower, the ohmic contact resistivity was slightly higher, and the electrode adhesion was also slightly lower. This is because the excessive etching depth caused slight etching damage on the back side of the substrate, increasing lattice defects and affecting the contact effect between the electrode and the substrate. Considering all test indicators, a substrate backside etching depth of 500nm is the optimal parameter for the electrode fabrication annealing process.

[0094] Example 6:

[0095] Device electrical performance testing of GaN Schottky diodes.

[0096] This embodiment conducts comprehensive electrical performance tests on GaN Schottky diodes fabricated using a fluorine ion implantation process. Simultaneously, a GaN Schottky diode of the same specifications without fluorine ion implantation is prepared as a blank control. By setting different fluorine ion distribution depth parameters, the impact of fluorine ion implantation on the device's electrical performance is investigated. The reverse breakdown voltage, reverse leakage current, and forward conduction characteristics are tested in detail to verify the effectiveness of the fluorine ion implantation process in improving device performance. Specific test procedures are as follows:

[0097] Reverse withstand voltage characteristic test:

[0098] Three GaN Schottky diode samples with fluorine ion implantation depths of 300 nm, 325 nm, and 350 nm were selected. A blank control sample without fluorine ion implantation was also selected. The reverse withstand voltage of the four samples was tested at room temperature using a semiconductor parameter analyzer. The test voltage range was 0 to 1000 V, and the scan rate was controlled at 10 V / s. The reverse current change of the samples was recorded in real time. When the reverse current increased sharply, the corresponding voltage value was the reverse breakdown voltage of the sample. The reverse withstand voltage characteristics of the device were evaluated by this index.

[0099] Reverse leakage current characteristic test:

[0100] At room temperature, a reverse bias of 800V was applied to the four samples. After the bias was applied, the voltage was kept stable. Once the reverse leakage current of the samples tended to stabilize, the leakage current value was recorded. The reverse leakage current density was calculated in combination with the electrode area of ​​the device. The lower the leakage current density value, the better the reverse leakage current characteristics of the device, which can effectively reduce the energy loss of the device under reverse bias.

[0101] Forward conduction characteristic test:

[0102] Forward conduction characteristics were tested on four samples. A forward bias voltage of 0 to 5V was applied, and the corresponding forward current was recorded under each bias voltage. The forward current density was calculated based on the electrode area, and the forward current-voltage characteristic curve was plotted. At the same time, the forward conduction resistance of the sample was calculated based on the test data. The lower the forward conduction resistance, the better the forward conduction performance of the device, which can ensure the efficient conduction of the device under forward bias voltage.

[0103] Comparison table of electrical performance of devices with different fluoride ion distribution depths.

[0104] Sample type Fluoride ion distribution depth Reverse breakdown voltage Reverse leakage current density Forward conduction resistance Fluorine ion implantation treatment of samples 300nm 850V <![CDATA[9.2×10 -6 A / cm 2 ]]> <![CDATA[0.82Ω·cm 2 ]]> Fluorine ion implantation treatment of samples 325nm 900V <![CDATA[8.0×10 -6 A / cm 2 ]]> <![CDATA[0.80Ω·cm 2 ]]> Fluorine ion implantation treatment of samples 350nm 880V <![CDATA[8.5×10 -6 A / cm 2 ]]> <![CDATA[0.81Ω·cm 2 ]]> Blank control sample none 375V <![CDATA[5.2×10 -3 A / cm 2 ]]> <![CDATA[0.70Ω·cm 2 ]]>

[0105] The test data clearly show that the fluorine ion implantation process has a crucial positive impact on the electrical performance of GaN Schottky diodes, especially in terms of significantly improving reverse breakdown voltage and reverse leakage current characteristics. The blank control sample, which has not undergone fluorine ion implantation, has a reverse breakdown voltage of only 375V and a reverse leakage current density as high as 5.2 × 10⁻⁶. -3 A / cm 2 The three samples treated with fluorine ion implantation showed a significant increase in reverse breakdown voltage to over 850V, while the reverse leakage current density decreased to 1.0×10⁻⁶. -5 A / cm 2 The following demonstrates that the distribution region formed by fluoride ions in the GaN region at the Schottky contact edge effectively optimizes the electric field distribution of the device, alleviates the electric field concentration problem at the Schottky contact edge, and thus significantly improves the reverse breakdown voltage capability of the device while effectively suppressing the generation of reverse leakage current. Among the three samples treated with fluoride ion implantation, the sample with a fluoride ion distribution depth of 325 nm achieved the highest reverse breakdown voltage of 900 V, while the reverse leakage current density was as low as 8.0 × 10⁻⁶. -6 A / cm 2The forward conduction resistance of the samples was also at a low level, resulting in the best overall electrical performance. Although the performance of the samples with a distribution depth of 300nm and 350nm was slightly inferior to that of the 325nm sample, the performance improvement compared to the blank control sample was still very significant. Furthermore, the forward conduction resistance of all four samples was at a low level. The forward conduction resistance of the sample treated with fluorine ion implantation was slightly higher than that of the blank control sample, but the difference was minimal. This indicates that while the fluorine ion implantation process significantly improved the reverse breakdown voltage and reduced the reverse leakage current, it did not have a significant negative impact on the forward conduction performance of the device, thus ensuring the overall electrical performance of the device. Overall, the fluorine ion implantation process can effectively improve the electrical performance of GaN Schottky diodes, and a fluorine ion distribution depth of 325nm is the optimal process parameter.

[0106] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A fluorine ion implantation process for high-voltage, low-leakage-current GaN Schottky diodes, characterized in that, The specific steps of this process are as follows: Epitaxial layer fabrication: with Ge doping concentration of 10 18 cm -3 n + Using a GaN bulk substrate as the base, hydride vapor phase epitaxy was employed to grow Si doped to a concentration of 10 on the substrate surface. 17 cm -3 n with a thickness of 8.4μm - -GaN drift layer; Self-aligned injection: in n - - A Ni / SiO2 dual-layer hard mask is deposited on the GaN drift layer surface. A single photolithography process simultaneously defines the mesa isolation etching region and the fluorine ion implantation region. After completing the 1μm deep mesa isolation etching, the patterned dual-layer hard mask is used as the implantation mask. fluorine ion selective implantation is performed sequentially at energies of 40keV, 80keV, and 140keV, forming a 300-350nm deep GaN region with a concentration of 2×10⁻⁶ ions at the Schottky contact edge. 18 -10 19 cm -3 The fluoride ion distribution region is controlled such that the lateral distance between the fluoride ion implantation region and the Schottky contact edge is 0.1-0.3 μm. Polarization layer deposition: Remove the Ni / SiO2 double hard mask and deposit a polarization matching layer with a thickness of 50-100nm above the fluorine ion implantation region. The polarization matching layer is a gradient AlGaN layer with an Al composition that linearly changes from 0.1 to 0.3, or an AlGaN / GaN superlattice structure with a single-period thickness of 5-10nm and a period number of 10-20. Electrode fabrication annealing: A 100 nm thick SiO2 dielectric layer was deposited on the surface of the polarization matching layer. A circular Schottky contact window with a diameter of 100 μm was opened by photolithography and BOE wet etching. After immersion in HCl solution, the Pt / Au Schottky electrode and Ti / Pt / Au ohmic electrode were deposited and formed in sequence. The sample was placed in a N2 atmosphere for rapid thermal annealing at 400 °C for 10 minutes. Calibration of detection parameters: The forward IV, reverse IV and CV characteristics of the fabricated GaN-based Schottky barrier diodes were tested. The electric field distribution and peak value at the Schottky contact edge were detected. The composition parameters of the polarization matching layer and the process parameters of fluorine ion implantation were adjusted based on the test results.

2. The fluoride ion implantation process for the high-voltage, low-leakage-current GaN Schottky diode according to claim 1, characterized in that, In the epitaxial layer fabrication step, n is first prepared. + - The GaN bulk substrate is pretreated as follows: the substrate is ultrasonically cleaned in acetone solution for 10-15 min, then ultrasonically cleaned in isopropanol solution for 10-15 min, then immersed in a 1:3 mixture of hydrofluoric acid and deionized water for 30-60 s, and finally rinsed 3-5 times with ultrapure water with a resistivity ≥18.2 MΩ·cm and dried with high-purity nitrogen.

3. The fluoride ion implantation process for the high-voltage, low-leakage-current GaN Schottky diode according to claim 1, characterized in that, In the epitaxial layer preparation step, n is grown using a hydride vapor phase epitaxial process. - Before the GaN drift layer, a 200 nm thick GaN buffer layer is grown at 1080 °C and 100 Torr. Then, the reaction conditions are adjusted to 1050 °C and 50 Torr to grow a 200 nm thick GaN buffer layer. - - For the GaN drift layer, the flow rate of hydrogen chloride gas during growth is 50 sccm, the flow rate of ammonia gas is 3000 sccm, the flow rate of trimethylgallium gas is 20 sccm, and the fluctuation range of silane flow rate is controlled within ±2%.

4. The fluoride ion implantation process for the high-voltage, low-leakage-current GaN Schottky diode according to claim 1, characterized in that, In the self-aligned injection step, the deposition process of the Ni / SiO2 double-layer hard mask is as follows: a 50-100 nm thick SiO2 layer is deposited using plasma-enhanced chemical vapor deposition (PECVD), with silane and nitrous oxide as the reactant gases at a flow rate ratio of 1:10, a deposition temperature of 200 °C, a deposition pressure of 1 Torr, and a deposition rate of 10 nm / min; then, a 20-50 nm thick Ni layer is deposited using electron beam evaporation (EBBE), with a vacuum degree ≤2 × 10⁻⁶ during the deposition process. -4 Pa, deposition rate of 0.05 nm / s, and vacuum baking at 120℃ for 10 min after deposition.

5. The fluoride ion implantation process for the high-voltage, low-leakage-current GaN Schottky diode according to claim 1, characterized in that, In the self-aligned injection step, the single photolithography process is as follows: AZ5214 photoresist is spin-coated onto the surface of a double-layer hard mask at a spin speed of 3000 r / min for 30 s, with the photoresist thickness controlled at 1.4 μm; after spin-coating, it is pre-baked on a 110℃ hot plate for 90 s, followed by UV contact exposure at an exposure dose of 80-100 mJ / cm². 2 After exposure, develop in AZ300MIF developer for 45-60 seconds, rinse with deionized water, and then bake on a hot plate at 120°C for 120 seconds.

6. The fluoride ion implantation process for the high-voltage, low-leakage-current GaN Schottky diode according to claim 1, characterized in that, In the self-aligned injection step, the mesa isolation etching adopts inductively coupled plasma etching process. During the etching process, the ICP source power is 500W, the bias power is 100W, the etching gas Cl2 flow rate is 30sccm, the BCl3 flow rate is 10sccm, the cavity pressure is 5mTorr, the etching rate is controlled at 100nm / min, and a 30s pause is taken after every 100nm etching. The etching depth uniformity deviation is controlled within ±3%.

7. The fluoride ion implantation process for the high-voltage, low-leakage-current GaN Schottky diode according to claim 1, characterized in that, In the self-aligned implantation step, the cavity vacuum degree during the selective fluoride ion implantation process is ≤5×10⁻⁶. -6 Pa, with an injection angle of 7°, and single-stage injection doses corresponding to injection energies of 40keV, 80keV, and 140keV are respectively 4×10 Pa. 14 cm -2 5×10 14 cm -2 6×10 14 cm -2 The total injected dose was 1.5 × 10⁻⁶. 15 cm -2 .

8. The fluoride ion implantation process for the high-voltage, low-leakage-current GaN Schottky diode according to claim 1, characterized in that, In the polarization layer deposition step, the removal process of the Ni / SiO2 double-layer hard mask is as follows: First, the sample is placed in a nickel etching solution with a volume ratio of nitric acid to glacial acetic acid of 3:1 and immersed in a water bath at 40°C for 10-15 minutes, followed by rinsing with ultrapure water 3 times; then, the SiO2 layer is removed by inductively coupled plasma dry etching, with the etching gas being carbon tetrafluoride and oxygen at a flow ratio of 9:1, the ICP source power being 300W, the bias power being 50W, and the chamber pressure being 10mTorr. The etching endpoint is monitored in real time by an optical emission spectrometer.

9. The fluoride ion implantation process for the high-voltage, low-leakage-current GaN Schottky diode according to claim 1, characterized in that, In the polarization layer deposition step, the polarization matching layer is deposited using a metal-organic chemical vapor deposition process at a growth temperature of 900-1000℃ and a growth pressure of 100-200 Torr. N2 is used as the carrier gas, trimethylaluminum and trimethylgallium are used as metal sources, and ammonia is used as the nitrogen source. The deposition area of ​​the polarization matching layer completely covers the fluorine ion implantation area and extends outward by 0.5 μm along the lateral edge of the fluorine ion implantation area.

10. The fluorine ion implantation process for the high-voltage, low-leakage-current GaN Schottky diode according to claim 1, characterized in that, In the electrode fabrication annealing step, the deposition process of the Pt / Au Schottky electrode is as follows: under a vacuum degree ≤ 5 × 10⁻⁶. -5 Under a Pa environment, a 40 nm thick Pt layer and a 250 nm thick Au layer were sequentially deposited using electron beam evaporation. The Pt layer deposition rate was 0.05 nm / s, and the Au layer deposition rate was 0.1 nm / s. The sample stage temperature was maintained at 25 °C during the deposition process. The deposition process of the Ti / Pt / Au ohmic electrode was as follows: for n + - After performing inductively coupled plasma etching to a depth of 500 nm on the back side of the GaN bulk substrate, a 50 nm thick Ti layer, a 100 nm thick Pt layer, and a 50 nm thick Au layer were sequentially deposited using electron beam evaporation.

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