A method and apparatus for wafer dispatching

Abstract

The application provides a wafer dispatching method and device. A first model can arrange a production and processing sequence and time period of each wafer group on various devices, and a production technician can refer to an output of the first model and perform actual production scheduling, so that device production capacity can be reasonably allocated, and device utilization and production efficiency can be improved. In addition, it can be seen that the method provided by the application can automatically make decisions through the first model, and the analysis and decision efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit manufacturing, and more specifically, to a method and apparatus for wafer dispatching. Background Technology

[0002] As the integration density and complexity of devices in integrated circuits continue to increase, the control of the production process becomes particularly important. In the semiconductor manufacturing process, "wafer manufacturing" is the most crucial and complex part. Because different customers have different product types, process flows, and parameter requirements, the dispatching and management of wafer manufacturing is also quite difficult and complex.

[0003] Typically, wafer manufacturing production lines consist of multiple units, each containing multiple pieces of equipment, and each piece of equipment includes various types of processing resources. Furthermore, wafer manufacturing production lines may simultaneously process dozens of different batches and quantities of products. The dispatching of tasks for each product is affected by many factors. Key performance indicators of the production line, such as productivity and cycle time, are significantly impacted by dispatching management, directly affecting on-time delivery rates. Therefore, selecting appropriate dispatching methods for different products and batches of wafers is crucial for improving production capacity.

[0004] Therefore, a wafer dispatching method is needed to improve production efficiency. Summary of the Invention

[0005] This application provides a wafer dispatching method that can rationally allocate resources for processing wafer sets and improve production efficiency.

[0006] In a first aspect, a method for wafer dispatching is provided, which can be performed, for example, by a computing device, or by a component of the computing device (e.g., a chip or circuit). For example, the computing device can be a computer.

[0007] The method includes: acquiring first information, which includes information about multiple wafer groups, information about multiple target devices, information about the process corresponding to the wafer group, and information about the recipe corresponding to the wafer group; predicting the dispatching scheme for each of the multiple wafer groups based on the first information and a first model, wherein the first model includes a mixed integer programming model, the first information is the input of the first model, and the output of the first model is used to indicate the dispatching scheme for each of the multiple wafer groups, wherein the dispatching scheme includes information about the start processing time and the end processing time of the wafer group, and information about the target device corresponding to the wafer group during the processing time period.

[0008] In this embodiment of the application, the information of the wafer group includes at least one of the following: wafer group number, number of wafers in the wafer group, product type number of the wafer group, formulation of the wafer group, path width of the wafer group, arrival time of the wafer group, and processing steps of the wafer group.

[0009] In this embodiment of the application, the information of the target device includes at least one of the following: information of the loading port of the target device, information of the cavity of the target device, and information of the load of the cavity of the target device.

[0010] In this application embodiment, the process information includes one or more of the following: process number, periodic running time between processing steps of the target equipment, product type number corresponding to the wafer group, correspondence between wafer group and process number, and correspondence between process number and target equipment number.

[0011] In this embodiment of the application, the information of the formula includes at least one of the following: the formula number, the target equipment corresponding to the formula, and the processing time corresponding to the formula.

[0012] Based on the above technical solution, in this application, the first model can be used to schedule the production and processing sequence and time periods for each wafer group on various equipment. Production technicians can refer to the output of the first model and perform actual production scheduling, thereby rationally allocating equipment capacity and improving equipment utilization and production efficiency. Furthermore, it can be seen that the method provided in this application can automatically make decisions through the first model, improving analysis and decision-making efficiency.

[0013] In conjunction with the first aspect, in one possible implementation, the first model includes an objective function, multiple sets of variables, and constraints. The objective function is used to characterize the dispatching objectives of multiple wafer groups, the multiple sets of variables are determined based on the first information, and the constraints are used to constrain the values ​​of the variables in the sets of variables.

[0014] In conjunction with the first aspect, in one possible implementation, the objective function is the sum of two weighted functions, which include a function that minimizes the total completion time of the plurality of wafer sets and a function that minimizes the difference between the maximum and minimum loads of the cavity of the target device. The weight of the function that minimizes the total completion time of the plurality of wafer sets is w1, and the weight of the function that minimizes the difference between the maximum and minimum loads of the cavity of the target device is w2. Both w1 and w2 are real numbers greater than 0 and less than 1, and the sum of w1 and w2 is 1.

[0015] Based on the above technical solution, in this application, the "objective function" in the first model considers the maximum and minimum loads between different device cavities, ensuring load balance among the cavities.

[0016] In conjunction with the first aspect, in one possible implementation, multiple sets of variables correspond one-to-one with multiple wafer sets, and each set of variables includes at least one discrete variable and at least one continuous variable.

[0017] In conjunction with the first aspect, in one possible implementation, at least one discrete variable includes at least one of the following: whether the i-th wafer group in a plurality of wafer groups is assigned to the m-th target device in a plurality of target devices, whether the i-th wafer group in a plurality of wafer groups is assigned to the l-th loading port of the m-th device in a plurality of target devices, and whether the i-th wafer group in a plurality of wafer groups is assigned to the r-th path width of the m-th device in a plurality of target devices.

[0018] In conjunction with the first aspect, in one possible implementation, at least one continuous variable includes at least one of the following: the start processing time of the i-th wafer group in the plurality of wafer groups on the m-th device in the plurality of target devices; the start processing time of the i-th wafer group in the plurality of wafer groups on the l-th loading port of the m-th device in the plurality of target devices; the start processing time of the i-th wafer group in the plurality of wafer groups on the c-th cavity of the m-th device in the plurality of target devices; the end processing time of the i-th wafer group in the plurality of wafer groups on the m-th device in the plurality of target devices; the end processing time of the i-th wafer group in the plurality of wafer groups on the l-th loading port of the m-th device in the plurality of target devices; and the end processing time of the i-th wafer group in the plurality of wafer groups on the c-th cavity of the m-th device in the plurality of target devices; wherein i, m, l, r, and c are all positive integers greater than 0.

[0019] In conjunction with the first aspect, in one possible implementation, the constraints include at least one of the following: constraints on the allocation of the wafer set to the target device, constraints on the loading port of the wafer set to the target device, constraints on the path width of the wafer set to the target device, constraints on the start time of the wafer set on the target device, and constraints on the end time of the wafer set on the target device.

[0020] Among them, the constraints on the start time of the wafer set on the target equipment include at least one of the following: (1) the constraint on the start processing time of the wafer set at the loading port of the target equipment; (2) the constraint on the start processing time of the wafer set in the cavity of the target equipment; (3) the constraint on the earliest available time of the wafer set on the target equipment; and (4) the constraint on the transfer time of the wafer set between each processing step.

[0021] Among them, the constraints on the end time of the wafer set on the target device include at least one of the following: (1) the constraint on the end processing time of the wafer set at the loading port of the target device; (2) the constraint on the end processing time of the wafer set in the cavity of the target device.

[0022] Based on the above technical solution, this application considers the processing start time and processing end time of each wafer group on the target equipment through the "constraint of the start time of the wafer group on the target equipment" and "constraint of the end time of the wafer group on the target equipment" in the first model. This can reasonably allocate the loading port and cavity of the equipment for processing wafer groups, reduce the waste of production capacity caused by cavity idleness due to loading port bottleneck, improve the problem of unbalanced load of wafer group production line, and improve the utilization rate of equipment.

[0023] In conjunction with the first aspect, in one possible implementation, the target equipment includes both idle equipment and equipment that is currently processing.

[0024] Based on the above technical solution, this application considers multiple wafer sets and multiple target devices at the same time, that is, it models and solves multiple wafer sets to be scheduled at the same time to obtain global solution results, thus avoiding the local optimum problem caused by the current rule-based dispatching.

[0025] Secondly, this application proposes a wafer dispatching apparatus for performing the method described in the first aspect. Specifically, the apparatus may include units and / or modules for performing the method proposed in this application, such as an acquisition module and / or a calculation module. Exemplarily, the apparatus may be applied to a computing device, such as a computer.

[0026] Thirdly, this application provides a wafer dispatching apparatus, comprising: at least one processor for executing a computer program or instructions stored in a memory to perform the method described in the first aspect. Optionally, the apparatus further comprises a memory for storing the computer program or instructions. Optionally, the apparatus further comprises a communication interface through which the processor reads the computer program or instructions stored in the memory.

[0027] In one implementation, the device is a means for implementing the functions of the above-described method in a chip.

[0028] In another implementation, the device is a chip, chip system, or circuit used to implement the functions of the above methods in a chip.

[0029] Fourthly, this application provides a processor, including: an input circuit, an output circuit, and a processing circuit. The processing circuit is used to receive signals through the input circuit and to transmit signals through the output circuit, causing the processor to execute the method described in the first aspect.

[0030] In specific implementation, the processor can be one or more chips, the input circuit can be input pins, the output circuit can be output pins, and the processing circuit can be transistors, gate circuits, flip-flops, and various logic circuits. The input signal received by the input circuit can be received and input by, for example, but not limited to, a transceiver, and the signal output by the output circuit can be, for example, but not limited to, output to and transmitted by a transmitter. Furthermore, the input circuit and the output circuit can be the same circuit, which is used as both the input circuit and the output circuit at different times. This application does not limit the specific implementation of the processor and various circuits.

[0031] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0032] Fifthly, a processing apparatus is provided, including a processor and a memory. The processor is used to read instructions stored in the memory and to receive signals via a transceiver and transmit signals via a transmitter to execute the method described in the first aspect.

[0033] Optionally, the processor may be one or more, and the memory may be one or more.

[0034] Optionally, the memory may be integrated with the processor, or the memory may be separated from the processor.

[0035] In specific implementation, the memory can be a non-transitory memory, such as read-only memory (ROM), which can be integrated with the processor on the same chip or set on different chips. The embodiments of this application do not limit the type of memory or the way the memory and processor are set.

[0036] It should be understood that the relevant data interaction process, such as sending the first information, can be the process of the processor outputting the first information, and the receiving capability information can be the process of the processor receiving input capability information. Specifically, the data output by the processor can be sent to the transmitter, and the input data received by the processor can come from the transceiver. Here, the transmitter and the transceiver can be collectively referred to as the transceiver.

[0037] The processing device mentioned in the fifth aspect above can be one or more chips. The processor in the processing device can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. This memory can be integrated into the processor or located outside the processor and exist independently.

[0038] In a sixth aspect, a computing cluster is provided, including at least one computing device, each computing device including a processor and a memory; the processor of the at least one computing device is configured to execute instructions stored in the memory of the at least one computing device, such that the computing device cluster performs the method described in any possible implementation of the first aspect.

[0039] Optionally, the processor can be a general-purpose processor, which can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. This memory can be integrated into the processor or located outside the processor and exist independently.

[0040] In a seventh aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including the method described in the first aspect.

[0041] Eighthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method described in the first aspect.

[0042] A ninth aspect provides a chip system including a processor for calling and running a computer program from a memory, causing a device equipped with the chip system to perform the method of the first aspect described above. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of a system architecture to which this application applies.

[0044] Figure 2 This is a schematic flowchart of a wafer dispatching method 200 provided in this application.

[0045] Figure 3 This is a schematic block diagram of a wafer dispatching method provided in this application.

[0046] Figure 4 This is a schematic block diagram of the device 400 provided in this application.

[0047] Figure 5 This is a schematic block diagram of the device 500 provided in this application. Detailed Implementation

[0048] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0049] To facilitate understanding of the technical solutions provided in the embodiments of this application, the technical terms involved in this application are briefly introduced below. It should be noted that the introduction of technical terms in this application is only for the purpose of helping to understand the technical solutions and should not be construed as limiting the application.

[0050] 1. Wafer

[0051] It can be understood as an abbreviation for "semiconductor crystal wafer". Typically, it is a thin slice of cylindrical semiconductor crystal, used as a substrate in integrated circuit manufacturing processes. Because of its circular shape, it is called a wafer. The most common type is silicon wafer, but there are also gallium nitride wafers, silicon carbide wafers, etc. Generally, wafer production is mostly in the form of single-crystal silicon wafers.

[0052] 2. Waferlot

[0053] It can be understood as a combination of a batch of wafers, and in the manufacturing process, it is usually referred to as a "wafer group" as the processing unit.

[0054] 3. Wafer dispatch

[0055] "Wafer dispatching" can be understood as assigning wafer sets to designated equipment for production. In semiconductor manufacturing, it refers to the process of transferring processed wafers from one process step to the next. Specifically, it involves sending wafers that have completed a certain process in batches or individually to the next process step for further processing. For example, after the photolithography process, wafers need to be dispatched to the deposition process for film coating. The purpose of wafer dispatching is to ensure that wafers are processed sequentially and according to plan, and to avoid reduced production efficiency or wafer damage due to confusion or delays.

[0056] 4. Run path width

[0057] In wafer fabrication, "path width" can be understood as the combination of equipment and / or cavities that a wafer fab can use during the manufacturing process. In wafer fabrication, wafers undergo multiple process steps, such as photolithography, etching, and deposition. Each process step requires specific equipment and / or cavities to complete. During manufacturing, the availability and combination of equipment and / or cavities affect wafer quality and yield. A wider path width means more equipment and / or cavities can be used simultaneously, increasing production efficiency and yield.

[0058] For example, suppose a wafer set has four available etching devices (e.g., plasma etching devices) named device #A, device #B, device #C, and device #D. Each etching device has four cavities: cavity #1, cavity #2, cavity #3, and cavity #4. In this case, for any given device, a single cavity or a combination of multiple cavities can be used. For example, for device #A, each single cavity can be used (i.e., there are four possibilities); combinations of any two cavities can be used, such as cavity #1 and cavity #2, cavity #1 and cavity #3, cavity #1 and cavity #4, cavity #2 and cavity #3, cavity #3 and cavity #4; combinations of any three cavities can be used, such as cavity #1, cavity #2, cavity #3, etc.; or combinations of all four cavities can be used. Any of these implementations can be understood as a path width. Therefore, in this example, the path width of the wafer set can include: the combination of each cavity in device #A, the combination of each cavity in device #B, the combination of each cavity in device #C, and the combination of each cavity in device #D. It can also be understood that there are multiple dispatching methods for this wafer set.

[0059] 5. Manufacturing process

[0060] In the semiconductor manufacturing field, "process" can be understood as the various technological steps and procedures for producing semiconductor devices, or it can refer to information such as the equipment, processing technology, and processing time of the wafer assembly in each process step.

[0061] 6. Combinatorial optimization problem

[0062] Combinatorial optimization problems are an important class of problems in the field of mathematical optimization. They involve finding the optimal solution within a finite discrete set; in other words, choosing the optimal combination from a series of possible combinations. The mathematical model established to solve combinatorial optimization problems can be called a "model for solving combinatorial optimization problems." These models typically include variables, constraints, and an objective function. For example, variables can include "discrete variables" and "continuous variables." "Discrete variables" can be understood as variables in the model that are restricted to taking integer values, such as only 0 or 1, or positive integers; "continuous variables" can be understood as variables that can take continuous values ​​within a certain range. Constraints typically limit the range of values ​​for variables and ensure the feasibility of the solution. These constraints can be linear or nonlinear. The objective function represents the goal to be optimized, such as minimizing cost, maximizing profit, minimizing time, etc. Exemplary models for solving combinatorial optimization problems can include integer programming models, mixed integer programming models, mixed integer linear programming models, nonlinear integer programming models, combinatorial optimization models, dynamic programming models, constraint programming models, evolutionary algorithm models, and so on.

[0063] Semiconductor wafer fabrication (Fab) plants are highly complex, precise, and dynamic production environments. These plants need to process multiple types of wafer products simultaneously, each with varying batch sizes, delivery deadlines, and process flows. This presents significant challenges to production planning, scheduling, and execution. Maximizing equipment utilization and meeting the diverse time and process requirements of different products makes wafer fabrication dispatch management extremely difficult and complex. Typically, wafer fabrication production lines consist of multiple units, each containing multiple pieces of equipment, and each piece of equipment includes various processing resources. Furthermore, a wafer fabrication production line may need to process dozens of different batches and quantities of products simultaneously. Dispatching for each product is affected by numerous factors, significantly impacting key production line performance indicators such as productivity and cycle time, and directly affecting on-time delivery rates. Therefore, selecting appropriate dispatching methods for different products and batches of wafers is crucial for improving capacity. Thus, a wafer dispatching method is needed to improve production efficiency.

[0064] In view of this, this application proposes a wafer dispatching method. Through first information and a first model, the dispatching scheme for each wafer group in multiple wafer groups can be predicted. The output information of the first model can indicate the processing time period for that wafer group and the corresponding target equipment within that processing time period. This application achieves overall planning in wafer group dispatching and provides more comprehensive information to guide actual production, thereby improving wafer dispatching efficiency and capacity.

[0065] For example, the method provided in this application can be applied to the control process of wafer dispatch in the computer integrated manufacturing (CIM) system of a fab plant to optimize the problems of uneven load and low equipment utilization among equipment during the wafer dispatch process.

[0066] Figure 1 This is a schematic diagram of a system architecture to which this application applies, such as Figure 1 As shown, the system architecture includes an upstream system 110, a wafer dispatching device 120, and a downstream system 130.

[0067] The upstream system 110 may include, for example, a manufacturing execution system 111, an equipment automation program module 112, a user configuration module 113, and a reporting system 114. The manufacturing execution system 111 is typically responsible for collecting, monitoring, and optimizing the entire semiconductor manufacturing process; the equipment automation program module 112 is typically responsible for collecting, analyzing, and monitoring equipment status; the user configuration module 113 is typically used for users to manually configure customized business rules; and the reporting system 114 is typically used to provide and integrate user-generated data from various systems.

[0068] The wafer dispatching device 120 provided in this application can, for example, obtain first information from the upstream system 110. The first information includes information about wafer groups, information about multiple target devices, information about the process corresponding to each wafer group, and information about the recipe corresponding to each wafer group. The first information is processed by a first model to obtain the dispatching scheme corresponding to each wafer group. Then, the dispatching scheme of the wafer group is sent to the downstream system 130 for users to refer to when dispatching wafers.

[0069] Downstream system 130 may include, for example, a real-time dispatch system 131, a manufacturing execution system 132, and a reporting system 133. The real-time dispatch system 131 can trigger dispatch when the equipment is idle; for example, in existing solutions, dispatch is typically based on expert experience and business rules. In the downstream system, the manufacturing execution system 132 and the reporting system 133 can be used by the wafer dispatching device 120 to send the determined dispatching plans for each wafer group to the manufacturing execution system 132 and the reporting system 133 for user review.

[0070] Figure 2 This is a schematic block diagram of a wafer dispatching method 200 provided in this application, such as... Figure 2 As shown, the method includes:

[0071] 210. Obtain first information, which includes information on multiple wafer sets, information on multiple target devices, information on the process corresponding to the wafer set, and information on the formula corresponding to the wafer set.

[0072] In this embodiment of the application, "information on multiple wafer groups" can be understood as the information of each individual wafer group, that is, the information of each wafer group. The information of each wafer group includes at least one of the following: wafer group number, number of wafers in the wafer group, type of wafer group, formulation of wafer group, path width of wafer group, arrival time of wafer group, processing steps of wafer group, product type number of wafer group, etc.

[0073] As mentioned earlier, the "wafer set path width" can indicate, for example, which cavity of which target device the wafer set should be assigned to. For example, path width #A1 can indicate cavities #1 and #2 in target device #A; for example, path width #A2 can indicate cavities #1, #2, and #3 in target device #A; path width #B1 can indicate cavity #1 in target device #B; for example, path width #B2 can indicate cavities #1 and #3 in target device #B, and so on.

[0074] The "wafer set arrival time" can be understood as the time it takes for the wafer set to arrive at a specific production equipment or workstation. Typically, wafer sets move between different production equipment or workstations, such as from a wafer cleaner to an etching machine to a deposition machine. In this case, the "wafer set arrival time" can be understood as the time it takes for the wafer set to arrive at each production equipment or workstation. For example, if the wafer set arrival time is 09:00, it means that the wafer set will arrive at a specific production equipment or workstation at 09:00. The "wafer set product type number" can be understood as follows: because the process parameters during wafer set fabrication differ, the parameters for different products or batches of wafer sets will be different. Therefore, it is necessary to know the product type number corresponding to each wafer set in order to better design subsequent process steps for that wafer set.

[0075] In this embodiment of the application, the information of the target device includes at least one of the following: information about the loading port of the target device, information about the cavity of the target device, information about the load of the cavity of the target device, etc. For example, the information of the target device may also include the number of the target device.

[0076] For example, the "target device" in this application embodiment may include "idle device" and "device in processing". It can also be understood that any device specified by the user that can work normally (or device specified by the user that needs to be produced) can become the target device to be dispatched, regardless of whether it is currently idle or in processing.

[0077] In this embodiment of the application, "process information corresponding to a wafer group" can be understood as the process information corresponding to each of multiple wafer groups, that is, the process information corresponding to each wafer group. For example, "process information" includes at least one of the following: the periodic running time between processing steps of the target equipment, the product type number of the wafer group, the correspondence between wafer groups and process numbers, and the correspondence between process numbers and target equipment numbers. For example, it may also include the process number, which can indicate the process information.

[0078] The periodic runtime between processing steps of the target equipment can be understood as the time interval between two consecutive processing steps of the target equipment. For example, a wafer set requires multiple processes during processing. The periodic runtime can be understood as the time required between when equipment #1 completes one processing step of wafer set #1 and begins the same processing step for another wafer set #2. This time interval includes equipment preparation time, cleaning time, and wafer set handling time. For instance, if wafer set #2 is delayed by half an hour in the previous processing step due to a malfunction of equipment #2, equipment #1 will also need to wait an additional half hour after completing wafer set #1 before it can begin processing wafer set #2.

[0079] In this embodiment of the application, "the information of the recipe corresponding to the wafer group" can be understood as the information of the recipe corresponding to each of the multiple wafer groups, that is, the information of the recipe corresponding to each wafer group. For example, the recipe information includes at least one of the following: the recipe number, the target equipment corresponding to the recipe, and the processing time corresponding to the recipe.

[0080] In this embodiment of the application, the first information can be configured by the user, for example, it can be stored in a table or database, and loaded directly from the database when needed.

[0081] 220. Based on the first information and the first model, predict the dispatching scheme for each of the multiple wafer groups.

[0082] In this embodiment, the first model can be understood as a model used to solve combinatorial optimization problems. For example, the first model may include a mixed integer programming model. It should be noted that this embodiment does not limit the "first model" to a mixed integer programming model; any model that can solve combinatorial optimization problems similar to those proposed in this application's wafer dispatching process can be the first model in this embodiment.

[0083] In this embodiment, the input to the first model is first information, and the output of the first model is used to indicate the dispatching scheme for each of the multiple wafer groups. In this embodiment, the "dispatching scheme" includes information on the start and end times of the wafer group's processing, as well as information on the target equipment corresponding to the wafer group within the processing time period.

[0084] The "target equipment information" in the "dispatch scheme" of "the target equipment information corresponding to the wafer group within the processing time period" may include, for example, at least one of the following: the loading port of the target equipment, the cavity (or path width) of the target equipment. It can also be understood that, in the embodiments of this application, the output information of the first model can indicate the start and end processing times of each wafer group in multiple wafer groups on which loading ports and cavities of which equipment.

[0085] In this embodiment of the application, the first model includes an objective function, multiple sets of variables, and constraints. The objective function is used to characterize the dispatching target of multiple wafer groups, the multiple sets of variables are determined based on the first information, and the constraints are used to constrain the values ​​of the variables in the sets of variables.

[0086] In one possible implementation, the objective function is the sum of two weighted functions: one minimizing the total completion time of multiple wafer sets, and the other minimizing the difference between the maximum and minimum loads of the target device's cavity. The weight of the function minimizing the total completion time of the multiple wafer sets is w1, and the weight of the function minimizing the difference between the maximum and minimum loads of the target device's cavity is w2. Both w1 and w2 are real numbers greater than 0 and less than 1. For example, the objective function could be the following formula:

[0087]

[0088] Where w1 is the weight of the total completion time, w2 is the weight of the load balancing, and c is the cavity number of the device. make_span can be understood as the total completion time, and max_load... c min_load is the maximum load on cavity c. c Let w1 be the minimum load capacity of cavity c, where c is an integer greater than or equal to 1. w1 and w2 are both real numbers greater than 0 and less than 1, and the sum of w1 and w2 is 1.

[0089] In one possible implementation, multiple sets of variables correspond one-to-one with multiple wafer sets, and each set of variables includes at least one discrete variable and at least one continuous variable. The one-to-one correspondence between "multiple sets of variables and multiple wafer sets" can be understood as each wafer set corresponding to a separate set of variables.

[0090] In one possible implementation, at least one discrete variable includes at least one of the following: whether the i-th wafer group in a plurality of wafer groups is assigned to the m-th target device in a plurality of target devices, whether the i-th wafer group in a plurality of wafer groups is assigned to the l-th loading port of the m-th device in a plurality of target devices, and whether the i-th wafer group in a plurality of wafer groups is assigned to the r-th path width of the m-th device in a plurality of target devices.

[0091] As an example, "discrete variables include" at least one of the following: x i,m x i,m,l x i,m,r For example, x i,m x represents whether the i-th wafer group is assigned to the m-th device. i,m =0 indicates that the i-th wafer group has not been assigned to the m-th device; x i,m =1 indicates that the i-th wafer group is assigned to the m-th device. For example, x i,m,l Indicates whether the i-th wafer group is assigned to the l-th loading port of the m-th device, x i,m,l =0 indicates that the l-th loading port of the i-th wafer group has not been assigned to the m-th device, x i,m,l =1 indicates that the l-th loading port of the i-th wafer group is not assigned to the m-th device. For example, x i,m,r x represents whether the i-th wafer group is assigned to the r-th path width of the m-th device. i,m,r =0 represents the r-th path width of the i-th wafer group that is not assigned to the m-th device, x i,m,r =1 represents the r-th path width of the i-th wafer group that is not assigned to the m-th device.

[0092] In one possible implementation, at least one continuous variable includes at least one of the following: the start processing time of the i-th wafer group in the plurality of wafer groups on the m-th device in the plurality of target devices, the start processing time of the i-th wafer group in the plurality of wafer groups on the l-th loading port of the m-th device in the plurality of target devices, the start processing time of the i-th wafer group in the plurality of wafer groups on the c-th cavity of the m-th device in the plurality of target devices, the end processing time of the i-th wafer group in the plurality of wafer groups on the m-th device in the plurality of target devices, the end processing time of the i-th wafer group in the plurality of wafer groups on the l-th loading port of the m-th device in the plurality of target devices, and the end processing time of the i-th wafer group in the plurality of wafer groups on the c-th cavity of the m-th device in the plurality of target devices.

[0093] As an example, at least one "continuous variable" includes at least one of the following: start i,m , start i,m,l, start i,m,c end i,m end i,m,l end i,m,c For example, start i,m This variable represents the start processing time of the i-th wafer group on the m-th device; it is greater than or equal to 0. For example, start... i,m,l Characterizes the start processing time of the i-th wafer group at the l-th loading port of the m-th device; this variable is greater than or equal to 0. For example, start... i,m,c Characterizes the start time of processing of the i-th wafer group on the c-th cavity of the m-th device; this variable is greater than or equal to 0. For example, end i,m Characterizing the end processing time of the i-th wafer group on the m-th device, this variable is greater than 0; for example, end i,m,l Characterizing the end processing time of the i-th wafer group at the l-th loading port of the m-th device, this variable is greater than 0; for example, end i,m,c The variable represents the start time of processing of the i-th wafer group in the c-th cavity of the m-th device, and this variable is greater than 0.

[0094] In this embodiment of the application, r is a positive integer greater than 0.

[0095] In one possible implementation, the constraints include at least one of the following: constraints on the allocation of the wafer set to the target device, constraints on the loading port of the wafer set to the target device, constraints on the path width of the wafer set to the target device, constraints on the start time of the wafer set on the target device, and constraints on the end time of the wafer set on the target device.

[0096] Among them, "constraints on the start time of the wafer set on the target device" include at least one of the following: (1) constraints on the start processing time of the wafer set at the loading port of the target device; (2) constraints on the start processing time of the wafer set in the cavity of the target device; (3) constraints on the earliest available time of the wafer set on the target device; and (4) constraints on the transfer time of the wafer set between each processing step.

[0097] Wherein, “the constraint on the end time of the wafer assembly on the target device” includes at least one of the following: (1) the constraint on the end processing time of the wafer assembly at the loading port of the target device; (2) the constraint on the end processing time of the wafer assembly in the cavity of the target device.

[0098] For example, "constraints on wafer set allocation to target device" include:

[0099]

[0100] x i,m=0 indicates that the i-th wafer group has not been assigned to the m-th device; x i,m =1 indicates that the i-th wafer group is assigned to the m-th device.

[0101] For example, "constraints on wafer set allocation to loading port of target device" include:

[0102]

[0103] x i,m,l =0 indicates that the l-th loading port of the i-th wafer group has not been assigned to the m-th device; x i,m,l =1 indicates that the l-th loading port of the i-th wafer group has not been assigned to the m-th device.

[0104] For example, the "constraint on the path width assigned from the wafer set to the target device" includes:

[0105]

[0106] x i,m,r =0 indicates the r-th path width of the i-th wafer group that is not assigned to the m-th device; x i,m,r =1 represents the l-th path width of the i-th wafer group that is not assigned to the m-th device.

[0107] For example, the "constraint on the start time of the wafer set on the target device" includes:

[0108]

[0109] That is, the start time of the i-th wafer group is the same on the device m and the loading port l.

[0110]

[0111] That is, the start time of the i-th wafer group on the device m is equal to the earliest start time on the cavity.

[0112]

[0113] That is, the start time of the i-th wafer group on device m must meet the given time constraint.

[0114]

[0115] That is, after the wafer assembly is completed in the previous process, it needs to spend time transporting it to the next processing step. Among them, LOT_TRANSFER_TIME can be a constant (i.e., assuming the "transport time" is the same) or a variable, which is not limited.

[0116] For example, the "constraint on the end time of the wafer set on the target device" includes:

[0117]

[0118] That is, the end processing time of the i-th wafer group on device m and loading port l is equal to the latest end time on loading port l.

[0119]

[0120] That is, the end processing time of the i-th wafer group on device m is equal to the latest end time on the cavity.

[0121] In this embodiment of the application, the total completion time (make_span) and the maximum load of cavity c (max_load) are... c The minimum load of cavity c, min_load c The following formulas can be used to understand each:

[0122]

[0123]

[0124]

[0125] In this embodiment, I can be understood as the set of the total number of wafer groups, and i can be understood as any one of the total wafer groups; M can be understood as the set of the total number of target devices, and m can be understood as any one of the total target devices; C can be understood as the set of the total number of cavities in a target device, and c can be understood as any one of the total cavities in a target device; L is the set of all loading ports, and l can be understood as any one of the loading ports in this set; R is the set of all path widths, and r can be understood as any one of the path widths in the path width set. In this embodiment, i, m, l, r, and c can also be understood as positive integers greater than 0.

[0126] As can be seen, this application considers the start and end times of processing for each wafer group on the target equipment through the constraints of "start time constraint of wafer group on target equipment" and "end time constraint of wafer group on target equipment" in the first model. This allows for the reasonable allocation of loading ports and cavities of the equipment processing wafer groups, reducing wasted capacity due to cavity idleness caused by loading port bottlenecks, improving the load imbalance problem of wafer group production lines, and increasing equipment utilization. Furthermore, the "objective function" in the first model considers the maximum and minimum loads between different equipment cavities, ensuring load balance in the cavities. In addition, this application considers multiple wafer groups and multiple target equipment simultaneously, that is, it models and solves multiple wafer groups to be scheduled simultaneously, obtaining global solution results and avoiding the local optimum problem caused by the current rule-based dispatching.

[0127] Figure 3 This is another schematic block diagram of a wafer dispatching method provided in this application, such as... Figure 3 As shown, the acquired first information can be preprocessed. Then, based on the first model and the preprocessed first information, combined with the objective function, multiple variable groups, and multiple constraints, the values ​​of each variable in the variable groups are solved. The solved values ​​of each variable can indicate the start and end times of the wafer assembly, as well as the target equipment information corresponding to the wafer assembly within the processing time period. Alternatively, the output information of the first model can be understood as indicating the start and end times of the wafer assembly, as well as the target equipment information corresponding to the wafer assembly within the processing time period.

[0128] The method provided in this application embodiment comprehensively considers discrete variables, continuous variables, and various constraints through a first model, and can formulate a better target dispatching decision. The dispatching scheme obtained based on the output information of the first model can reasonably allocate the resources of the wafer processing group and improve production efficiency.

[0129] In one possible implementation, the output of the first model includes the value of each variable, which indicates the dispatching scheme. For example, the output of the first model can be converted into a table to present the dispatching scheme more clearly and conveniently. As shown in Table 1 below, for example, the dispatching scheme may include the wafer group number, the product type number of the wafer group, the process number of the wafer group, the equipment number, the loading port number of the equipment, the path width number, the cavity number, the number of wafers in each wafer group, the start time (start_time) of each wafer group, and the end time (end_time) of each wafer group.

[0130] Table 1

[0131]

[0132] It should be noted that Table 1 is only an example. For example, Table 1 may also include other data, and this application embodiment does not limit this.

[0133] As mentioned earlier, in semiconductor manufacturing, wafer assemblies require multiple processes, each requiring different equipment. Therefore, it can be seen that the method provided in this application can schedule the production process sequence and time periods for each wafer assembly on various devices. Production technicians can refer to the output of the first model and perform actual production scheduling, thereby rationally allocating equipment capacity and improving equipment utilization and production efficiency. Furthermore, it can be seen that the method provided in this application can automatically make decisions through the first model, improving analysis and decision-making efficiency.

[0134] It is understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0135] It should also be understood that the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects, and are not used to limit the size, content, order, timing, priority or importance of multiple objects.

[0136] It should also be understood that, in this application, "at least one" means one or more, and "more than one" means two or more. "At least one item" or similar expressions mean one or more items, that is, any combination of these items, including any combination of single items or multiple items. For example, at least one of a, b, or c means: a, b, c, a and b, a and c, b and c, or a and b and c.

[0137] It should also be understood that, in the various embodiments of this application, determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0138] Those skilled in the art will recognize that, based on the units and algorithm steps described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0139] This application embodiment can divide the computing device into functional modules according to the above method example. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware or as software functional modules. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The following description uses the division of functional modules according to each function as an example.

[0140] Figure 4 This is a schematic block diagram of a wafer dispatching apparatus 400 provided in an embodiment of this application. As shown in the figure, the apparatus 400 may include: an acquisition module 410 and a calculation module 420.

[0141] The modules described above are used to execute the respective steps of the methods mentioned above, which will not be elaborated here.

[0142] It should also be understood that the device 400 here is embodied in the form of a functional unit. The term "unit" here may refer to application-specific integrated circuits (ASICs), electronic circuits, processors (e.g., shared processors, proprietary processors, or group processors) and memories for executing one or more software or firmware programs, combined logic circuits, and / or other suitable components that support the described functions.

[0143] The apparatus 400 of each of the above-described schemes has the function of implementing the corresponding steps of the method 200 described above. The function can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the determining unit can be replaced by a processor to execute the transmit / receive operations and related processing operations in each method embodiment. Furthermore, the acquisition module and the calculation module can be processing circuits.

[0144] It should be pointed out that, Figure 4 The device mentioned can be the computing device in the foregoing method embodiments, or it can be a chip or chip system corresponding to the computing device, such as a system on a chip (SoC). The acquisition module and the computing module can be a processor, microprocessor, or integrated circuit integrated on the chip. No limitation is made here.

[0145] Figure 5This is a schematic block diagram of another wafer dispatching apparatus 500 provided in this application embodiment. As shown, the apparatus 500 includes at least one processor 520. The processor 520 is coupled to a memory for executing instructions stored in the memory to transmit and / or receive signals. Optionally, the apparatus 500 also includes a memory 530 for storing instructions. Optionally, the apparatus 500 also includes a transceiver 510, which the processor 520 controls to transmit and / or receive signals.

[0146] It should be understood that the processor 520 and memory 530 described above can be combined into a single processing device, with the processor 520 executing the program code stored in the memory 530 to achieve the aforementioned functions. In specific implementations, the memory 530 can be integrated into the processor 520 or independent of the processor 520.

[0147] It should also be understood that transceiver 510 may include a transceiver (or receiver) and a transmitter (or transmitter). The transceiver may further include an antenna, and the number of antennas may be one or more. Transceiver 510 may have a communication interface or interface circuitry.

[0148] Specifically, the processor 520 in the device 500 may correspond to the acquisition module 410 and the calculation module 420 in the device 400.

[0149] As one option, the device 500 is used to implement the various steps in the embodiments of method 200 above.

[0150] For example, processor 520 is used to execute computer programs or instructions stored in memory 530 to implement the various steps in method 200 above.

[0151] In this embodiment, a computer program product containing instructions is also provided. The computer program product may be a software or program product containing instructions capable of running on a computing device cluster or stored on any available medium. When run by the computing device cluster, it causes the computing device cluster to perform the methods provided above, or causes the computing device cluster to implement the functions of the apparatus provided above.

[0152] In this embodiment, a computer-readable storage medium is also provided. This computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., digital video disc (DVD)), or a semiconductor medium (e.g., a solid-state drive). The computer-readable storage medium includes instructions that, when executed on a computing device, cause the computing device to perform the method described above.

[0153] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0154] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0155] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0156] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0157] In addition, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0158] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0159] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for wafer dispatching, characterized in that, include: Obtain first information, which includes information on multiple wafer sets, information on multiple target devices, information on the process corresponding to the wafer set, and information on the formula corresponding to the wafer set; Based on the first information and the first model, the dispatching scheme for each of the multiple wafer groups is predicted. The first model includes a mixed integer programming model. The input of the first model is the first information. The output of the first model is used to indicate the dispatching scheme for each of the multiple wafer groups. The dispatching scheme includes information on the start processing time and end processing time of the wafer group, as well as information on the target equipment corresponding to the wafer group during the processing time period.

2. The method according to claim 1, characterized in that, The first model includes an objective function, multiple sets of variables, and constraints. The objective function is used to characterize the dispatching target of the multiple wafer sets. The multiple sets of variables are determined based on the first information. The constraints are used to constrain the values ​​of the variables in the sets of variables.

3. The method according to claim 2, characterized in that, The objective function is the sum of two weighted functions, which include a function that minimizes the total completion time of the plurality of wafer sets and a function that minimizes the difference between the maximum and minimum loads of the cavity of the target device. The weight of the function that minimizes the total completion time of the plurality of wafer sets is w1, and the weight of the function that minimizes the difference between the maximum and minimum loads of the cavity of the target device is w2. Both w1 and w2 are real numbers greater than 0 and less than 1, and the sum of w1 and w2 is 1.

4. The method according to claim 2 or 3, characterized in that, The multiple variable groups correspond one-to-one with the multiple wafer groups, and each variable group includes at least one discrete variable and at least one continuous variable.

5. The method according to claim 4, characterized in that, The at least one discrete variable includes at least one of the following: whether the i-th wafer group in the plurality of wafer groups is assigned to the m-th target device in the plurality of target devices; whether the i-th wafer group in the plurality of wafer groups is assigned to the l-th loading port of the m-th device in the plurality of target devices; and whether the i-th wafer group in the plurality of wafer groups is assigned to the r-th path width of the m-th device in the plurality of target devices. The at least one continuous variable includes at least one of the following: the start processing time of the i-th wafer group in the plurality of wafer groups on the m-th device in the plurality of target devices, the start processing time of the i-th wafer group in the plurality of wafer groups on the l-th loading port of the m-th device in the plurality of target devices, the start processing time of the i-th wafer group in the plurality of wafer groups on the c-th cavity of the m-th device in the plurality of target devices, the end processing time of the i-th wafer group in the plurality of wafer groups on the m-th device in the plurality of target devices, the end processing time of the i-th wafer group in the plurality of wafer groups on the l-th loading port of the m-th device in the plurality of target devices, and the end processing time of the i-th wafer group in the plurality of wafer groups on the c-th cavity of the m-th device in the plurality of target devices; Where i, m, l, r, and c are all positive integers greater than 0.

6. The method according to any one of claims 2 to 5, characterized in that, The constraints include at least one of the following: the constraint of the wafer set being assigned to the target device, the constraint of the wafer set being assigned to the loading port of the target device, the constraint of the path width of the wafer set being assigned to the target device, the constraint of the start time of the wafer set on the target device, and the constraint of the end time of the wafer set on the target device.

7. The method according to any one of claims 1 to 6, characterized in that, The target equipment includes idle equipment and equipment that is being processed.

8. The method according to any one of claims 1 to 7, characterized in that, The information of the wafer set includes at least one of the following: the wafer set number, the number of wafers in the wafer set, the product type number of the wafer set, the formulation of the wafer set, the path width of the wafer set, the arrival time of the wafer set, and the processing steps of the wafer set; The information of the target device includes at least one of the following: information about the loading port of the target device, information about the cavity of the target device, and information about the load of the cavity of the target device; The process information includes one or more of the following: the process number, the periodic operating time between the processing steps of the target equipment, the product type number corresponding to the wafer set, the correspondence between the wafer set and the process number, and the correspondence between the process number and the number of the target equipment. The information of the formula includes at least one of the following: the formula number, the target equipment corresponding to the formula, and the processing time corresponding to the formula.

9. A wafer dispatching apparatus, characterized in that, include: The acquisition module and the calculation module, among which, The acquisition module is used to acquire first information, which includes information on multiple wafer sets, information on multiple target devices, information on the process corresponding to the wafer set, and information on the formula corresponding to the wafer set. The calculation module is used to predict the dispatching scheme for each of the plurality of wafer groups based on the first information and the first model. The first model includes a mixed integer programming model. The input of the first model is the first information. The output of the first model is used to indicate the dispatching scheme for each of the plurality of wafer groups. The dispatching scheme includes information on the start processing time and end processing time of the wafer group, as well as information on the target equipment corresponding to the wafer group during the processing time period.

10. The apparatus according to claim 9, characterized in that, The first model includes an objective function, multiple sets of variables, and constraints. The objective function is used to characterize the dispatching target of the multiple wafer sets. The multiple sets of variables are determined based on the first information. The constraints are used to constrain the values ​​of the variables in the sets of variables.

11. The apparatus according to claim 10, characterized in that, The objective function is the sum of two weighted functions, which include a function that minimizes the total completion time of the plurality of wafer sets and a function that minimizes the difference between the maximum and minimum loads of the cavity of the target device. The weight of the function that minimizes the total completion time of the plurality of wafer sets is w1, and the weight of the function that minimizes the difference between the maximum and minimum loads of the cavity of the target device is w2. Both w1 and w2 are real numbers greater than 0 and less than 1, and the sum of w1 and w2 is 1.

12. The apparatus according to claim 10 or 11, characterized in that, The multiple variable groups correspond one-to-one with the multiple wafer groups, and each variable group includes at least one discrete variable and at least one continuous variable.

13. The apparatus according to claim 12, characterized in that, The at least one discrete variable includes at least one of the following: whether the i-th wafer group in the plurality of wafer groups is assigned to the m-th target device in the plurality of target devices; whether the i-th wafer group in the plurality of wafer groups is assigned to the l-th loading port of the m-th device in the plurality of target devices; and whether the i-th wafer group in the plurality of wafer groups is assigned to the r-th path width of the m-th device in the plurality of target devices. The at least one continuous variable includes at least one of the following: the start processing time of the i-th wafer group in the plurality of wafer groups on the m-th device in the plurality of target devices, the start processing time of the i-th wafer group in the plurality of wafer groups on the l-th loading port of the m-th device in the plurality of target devices, the start processing time of the i-th wafer group in the plurality of wafer groups on the c-th cavity of the m-th device in the plurality of target devices, the end processing time of the i-th wafer group in the plurality of wafer groups on the m-th device in the plurality of target devices, the end processing time of the i-th wafer group in the plurality of wafer groups on the l-th loading port of the m-th device in the plurality of target devices, and the end processing time of the i-th wafer group in the plurality of wafer groups on the c-th cavity of the m-th device in the plurality of target devices; Where i, m, l, r, and c are all positive integers greater than 0.

14. The apparatus according to any one of claims 10 to 13, characterized in that, The constraints include at least one of the following: the constraint of the wafer set being assigned to the target device, the constraint of the wafer set being assigned to the loading port of the target device, the constraint of the path width of the wafer set being assigned to the target device, the constraint of the start time of the wafer set on the target device, and the constraint of the end time of the wafer set on the target device.

15. The apparatus according to any one of claims 9 to 14, characterized in that, The target equipment includes idle equipment and equipment that is being processed.

16. The apparatus according to any one of claims 9 to 15, characterized in that, The information of the wafer set includes at least one of the following: the wafer set number, the number of wafers in the wafer set, the product type number of the wafer set, the formulation of the wafer set, the path width of the wafer set, the arrival time of the wafer set, and the processing steps of the wafer set; The information of the target device includes at least one of the following: information about the loading port of the target device, information about the cavity of the target device, and information about the load of the cavity of the target device; The process information includes one or more of the following: the process number, the periodic operating time between the processing steps of the target equipment, the product type number corresponding to the wafer set, the correspondence between the wafer set and the process number, and the correspondence between the process number and the number of the target equipment. The information of the formula includes at least one of the following: the formula number, the target equipment corresponding to the formula, and the processing time corresponding to the formula.

17. A computing device, characterized in that, It includes a processor and a memory, wherein the processor executes instructions in the memory such that the processor performs the method as described in any one of claims 1 to 8.

18. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing device cluster, the computing device cluster causes the computing device cluster to perform the method as described in any one of claims 1 to 8.

19. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a cluster of computing devices, perform the method as described in any one of claims 1 to 8.

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