Semiconductor package structure and application thereof
By embedding piezoelectric materials into a semiconductor packaging structure and forming a circuit loop, the current value is measured to obtain the internal stress of the chip, which solves the problems of accuracy limitations and environmental constraints in the existing technology, and realizes reliable monitoring and testing of the internal stress of the chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- PIONEER ORIGINAL (SHANGHAI) NEW TECHNOLOGY RESEARCH CO LTD
- Filing Date
- 2024-11-29
- Publication Date
- 2026-06-02
AI Technical Summary
Existing technologies have limitations in accuracy for chip stress testing, cannot effectively measure the internal stress state of wire-bonded chips, and cannot test thermal stress in a single state, thus limiting the evaluation of chip performance under different environments.
The method involves embedding piezoelectric materials in a semiconductor packaging structure, forming a circuit loop through wire bonding, and measuring the current value to obtain the internal stress of the chip. It includes a combination structure of substrate, semiconductor wafer, dielectric layer, pads, and conductive bonding elements.
It enables effective monitoring of micro-region stress inside the chip, improves the reliability of stress testing, does not damage the chip structure, is low in cost, and is compatible with semiconductor processes.
Smart Images
Figure CN122138672A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor packaging structure and its application. Background Technology
[0002] As a core component of modern electronic devices, testing the internal stress of chips is of great significance. Because chips are highly integrated and sealed, traditional physical testing methods struggle to penetrate this protective shell to accurately measure the internal stress state. Therefore, current methods primarily rely on stress simulation technology to assess the stress conditions chips may encounter during operation. However, while this technology can provide some qualitative analysis results, its accuracy remains significantly limited, failing to meet the ever-increasing demands for chip reliability and stability.
[0003] To overcome the limitations of qualitative analysis accuracy, existing technologies attempt to indirectly measure stress by constructing a Wheatstone bridge resistor on the chip surface. While this method shows potential in some aspects, it also faces several significant drawbacks: 1) Process limitations: This method is mainly based on WLCSP and Flip Chip processes, which cannot effectively measure the stress state inside the wire-bonded chip; 2) Structural distortion: To implement this method, a WLCSP layer needs to be added above the chip strain gauge. This additional structure not only increases the complexity of the process, but more importantly, it may cause distortion of the surface structure of the object under test, thus failing to accurately reflect the intrinsic stress state of the chip; 3) Testing environment limitations: This method requires the chip to be mounted on a PCB board for testing. However, in practical applications, the chip may also be affected by external factors such as thermal stress when operating alone. Since this method cannot test the thermal stress of the chip in its individual state, it has certain limitations in evaluating the chip's performance under different operating environments. Summary of the Invention
[0004] This invention provides a semiconductor packaging structure and its application.
[0005] In a first aspect, the present invention provides a semiconductor packaging structure, comprising:
[0006] substrate;
[0007] A semiconductor wafer formed on the first surface of the substrate;
[0008] A dielectric layer formed on the semiconductor wafer;
[0009] A first pad and a second pad are formed in the dielectric layer, and the first pad and the second pad are connected in the dielectric layer by a metal interconnect layer.
[0010] A first conductive solder element is formed on the first solder pad and a second conductive solder element is formed on the second solder pad, wherein the second conductive solder element and the second solder pad are connected by a layer of piezoelectric material;
[0011] A third conductive welding element and a fourth conductive welding element are formed on the second surface of the substrate. The third conductive welding element is connected to the first metal layer on the first surface of the substrate through a first through-hole metal, and the fourth conductive welding element is connected to the second metal layer on the first surface of the substrate through a second through-hole metal.
[0012] The first conductive welding element and the first metal layer are connected by a welding wire, and the second conductive welding element and the second metal layer are connected by a welding wire.
[0013] An encapsulation layer that encapsulates the semiconductor wafer on a first surface of the substrate.
[0014] Secondly, the present invention provides a method for stress testing of semiconductor packaging structures, comprising:
[0015] Provides the semiconductor packaging structure as described above;
[0016] Under the condition that the semiconductor packaging structure is subjected to thermal stress or mechanical stress, the third conductive welding element and the fourth conductive welding element are electrically connected, and the first conductive welding element, the second conductive welding element, the third conductive welding element and the fourth conductive welding element constitute a circuit loop.
[0017] The thermal or mechanical stress on the semiconductor package structure is obtained by measuring the current value of the circuit loop.
[0018] Thirdly, the present invention provides a method for fabricating a semiconductor packaging structure, comprising:
[0019] Provide substrate;
[0020] A semiconductor wafer is formed on the first surface of the substrate;
[0021] A dielectric layer is formed on the semiconductor wafer;
[0022] A first pad and a second pad are formed in the dielectric layer, and the first pad and the second pad are connected in the dielectric layer through a metal interconnect layer;
[0023] A first conductive soldering element is formed on the first solder pad, and a second conductive soldering element is formed on the second solder pad. The second conductive soldering element and the second solder pad are connected by a layer of piezoelectric material.
[0024] A third conductive welding element and a fourth conductive welding element are formed on the second surface of the substrate. The third conductive welding element is connected to the first metal layer on the first surface of the substrate through a first through-hole metal, and the fourth conductive welding element is connected to the second metal layer on the first surface of the substrate through a second through-hole metal.
[0025] The first conductive welding element and the first metal layer are connected by a welding wire, and the second conductive welding element and the second metal layer are connected by a welding wire.
[0026] An encapsulation layer is provided that encapsulates the semiconductor wafer on a first surface of the substrate. Attached Figure Description
[0027] Figure 1 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to the present invention;
[0028] Figure 2 This is a cross-sectional schematic diagram of the dielectric layer in a semiconductor packaging structure according to the present invention;
[0029] Figure 3 This is another cross-sectional schematic diagram of a semiconductor packaging structure according to the present invention;
[0030] Figure 4 This is another cross-sectional schematic diagram of a semiconductor packaging structure according to the present invention;
[0031] Figure 5 This is a planar schematic diagram of a semiconductor packaging structure according to the present invention;
[0032] Figure 6 This is a schematic diagram of the substrate fabrication process for a semiconductor packaging structure according to the present invention;
[0033] Figure 7 This is a flowchart illustrating a method for stress testing of a semiconductor packaging structure according to the present invention;
[0034] Figure 8 This is a schematic flowchart of a method for fabricating a semiconductor packaging structure according to the present invention;
[0035] Figure label:
[0036] 1. Substrate; 2. Semiconductor wafer; 31. First pad; 32. Second pad; 33. Metal interconnect layer; 34. First dielectric layer; 35. First groove; 36. Second groove; 37. Third dielectric layer; 41. First conductive welding element; 42. Second conductive welding element; 43. Third conductive welding element; 44. Fourth conductive welding element; 5. Piezoelectric material layer; 6. Bonding wire; 7. Package; 8. Bonding metal layer; +, Positive electrode of piezoelectric material layer; -, Negative electrode of piezoelectric material layer. Detailed Implementation
[0037] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. The following content is for illustrative purposes only and is not intended to limit the scope of the invention.
[0038] In the description of this invention, it should be understood that the terms "first" and "second," etc., are used to distinguish different objects, rather than to describe a specific order.
[0039] In the description of this invention, it should be noted that, unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for descriptive purposes only and is not intended to limit the invention. Those skilled in the art can understand the specific meaning of the terms in this invention based on the specific circumstances.
[0040] like Figure 1 As shown, the present invention provides a semiconductor packaging structure, comprising:
[0041] substrate1;
[0042] Semiconductor wafer 2 formed on the first surface of the substrate;
[0043] A dielectric layer formed on a semiconductor wafer;
[0044] A first pad 31 and a second pad 32 are formed in the dielectric layer, and the first pad and the second pad are connected in the dielectric layer by a metal interconnect layer 33.
[0045] A first conductive solder element 41 is formed on a first solder pad and a second conductive solder element 42 is formed on a second solder pad, wherein the second conductive solder element and the second solder pad are connected by a layer of piezoelectric material 5.
[0046] A third conductive welding element 43 and a fourth conductive welding element 44 are formed on the second surface of the substrate. The third conductive welding element is connected to the first metal layer 12 on the first surface of the substrate through the first through-hole metal 11, and the fourth conductive welding element is connected to the second metal layer 14 on the first surface of the substrate through the second through-hole metal 13.
[0047] The first conductive welding element and the first metal layer are connected by welding wire 6, and the second conductive welding element and the second metal layer are connected by welding wire 6.
[0048] Encapsulation layer 7 encapsulates the semiconductor wafer on the first surface of the substrate.
[0049] Figure 2 It shows Figure 1In some embodiments, the dielectric layer includes a first dielectric layer 34 disposed on the semiconductor wafer, a metal interconnect layer disposed on the first dielectric layer, and a second dielectric layer disposed on the metal interconnect layer. The first dielectric layer insulates the metal interconnect layer from the semiconductor wafer, and a first pad and a second pad are disposed in the second dielectric layer. It should be noted that both the first and second pads are passive structures and do not need to be connected to electrodes on the semiconductor wafer. The metal interconnect layer is connected to the first and second pads respectively through a third through-hole metal 15 disposed below the first and second pads. The second dielectric layer includes a first groove 35 and a second groove 36, with the first pad disposed in the first groove and the second pad disposed in the second groove. A piezoelectric material layer is disposed on the second pad, and a bonding metal layer 8 is disposed on the piezoelectric material layer. A third dielectric layer 37 is disposed on the surface of the second dielectric layer.
[0050] In some embodiments, a semiconductor wafer is bonded to the first surface of a substrate, using adhesive materials including, but not limited to, conductive silver paste, adhesive film, and gold-tin. In addition to the first and second metal layers, the first surface of the substrate has several other metal layers. In addition to the third and fourth conductive bonding elements, the second surface of the substrate has several other conductive bonding elements, each of which is connected to a corresponding metal layer via a through-hole. The encapsulation layer is made of resin, encapsulating the semiconductor wafer on the first surface of the substrate to seal it. The dielectric material in the first dielectric layer is one of ELK, ULK, USG, or BPSG. Both the first and second pads are square with dimensions of 50×50um to 100×100um, and are parallel to each other and fabricated simultaneously. The metal interconnect layer, the first through-hole metal, the second through-hole metal, the third through-hole metal, the first pad, the second pad, and the bonding wire are made of copper or aluminum. The metal interconnect layer is a conductive wire, and the spaces between adjacent third through-hole metals are filled with dielectric material. The first, second, third, and fourth conductive welding elements are conductive welding pillars or conductive welding balls. The first conductive welding element is positioned above the first groove, and the second conductive welding element is positioned above the second groove. A third dielectric layer separates the first and second conductive welding elements. The third dielectric layer is a passivation layer, and an opening is formed by cutting open the passivation layer in the central region of the first and second pads. The passivation layer is a multilayer structure comprising silicon nitride and silicon oxide. The piezoelectric material layer has the same dimensions as the second pad, with a thickness of 5–10 μm, and the bonding metal layer has a thickness of 1–2 μm. The piezoelectric material layer and the bonding metal layer are formed by sputtering. The piezoelectric material is one of ZnO, PZT, or AlN, and the bonding metal layer includes, but is not limited to, a gold layer, a nickel-palladium-gold layer, and a titanium-aluminum layer. It is understood that the nickel-palladium-gold layer is a multilayer structure comprising nickel, palladium, and gold, and the titanium-aluminum layer is a multilayer structure comprising titanium and aluminum. For detailed descriptions of the characteristics of the aforementioned piezoelectric materials, please refer to Table 1.
[0051] Table 1 Properties of different piezoelectric materials
[0052] Piezoelectric material ZnO PZT AIN Density / (g / cm 3 )]]> 5.61 7.8 3.3 Elastic modulus / Gpa 110～140 61 300～500 Hardness / Gpa 4～5 7～18 15 Piezoelectric coefficient / (pC / N) 12 289～380，117 4.5，6.4 Electromechanical coupling coefficient / % 1.5～1.7 20～35 3.1～8 Longitudinal (transverse) wave velocity / (m / s) 6336(2650) 4500(2200) 11050(6090) Relative dielectric constant 8.66 380 8.65 Thermal expansion coefficient 4 175 4
[0053] Figure 3 A cross-sectional schematic diagram of some other embodiments of a semiconductor packaging structure according to the present invention is shown. The semiconductor packaging structure is configured to connect a third conductive bonding element and a fourth conductive bonding element via wires. The first conductive bonding element, the second conductive bonding element, the third conductive bonding element, and the fourth conductive bonding element constitute a circuit loop. The thermal stress or mechanical stress on the semiconductor packaging structure is obtained by measuring the current value of the circuit loop.
[0054] Figure 4 It shows Figure 3 In some implementations, the negative electrode of the piezoelectric material layer is connected to the second pad, and the positive electrode is connected to the bonding metal layer. When the semiconductor package structure is subjected to external thermal or mechanical stress, stress is generated on the surface of the piezoelectric material layer, creating a voltage difference between the positive and negative electrodes. At this time, a current is generated in the circuit due to the voltage difference, where the second and fourth conductive bonding elements form the positive electrode path. See [link to relevant documentation]. Figure 4 The yellow portion, where the first and third conductive welding elements form the negative electrode path, see [link / reference]. Figure 4 The blue part.
[0055] In some implementations, PZT is selected as the piezoelectric material, with a piezoelectric coefficient of 1000 pC / N and a piezoelectric material layer size of 50 × 50 μm. The metal circuit cross-section is 10 μm × 10 μm, and the circuit loop length is 40 mm. Under the above conditions, the semiconductor package structure is heated, and the thermal stress inside the semiconductor package structure gradually increases with temperature. When the temperature reaches 260 degrees Celsius, the circuit loop generates a current of 112 pA. If the ammeter reads a current of 112 pA, it is determined that the semiconductor wafer surface is subjected to a pressure of 300 MPa.
[0056] The remaining embodiments of the semiconductor packaging structure of the present invention will be described in detail below:
[0057] In some embodiments, the semiconductor packaging structure of the present invention is used for stress testing of QFN type chips. The package material is epoxy resin. Figure 5This diagram illustrates a planar schematic of a semiconductor packaging structure for stress testing of QFN-type chips according to the present invention. The frame consists of several frame pins and a single frame base. The frame is a single-layer structure made entirely of copper. It is first formed using etching or stamping, then a metal is electroplated onto the copper surface. This metal serves as the contact area between the bonding wires and the frame, including but not limited to silver and nickel-palladium-gold. Finally, the chip is placed on the frame base, and bonding wires are used to connect the pads to the frame pins.
[0058] In some embodiments, the semiconductor packaging structure of the present invention is applied to stress testing of WB-CSP type chips. The package material is epoxy resin. Figure 6 This diagram illustrates the substrate fabrication process for the semiconductor packaging structure used in stress testing of WB-CSP type chips according to the present invention. The substrate has a multilayer structure. First, a central dielectric layer is fabricated. Then, a hole is drilled in the center of the central dielectric layer and filled with copper to form a through-hole. Next, metal layers are fabricated on the upper and lower surfaces of the central dielectric layer. Finally, the metal layers on the upper and lower surfaces are covered with solder mask.
[0059] In some embodiments, the semiconductor packaging structure of the present invention is applied to stress testing of WB-BGA type chips. The package is made of epoxy resin. The substrate has a multilayer structure. First, a central dielectric layer is fabricated. Then, a hole is drilled in the center of the central dielectric layer and filled with copper to form a through-hole. Next, metal layers are fabricated on the upper and lower surfaces of the central dielectric layer. Finally, the metal layers on the upper and lower surfaces are covered with solder mask.
[0060] This invention discloses a semiconductor packaging structure that, by embedding piezoelectric material inside a semiconductor wafer and using bonding wires to extract and measure the electrical signal of the piezoelectric material, obtains the internal pressure value of the semiconductor wafer, enabling effective monitoring of micro-region stress inside the chip; it does not damage the chip's structure and material, improves the reliability of stress test results; it is fully compatible with semiconductor processes and has low implementation costs.
[0061] like Figure 7 As shown, the present invention provides a method for stress testing of semiconductor package structures, including the following steps:
[0062] S1. Provide a semiconductor packaging structure;
[0063] Provide such as Figure 1 The semiconductor packaging structure shown.
[0064] S2. Under the condition that the semiconductor packaging structure is subjected to thermal stress or mechanical stress, the third conductive welding element and the fourth conductive welding element are electrically connected, and the first conductive welding element, the second conductive welding element, the third conductive welding element and the fourth conductive welding element constitute a circuit loop.
[0065] S3. Based on the current value of the measurement circuit loop, obtain the thermal or mechanical stress on the semiconductor package structure.
[0066] Based on the current value of the measuring circuit loop and the piezoelectric coefficient of the piezoelectric material, the thermal or mechanical stress on the semiconductor packaging structure is obtained.
[0067] It should be noted that the specific limitations of a stress testing method for a semiconductor packaging structure are as described above regarding the limitations of a semiconductor packaging structure. The two methods have the same function and role, and will not be repeated here.
[0068] like Figure 8 As shown, the present invention provides a method for fabricating a semiconductor packaging structure, comprising the following steps:
[0069] S11, Provide a substrate;
[0070] S12. A semiconductor wafer is formed on the first surface of the substrate;
[0071] S13. Forming a dielectric layer on a semiconductor wafer;
[0072] A first dielectric layer is disposed on a semiconductor wafer, a metal interconnect layer is disposed on the first dielectric layer, and a second dielectric layer is disposed on the metal interconnect layer. The first dielectric layer insulates the metal interconnect layer from the semiconductor wafer.
[0073] S14. Form a first pad and a second pad in the dielectric layer, and connect the first pad and the second pad in the dielectric layer through a metal interconnect layer.
[0074] The first pad and the second pad are disposed in the second dielectric layer, and the metal interconnect layer is connected to the first pad and the second pad respectively through the third through-hole metal disposed below the first pad and the second pad.
[0075] S15. A first conductive welding element is formed on a first pad, a second conductive welding element is formed on a second pad, and the second conductive welding element and the second pad are connected by a layer of piezoelectric material.
[0076] S16. A third conductive welding element and a fourth conductive welding element are formed on the second surface of the substrate. The third conductive welding element is connected to the first metal layer on the first surface of the substrate through a first through-hole metal, and the fourth conductive welding element is connected to the second metal layer on the first surface of the substrate through a second through-hole metal.
[0077] S17. Connect the first conductive welding element and the first metal layer with a welding wire, and connect the second conductive welding element and the second metal layer with a welding wire.
[0078] S18. Provide a packaging layer that encapsulates a semiconductor wafer on a first surface of a substrate.
[0079] The second dielectric layer includes a first groove and a second groove. A first pad is disposed in the first groove, and a second pad is disposed in the second groove. A first conductive welding element is disposed above the first groove, and a second conductive welding element is disposed above the second groove. A third dielectric layer is disposed on the surface of the second dielectric layer, and the third dielectric layer separates the first conductive welding element and the second conductive welding element.
[0080] It should be noted that the specific limitations of the preparation method of a semiconductor packaging structure are as described above for the limitations of a semiconductor packaging structure. The two have the same function and role, and will not be repeated here.
[0081] In summary, the present invention provides a semiconductor packaging structure and its application. By embedding piezoelectric materials inside a semiconductor wafer and using bonding wires to extract and measure the electrical signals of the piezoelectric materials, the internal pressure value of the semiconductor wafer can be obtained, enabling effective monitoring of micro-region stress inside the chip. This does not damage the chip's structure and materials, improves the reliability of stress test results, is fully compatible with semiconductor processes, and has low implementation costs.
[0082] The various embodiments in this specification are described in a progressive manner. For directly identical or similar parts of each embodiment, refer to the other embodiments. Each embodiment focuses on its differences from other embodiments. It should be noted that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as these combinations of technical features do not contradict each other, they should be considered within the scope of this specification.
[0083] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.
Claims
1. A semiconductor packaging structure, characterized in that, include: substrate; A semiconductor wafer formed on the first surface of the substrate; A dielectric layer formed on the semiconductor wafer; A first pad and a second pad are formed in the dielectric layer, and the first pad and the second pad are connected in the dielectric layer by a metal interconnect layer. A first conductive solder element is formed on the first solder pad and a second conductive solder element is formed on the second solder pad, wherein the second conductive solder element and the second solder pad are connected by a layer of piezoelectric material; A third conductive welding element and a fourth conductive welding element are formed on the second surface of the substrate. The third conductive welding element is connected to the first metal layer on the first surface of the substrate through a first through-hole metal, and the fourth conductive welding element is connected to the second metal layer on the first surface of the substrate through a second through-hole metal. The first conductive welding element and the first metal layer are connected by a welding wire, and the second conductive welding element and the second metal layer are connected by a welding wire. An encapsulation layer that encapsulates the semiconductor wafer on a first surface of the substrate.
2. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor package structure is configured to connect the third conductive welding element and the fourth conductive welding element via wires. The first conductive welding element, the second conductive welding element, the third conductive welding element, and the fourth conductive welding element constitute a circuit loop. The thermal stress or mechanical stress on the semiconductor package structure is obtained by measuring the current value of the circuit loop.
3. The semiconductor packaging structure according to claim 1, characterized in that, The dielectric layer includes a first dielectric layer disposed on the semiconductor wafer, a metal interconnect layer disposed on the first dielectric layer, and a second dielectric layer disposed on the metal interconnect layer. The first dielectric layer insulates the metal interconnect layer from the semiconductor wafer, and the first pad and the second pad are disposed in the second dielectric layer.
4. The semiconductor packaging structure according to claim 3, characterized in that, The metal connection layer is connected to the first pad and the second pad respectively through a third through-hole metal disposed below the first pad and the second pad.
5. The semiconductor packaging structure according to claim 3, characterized in that, The second dielectric layer includes a first groove and a second groove. The first pad is disposed in the first groove, and the second pad is disposed in the second groove. The first conductive soldering element is disposed above the first groove, and the second conductive soldering element is disposed above the second groove. A third dielectric layer is disposed on the surface of the second dielectric layer, and the third dielectric layer separates the first conductive soldering element and the second conductive soldering element.
6. The semiconductor packaging structure according to claim 1, characterized in that, The piezoelectric material is one of ZnO, PZT or AlN.
7. The semiconductor packaging structure according to claim 1, characterized in that, The conductive welding element is a conductive welding column or a conductive welding ball.
8. The semiconductor packaging structure according to claim 1, characterized in that, A piezoelectric material layer is disposed on the second pad, and the thickness of the piezoelectric material layer is 5-10 μm.
9. The semiconductor packaging structure according to claim 1, characterized in that, A piezoelectric material layer is disposed on the second pad, and a bonding metal layer is disposed on the piezoelectric material layer, the thickness of the bonding metal layer being 1-2 μm.
10. A method for stress testing of a semiconductor package structure, characterized in that, include: Provide a semiconductor packaging structure as described in any one of claims 1-9; Under the condition that the semiconductor packaging structure is subjected to thermal stress or mechanical stress, the third conductive welding element and the fourth conductive welding element are electrically connected, and the first conductive welding element, the second conductive welding element, the third conductive welding element and the fourth conductive welding element constitute a circuit loop. The thermal or mechanical stress on the semiconductor package structure is obtained by measuring the current value of the circuit loop.
11. The method for testing the stress of a semiconductor package structure according to claim 10, characterized in that, The method of obtaining the thermal or mechanical stress on the semiconductor package structure based on measuring the current value of the circuit loop includes: Based on the measured current value of the circuit loop and the piezoelectric coefficient of the piezoelectric material, the thermal or mechanical stress on the semiconductor packaging structure is obtained.
12. A method for fabricating a semiconductor packaging structure, characterized in that, include: Provide substrate; A semiconductor wafer is formed on the first surface of the substrate; A dielectric layer is formed on the semiconductor wafer; A first pad and a second pad are formed in the dielectric layer, and the first pad and the second pad are connected in the dielectric layer through a metal interconnect layer; A first conductive soldering element is formed on the first solder pad, and a second conductive soldering element is formed on the second solder pad. The second conductive soldering element and the second solder pad are connected by a layer of piezoelectric material. A third conductive welding element and a fourth conductive welding element are formed on the second surface of the substrate. The third conductive welding element is connected to the first metal layer on the first surface of the substrate through a first through-hole metal, and the fourth conductive welding element is connected to the second metal layer on the first surface of the substrate through a second through-hole metal. The first conductive welding element and the first metal layer are connected by a welding wire, and the second conductive welding element and the second metal layer are connected by a welding wire. An encapsulation layer is provided that encapsulates the semiconductor wafer on a first surface of the substrate.
13. The preparation method according to claim 12, characterized in that, The process of forming a dielectric layer on the semiconductor wafer includes: A first dielectric layer is disposed on the semiconductor wafer, a metal interconnect layer is disposed on the first dielectric layer, and a second dielectric layer is disposed on the metal interconnect layer, wherein the first dielectric layer insulates the metal interconnect layer from the semiconductor wafer.
14. The preparation method according to claim 13, characterized in that, The step of forming a first pad and a second pad in the dielectric layer, and connecting the first pad and the second pad in the dielectric layer through a metal interconnect layer, includes: The first pad and the second pad are disposed in the second dielectric layer, and the metal connection layer is connected to the first pad and the second pad respectively through a third through-hole metal disposed below the first pad and the second pad.
15. The preparation method according to claim 13, characterized in that, The second dielectric layer includes a first groove and a second groove. The first pad is disposed in the first groove, and the second pad is disposed in the second groove. The first conductive soldering element is disposed above the first groove, and the second conductive soldering element is disposed above the second groove. A third dielectric layer is disposed on the surface of the second dielectric layer, and the third dielectric layer separates the first conductive soldering element and the second conductive soldering element.