Switching device and method of manufacturing the same

Abstract

This disclosure relates to the field of semiconductor technology, specifically to an interconnect device and its fabrication method. The interconnect device includes: a glass substrate having a continuous first surface; a silicon-based integrated passive device protruding from the first surface away from the glass substrate and in direct contact with the first surface; an insulating layer disposed on the first surface and at least covering the surface of the silicon-based integrated passive device; and a redistribution layer disposed on the side of the insulating layer away from the glass substrate, including multiple redistribution patterns. The redistribution patterns are electrically connected to the silicon-based integrated passive device through conductive paths located inside the insulating layer. This application provides a higher placement density for active chips on the redistribution layer by protruding the silicon-based passive device from the glass substrate surface and covering and filling it with an insulating layer; and the redistribution patterns are directly interconnected with the passive device through extremely short conductive paths, significantly shortening the interconnection path.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to an adapter device and its fabrication method. Background Technology

[0002] With the rapid development of technologies such as 5G, artificial intelligence (AI), and high-performance computing (HPC), glass interposers are considered one of the core technologies for next-generation high-performance packaging due to their excellent RF performance, adjustable coefficient of thermal expansion, and advantages of large size and low cost. In the application of glass interposers, integrated passive devices (IPDs) are crucial for improving system power integrity, signal integrity, and realizing RF front-end functions.

[0003] However, existing IPD integration methods typically employ surface mount technology or flip-chip bonding, placing active chips and passive devices side-by-side on the surface of the adapter board. This planar layout limits the density of active chips, and the interconnections between active chips and passive devices require long redistribution layer (RDL) traces or substrate wiring. Long interconnect paths introduce significant parasitic inductance, affecting power integrity and causing signal attenuation and interference for high-frequency signal transmission, failing to meet the stringent electrical performance requirements of high-performance computing chips and RF systems. Therefore, the industry urgently needs a technical solution that can achieve high-density passive device integration on a glass adapter board, without occupying surface space, with short interconnect paths, good process compatibility, and high reliability. Summary of the Invention

[0004] This application provides an adapter and its fabrication method, aiming to solve the problem of how to achieve high-density embedded integration of silicon-based passive devices, while providing a flat surface and short-path wiring structure for subsequent interconnection with active chips.

[0005] The first aspect of this application provides an adapter device, the adapter device comprising: A glass substrate having a continuous first surface; A silicon-based integrated passive device, wherein the silicon-based integrated passive device protrudes from the first surface on the side away from the glass substrate and is in direct contact with the first surface, and the thickness of the silicon-based integrated passive device is less than or equal to 30 μm; An insulating layer is disposed on the first surface and at least covers the surface of the silicon-based integrated passive device, wherein the maximum thickness of the insulating layer is greater than the thickness of the silicon-based integrated passive device; A redistribution layer is disposed on the side of the insulating layer away from the glass substrate, and includes multiple redistribution patterns. The redistribution patterns are electrically connected to the silicon-based integrated passive device through conductive paths located inside the insulating layer, and the redistribution patterns are used to form electrical connections with active chips.

[0006] In one alternative embodiment, the silicon-based integrated passive device is fixed to the first surface by a bonding layer.

[0007] In one alternative embodiment, the bonding layer comprises an anodic bonding layer or a bonding adhesive layer.

[0008] In one alternative embodiment, the orthographic projection of the redistribution pattern on the glass substrate does not overlap with the orthographic projection of the silicon-based integrated passive device on the glass substrate.

[0009] In one optional embodiment, at least one first conductive via is provided on the glass substrate, the first conductive via penetrating the glass substrate along the thickness direction, and the first conductive via is filled with conductive material.

[0010] In one alternative embodiment, the orthographic projection of the first conductive via on the glass substrate does not overlap with the orthographic projection of the silicon-based integrated passive device on the glass substrate; The orthographic projection of the first conductive via on the glass substrate and the orthographic projection of the redistribution pattern on the glass substrate at least partially overlap, and the redistribution pattern and the first conductive via are electrically connected through conductive vias penetrating the insulating layer.

[0011] In one optional embodiment, the insulating layer has a plurality of grooves on the side away from the glass substrate, and the plurality of redistribution patterns are disposed one-to-one in the plurality of grooves.

[0012] In one alternative embodiment, the redistribution pattern is flush with the surface of the insulating layer on the side away from the glass substrate.

[0013] In one alternative embodiment, the insulating layer is an ABF film layer.

[0014] A second aspect of this application provides a method for fabricating an adapter device, the method comprising: A glass substrate is provided, the glass substrate having a continuous first surface; A silicon-based integrated passive device is bonded to the first surface of the glass substrate. The silicon-based integrated passive device protrudes from the side of the first surface away from the glass substrate and is in direct contact with the first surface. The thickness of the silicon-based integrated passive device is less than or equal to 30 μm. An insulating layer is formed on the first surface, the insulating layer at least covering the surface of the silicon-based integrated passive device, and the maximum thickness of the insulating layer is greater than the thickness of the silicon-based integrated passive device; A redistribution layer is formed on the side of the insulating layer away from the glass substrate. The redistribution layer includes a plurality of redistribution patterns. The redistribution patterns are electrically connected to the silicon-based integrated passive device through conductive paths located inside the insulating layer, and the redistribution patterns are used to form electrical connections with active chips.

[0015] Beneficial effects: This application provides an adapter and its fabrication method. The adapter includes: a glass substrate having a continuous first surface; a silicon-based integrated passive device (SID) protruding from the first surface away from the glass substrate and in direct contact with the first surface, wherein the thickness of the SID is less than or equal to 30 μm; an insulating layer disposed on the first surface and at least covering the surface of the SID, wherein the maximum thickness of the insulating layer is greater than the thickness of the SID; and a redistribution layer disposed on the insulating layer away from the glass substrate, comprising a plurality of redistribution patterns, wherein the redistribution patterns form an electrical connection with the SID through conductive paths located inside the insulating layer, and the redistribution patterns are used to form an electrical connection with an active chip.

[0016] This application simplifies the process by protruding silicon-based passive devices onto the surface of a glass substrate with a thickness of ≤30μm, and then covering and leveling the surface with an insulating layer to form a smooth surface. This avoids the complex etching steps of traditional slotting and embedding processes. Simultaneously, the passive devices are directly embedded in the insulating layer on the substrate surface, freeing up surface space and allowing for higher density of active chips on the redistribution layer. Furthermore, the redistribution patterns directly interconnect with the passive devices through extremely short conductive paths, significantly shortening the interconnection path, reducing parasitic inductance and resistance, and effectively improving power integrity and high-frequency signal transmission quality.

[0017] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of an adapter device according to an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a glass substrate provided in a method for fabricating an adapter according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure for forming a first conductive via in a method for fabricating an adapter according to an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a bonded silicon-based integrated passive device in a method for fabricating an adapter according to an embodiment of this application; Figure 5 This is a schematic diagram of the structure in which an insulating layer is formed in a method for fabricating an adapter according to an embodiment of this application; Figure 6 This is a schematic flowchart of a method for fabricating an adapter according to an embodiment of this application.

[0020] Explanation of reference numerals in the attached figures: 11. Glass substrate; 12. Silicon-based integrated passive device; 13. Insulating layer; 14. Redistribution layer; 141. Redistribution pattern; 15. First conductive via. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0022] With the rapid development of technologies such as 5G, artificial intelligence (AI), and high-performance computing (HPC), electronic systems are placing increasingly higher demands on chip packaging density, signal transmission speed, power management, and miniaturization. Traditional two-dimensional planar packaging can no longer meet the requirements of system integration and electrical performance, making three-dimensional heterogeneous integration technology an important development direction in the current semiconductor packaging field. Among these technologies, glass interposers are considered one of the core technologies for next-generation high-performance packaging due to their excellent radio frequency performance, adjustable coefficient of thermal expansion, and advantages of large size and low cost.

[0023] In glass interface board (IPC) applications, integrating passive components is crucial for improving system power integrity, signal integrity, and enabling RF front-end functions. Decoupling capacitors, inductors, and other passive components need to be physically located as close as possible to active chips to reduce parasitic inductance and resistance, and improve transient response speed. However, existing IPC integration methods still have the following problems: Surface mount technology occupies valuable space: Traditional IPD integration typically uses surface mount technology or flip-chip bonding to arrange active chips and passive components side-by-side on the surface of the adapter board. This planar layout occupies extremely valuable surface area of ​​the glass adapter board, limiting the density of active chips and making it difficult to meet the needs of high-density integration.

[0024] Long interconnect paths limit electrical performance: In surface mount technology, the interconnection between active chips and passive devices requires long RDL traces or substrate wiring. Long interconnect paths introduce significant parasitic inductance, affecting power integrity and causing signal attenuation and interference for high-frequency signal transmission, failing to meet the stringent electrical performance requirements of high-performance computing chips and RF systems.

[0025] Embedded solutions present technological challenges: To address the aforementioned issues, the industry has attempted to embed passive devices within the substrate. However, existing embedded solutions typically require pre-etching grooves in the substrate, placing the passive device within the grooves, and then filling with dielectric material for planarization. This "grooving embedding" process has the following drawbacks: it requires high-precision groove etching, resulting in a complex and costly process; the matching requirements between the groove depth and the passive device thickness are stringent, placing demanding requirements on the process window; and the surface flatness after embedding is affected by the groove machining accuracy and filling process, making it difficult to guarantee the photolithography quality of subsequent high-precision RDLs.

[0026] Thickness and material compatibility issues: Conventional passive devices are relatively thick, making it difficult to directly embed them into thin dielectric layers. Even with thinning processes, improper thickness control can still result in significant step height differences after embedding, causing surface undulations in the dielectric layer and affecting the yield of subsequent fine-linewidth RDL fabrication. Furthermore, mismatches in the coefficients of thermal expansion between different materials can introduce thermal stress, impacting package reliability.

[0027] To address the aforementioned issues, the industry urgently needs a technical solution that can achieve high-density passive device integration on a glass adapter board, without occupying surface space, with short interconnect paths, good process compatibility, and high reliability.

[0028] In view of this, embodiments of this application provide an adapter device. Figure 1 A schematic diagram of the structure of an adapter according to an embodiment of this application is shown, as follows: Figure 1 As shown, the adapter includes a glass substrate 11, which serves as the supporting foundation for the entire adapter. Utilizing the extremely low dielectric loss and adjustable thermal expansion coefficient of the glass material, it provides excellent electrical performance for high-frequency signal transmission and simultaneously forms a good thermal match with the silicon-based chip, reducing the risk of thermal stress. The glass substrate 11 has a continuous first surface, which is used for bonding the silicon-based integrated passive device 12 and serves as the surface for forming the insulating layer 13.

[0029] In this embodiment, the adapter further includes a silicon-based integrated passive device 12. The silicon-based integrated passive device 12 protrudes from the first surface on the side away from the glass substrate 11 and is in direct contact with the first surface. The silicon-based integrated passive device 12 is fabricated using mature silicon-based semiconductor technology, enabling high-density integration of various passive components such as capacitors, inductors, and resistors within a small silicon chip area. In this embodiment, by protruding the silicon-based integrated passive device 12 onto the surface of the glass substrate 11, unlike the traditional slotting and embedding process, no etching of the glass substrate 11 is required. Fixing is achieved solely through bonding, significantly simplifying the process and avoiding problems related to alignment accuracy, depth control, and stress concentration associated with slotting.

[0030] The thickness of the silicon-based integrated passive device 12 is less than or equal to 30 μm. By strictly controlling the thickness of the silicon-based integrated passive device 12 to within 30 μm, the silicon-based integrated passive device 12 can perfectly adapt to the filling capacity of the insulating layer 13 material. Specifically, when the protruding device height does not exceed 30 μm, the subsequent fabrication process of the insulating layer 13 can completely fill the corner space around the silicon-based integrated passive device 12 without voids, and form a flat surface by covering the top of the silicon-based integrated passive device 12, thereby completely eliminating the step effect caused by the excessive thickness of the silicon-based integrated passive device 12. This provides a highly flat foundation for the subsequent photolithography process of the redistribution layer 14, significantly improving the fabrication yield and reliability of the fine-line width redistribution pattern 141.

[0031] In some optional embodiments, the silicon-based integrated passive device 12 is fixed to the first surface of the glass substrate 11 via a bonding layer. Using a bonding layer to directly bond the passive device to the glass substrate surface allows for a tight physical connection between the two, eliminating the need for slotting in the substrate and simplifying the manufacturing process. Furthermore, the thermal expansion coefficient of glass is similar to that of silicon; the tight bond formed by the bonding layer effectively suppresses stress caused by thermal mismatch during temperature changes, contributing to improved long-term device reliability.

[0032] Furthermore, the bonding layer can be selected from different types according to process requirements, such as anodic bonding layers or bonding adhesive layers. Anodic bonding is suitable for scenarios requiring high bonding strength and long-term stability, and can form a strong interface with atomic-level bonding under high temperature and high pressure conditions; while bonding adhesive layers have the advantages of low processing temperature and simple operation, and are suitable for the integration of temperature-sensitive devices. Those skilled in the art can flexibly select the appropriate bonding method according to the specific application scenario and process conditions.

[0033] In this embodiment, the adapter further includes an insulating layer 13 disposed on the first surface, and the insulating layer 13 at least covers the surface of the silicon-based integrated passive device 12. The maximum thickness of the insulating layer 13 is greater than the thickness of the silicon-based integrated passive device 12, so that the insulating layer 13 completely covers the side surface and side of the silicon-based integrated passive device 12 away from the glass substrate 11. The insulating layer 13 covers and wraps the protruding passive device, fills the surrounding space, and forms a flat upper surface, providing an ideal process substrate for subsequent high-precision wiring.

[0034] In some optional embodiments, the insulating layer 13 can be an insulating material with excellent flow and filling properties. For example, the insulating layer 13 can be an ABF (Ajinomoto Build-up Film) layer, and the material of the insulating layer 13 is an ABF film. ABF material exhibits good flowability under heated and pressurized lamination processes, which can fully fill the corner areas between the silicon-based integrated passive device 12 and the glass substrate 11, as well as the tiny gaps around the device, ensuring void-free coverage. Simultaneously, the lamination process, combined with the inherent properties of ABF material, can form a relatively flat surface after covering the protruding passive device, providing a good foundation for the subsequent photolithography process of the redistribution layer. It should be noted that the formation method of the insulating layer 13 in the embodiments of this application is not limited to lamination. Those skilled in the art can also choose other film formation methods such as chemical vapor deposition or spin coating according to actual process conditions, as long as the function of covering the passive device and forming a flat surface can be achieved.

[0035] In this embodiment, the adapter further includes a redistribution layer 14, which is disposed on the side of the insulating layer 13 away from the glass substrate 11. The redistribution layer 14 includes multiple redistribution patterns 141. These redistribution patterns 141 are electrically connected to the silicon-based integrated passive device 12 via conductive paths (not shown in the figure) located inside the insulating layer 13, and are also used to form electrical connections with active chips. The redistribution layer 14 is fabricated on the flat surface of the insulating layer 13, enabling fine-linewidth, high-density wiring patterns. It directly connects to the underlying silicon-based integrated passive device 12 via extremely short conductive paths, significantly shortening the interconnection path and reducing parasitic inductance and resistance. Simultaneously, the wiring patterns on its surface provide an electrical interface for subsequent mounting of active chips, achieving close-range, low-loss interconnection between the silicon-based integrated passive device 12 and the active chip.

[0036] In some optional embodiments, the orthographic projection of the redistribution pattern 141 on the glass substrate 11 does not overlap with the orthographic projection of the silicon-based integrated passive device 12 on the glass substrate 11. By employing this staggered layout design, the traces of the redistribution layer 14 avoid the area directly above the silicon-based integrated passive device 12, effectively preventing the impact of minute surface undulations on the fine line lithography accuracy, and further improving the fabrication yield of the redistribution layer 14. Simultaneously, this layout disperses the interconnect paths horizontally, avoiding a large number of conductive vias concentrated above the silicon-based integrated passive device 12, which helps to disperse thermomechanical stress and prevent localized stress concentration from causing interface cracking or reliability failure, thereby optimizing the overall structural stability of the device. Furthermore, the non-overlapping layout also provides greater flexibility in the routing design of the redistribution layer 14, facilitating fan-out routing based on the electrode distribution of the active chip.

[0037] In some optional embodiments, at least one first conductive via 15 is provided on the glass substrate 11. The first conductive via 15 penetrates the glass substrate 11 along its thickness direction and is filled with conductive material. The first conductive via 15 is used to realize vertical electrical interconnection between the upper and lower sides of the glass substrate 11, transmitting the signal on the redistribution layer 14 from the top surface of the glass substrate 11 to the bottom surface of the glass substrate 11 (the side opposite to the first plane), thereby forming an electrical connection with the system motherboard or external circuit disposed on the bottom surface. By integrating conductive vias in the glass substrate 11, the embodiments of this application can maintain a complete vertical electrical path while realizing the embedding of surface passive devices, enabling the adapter device to have a true three-dimensional adapter function. The low dielectric loss characteristics of the glass material combined with the filling of low-resistance conductive materials such as copper result in minimal loss of high-frequency signals during vertical transmission, effectively ensuring signal integrity. At the same time, the first conductive via 15 can be flexibly distributed in different areas of the substrate, providing abundant connection points for the fan-out wiring of the redistribution layer 14, improving the design freedom of the wiring.

[0038] In some optional embodiments, the orthographic projection of the first conductive via 15 on the glass substrate 11 does not overlap with the orthographic projection of the silicon-based integrated passive device 12 on the glass substrate 11. By staggering the first conductive via 15 and the silicon-based integrated passive device 12, their vertical stacking can be avoided, preventing excessive local thermal stress caused by differences in the thermal expansion coefficients of the materials during temperature changes. This effectively reduces the risk of interface cracking or device damage, and improves the structural stability and long-term reliability of the device.

[0039] Simultaneously, the orthographic projection of the first conductive via 15 on the glass substrate 11 at least partially overlaps with the orthographic projection of the redistribution pattern 141 on the glass substrate 11, and the redistribution pattern 141 and the first conductive via 15 are electrically connected through conductive vias (not shown in the figure) penetrating the insulating layer 13. This layout allows the redistribution layer 14 to interconnect with the lower first conductive via 15 via a very short vertical path, further shortening the signal transmission distance from the active chip to the system motherboard and reducing parasitic inductance and resistance. In addition, directly connecting the redistribution pattern 141 and the first conductive via 15 vias avoids complex horizontal wiring, simplifies wiring design, and improves wiring density and signal transmission efficiency.

[0040] In some optional embodiments, the insulating layer 13 has a plurality of grooves on the side away from the glass substrate 11, and the plurality of redistribution patterns 141 are correspondingly disposed in the plurality of grooves. This embedded wiring structure allows the redistribution patterns to be contained within the insulating layer rather than protruding from the surface of the insulating layer, which can effectively avoid mechanical damage to the lines in subsequent processes, and at the same time facilitates the achievement of finer line widths and spacings, thereby increasing wiring density.

[0041] Furthermore, the surface of the redistribution pattern 141 away from the glass substrate 11 is flush with the surface of the insulating layer 13 away from the glass substrate 11. Through planarization processes such as chemical mechanical polishing, the upper surface of the redistribution pattern 141 and the surface of the insulating layer 13 are made coplanar, forming a composite surface with extremely high flatness. This flush structure not only eliminates the step effect that may be caused by line bumps, providing an ideal process substrate for subsequent multilayer wiring or multi-chip stacking, but also ensures that the connection interface between the chip bumps and the redistribution pattern is subjected to uniform stress during active chip mounting, effectively improving interconnect reliability and assembly yield.

[0042] This application provides an adapter and its fabrication method. The adapter includes: a glass substrate having a continuous first surface; a silicon-based integrated passive device (SID) protruding from the first surface away from the glass substrate and in direct contact with the first surface, wherein the thickness of the SID is less than or equal to 30 μm; an insulating layer disposed on the first surface and at least covering the surface of the SID, wherein the maximum thickness of the insulating layer is greater than the thickness of the SID; and a redistribution layer disposed on the insulating layer away from the glass substrate, comprising a plurality of redistribution patterns, wherein the redistribution patterns form an electrical connection with the SID through conductive paths located inside the insulating layer, and the redistribution patterns are used to form an electrical connection with an active chip.

[0043] This application simplifies the process by protruding silicon-based passive devices onto the surface of a glass substrate with a thickness of ≤30μm, and then covering and leveling the surface with an insulating layer to form a smooth surface. This avoids the complex etching steps of traditional slotting and embedding processes. Simultaneously, the passive devices are directly embedded in the insulating layer on the substrate surface, freeing up surface space and allowing for higher density of active chips on the redistribution layer. Furthermore, the redistribution patterns directly interconnect with the passive devices through extremely short conductive paths, significantly shortening the interconnection path, reducing parasitic inductance and resistance, and effectively improving power integrity and high-frequency signal transmission quality.

[0044] Based on the same inventive concept, this application discloses a method for manufacturing an adapter device. Figure 6 A schematic flowchart illustrating a method for fabricating an adapter according to an embodiment of this application is shown. Figure 6 As shown, the preparation method includes the following steps: S101. A glass substrate is provided, the glass substrate having a continuous first surface.

[0045] S102. A silicon-based integrated passive device 12 is bonded to the first surface of the glass substrate 11. The silicon-based integrated passive device protrudes from the first surface on the side away from the glass substrate and is in direct contact with the first surface. The thickness of the silicon-based integrated passive device is less than or equal to 30 μm.

[0046] S103. An insulating layer is formed on the first surface, the insulating layer at least covering the surface of the silicon-based integrated passive device, and the maximum thickness of the insulating layer is greater than the thickness of the silicon-based integrated passive device.

[0047] S104. A redistribution layer is formed on the side of the insulating layer away from the glass substrate. The redistribution layer includes a plurality of redistribution patterns, and the redistribution patterns are electrically connected to the silicon-based integrated passive device through conductive paths located inside the insulating layer.

[0048] In specific implementation step 101, the glass substrate 11 is provided as a carrier. Figure 2 This illustration shows a schematic diagram of the structure of a glass substrate provided in a method for fabricating an adapter according to an embodiment of this application. Figure 2 As shown, the glass substrate 11 has a continuous first surface.

[0049] Figure 3 This illustration shows a schematic diagram of the structure for forming a first conductive via in a method for fabricating an adapter according to an embodiment of this application. Figure 3 As shown, at least one first conductive via 15 is formed on the glass substrate 11. The first conductive via 15 penetrates the glass substrate 11 along the thickness direction of the glass substrate 11 and is filled with conductive material.

[0050] When implementing step 102, Figure 4 This illustration shows a schematic diagram of the structure of a bonded silicon-based integrated passive device in a fabrication method of an adapter according to an embodiment of this application. Figure 4As shown, after forming the first conductive via 15, a silicon-based integrated passive device 12 is bonded to the first surface of the glass substrate 11. The silicon-based integrated passive device protrudes from the side of the first surface away from the glass substrate and is in direct contact with the first surface. The thickness of the silicon-based integrated passive device is less than or equal to 30 μm. The orthographic projection of the first conductive via 15 onto the glass substrate 11 does not overlap with the orthographic projection of the silicon-based integrated passive device 12 onto the glass substrate 11.

[0051] When implementing step 103, Figure 5 This illustration shows a schematic diagram of the structure for forming an insulating layer in a method for fabricating an adapter according to an embodiment of this application. Figure 5 As shown, an insulating layer 13 is formed on the first surface, the insulating layer 13 at least covers the surface of the silicon-based integrated passive device 12, and the maximum thickness of the insulating layer 13 is greater than the thickness of the silicon-based integrated passive device.

[0052] When implementing step 104, such as Figure 1 As shown, a redistribution layer 14 is formed on the side of the insulating layer 13 away from the glass substrate 11. The redistribution layer 14 includes multiple redistribution patterns 141, which are electrically connected to the silicon-based integrated passive device 12 through conductive paths located inside the insulating layer 13. Specifically, multiple grooves are formed on the surface of the insulating layer 13 away from the glass substrate 11, and the redistribution patterns 141 are formed in the grooves. The upper surface of the redistribution patterns 141 is made coplanar with the surface of the insulating layer 13 through planarization processes such as chemical mechanical polishing, forming a composite surface with extremely high flatness.

[0053] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0054] In the description of this specification, it should be understood that the terms "center," "thickness," "upper," "lower," "front," "rear," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0055] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0056] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0057] The foregoing application provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0058] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0059] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0060] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0061] The above provides a detailed description of an adapter device and its fabrication method. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. An adapter device, characterized in that, The adapter includes: A glass substrate having a continuous first surface; A silicon-based integrated passive device, wherein the silicon-based integrated passive device protrudes from the first surface on the side away from the glass substrate and is in direct contact with the first surface, and the thickness of the silicon-based integrated passive device is less than or equal to 30 μm; An insulating layer is disposed on the first surface and at least covers the surface of the silicon-based integrated passive device, wherein the maximum thickness of the insulating layer is greater than the thickness of the silicon-based integrated passive device; A redistribution layer is disposed on the side of the insulating layer away from the glass substrate, and includes multiple redistribution patterns. The redistribution patterns are electrically connected to the silicon-based integrated passive device through conductive paths located inside the insulating layer, and the redistribution patterns are used to form electrical connections with active chips.

2. The adapter device according to claim 1, characterized in that, The silicon-based integrated passive device is fixed to the first surface by a bonding layer.

3. The adapter device according to claim 2, characterized in that, The bonding layer includes an anodic bonding layer or a bonding adhesive layer.

4. The adapter device according to claim 1, characterized in that, The orthographic projection of the redistribution pattern on the glass substrate does not overlap with the orthographic projection of the silicon-based integrated passive device on the glass substrate.

5. The adapter device according to claim 1, characterized in that, The glass substrate has at least one first conductive via, which penetrates the glass substrate along its thickness direction and is filled with conductive material.

6. The adapter device according to claim 5, characterized in that, The orthographic projection of the first conductive via on the glass substrate does not overlap with the orthographic projection of the silicon-based integrated passive device on the glass substrate; The orthographic projection of the first conductive via on the glass substrate and the orthographic projection of the redistribution pattern on the glass substrate at least partially overlap, and the redistribution pattern and the first conductive via are electrically connected through conductive vias penetrating the insulating layer.

7. The adapter device according to claim 1, characterized in that, The insulating layer has multiple grooves on the side away from the glass substrate, and the multiple redistribution patterns are arranged one-to-one in the multiple grooves.

8. The adapter device according to claim 7, characterized in that, The redistribution pattern is flush with the surface of the insulating layer on the side away from the glass substrate.

9. The adapter device according to claim 1, characterized in that, The insulating layer is an ABF film layer.

10. A method for manufacturing an adapter, characterized in that, The preparation method includes: A glass substrate is provided, the glass substrate having a continuous first surface; A silicon-based integrated passive device is bonded to the first surface of the glass substrate. The silicon-based integrated passive device protrudes from the side of the first surface away from the glass substrate and is in direct contact with the first surface. The thickness of the silicon-based integrated passive device is less than or equal to 30 μm. An insulating layer is formed on the first surface, the insulating layer at least covering the surface of the silicon-based integrated passive device, and the maximum thickness of the insulating layer is greater than the thickness of the silicon-based integrated passive device; A redistribution layer is formed on the side of the insulating layer away from the glass substrate. The redistribution layer includes a plurality of redistribution patterns, which are electrically connected to the silicon-based integrated passive device through conductive paths located inside the insulating layer.

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