Shift register and driving method thereof, gate driving circuit and display device

Abstract

A shift register, its driving method, gate driving circuit, and display device are disclosed. The shift register includes a control sub-circuit and an output sub-circuit. The control sub-circuit is configured to provide signals to a first node (ND1) and a second node (ND2) under the control of signals from a signal input terminal (IN), a clock signal terminal (CLK), at least one low-level power supply terminal (VN1), at least one high-level power supply terminal (VN2), and a third node (N3). The output sub-circuit is configured to provide a signal (Gn) to a third node (ND3) and at least one output signal terminal under the control of signals from at least one high-level power supply terminal (VN2), at least one low-level power supply terminal (VN1), the first node (ND1), and the second node (ND2).

Description

Shift register and driving method thereof, gate driving circuit and display device

[0001] The present application claims priority to the Chinese patent application with the specification of PCT / CN2024 / 122662, the title of "Shift register and driving method thereof, gate driving circuit and display device", which was filed on September 30, 2024, the content of which should be understood as incorporated by reference into the present application. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, display technology, in particular to a shift register and driving method thereof, a gate driving circuit and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] The present disclosure provides a shift register and driving method thereof, a gate driving circuit and a display device.

[0006] In a first aspect, the present disclosure provides a shift register, comprising: a control sub-circuit and an output sub-circuit;

[0007] The control sub-circuit is electrically connected with a signal input end, a clock signal end, at least one low-level power supply end, at least one high-level power supply end, a first node, a second node and a third node, respectively, and is configured to provide signals to the first node and the second node under the control of signals of the signal input end, the clock signal end, the at least one low-level power supply end, the at least one high-level power supply end and the third node;

[0008] The output sub-circuit is electrically connected with at least one output signal terminal, at least one high-level power supply terminal, at least one low-level power supply terminal, the first node, the second node and the third node respectively, and is configured to provide signals to the third node and the at least one output signal terminal under the control of signals of the at least one high-level power supply terminal, the at least one low-level power supply terminal, the first node and the second node.

[0009] In a second aspect, the disclosure further provides a gate drive circuit, comprising: a plurality of cascaded shift registers as described above.

[0010] In a third aspect, the disclosure further provides a display device, having a display area and a non-display area, wherein the display area is provided with pixel drive circuits arranged in an array, and the non-display area is provided with the gate drive circuit as described above.

[0011] In a fourth aspect, the disclosure further provides a driving method of a shift register, configured to drive the shift register as described above, and the method comprises:

[0012] The control sub-circuit provides signals to the first node and the second node under the control of signals of the signal input terminal, the clock signal terminal, the at least one low-level power supply terminal, the at least one high-level power supply terminal and the third node;

[0013] The output sub-circuit provides signals to the third node and the at least one output signal terminal under the control of signals of the at least one high-level power supply terminal, the at least one low-level power supply terminal, the first node and the second node.

[0014] Other aspects can become apparent from a review of the drawings and detailed description.

[0015] SUMMARY OF DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the technical solutions of the disclosure, and constitute a part of the specification, and are used together with the embodiments of the disclosure to explain the technical solutions of the disclosure, and do not constitute a limitation on the technical solutions of the disclosure.

[0017] Fig. 1 is a structural schematic diagram of a shift register provided by an example embodiment of the disclosure;

[0018] Fig. 2 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0019] Fig. 3 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0020] Fig. 4 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0021] Fig. 5 is an equivalent circuit diagram of a control sub-circuit provided by an example embodiment;

[0022] Figure 6 is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0023] Figure 7 is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0024] Figure 8 is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0025] Figure 9A is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0026] Figure 9B is an equivalent circuit diagram of a control sub-circuit according to an example embodiment;

[0027] Figure 10 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment;

[0028] Figure 11 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment;

[0029] Figure 12 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment;

[0030] Figure 13 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0031] Figure 14 is a timing diagram of the operation of the shift register of Figure 13;

[0032] Figure 15 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0033] Figure 16A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0034] Figure 16B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0035] Figure 17A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0036] Figure 17B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0037] Figure 18 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0038] Figure 19 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0039] Figure 20A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0040] Figure 20B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0041] Figure 21A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0042] Figure 21B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0043] Figure 22 is an equivalent circuit diagram of a shift register according to an example embodiment;

[0044] Figure 23A is an equivalent circuit diagram of a shift register according to an example embodiment;

[0045] Figure 23B is an equivalent circuit diagram of a shift register according to an example embodiment;

[0046] Figure 24 is an equivalent circuit diagram of a reset sub-circuit according to an example embodiment;

[0047] Figure 25 is a structural circuit diagram of a display device according to an example embodiment;

[0048] Figure 26 is an output timing diagram of a multi-stage shift register according to an example embodiment;

[0049] Figure 27 is a structural circuit diagram of a display device according to an example embodiment;

[0050] Figure 28 is an output timing diagram of a multi-stage shift register according to an example embodiment;

[0051] Figure 29 is a structural schematic diagram of a shift register according to an embodiment of the present disclosure;

[0052] Figure 30 is a structural schematic diagram of a shift register according to an example embodiment;

[0053] Figure 31 is a connection schematic diagram of the shift register according to Figure 30;

[0054] Figure 32 is an equivalent circuit diagram of a first node control sub-circuit in the shift register according to Figure 31;

[0055] Figure 33 is an equivalent circuit diagram of a second node control sub-circuit in the shift register according to Figure 31;

[0056] Figure 34 is an equivalent circuit diagram of a first output control sub-circuit in the shift register according to Figure 31;

[0057] Figure 35 is an equivalent circuit diagram of a first output control sub-circuit in the shift register according to Figure 31;

[0058] Figure 36 is an equivalent circuit diagram of a first output control sub-circuit in the shift register according to Figure 31;

[0059] Fig. 37 is an equivalent circuit diagram one of the second output control sub-circuit in the shift register provided in Fig. 31;

[0060] Fig. 38 is an equivalent circuit diagram two of the second output control sub-circuit in the shift register provided in Fig. 31;

[0061] Fig. 39 is an equivalent circuit diagram three of the second output control sub-circuit in the shift register provided in Fig. 31;

[0062] Fig. 40 is an equivalent circuit diagram four of the second output control sub-circuit in the shift register provided in Fig. 31;

[0063] Fig. 41 is an equivalent circuit diagram five of the second output control sub-circuit in the shift register provided in Fig. 31;

[0064] Fig. 42 is a connection diagram two of the shift register provided in Fig. 30;

[0065] Fig. 43 is an equivalent circuit diagram of the first node control sub-circuit in the shift register provided in Fig. 42;

[0066] Fig. 44 is an equivalent circuit diagram of the second node control sub-circuit in the shift register provided in Fig. 42;

[0067] Fig. 45 is an equivalent circuit diagram of the first output control sub-circuit in the shift register provided in Fig. 42;

[0068] Fig. 46 is an equivalent circuit diagram one of the second output control sub-circuit in the shift register provided in Fig. 42;

[0069] Fig. 47 is an equivalent circuit diagram two of the second output control sub-circuit in the shift register provided in Fig. 42;

[0070] Fig. 48 is another structure diagram of the shift register provided in Fig. 29;

[0071] Fig. 49 is an equivalent circuit diagram of the power-on control sub-circuit;

[0072] Fig. 50 is an equivalent circuit diagram one of the shift register provided in Fig. 31;

[0073] Fig. 51 is a driving timing diagram of the shift register provided in Fig. 50 in a refresh frame;

[0074] Fig. 52 is an equivalent circuit diagram two of the shift register provided in Fig. 31;

[0075] Fig. 53 is an equivalent circuit diagram three of the shift register provided in Fig. 31;

[0076] Fig. 54 is an equivalent circuit diagram four of the shift register provided in Fig. 31;

[0077] Figure 55 is an equivalent circuit diagram five of the shift register provided in Figure 31;

[0078] Figure 56 is an equivalent circuit diagram six of the shift register provided in Figure 31;

[0079] Figure 57 is an equivalent circuit diagram seven of the shift register provided in Figure 31;

[0080] Figure 58 is an equivalent circuit diagram eight of the shift register provided in Figure 31;

[0081] Figure 59 is an equivalent circuit diagram nine of the shift register provided in Figure 31;

[0082] Figure 60 is an equivalent circuit diagram ten of the shift register provided in Figure 31;

[0083] Figure 61 is an equivalent circuit diagram one of the shift register provided in Figure 42;

[0084] Figure 62 is an equivalent circuit diagram two of the shift register provided in Figure 42;

[0085] Figure 63 is a flow chart of a driving method of a shift register;

[0086] Figure 64 is a schematic diagram one of a cascade of multiple shift registers;

[0087] Figure 65 is a schematic diagram two of a cascade of multiple shift registers;

[0088] Figure 66 is a schematic diagram of a display device provided in an embodiment of the present disclosure;

[0089] Figure 67 is a signal timing diagram of a clock signal end in a refresh frame and a holding frame.

[0090] Detailed description

[0091] To make the purpose, technical solutions and advantages of the present disclosure clearer, below, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. One of ordinary skill in the art can easily understand that the manner and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0092] The scale of the drawings in this disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted as needed. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in this disclosure are only schematic diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the drawings.

[0093] The ordinal numbers "first", "second", "third" and the like in this specification are used to avoid confusion among components, and are not intended to be limiting in terms of number.

[0094] In this specification, in order to facilitate the description and simplify the description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the positional relationship of the components with reference to the drawings, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on this disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0095] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication between two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0096] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0097] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0098] In the present specification, "electrically connected" includes a case where components are connected through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can transmit and receive an electrical signal between the components to be connected. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0099] In the present specification, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus, a state where the angle is -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus, a state where the angle is 85° or more and 95° or less is also included.

[0100] In the present specification, "film" and "layer" can be replaced with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0101] In the present specification, "disposed in the same layer" means that two (or more) structures are patterned by the same patterning process, and the materials thereof can be the same or different. For example, the materials of the precursors for forming the plurality of structures disposed in the same layer are the same, and the finally formed materials can be the same or different.

[0102] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, and deformation, and the like.

[0103] In the present disclosure, "about" means not strictly limited to the boundary, and allows values within a range of process and measurement errors.

[0104] The current display device uses a cascade driving circuit to generate a scanning signal, but the current cascade driving circuit output mode is relatively single and cannot meet the display requirements.

[0105] FIG. 1 is a structural schematic diagram of a shift register provided by an example embodiment of the present disclosure, as shown in FIG. 1, the shift register can include a control sub-circuit and an output sub-circuit.

[0106] The control sub-circuit is electrically connected with a signal input end IN, a first clock signal end CLK1, a first node N1, and a second node N2, respectively, and is configured to provide a signal to the first node N1 or the second node N2 under the control of signals of the signal input end IN and the first clock signal end CLK1.

[0107] The output sub-circuit is electrically connected with the first node N1, the second node N2, at least one power signal terminal Vn and at least one output signal terminal Gn respectively, and is configured to provide a signal to the at least one output signal terminal Gn under the control of signals of the first node N1, the second node N2 and the at least one power signal terminal Vn; and the length of the effective level signal provided by the output sub-circuit is greater than the length of a period of the signal provided by the first clock signal terminal.

[0108] The effective level signal provided by the output sub-circuit refers to a high level signal output by the shift register in one working process, wherein the working process includes the P1 stage to the P4 stage. In combination with the timing diagram shown in FIG. 14, in the P2 stage and the P3 stage, the high level signal provided by the output sub-circuit to the signal output terminal OUT can be the effective level signal provided by the output sub-circuit. The length of one period of the signal provided by the first clock terminal 1H can be the sum of the length of one high level signal and the length of an adjacent low level signal. The length of the effective level signal shown in FIG. 14 is about 3H, the length of the effective level signal shown in FIG. 26 is about 1.5H, and the length of the effective level signal shown in FIG. 28 is about 3H.

[0109] In an example embodiment, the signal of the first clock signal terminal CLK1 can be a periodic pulse signal.

[0110] In an example embodiment, as shown in FIG. 1, the shift register can further include a reset sub-circuit electrically connected with the reset signal terminal RST, the first node N1 and the seventh power terminal V7 respectively, and configured to provide the signal of the seventh power terminal V7 to the first node N1 under the control of the signal of the reset signal terminal RST.

[0111] In an example embodiment, the signal of the seventh power terminal V7 is a low level signal, and the reset sub-circuit provides the signal of the seventh power terminal V7 to the first node N1 under the control of the signal of the reset signal terminal RST, so as to initialize the first node N1.

[0112] In the embodiments of the present disclosure, the control sub-circuit can provide a signal to the first node or the second node under the control of the signals of the signal input terminal and the first clock signal terminal, the reset sub-circuit can provide the signal of the seventh power terminal to the first node under the control of the signal of the reset signal terminal, and the output sub-circuit can provide a signal to the at least one output signal terminal under the control of the signals of the first node, the second node and the at least one power signal terminal. By providing the signal to the at least one output signal terminal under the control of the signals of the signal input terminal and the first clock signal terminal, the signal output of the shift register is realized, and the positive and negative of the pulse of the signal on the signal input terminal can determine the positive and negative of the pulse of the output signal of the shift register.

[0113] In an example embodiment, the control sub-circuit can comprise a first control sub-circuit, and the first control sub-circuit is further electrically connected with the first power terminal V1 and the second power terminal V2.

[0114] Figure 2 is an equivalent circuit diagram of the control sub-circuit according to an example embodiment. As shown in Figure 2, the first control sub-circuit is further electrically connected with the first power terminal V1 and the second power terminal V2, and the first control sub-circuit can comprise a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3.

[0115] In an example embodiment, as shown in Figure 2, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power terminal V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the third capacitor C3 comprises a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0116] In an example embodiment, as shown in Figure 2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0117] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0118] An example structure of the control sub-circuit is shown in Figure 2. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0119] Fig. 3 is an equivalent circuit diagram of the control sub-circuit according to an example embodiment. As shown in Fig. 3, the first control sub-circuit is also electrically connected with a first power supply end V1 and a second power supply end V2. The first control sub-circuit can include a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9.

[0120] In an example embodiment, as shown in Fig. 3, the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2. The control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1. The control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1. The control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1. The control electrode of the ninth transistor T9 is electrically connected with the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6.

[0121] In an example embodiment, as shown in Fig. 3, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are P-type transistors.

[0122] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0123] An example structure of the control sub-circuit is shown in Fig. 3. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0124] In an example embodiment, the control sub-circuit can include a third control sub-circuit, which is also electrically connected with the first power supply end V1.

[0125] Fig. 4 is an equivalent circuit diagram of the control sub-circuit according to an example embodiment. As shown in Fig. 4, the third control sub-circuit is also electrically connected to the first power supply end V1. The third control sub-circuit can include a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3.

[0126] In an example embodiment, as shown in Fig. 4, the control electrode of the third transistor T3 is electrically connected to the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input end IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2. The control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the first clock signal end CLK1, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4. The control electrode of the sixth transistor T6 is electrically connected to the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply end V1. The control electrode of the seventh transistor T7 is electrically connected to the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first power supply end V1. The control electrode of the eighth transistor T8 is electrically connected to the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1. The third capacitor C3 includes a first plate C31 and a second plate C32. The first plate C31 of the third capacitor is electrically connected to the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected to the third node N3.

[0127] In an example embodiment, as shown in Fig. 4, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0128] In an example embodiment, the signal of the first power supply end V1 is a high-level signal.

[0129] Fig. 4 shows an example structure of the control sub-circuit. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0130] Fig. 5 is an equivalent circuit diagram of the control sub-circuit according to an example embodiment. As shown in Fig. 5, the third control sub-circuit is also electrically connected to the first power supply end V1. The third control sub-circuit can include a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.

[0131] In an example embodiment, as shown in FIG. 5, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal terminal CLK1, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal terminal CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6.

[0132] In an example embodiment, as shown in FIG. 5, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are P-type transistors.

[0133] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal.

[0134] An example structure of the control sub-circuit is shown in FIG. 5. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0135] FIG. 6 is an equivalent circuit diagram of the control sub-circuit provided in an example embodiment. As shown in FIG. 6, the first control sub-circuit is further electrically connected with the first power supply terminal V1 and the second power supply terminal V2, and the first control sub-circuit comprises the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8.

[0136] In an example embodiment, as shown in FIG. 6, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1.

[0137] In an example embodiment, as shown in FIG. 6, the fifth transistor T5 is an N-type transistor, and the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0138] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0139] An example structure of the control sub-circuit is shown in FIG. 6. It is easily understood by those skilled in the art that the implementation of the control sub-circuit is not limited to this.

[0140] In an example embodiment, the control sub-circuit can include a second control sub-circuit, and the second control sub-circuit is also electrically connected to the first power supply terminal V1, the second power supply terminal V2, and the third power supply terminal V3.

[0141] FIG. 7 is an equivalent circuit diagram of the control sub-circuit provided by an example embodiment. As shown in FIG. 7, the second control sub-circuit is also electrically connected to the first power supply terminal V1, the second power supply terminal V2, and the third power supply terminal V3, and the second control sub-circuit includes the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8. The fifth transistor T5 is a double-gate transistor and includes a first control electrode and a second control electrode.

[0142] In an example embodiment, as shown in FIG. 7, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the first control electrode of the fifth transistor T5 is electrically connected with the signal input terminal IN, the second control electrode of the fifth transistor T5 is electrically connected with the third power supply terminal V3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1.

[0143] In an example embodiment, as shown in FIG. 7, the fifth transistor T5 is an N-type transistor, and the third transistor T3, the sixth transistor T6 and the eighth transistor T8 are P-type transistors.

[0144] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, the signal of the second power supply terminal V2 is a low-level signal, and the signal of the third power supply terminal V3 is a low-level signal.

[0145] In an example embodiment, the voltage value of the third power supply terminal V3 is less than or equal to the voltage value of the second power supply terminal V2.

[0146] An example structure of the control sub-circuit is shown in FIG. 7. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0147] FIG. 8 is an equivalent circuit diagram of the control sub-circuit provided in an example embodiment. As shown in FIG. 8, the first control sub-circuit is further electrically connected with the first power supply terminal V1 and the second power supply terminal V2, and the first control sub-circuit can include the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the third capacitor C3.

[0148] In an example embodiment, as shown in FIG. 8, the control electrode of the third transistor T3 is electrically connected with the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply terminal V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input terminal IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply terminal V1; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0149] In an example embodiment, as shown in FIG. 8, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0150] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0151] An example structure of the control sub-circuit is shown in FIG. 8. It is easy for those skilled in the art to understand that the implementation of the control sub-circuit is not limited to this.

[0152] In an example embodiment, the control sub-circuit is further electrically connected with the second clock signal terminal CLK2 and the first power supply terminal V1, and is configured to provide the signal of the first power supply terminal V1 to the second node N2 under the control of the first node N1 and the signal of the second clock signal terminal CLK2.

[0153] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal.

[0154] In the embodiments of the present disclosure, the control sub-circuit can provide the signal of the first power supply terminal V1 to the second node N2 under the control of the first node N1 and the signal of the second clock signal terminal CLK2, thereby increasing the anti-noise capability of the second node N2.

[0155] FIG. 9A is an equivalent circuit diagram of the control sub-circuit provided by an example embodiment, and FIG. 9B is an equivalent circuit diagram of the control sub-circuit provided by an example embodiment. As shown in FIG. 9A and FIG. 9B, the control sub-circuit can further include a tenth transistor T10 and an eleventh transistor T11.

[0156] In an example embodiment, as shown in FIG. 9A, the control electrode of the tenth transistor T10 is electrically connected with the first node N1, the first electrode of the tenth transistor T10 is electrically connected with the first power supply end V1, and the second electrode of the tenth transistor T10 is electrically connected with the seventh node N7; the control electrode of the eleventh transistor T11 is electrically connected with the second clock signal end CLK2, the first electrode of the eleventh transistor T11 is electrically connected with the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected with the second node N2.

[0157] In an example embodiment, as shown in FIG. 9B, the control electrode of the tenth transistor T10 is electrically connected with the second clock signal end CLK2, the first electrode of the tenth transistor T10 is electrically connected with the first node N1, and the second electrode of the tenth transistor T10 is electrically connected with the seventh node N7; the control electrode of the eleventh transistor T11 is electrically connected with the second node N2, the first electrode of the eleventh transistor T11 is electrically connected with the seventh node N7, and the second electrode of the eleventh transistor T11 is electrically connected with the first power supply end V1.

[0158] In an example embodiment, as shown in FIGS. 9A and 9B, the tenth transistor T10 and the eleventh transistor T11 are P-type transistors.

[0159] In the embodiments of the present disclosure, the tenth transistor T10 and the eleventh transistor T11 form the anti-noise circuit, and the anti-noise capability of the second node N2 is increased.

[0160] In the embodiments of the present disclosure, only the anti-noise circuit formed by the tenth transistor T10 and the eleventh transistor T11 based on the control sub-circuit shown in FIG. 2 is exemplified, and the implementation manners of the anti-noise circuit formed by the tenth transistor T10 and the eleventh transistor T11 based on the control sub-circuits shown in FIGS. 3 to 8 are the same as or similar to those, which are not limited and elaborated herein.

[0161] An example structure of the control sub-circuit is shown in FIGS. 9A and 9B. It is easy for those skilled in the art to understand that the implementation manner of the control sub-circuit is not limited thereto.

[0162] In an example embodiment, the at least one power supply signal end can include a fourth power supply end V4 and a fifth power supply end V5, and the at least one output signal end can include a signal output end OUT; an output sub-circuit is configured to provide the signal of the fourth power supply end V4 or the fifth power supply end V5 to the signal output end OUT under the control of the signals of the first node N1 and the second node N2.

[0163] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, and the signal of the fifth power supply end V5 is a low-level signal.

[0164] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0165] FIG. 10 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment. As shown in FIG. 10, the output sub-circuit can include a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1, and a second capacitor C2.

[0166] In an example embodiment, as shown in FIG. 10, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected to the first node N1, and the second plate C22 of the second capacitor is electrically connected to the first power supply terminal V1.

[0167] In an example embodiment, as shown in FIG. 10, the first transistor T1, the second transistor T2, and the fourth transistor T4 are P-type transistors.

[0168] An example structure of the output sub-circuit is shown in FIG. 10. It is easily understood by those skilled in the art that the implementation of the output sub-circuit is not limited thereto.

[0169] In an example embodiment, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, and the output sub-circuit is configured to provide the signal of the sixth power supply terminal V6 or the eighth power supply terminal V8 to the signal output terminal OUT and provide the signal of the fourth power supply terminal V4 or the fifth power supply terminal V5 to the cascade output terminal CR under the control of the signals at the first node N1 and the second node N2.

[0170] In an example embodiment, the signal of the fourth power supply end V4 is a high level signal, the signal of the fifth power supply end V5 is a low level signal, the signal of the sixth power supply end V6 is a high level signal, and the signal of the eighth power supply end V8 is a low level signal.

[0171] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0172] FIG. 11 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment. As shown in FIG. 11, the output sub-circuit can include a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0173] In an example embodiment, as shown in FIG. 11, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0174] In an example embodiment, as shown in FIG. 11, the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0175] An example structure of the output sub-circuit is shown in FIG. 11. It is easy for those skilled in the art to understand that the implementation of the output sub-circuit is not limited thereto.

[0176] Fig. 12 is an equivalent circuit diagram of an output sub-circuit according to an example embodiment. As shown in Fig. 12, the output sub-circuit can include a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0177] In an example embodiment, a control electrode of the first transistor T1 is electrically connected with the first node N1, a first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and a second electrode of the first transistor T1 is electrically connected with the cascade output end CR; a control electrode of the second transistor T2 is electrically connected with the eighth node N8, a first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and a second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; a control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, a first electrode of the fourth transistor T4 is electrically connected with the second node N2, and a second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; a control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, a first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and a second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; a control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, a first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and a second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; a control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, a first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and a second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output end OUT.

[0178] In an example embodiment, as shown in Fig. 12, the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors.

[0179] An example structure of the output sub-circuit is shown in Fig. 12. It is easily understood by those skilled in the art that the implementation of the output sub-circuit is not limited to this.

[0180] Fig. 13 is an equivalent circuit diagram of a shift register according to an example embodiment, as shown in Fig. 13, at least one power signal terminal includes: a fourth power terminal V4 and a fifth power terminal V5, at least one output signal terminal includes: a signal output terminal OUT, the control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8 and a third capacitor C3, the output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0181] In an example embodiment, a control electrode of the first transistor T1 is electrically connected with the first node N1, a first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and a second electrode of the first transistor T1 is electrically connected with the signal output end OUT; a control electrode of the second transistor T2 is electrically connected with the eighth node N8, a first electrode of the second transistor T2 is electrically connected with the signal output end OUT, and a second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; a control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, a first electrode of the third transistor T3 is electrically connected with the signal input end IN, and a second electrode of the third transistor T3 is electrically connected with the second node N2; a control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, a first electrode of the fourth transistor T4 is electrically connected with the second node N2, and a second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; a control electrode of the fifth transistor T5 is electrically connected with the third node N3, a first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and a second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; a control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, a first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and a second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; a control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, a first electrode of the seventh transistor T7 is electrically connected with the third node N3, and a second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; a control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, a first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and a second electrode of the eighth transistor T8 is electrically connected with the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the signal output end OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0182] In an example embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are P-type transistors.

[0183] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0184] In an example embodiment, the signal of the fourth power supply end V4 is a high level signal, and the signal of the fifth power supply end V5 is a low level signal.

[0185] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0186] An example structure of the shift register is shown in FIG. 13. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0187] FIG. 14 is a working timing diagram of the shift register provided in FIG. 13. The working process of the first stage shift register exemplified by FIG. 13 is described below. The signal of the signal input end IN is the signal of the initial signal line STV, and the working process of the shift register can include:

[0188] The first stage P1: the signal of the signal input end IN is a high level signal, the signal of the first clock signal end CLK1 is a high level signal, the third node N3 maintains a high level signal, the second node N2 and the eighth node N8 maintain a low level signal, the fourth node N4 and the first node N1 maintain a high level signal, and the signal output end OUT outputs a low voltage signal.

[0189] The second stage P2: the signal of the signal input end IN is a high level signal, the seventh transistor T7 and the sixth transistor T6 are turned off, and the voltage of the third node N3 changes with the signal of the first clock signal end CLK1; when the signal of the first clock signal end CLK1 is a low level signal, the voltage of the third node N3 is lowered by the signal of the first clock signal end CLK1, the fifth transistor T5 is turned on, the low voltage signal of the second power supply end V2 is written to the fourth node N4, the eighth transistor T8 is turned on, the signals of the fourth node N4 and the first node N1 change from a high level signal to a low level signal, the first transistor T1 is turned on, the high level signal of the fourth power supply end V4 is written to the signal output end OUT, and the signal output end OUT outputs a high level signal. When the signal of the first clock signal end CLK1 is a high level signal, the voltage of the third node N3 is lowered by the signal of the first clock signal end CLK1, and the fifth transistor T5 is turned off; the eighth transistor T8 is turned off, and the first node N1 maintains a low level signal under the action of the second capacitor C2, the first transistor T1 is turned on, the high level signal of the fourth power supply end V4 is written to the signal output end OUT, and the signal output end OUT outputs a high level signal.

[0190] The third stage P3: the signal of the signal input terminal IN is low signal, the seventh transistor T7 and the sixth transistor T6 are turned on respectively, the signal of the first power supply terminal V1 is written into the third node N3 and charges the third capacitor C3, and the signal of the first power supply terminal V1 is written into the fourth node N4; since the first power supply terminal V1 is high signal, the signals of the third node N3 and the fourth node N4 are high signal respectively. The signal of the first clock signal terminal CLK1 is high signal, the eighth transistor T8 is disconnected, the first node N1 maintains low signal under the action of the second capacitor C2, the first transistor T1 is turned on, the high signal of the fourth power supply terminal V4 is written into the signal output terminal OUT, and the signal output terminal OUT outputs high signal.

[0191] The fourth stage P4: the signal of the signal input terminal IN is low signal, the sixth transistor T6 and the seventh transistor T7 are turned on, the signals of the third node N3 and the fourth node N4 are high signal respectively. The signal of the first clock signal terminal CLK1 is low signal, the eighth transistor T8 is turned on, the high signal of the fourth node N4 is written into the first node N1, the first node N1 changes from low signal to high signal, and the first transistor T1 is disconnected. The third transistor T3 is turned on, the fourth transistor T4 is turned on since the fifth power supply terminal V5 is low signal, and the low signal of the signal input terminal IN is written into the second node N2 and the eighth node N8 respectively. The eighth node N8 is low signal, the second transistor T2 is turned on, and the signal of the fifth power supply terminal V5 is written into the signal output terminal OUT; since the fifth power supply terminal V5 is low signal, the signal output terminal OUT outputs low signal. Since the signal output terminal OUT changes from high signal to low signal, the eighth node N8 is continuously pulled down in this stage by the coupling effect of the first capacitor C1, the voltage is lower than the voltage of the fifth power supply terminal V5, the fourth transistor T4 enters the cut-off state at this time, the low voltage of the eighth node N8 is maintained, so as to ensure that the second transistor T2 is continuously opened and the signal output terminal OUT outputs no step.

[0192] The working processes of the shift registers in the following embodiments are similar to the above, and the following embodiments will not be described in detail.

[0193] FIG. 15 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment, as shown in FIG. 15, the at least one power supply signal terminal includes: the fourth power supply terminal V4 and the fifth power supply terminal V5, the at least one output signal terminal includes: the signal output terminal OUT, the control sub-circuit includes: the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9, and the output sub-circuit includes: the first transistor T1, the second transistor T2, the fourth transistor T4, the first capacitor C1 and the second capacitor C2.

[0194] In an example embodiment, as shown in FIG. 15, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the signal output end OUT; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the signal output end OUT, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the signal output end OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0195] In an example embodiment, as shown in FIG. 15, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are P-type transistors.

[0196] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0197] In an example embodiment, the signal of the fourth power supply terminal V4 is a high level signal, and the signal of the fifth power supply terminal V5 is a low level signal.

[0198] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0199] An example structure of the shift register is shown in FIG. 15. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0200] FIG. 16A is an equivalent circuit diagram of the shift register provided by an example embodiment. As shown in FIG. 16A, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0201] In an example embodiment, as shown in FIG. 16A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0202] In an example embodiment, as shown in FIG. 16A, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0203] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0204] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, the signal of the sixth power terminal V6 is a high-level signal, and the signal of the eighth power terminal V8 is a low-level signal.

[0205] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0206] An example structure of the shift register is shown in FIG. 16A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0207] FIG. 16B is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 16B, the at least one power signal terminal includes the fourth power terminal V4, the fifth power terminal V5, the sixth power terminal V6, and the eighth power terminal V8, the at least one output signal terminal includes the signal output terminal OUT and the cascade output terminal CR, the control sub-circuit includes the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the third capacitor C3, and the output sub-circuit includes the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the first capacitor C1, the second capacitor C2, and the fourth capacitor C4.

[0208] In an example embodiment, as shown in FIG. 16B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 comprises a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 comprises a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.The third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal terminal CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output terminal OUT.

[0209] In an example embodiment, as shown in FIG. 16B, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0210] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0211] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, the signal of the sixth power terminal V6 is a high-level signal, and the signal of the eighth power terminal V8 is a low-level signal.

[0212] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0213] An example structure of the shift register is shown in FIG. 16B. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0214] FIG. 17A is an equivalent circuit diagram of a shift register provided in an example embodiment. As shown in FIG. 17A, at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6 and an eighth power terminal V8, at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, a control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9, and an output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1 and a second capacitor C2.

[0215] In an example embodiment, as shown in FIG. 17A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the fifth power supply end V5 of the second transistor T2 is electrically connected; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0216] In an example embodiment, as shown in FIG. 17A, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0217] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0218] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, the signal of the sixth power terminal V6 is a high-level signal, and the signal of the eighth power terminal V8 is a low-level signal.

[0219] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0220] An example structure of the shift register is shown in FIG. 17A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0221] FIG. 17B is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 17B, the at least one power signal terminal includes the fourth power terminal V4, the fifth power terminal V5, the sixth power terminal V6, and the eighth power terminal V8, the at least one output signal terminal includes the signal output terminal OUT and the cascade output terminal CR, the control sub-circuit includes the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9, and the output sub-circuit includes the first transistor T1, the second transistor T2, the fourth transistor T4, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the first capacitor C1, the second capacitor C2, and the fourth capacitor C4.

[0222] In an example embodiment, as shown in FIG. 17B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the fifth power supply end V5 of the second transistor T2 is electrically connected; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the fifth node N5, the first electrode of the fifth transistor T5 is electrically connected with the first clock signal end CLK1 or the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T4 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the ninth transistor T9 is electrically connected with the first clock signal end CLK1, the first electrode of the ninth transistor T9 is electrically connected with the fifth node N5, and the second electrode of the ninth transistor T9 is electrically connected with the sixth node N6; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR.The second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power terminal V4. The fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output terminal OUT.

[0223] In an example embodiment, as shown in FIG. 17B, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0224] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, and the signal of the second power terminal V2 is a low-level signal.

[0225] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, the signal of the fifth power terminal V5 is a low-level signal, the signal of the sixth power terminal V6 is a high-level signal, and the signal of the eighth power terminal V8 is a low-level signal.

[0226] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0227] An example structure of the shift register is shown in FIG. 17B. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0228] FIG. 18 is an equivalent circuit diagram of a shift register provided in an example embodiment. As shown in FIG. 18, at least one power signal terminal includes a fourth power terminal V4 and a fifth power terminal V5, at least one output signal terminal includes a signal output terminal OUT, a control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8, and an output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0229] In an example embodiment, as shown in FIG. 18, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power supply terminal V4, and the second electrode of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the fifth power supply terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power supply terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the first electrode of the fifth transistor T5 is electrically connected to the second power supply terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power supply terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate of the second capacitor is electrically connected to the first node N1, and the second plate of the second capacitor is electrically connected to the fourth power supply terminal V4.

[0230] In an example embodiment, as shown in FIG. 18, the fifth transistor T5 is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are P-type transistors.

[0231] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0232] In an example embodiment, the signal of the fourth power supply terminal V4 is a high-level signal, and the signal of the fifth power supply terminal V5 is a low-level signal.

[0233] An example structure of the shift register is shown in FIG. 18. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0234] Figure 19 is an equivalent circuit diagram of a shift register according to an example embodiment. As shown in Figure 19, the at least one power signal terminal includes a fourth power terminal V4 and a fifth power terminal V5, the at least one output signal terminal includes a signal output terminal OUT, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0235] In an example embodiment, as shown in Figure 19, the control electrode of the first transistor T1 is electrically connected to the first node N1, the first electrode of the first transistor T1 is electrically connected to the fourth power terminal V4, and the second electrode of the first transistor T1 is electrically connected to the signal output terminal OUT; the control electrode of the second transistor T2 is electrically connected to the eighth node N8, the first electrode of the second transistor T2 is electrically connected to the signal output terminal OUT, and the second electrode of the second transistor T2 is electrically connected to the fifth power terminal V5; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CLK1, the first electrode of the third transistor T3 is electrically connected to the signal input terminal IN, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the fifth power terminal V5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the eighth node N8; the fifth transistor T5 is a double-gate transistor and includes a first control electrode and a second control electrode, the first control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the second control electrode of the fifth transistor T5 is electrically connected to the third power terminal V3, the first electrode of the fifth transistor T5 is electrically connected to the second power terminal V2, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the signal input terminal IN, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the first power terminal V1; the control electrode of the eighth transistor T8 is electrically connected to the first clock signal terminal CLK1, the first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected to the eighth node N8, and the second plate C12 of the first capacitor is electrically connected to the signal output terminal OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate of the second capacitor is electrically connected to the first node N1, and the second plate of the second capacitor is electrically connected to the fourth power terminal V4.

[0236] In an example embodiment, as shown in FIG. 18, the fifth transistor T5 is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6 and the eighth transistor T8 are P-type transistors.

[0237] In an example embodiment, the signal of the first power terminal V1 is a high-level signal, the signal of the second power terminal V2 is a low-level signal, and the signal of the third power terminal V3 is a low-level signal.

[0238] In an example embodiment, the voltage value of the third power terminal V3 is less than or equal to the voltage value of the second power terminal V2.

[0239] In an example embodiment, the signal of the fourth power terminal V4 is a high-level signal, and the signal of the fifth power terminal V5 is a low-level signal.

[0240] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0241] An example structure of the shift register is shown in FIG. 19. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0242] FIG. 20A is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 20A, the at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6 and an eighth power terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1 and a second capacitor C2.

[0243] In an example embodiment, as shown in FIG. 20A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0244] In an example embodiment, as shown in FIG. 20A, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0245] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0246] In an example embodiment, the signal of the fourth power supply terminal V4 is a high level signal, the signal of the fifth power supply terminal V5 is a low level signal, the signal of the sixth power supply terminal V6 is a high level signal, and the signal of the eighth power supply terminal V8 is a low level signal.

[0247] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0248] An example structure of the shift register is shown in FIG. 20A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0249] FIG. 20B is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 20B, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0250] In an example embodiment, as shown in FIG. 20B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output end OUT.

[0251] In an example embodiment, as shown in FIG. 20B, the fifth transistor is an N-type transistor, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0252] In an example embodiment, the signal of the first power supply end V1 is a high level signal, and the signal of the second power supply end V2 is a low level signal.

[0253] In an example embodiment, the signal of the fourth power supply end V4 is a high level signal, the signal of the fifth power supply end V5 is a low level signal, the signal of the sixth power supply end V6 is a high level signal, and the signal of the eighth power supply end V8 is a low level signal.

[0254] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0255] An example structure of the shift register is shown in FIG. 20B. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0256] FIG. 21A is an equivalent circuit diagram of a shift register provided by an example embodiment. As shown in FIG. 21A, at least one power supply signal end includes: a fourth power supply end V4, a fifth power supply end V5, a sixth power supply end V6 and an eighth power supply end V8, at least one output signal end includes: a signal output end OUT and a cascade output end CR, a control sub-circuit includes: a third transistor T3, a fifth transistor T5, a sixth transistor T6 and an eighth transistor T8, and an output sub-circuit includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1 and a second capacitor C2.

[0257] In an example embodiment, as shown in FIG. 21A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the fifth transistor T5 is a double-gate transistor, the first control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the second control electrode of the fifth transistor T5 is electrically connected with the third power supply end V3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4.

[0258] In an example embodiment, as shown in FIG. 21A, the fifth transistor is an N-type transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0259] In an example embodiment, the signal of the first power terminal V1 is a high level signal, the signal of the second power terminal V2 is a low level signal, and the signal of the third power terminal V3 is a low level signal.

[0260] In an example embodiment, the voltage of the third power terminal V3 is less than or equal to the voltage of the second power terminal V2.

[0261] In an example embodiment, the signal of the fourth power terminal V4 is a high level signal, the signal of the fifth power terminal V5 is a low level signal, the signal of the sixth power terminal V6 is a high level signal, and the signal of the eighth power terminal V8 is a low level signal.

[0262] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0263] An example structure of the shift register is shown in FIG. 21A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0264] FIG. 21B is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 21B, the at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6, and an eighth power terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, and an eighth transistor T8, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0265] In an example embodiment, as shown in FIG. 21B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the fifth transistor T5 is a double-gate transistor, the first control electrode of the fifth transistor T5 is electrically connected with the signal input end IN, the second control electrode of the fifth transistor T5 is electrically connected with the third power supply end V3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected with the signal input end IN, the first electrode of the sixth transistor T6 is electrically connected with the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the eighth transistor T8 is electrically connected with the first clock signal end CLK1, the first electrode of the eighth transistor T8 is electrically connected with the fourth node N4, and the second electrode of the eighth transistor T8 is electrically connected with the first node N1; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the fourth capacitor C4 includes a first plate C41 and a second plate C42, the first plate C41 of the fourth capacitor is electrically connected with the ninth node N9, and the second plate C42 of the fourth capacitor is electrically connected with the signal output end OUT.

[0266] In an example embodiment, as shown in FIG. 21B, the fifth transistor is an N-type transistor, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the twelfth transistor T12, the thirteenth transistor T13 and the fourteenth transistor T14 are P-type transistors.

[0267] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, the signal of the second power supply end V2 is a low-level signal, and the signal of the third power supply end V3 is a low-level signal.

[0268] In an example embodiment, the voltage value of the third power supply end V3 is less than or equal to the voltage value of the second power supply end V2.

[0269] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, the signal of the fifth power supply end V5 is a low-level signal, the signal of the sixth power supply end V6 is a high-level signal, and the signal of the eighth power supply end V8 is a low-level signal.

[0270] In an example embodiment, the fourth power supply end V4 and the first power supply end V1 can be the same signal end, and the fifth power supply end V5 and the second power supply end V2 can be the same signal end.

[0271] An example structure of the shift register is shown in FIG. 21B. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0272] FIG. 22 is an equivalent circuit diagram of a shift register provided by an example embodiment. As shown in FIG. 22, the at least one power supply signal end includes a fourth power supply end V4 and a fifth power supply end V5, the at least one output signal end includes a signal output end OUT, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a first capacitor C1 and a second capacitor C2.

[0273] In an example embodiment, as shown in FIG. 22, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the signal output end OUT; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the signal output end OUT, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the signal output end OUT; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0274] In an example embodiment, as shown in FIG. 22, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0275] In an example embodiment, the signal of the first power supply end V1 is a high-level signal, and the signal of the second power supply end V2 is a low-level signal.

[0276] In an example embodiment, the signal of the fourth power supply end V4 is a high-level signal, and the signal of the fifth power supply end V5 is a low-level signal.

[0277] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0278] An example structure of the shift register is shown in FIG. 22. It is easily understood by those skilled in the art that the implementation of the shift register is not limited to this.

[0279] FIG. 23A is an equivalent circuit diagram of the shift register provided in an example embodiment. As shown in FIG. 23A, the at least one power supply signal terminal includes a fourth power supply terminal V4, a fifth power supply terminal V5, a sixth power supply terminal V6, and an eighth power supply terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2.

[0280] In an example embodiment, as shown in FIG. 23A, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the twelfth transistor T12 is electrically connected with the first node N1, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the eighth node N8, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the first capacitor C1 includes a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 includes a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 includes a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.

[0281] In an example embodiment, as shown in FIG. 23A, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the twelfth transistor T12, and the thirteenth transistor T13 are P-type transistors.

[0282] In an example embodiment, the signal of the first power terminal V1 is a high level signal, and the signal of the second power terminal V2 is a low level signal.

[0283] In an example embodiment, the signal of the fourth power terminal V4 is a high level signal, the signal of the fifth power terminal V5 is a low level signal, the signal of the sixth power terminal V6 is a high level signal, and the signal of the eighth power terminal V8 is a low level signal.

[0284] In an example embodiment, the fourth power terminal V4 and the first power terminal V1 can be the same signal terminal, and the fifth power terminal V5 and the second power terminal V2 can be the same signal terminal.

[0285] An example structure of the shift register is shown in FIG. 23A. It is easy for those skilled in the art to understand that the implementation of the shift register is not limited to this.

[0286] FIG. 23B is an equivalent circuit diagram of the shift register provided by an example embodiment. As shown in FIG. 23B, the at least one power signal terminal includes a fourth power terminal V4, a fifth power terminal V5, a sixth power terminal V6, and an eighth power terminal V8, the at least one output signal terminal includes a signal output terminal OUT and a cascade output terminal CR, the control sub-circuit includes a third transistor T3, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3, and the output sub-circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4.

[0287] In an example embodiment, as shown in FIG. 23B, the control electrode of the first transistor T1 is electrically connected with the first node N1, the first electrode of the first transistor T1 is electrically connected with the fourth power supply end V4, and the second electrode of the first transistor T1 is electrically connected with the cascade output end CR; the control electrode of the second transistor T2 is electrically connected with the eighth node N8, the first electrode of the second transistor T2 is electrically connected with the cascade output end CR, and the second electrode of the second transistor T2 is electrically connected with the fifth power supply end V5; the control electrode of the third transistor T3 is electrically connected with the first clock signal end CLK1, the first electrode of the third transistor T3 is electrically connected with the signal input end IN, and the second electrode of the third transistor T3 is electrically connected with the second node N2; the control electrode of the fourth transistor T4 is electrically connected with the fifth power supply end V5, the first electrode of the fourth transistor T4 is electrically connected with the second node N2, and the second electrode of the fourth transistor T4 is electrically connected with the eighth node N8; the control electrode of the fifth transistor T5 is electrically connected with the third node N3, the first electrode of the fifth transistor T5 is electrically connected with the second power supply end V2, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1; the control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first node N1, and the second electrode of the sixth transistor T6 is electrically connected with the first power supply end V1; the control electrode of the seventh transistor T7 is electrically connected with the signal input end IN, the first electrode of the seventh transistor T7 is electrically connected with the third node N3, and the second electrode of the seventh transistor T7 is electrically connected with the first power supply end V1; the control electrode of the twelfth transistor T12 is electrically connected with the ninth node N9, the first electrode of the twelfth transistor T12 is electrically connected with the sixth power supply end V6, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT; the control electrode of the thirteenth transistor T13 is electrically connected with the second node N2, the first electrode of the thirteenth transistor T13 is electrically connected with the signal output end OUT, and the second electrode of the thirteenth transistor T13 is electrically connected with the eighth power supply end V8; the control electrode of the fourteenth transistor T14 is electrically connected with the fifth power supply end V5, the first electrode of the fourteenth transistor T14 is electrically connected with the first node N1, and the second electrode of the fourteenth transistor T14 is electrically connected with the ninth node N9; the first capacitor C1 comprises a first plate C11 and a second plate C12, the first plate C11 of the first capacitor is electrically connected with the eighth node N8, and the second plate C12 of the first capacitor is electrically connected with the cascade output end CR; the second capacitor C2 comprises a first plate C21 and a second plate C22, the first plate C21 of the second capacitor is electrically connected with the first node N1, and the second plate C22 of the second capacitor is electrically connected with the fourth power supply end V4; the third capacitor C3 comprises a first plate C31 and a second plate C32, the first plate C31 of the third capacitor is electrically connected with the first clock signal end CLK1, and the second plate C32 of the third capacitor is electrically connected with the third node N3.The fourth capacitor C4 includes a first plate C41 and a second plate C42. The first plate C41 of the fourth capacitor is electrically connected to the ninth node N9. The second plate C42 of the fourth capacitor is electrically connected to the signal output terminal OUT.

[0288] In an example embodiment, as shown in FIG. 23B, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are P-type transistors.

[0289] In an example embodiment, the signal of the first power supply terminal V1 is a high-level signal, and the signal of the second power supply terminal V2 is a low-level signal.

[0290] In an example embodiment, the signal of the fourth power supply terminal V4 is a high-level signal, the signal of the fifth power supply terminal V5 is a low-level signal, the signal of the sixth power supply terminal V6 is a high-level signal, and the signal of the eighth power supply terminal V8 is a low-level signal.

[0291] In an example embodiment, the fourth power supply terminal V4 and the first power supply terminal V1 can be the same signal terminal, and the fifth power supply terminal V5 and the second power supply terminal V2 can be the same signal terminal.

[0292] An example structure of the shift register is shown in FIG. 23B. It is easily understood by those skilled in the art that the implementation of the shift register is not limited to this.

[0293] FIG. 24 is an equivalent circuit diagram of a reset sub-circuit provided in an example embodiment. As shown in FIG. 24, the reset sub-circuit includes a fifteenth transistor T15.

[0294] In an example embodiment, as shown in FIG. 24, the control electrode of the fifteenth transistor T15 is electrically connected to the reset signal terminal RST. The first electrode of the fifteenth transistor T15 is electrically connected to the seventh power supply terminal V7. The second electrode of the fifteenth transistor T15 is electrically connected to the first node N1.

[0295] In an example embodiment, the signal of the seventh power supply terminal V7 is a low-level signal.

[0296] An example structure of the reset sub-circuit is shown in FIG. 24. It is easily understood by those skilled in the art that the implementation of the reset sub-circuit is not limited to this.

[0297] The disclosure also provides a gate drive circuit, including: a plurality of cascaded shift registers, at least one output signal terminal of at least one level of the shift registers includes: a signal output terminal;

[0298] The signal output end of the i-th stage shift register is electrically connected with the signal input end of the i+L-th stage shift register, 1≤i≤M-L, M is the total stage number of the shift register, M≥1, and L is a positive integer greater than or equal to 1.

[0299] The shift register is the shift register provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here again.

[0300] The display device provided by the embodiment of the present disclosure also includes a display area and a non-display area, the display area is provided with pixel driving circuits arranged in an array, the non-display area is provided with a gate driving circuit, the pixel driving circuit includes at least one light-emitting control transistor, and at least one light-emitting control transistor in at least one row of pixel driving circuits is electrically connected with at least one stage of shift registers in the gate driving circuit.

[0301] The gate driving circuit is the gate driving circuit provided by any one of the foregoing embodiments, and has similar implementation principles and implementation effects, which will not be described here again.

[0302] FIG. 25 is a structural circuit diagram of a display device provided by an exemplary embodiment, as shown in FIG. 25, the control sub-circuit is electrically connected with the signal input end IN and the first clock signal end CLK1 respectively, the display device further includes an initial signal line STV, a first clock signal line CK1 and a second clock signal line CK2, the signal input end IN of at least one stage of shift registers is electrically connected with the initial signal line STV, the first clock signal end CLK1 is electrically connected with one of the first clock signal line CK1 and the second clock signal line CK2, and the signal lines connected with the first clock signal ends CLK1 of adjacent shift registers are different.

[0303] FIG. 26 is an output timing diagram of a multi-stage shift register provided by an exemplary embodiment, as shown in FIG. 26, the signal input end IN of the first stage shift register is electrically connected with the initial signal line STV, the signal output end of the i-th stage shift register is electrically connected with the signal input end of the i+1-th stage shift register, the first clock signal end CLK1 of at least one stage of shift registers is electrically connected with one of the first clock signal line CK1 and the second clock signal line CK2, and the timing diagram shown in FIG. 26 can be output, so as to realize the shift of the output signal.

[0304] Fig. 27 is a structural circuit diagram of a display device according to an example embodiment. As shown in Fig. 27, the control sub-circuit is electrically connected to the signal input end IN and the first clock signal end CLK1 respectively. The display device further comprises an initial signal line STV, a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4. The signal input end IN of the at least one stage of shift register is electrically connected to the initial signal line STV. The first clock signal end CLK1 of the 4M-3 stage of shift register is electrically connected to the first clock signal line CK1. The first clock signal end CLK1 of the 4M-2 stage of shift register is electrically connected to the second clock signal line CK2. The first clock signal end CLK1 of the 4M-1 stage of shift register is electrically connected to the third clock signal line CK3. The first clock signal end CLK1 of the 4M stage of shift register is electrically connected to the fourth clock signal line CK4. Wherein, M is the total number of stages of shift register, and M≥1.

[0305] Fig. 28 is an output timing diagram of a multi-stage shift register according to an example embodiment. As shown in Fig. 28, the signal input end IN of the first stage of shift register is electrically connected to the initial signal line STV. The signal output end of the i stage of shift register is electrically connected to the signal input end of the i+2 stage of shift register. The first clock signal end CLK1 of the 4M-3 stage of shift register is electrically connected to the first clock signal line CK1. The first clock signal end CLK1 of the 4M-2 stage of shift register is electrically connected to the second clock signal line CK2. The first clock signal end CLK1 of the 4M-1 stage of shift register is electrically connected to the third clock signal line CK3. The first clock signal end CLK1 of the 4M stage of shift register is electrically connected to the fourth clock signal line CK4. The timing diagram shown in Fig. 28 can be output, and the shift of the output signal is realized.

[0306] The disclosure further provides a driving method of a shift register configured to drive the shift register. The driving method of the shift register can comprise:

[0307] The control sub-circuit provides signals to the first node or the second node under the control of signals at the signal input end and the first clock signal end.

[0308] The output sub-circuit provides signals to the at least one output signal end under the control of signals at the first node, the second node, and the at least one power signal end.

[0309] The duration of the valid level signal provided by the output sub-circuit is greater than the period of the signal provided by the first clock signal end.

[0310] The shift register is the shift register provided by any one of the preceding example embodiments, and has similar principles and effects, which will not be described here again.

[0311] Figure 29 is a structural schematic diagram of a shift register provided by an embodiment of the present disclosure. As shown in Figure 29, the shift register provided by the embodiment of the present disclosure can include a control sub-circuit and an output sub-circuit.

[0312] As shown in Figure 29, the control sub-circuit is electrically connected with the signal input end IN, the clock signal end CK, at least one low-level power supply end VN1, at least one high-level power supply end VN2, the first node ND1, the second node ND2, and the third node ND3, respectively, and is configured to provide signals to the first node ND1 and the second node ND2 under the control of signals of the signal input end IN, the clock signal end CK, at least one low-level power supply end VN1, at least one high-level power supply end VN2, and the third node ND3; the output sub-circuit is electrically connected with at least one output signal end Gn, at least one high-level power supply end VN2, at least one low-level power supply end VN1, the first node ND1, the second node ND2, and the third node ND3, respectively, and is configured to provide signals to the third node ND3 and at least one output signal end Gn under the control of signals of at least one high-level power supply end VN2, at least one low-level power supply end VN1, the first node ND1, and the second node ND2.

[0313] Figure 30 is a structural schematic diagram of a shift register provided by an exemplary embodiment. As shown in Figure 30, the control sub-circuit includes a first node control sub-circuit and a second node control sub-circuit, and the output sub-circuit includes a first output control sub-circuit and a second output control sub-circuit.

[0314] As shown in Figure 30, the first node control sub-circuit is electrically connected with the signal input end IN, the clock signal end CK, at least one high-level power supply end VN2, the first node ND1, and the second node ND2, respectively, and is configured to provide signals of at least one high-level power supply end VN2 to the first node ND1 and provide signals of the signal input end IN to the second node ND2 under the control of signals of at least one of the signal input end IN and the clock signal end CK; the second node control sub-circuit is electrically connected with at least one low-level power supply end VN1, the first node ND1, and the third node ND3, respectively, and is configured to provide signals of at least one low-level power supply end VN1 to the first node ND1 under the control of signals of the third node ND3.

[0315] As shown in FIG. 30, the first output control sub-circuit is electrically connected with at least one of the at least one high-level power supply end VN2 and the at least one low-level power supply end VN1, the second node ND2 and the third node ND3, and is configured to provide the signal of the second node ND2 to the third node ND3 under the control of the signal of at least one of the at least one high-level power supply end VN2 and the at least one low-level power supply end VN1; and the second output control sub-circuit is electrically connected with the at least one high-level power supply end VN2, the at least one low-level power supply end VN1, the at least one output signal end Gn, the first node ND1 and the third node ND3, and is configured to provide the signal of at least one of the at least one high-level power supply end VN2 and the at least one low-level power supply end VN2 to the at least one output signal end Gn under the control of the signals of the first node ND1 and the third node ND3.

[0316] As shown in FIG. 31, the at least one output signal end Gn includes a cascade output end CR and a signal output end OUT, the at least one high-level power supply end connected with the output sub-circuit includes a first high-level power supply end VH1 and a second high-level power supply end VH2, the at least one low-level power supply end connected with the output sub-circuit includes a first low-level power supply end VL1 and a second low-level power supply end VL2, the at least one high-level power supply end connected with the control sub-circuit includes the second high-level power supply end VH2, and the at least one low-level power supply end connected with the control sub-circuit includes at least one of the first low-level power supply end VL1 and the second low-level power supply end VL2.

[0317] The at least one output signal end Gn in the present disclosure includes a cascade output end CR and a signal output end OUT, wherein the cascade output end CR can provide a cascade signal to the signal input end of the remaining stage shift register, and the signal output end OUT can provide a driving signal to the pixel driving circuit located in the display area. The present disclosure outputs the cascade signal and the driving signal by using different signal ends, which not only facilitates the transmission of the cascade signal, but also reduces the load of the signal output end, and can make the shift register applicable to the display product capable of realizing high-frequency driving.

[0318] Fig. 32 is an equivalent circuit diagram of the first node control sub-circuit in the shift register provided in Fig. 31. As shown in Fig. 32, the first node control sub-circuit comprises a first transistor T1, a second transistor T2 and a third transistor T3. Wherein, the control electrode of the first transistor T1 is electrically connected with the clock signal end CK, the first electrode of the first transistor T1 is electrically connected with the signal input end IN, and the second electrode of the first transistor T1 is electrically connected with the second node ND2; the control electrode of the second transistor T2 is electrically connected with the signal input end IN, the first electrode of the second transistor T2 is electrically connected with the second high-level power supply end VH2, and the second electrode of the second transistor T2 is electrically connected with the fourth node ND4; the control electrode of the third transistor T3 is electrically connected with the clock signal end CK, the first electrode of the third transistor T3 is electrically connected with the fourth node ND4, and the second electrode of the third transistor T3 is electrically connected with the first node ND1.

[0319] In the example embodiment, at least one of the first transistor T1 to the third transistor T3 is a P-type transistor.

[0320] Fig. 33 is an equivalent circuit diagram of the second node control sub-circuit in the shift register provided in Fig. 31. As shown in Fig. 33, the second node control sub-circuit comprises a fourth transistor T4. The fourth transistor T4 is a single-gate structure, or the control electrode of the fourth transistor T4 comprises a first control electrode and a second control electrode, and the shift register is arranged on a substrate, and the second control electrode is arranged on the side of the first control electrode close to the substrate. Wherein, when the fourth transistor T4 is a single-gate structure, the control electrode of the fourth transistor T4 is electrically connected with the third node ND3, the first electrode of the fourth transistor T4 is electrically connected with one of the first low-level power supply end VL1 and the second low-level power supply end VL2, and the second electrode of the fourth transistor T4 is electrically connected with the first node ND1. When the control electrode of the fourth transistor T4 comprises a first control electrode and a second control electrode, the first control electrode of the fourth transistor T4 is electrically connected with the third node ND3, the second control electrode of the fourth transistor T4 is electrically connected with one of the first low-level power supply end VL1, the second low-level power supply end VL2 and the third low-level power supply end VL3, the first electrode of the fourth transistor T4 is electrically connected with one of the first low-level power supply end VL1 and the second low-level power supply end VL2, and the second electrode of the fourth transistor T4 is electrically connected with the first node ND1.

[0321] When the control electrode of the fourth transistor T4 comprises a first control electrode and a second control electrode, the present disclosure can ensure the threshold voltage stability of the fourth transistor T4 and reduce the threshold voltage shift of the fourth transistor after being biased by electrically connecting the first control electrode and the second control electrode of the control electrode of the fourth transistor with one of the first low-level power supply end VL1, the second low-level power supply end VL2 and the third low-level power supply end VL3.

[0322] In an example embodiment, the fourth transistor T4 is an N-type transistor. Since the first pole of the fourth transistor T4 is connected to the low-level power supply end, the present disclosure sets the fourth transistor as an N-type transistor to reduce the power consumption of the shift register.

[0323] In an example embodiment, the voltage value of the signal of the third low-level power supply end VL3 is higher than the voltage value of the signal of at least one signal end of the first low-level power supply end VL1 and the second low-level power supply end VL2.

[0324] In an example embodiment, FIG. 34 is an equivalent circuit diagram one of the first output control sub-circuit in the shift register provided in FIG. 31. As shown in FIG. 34, the first output control sub-circuit includes: a fifth transistor T5. Wherein, the control pole of the fifth transistor T5 is electrically connected with one of the first low-level power supply end VL1 and the second low-level power supply end VL2, the first pole of the fifth transistor T5 is electrically connected with the second node ND2, and the second pole of the fifth transistor T5 is electrically connected with the third node ND3.

[0325] In an example embodiment, FIG. 35 is an equivalent circuit diagram two of the first output control sub-circuit in the shift register provided in FIG. 31. As shown in FIG. 35, the first output control sub-circuit includes: a fifth transistor T5. Wherein, the control pole of the fifth transistor T5 is electrically connected with the third low-level power supply end VL3, the first pole of the fifth transistor T5 is electrically connected with the second node ND2, and the second pole of the fifth transistor T5 is electrically connected with the third node ND3.

[0326] In an example embodiment, the difference between the voltage value of the signal of the third low-level power supply end VL3 and the voltage value of the signal of the second low-level power supply end VL2 is greater than the threshold voltage of the fifth transistor.

[0327] In an example embodiment, since the signal input by the signal input end IN in part of the time period is the signal of the second low-level power supply end VL2, the control pole of the fifth transistor T5 is electrically connected with the third low-level power supply end VL3, and the difference between the voltage value of the signal of the third low-level power supply end VL3 and the voltage value of the signal of the second low-level power supply end VL2 is greater than the threshold voltage of the fifth transistor, so that when the signal of the first pole of the fifth transistor is the signal of at least one signal end of the second low-level power supply end VL2, the fifth transistor T5 is disconnected, which can improve the leakage of the fifth transistor T5, improve the stability of the signal of the second node N2, improve the display abnormality and flicker problem of the display product when displaying at a low refresh rate, and improve the display effect of the display product.

[0328] In the shift register provided in FIG. 34 and FIG. 35, the fifth transistor T5 is a P-type transistor in the exemplary embodiment. Since the control electrode of the fifth transistor T5 is electrically connected with one of the first low-level power supply end VL1 and the second low-level power supply end VL2, the fifth transistor T5 is always in the on state.

[0329] In the shift register provided in FIG. 36, the fifth transistor T5 is an N-type transistor in the exemplary embodiment. The fifth transistor T5 being an N-type transistor can reduce the leakage current, improve the display abnormality and flicker problem of the display product when displaying at a low refresh rate, and improve the display effect of the display product.

[0330] In the shift register provided in FIG. 36, the fifth transistor T5 is an N-type transistor in the exemplary embodiment. Since the control electrode of the fifth transistor T5 is electrically connected with one of the first high-level power supply end VH1 and the second high-level power supply end VH2, the fifth transistor T5 is always in the on state.

[0331] In the shift register provided in FIG. 36, the fifth transistor T5 is an N-type transistor in the exemplary embodiment. Since the control electrode of the fifth transistor T5 is electrically connected with one of the first high-level power supply end VH1 and the second high-level power supply end VH2, the fifth transistor T5 is always in the on state.

[0332] In an example embodiment, FIG. 37 is an equivalent circuit diagram one of the second output control sub-circuit in the shift register provided in FIG. 31, and FIG. 38 is an equivalent circuit diagram two of the second output control sub-circuit in the shift register provided in FIG. 31. As shown in FIG. 37 and FIG. 38, the second output control sub-circuit comprises a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1 and a second capacitor C2, at least one capacitor of the first capacitor C1 and the second capacitor C2 comprises a first plate and a second plate. Wherein, the control electrode of the sixth transistor T6 is electrically connected with the first node ND1, the first electrode of the sixth transistor T6 is electrically connected with the second high level power supply end VH2, and the second electrode of the sixth transistor T6 is electrically connected with the cascade output end CR; the control electrode of the seventh transistor T7 is electrically connected with the third node ND3, the first electrode of the seventh transistor T7 is electrically connected with the second low level power supply end VL2, and the second electrode of the seventh transistor T7 is electrically connected with the cascade output end CR; the control electrode of the eighth transistor T8 is electrically connected with the first node ND1, the first electrode of the eighth transistor T8 is electrically connected with the first high level power supply end VH1, and the second electrode of the eighth transistor T8 is electrically connected with the signal output end OUT; the control electrode of the ninth transistor T9 is electrically connected with the third node ND3, the first electrode of the ninth transistor T9 is electrically connected with the first low level power supply end VL1, and the second electrode of the ninth transistor T9 is electrically connected with the signal output end OUT; the first plate of the first capacitor C1 is electrically connected with the first node ND1, and the second plate of the first capacitor C1 is electrically connected with one of the first high level power supply end VH1 and the second high level power supply end VH2; the first plate of the second capacitor C2 is electrically connected with the third node ND3, and the second plate of the second capacitor C2 is electrically connected with the cascade output end CR. FIG. 37 is illustrated by taking an example that the second plate of the first capacitor C1 is electrically connected with the second high level power supply end VH2, and FIG. 38 is illustrated by taking an example that the second plate of the first capacitor C1 is electrically connected with the first high level power supply end VH1.

[0333] In an example embodiment, as shown in FIG. 37 and FIG. 38, at least one transistor of the sixth transistor T6 to the ninth transistor T9 is a P-type transistor.

[0334] In an exemplary embodiment, FIG. 39 is an equivalent circuit diagram three of the second output control sub-circuit in the shift register provided in FIG. 31, FIG. 40 is an equivalent circuit diagram four of the second output control sub-circuit in the shift register provided in FIG. 31, and FIG. 41 is an equivalent circuit diagram five of the second output control sub-circuit in the shift register provided in FIG. 31. The second output control sub-circuit provided in FIGS. 39-41 is different from the second output control sub-circuit provided in FIG. 37 in that the second output control sub-circuit provided in FIGS. 39-41 further comprises at least one of a tenth transistor T10 and an eleventh transistor T11; at least one of the tenth transistor T10 and the eleventh transistor T11 is a single-gate structure, or a control electrode of at least one of the tenth transistor T10 and the eleventh transistor T11 comprises a first control electrode and a second control electrode, and the shift register is disposed on a substrate, and the second control electrode is disposed on a side of the first control electrode close to the substrate.

[0335] In an exemplary embodiment, when the tenth transistor T10 is a single-gate structure, the control electrode of the tenth transistor T10 is electrically connected with the first node ND1, the first electrode of the tenth transistor T10 is electrically connected with the second low-level power supply end VL2, and the second electrode of the tenth transistor T10 is electrically connected with the cascade output end CR. When the control electrode of the tenth transistor T10 comprises the first control electrode and the second control electrode, the first control electrode of the tenth transistor T10 is electrically connected with the first node ND1, the second control electrode of the tenth transistor T10 is electrically connected with at least one of the first low-level power supply end VL1, the second low-level power supply end VL2, and the third low-level power supply end VL3, the first electrode of the tenth transistor T10 is electrically connected with the second low-level power supply end VL2, and the second electrode of the tenth transistor T10 is electrically connected with the cascade output end CR.

[0336] In an exemplary embodiment, when the eleventh transistor T11 is a single-gate structure, the control electrode of the eleventh transistor T11 is electrically connected with the first node ND1, the first electrode of the eleventh transistor T11 is electrically connected with the first low-level power supply end VL1, and the second electrode of the eleventh transistor T11 is electrically connected with the signal output end OUT. When the control electrode of the eleventh transistor T11 comprises the first control electrode and the second control electrode, the first control electrode of the eleventh transistor T11 is electrically connected with the first node ND1, the second control electrode of the eleventh transistor T11 is electrically connected with at least one of the first low-level power supply end VL1, the second low-level power supply end VL2, and the third low-level power supply end VL3, the first electrode of the eleventh transistor T11 is electrically connected with the first low-level power supply end VL1, and the second electrode of the eleventh transistor T11 is electrically connected with the signal output end OUT.

[0337] FIG. 39 is a connection diagram of the second output control sub-circuit including only the tenth transistor T10, FIG. 40 is a connection diagram of the second output control sub-circuit including only the eleventh transistor T11, and FIG. 41 is a connection diagram of the second output control sub-circuit including both the tenth transistor T10 and the eleventh transistor T11.

[0338] In an exemplary embodiment, at least one of the tenth transistor T10 and the eleventh transistor T11 is an N-type transistor.

[0339] The tenth transistor T10 in the present disclosure can output a signal to the cascade output terminal together with the seventh transistor T7, can reduce the time length of the falling edge of the output signal of the cascade output terminal, can ensure the stability of the signal of the cascade output terminal, and thus can make the shift register applicable to a high-frequency driveable display device.

[0340] The eleventh transistor T11 in the present disclosure can output a signal to the signal output terminal together with the ninth transistor T9, can reduce the time length of the falling edge of the output signal of the signal output terminal, can ensure the stability of the signal of the signal output terminal, and thus can make the shift register applicable to a high-frequency driveable display device.

[0341] In an exemplary embodiment, the signal received by the first high-level power supply terminal VH1 is the same as the signal received by the second high-level power supply terminal VH2, or the signal received by the first low-level power supply terminal VL1 is the same as the signal received by the second low-level power supply terminal.

[0342] In an exemplary embodiment, FIG. 42 is a connection diagram two of the shift register provided in FIG. 30. As shown in FIG. 42, the at least one output signal terminal Gn includes the signal output terminal OUT, the at least one high-level power supply terminal connected to the output sub-circuit includes the high-level power supply terminal VH, the at least one low-level power supply terminal connected to the output sub-circuit includes the first low-level power supply terminal VL1, the at least one high-level power supply terminal connected to the control sub-circuit includes the high-level power supply terminal VH, and the at least one low-level power supply terminal connected to the control sub-circuit includes the first low-level power supply terminal VL1.

[0343] Fig. 43 is an equivalent circuit diagram of the first node control sub-circuit in the shift register provided in Fig. 42. As shown in Fig. 43, the first node control sub-circuit comprises a first transistor T1, a second transistor T2 and a third transistor T3. Wherein, the control electrode of the first transistor T1 is electrically connected with the clock signal end CK, the first electrode of the first transistor T1 is electrically connected with the signal input end IN, and the second electrode of the first transistor T1 is electrically connected with the second node ND2; the control electrode of the second transistor T2 is electrically connected with the signal input end IN, the first electrode of the second transistor T2 is electrically connected with the high level power supply end, and the second electrode of the second transistor T2 is electrically connected with the fourth node ND4; the control electrode of the third transistor T3 is electrically connected with the clock signal end CK, the first electrode of the third transistor T3 is electrically connected with the fourth node ND4, and the second electrode of the third transistor T3 is electrically connected with the first node ND1.

[0344] In an example embodiment, as shown in Fig. 43, at least one of the first transistor T1 to the third transistor T3 is a P-type transistor.

[0345] Fig. 44 is an equivalent circuit diagram of the second node control sub-circuit in the shift register provided in Fig. 42. As shown in Fig. 43, the second node control sub-circuit comprises a fourth transistor T4, which is a single-gate structure, or the control electrode of the fourth transistor T4 comprises a first control electrode and a second control electrode, the shift register is arranged on a substrate, and the second control electrode is arranged on the side of the first control electrode close to the substrate.

[0346] In an example embodiment, when the fourth transistor T4 is a single-gate structure, the control electrode of the fourth transistor T4 is electrically connected with the third node ND3, the first electrode of the fourth transistor T4 is electrically connected with the first low level power supply end VL1, and the second electrode of the fourth transistor T4 is electrically connected with the first node ND1.

[0347] In an example embodiment, when the control electrode of the fourth transistor T4 comprises a first control electrode and a second control electrode, the first control electrode of the fourth transistor T4 is electrically connected with the third node ND3, the second control electrode of the fourth transistor T4 is electrically connected with at least one of the first low level power supply end VL1 and the second low level power supply end VL2, the first electrode of the fourth transistor T4 is electrically connected with the first low level power supply end VL1, and the second electrode of the fourth transistor T4 is electrically connected with the first node ND1.

[0348] In the example embodiment, the control electrode of the fourth transistor T4 includes the first control electrode and the second control electrode, and the control electrode of the fourth transistor T4 is electrically connected with one of the first low-level power supply end VL1, the second low-level power supply end VL2 and the third low-level power supply end VL3, so that the threshold voltage stability of the fourth transistor T4 can be ensured and the threshold voltage offset of the fourth transistor under bias can be reduced.

[0349] In the example embodiment, the fourth transistor T4 is an N-type transistor. In the example embodiment, the fourth transistor T4 is an N-type transistor. Since the first electrode of the fourth transistor T4 is connected with the low-level power supply end, the fourth transistor is set as an N-type transistor, so that the power consumption of the shift register can be reduced.

[0350] FIG. 45 is an equivalent circuit diagram of the first output control sub-circuit in the shift register provided in FIG. 42. As shown in FIG. 45, the first output control sub-circuit includes the fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected with the first low-level power supply end VL1, the first electrode of the fifth transistor T5 is electrically connected with the second node ND2, and the second electrode of the fifth transistor T5 is electrically connected with the third node ND3.

[0351] In the example embodiment, the fifth transistor T5 is a P-type transistor. Since the control electrode of the fifth transistor T5 is electrically connected with the first low-level power supply end VL1, the fifth transistor T5 is always in the on state.

[0352] FIG. 46 is an equivalent circuit diagram of the second output control sub-circuit in the shift register provided in FIG. 42. As shown in FIG. 46, the second output control sub-circuit includes the sixth transistor T6, the seventh transistor T7, the first capacitor C1 and the second capacitor C2. At least one of the first capacitor C1 and the second capacitor C2 includes the first electrode plate and the second electrode plate. The control electrode of the sixth transistor T6 is electrically connected with the first node ND1, the first electrode of the sixth transistor T6 is electrically connected with the high-level power supply end, and the second electrode of the sixth transistor T6 is electrically connected with the signal output end OUT. The control electrode of the seventh transistor T7 is electrically connected with the third node ND3, the first electrode of the seventh transistor T7 is electrically connected with the first low-level power supply end VL1, and the second electrode of the seventh transistor T7 is electrically connected with the signal output end OUT. The first electrode plate of the first capacitor C1 is electrically connected with the first node ND1, and the second electrode plate of the first capacitor C1 is electrically connected with the high-level power supply end. The first electrode plate of the second capacitor C2 is electrically connected with the third node ND3, and the second electrode plate of the second capacitor C2 is electrically connected with the signal output end OUT.

[0353] In the example embodiment, at least one of the sixth transistor T6 and the seventh transistor T7 is a P-type transistor.

[0354] Fig. 47 is an equivalent circuit diagram two of the second output control sub-circuit in the shift register provided in Fig. 42. The second output control sub-circuit provided in Fig. 47 is different from the second output control sub-circuit provided in Fig. 46 in that the second output control sub-circuit provided in Fig. 47 further comprises: a twelfth transistor T12, the twelfth transistor T12 is a single-gate structure, or the control electrode of the twelfth transistor T12 comprises: a first control electrode and a second control electrode, the shift register is arranged on a substrate, and the second control electrode is arranged on the side of the first control electrode close to the substrate. Wherein, when the twelfth transistor T12 is a single-gate structure, the control electrode of the twelfth transistor T12 is electrically connected with the first node ND1, the first electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT, and the second electrode of the twelfth transistor T12 is electrically connected with the first low-level power supply end VL1; when the control electrode of the twelfth transistor T12 comprises: a first control electrode and a second control electrode, the first control electrode of the twelfth transistor T12 is electrically connected with the first node ND1, the second control electrode of the twelfth transistor T12 is electrically connected with one of the first low-level power supply end VL1 and the second low-level power supply end VL2, the first electrode of the twelfth transistor T12 is electrically connected with the signal output end OUT, and the second electrode of the twelfth transistor T12 is electrically connected with the first low-level power supply end VL1.

[0355] In an example embodiment, the twelfth transistor T12 is an N-type transistor.

[0356] The twelfth transistor T12 in the present disclosure can output a signal to the signal output end together with the seventh transistor T7, so as to ensure the stability of the signal of the signal output end.

[0357] Fig. 48 is another structural schematic diagram of the shift register provided in Fig. 29. As shown in Fig. 48, the shift register further comprises: a power-on control sub-circuit. Wherein, the power-on control sub-circuit is electrically connected with the power-on control signal end CX, at least one high-level power supply end VN2 and the first node ND1 respectively, and is configured to provide the signal of the at least one high-level power supply end VN2 to the first node ND1 under the control of the signal of the power-on control signal end CX.

[0358] Fig. 49 is an equivalent circuit diagram of the power-on control sub-circuit. As shown in Fig. 49, the power-on control sub-circuit comprises: a thirteenth transistor T13. Wherein, the control electrode of the thirteenth transistor T13 is electrically connected with the power-on control signal end CX, the first electrode of the thirteenth transistor T13 is electrically connected with the at least one high-level power supply end VN2, and the second electrode of the thirteenth transistor T13 is electrically connected with the first node ND1.

[0359] In the example embodiment, the power-on control signal terminal CX is an effective level signal in the power-on stage and is an ineffective level signal in the display stage. The effective level signal of the signal terminal refers to a signal that makes the transistor connected to the signal terminal conductive, and the ineffective level signal of the signal terminal refers to a signal that makes the transistor connected to the signal terminal non-conductive.

[0360] In the example embodiment, the setting of the power-on control sub-circuit can prevent the power-on flash screen of the display device, and can improve the reliability of the shift register.

[0361] Fig. 50 is an equivalent circuit diagram one of the shift register provided in Fig. 31. As shown in Fig. 50, the at least one output signal terminal includes: a cascade output terminal CR and a signal output terminal OUT, and the shift register can further include: a control sub-circuit and an output sub-circuit, or a control sub-circuit, an output sub-circuit and a power-on control sub-circuit. Wherein, the power-on control sub-circuit, the control sub-circuit includes: a first transistor to a fourth transistor, the output transistor includes: a fifth transistor T5 to a ninth transistor T9, a first capacitor C1 and a second capacitor C2, and the power-on control sub-circuit includes: a thirteenth transistor T13. Wherein, the fourth transistor T4 is a single gate structure, or the control electrode of the fourth transistor T4 includes: a first control electrode and a second control electrode. Wherein, the control electrode of the first transistor T1 is electrically connected with a clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected with a signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected with a second node ND2; the control electrode of the second transistor T2 is electrically connected with the signal input terminal IN, the first electrode of the second transistor T2 is electrically connected with a second high level power supply terminal VH2, and the second electrode of the second transistor T2 is electrically connected with a fourth node ND4; the control electrode of the third transistor T3 is electrically connected with the clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected with the fourth node ND4, the second electrode of the third transistor T3 is electrically connected with a first node ND1, and when the fourth transistor T4 is a single gate structure, the control electrode of the fourth transistor T4 is electrically connected with a third node ND3, the first electrode of the fourth transistor T4 is electrically connected with one of a first low level power supply terminal VL1 and a second low level power supply terminal VL2, and the second electrode of the fourth transistor T4 is electrically connected with the first node ND1.The control electrode of the fourth transistor T4 includes: when the control electrode of the fourth transistor T4 includes the first control electrode and the second control electrode, the first control electrode of the fourth transistor T4 is electrically connected with the third node ND3, the second control electrode of the fourth transistor T4 is electrically connected with one of the first low-level power supply end VL1, the second low-level power supply end VL2 and the third low-level power supply end VL3, the first electrode of the fourth transistor T4 is electrically connected with one of the first low-level power supply end VL1 and the second low-level power supply end VL2, and the second electrode of the fourth transistor T4 is electrically connected with the first node ND1; the control electrode of the fifth transistor T5 is electrically connected with one of the first low-level power supply end VL1, the second low-level power supply end VL2 and the third low-level power supply end VL3, the first electrode of the fifth transistor T5 is electrically connected with the second node ND2, the second electrode of the fifth transistor T5 is electrically connected with the third node ND3, the control electrode of the sixth transistor T6 is electrically connected with the first node ND1, the first electrode of the sixth transistor T6 is electrically connected with the second high-level power supply end VH2, and the second electrode of the sixth transistor T6 is electrically connected with the cascade output end CR; the control electrode of the seventh transistor T7 is electrically connected with the third node ND3, the first electrode of the seventh transistor T7 is electrically connected with the second low-level power supply end VL2, and the second electrode of the seventh transistor T7 is electrically connected with the cascade output end CR; the control electrode of the eighth transistor T8 is electrically connected with the first node ND1, the first electrode of the eighth transistor T8 is electrically connected with the first high-level power supply end VH1, and the second electrode of the eighth transistor T8 is electrically connected with the signal output end OUT; the control electrode of the ninth transistor T9 is electrically connected with the third node ND3, the first electrode of the ninth transistor T9 is electrically connected with the first low-level power supply end VL1, and the second electrode of the ninth transistor T9 is electrically connected with the signal output end OUT; the first electrode plate of the first capacitor C1 is electrically connected with the first node ND1, and the second electrode plate of the first capacitor C1 is electrically connected with the second high-level power supply end VH2; the first electrode plate of the second capacitor C2 is electrically connected with the third node ND3, and the second electrode plate of the second capacitor C2 is electrically connected with the cascade output end CR.

[0362] In the example embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 in the shift register provided in FIG. 50 are P-type transistors. The fourth transistor T4 is an N-type transistor.

[0363] In the example embodiment, the shift register is arranged in the display device. The working process of the display device includes a power-on stage and a display stage. The display device displays content in the display stage, and the content displayed by the display device includes a plurality of display frames. The driving mode of the display device includes a first driving mode and a second driving mode. The refresh rate of the display device in the first driving mode is less than the refresh rate of the display device in the second driving mode. For example, the refresh rate of the first driving mode can be 1HZ-60HZ, and the refresh rate of the second driving mode can be 60HZ-480HZ. The content displayed by the display substrate includes a plurality of display frames. In the second driving mode, at least one display frame includes a refresh frame. In the first driving mode, at least one display frame includes a refresh frame and at least one holding frame.

[0364] In the display stage, the signal of the power-on control signal end CX is an invalid level signal. The thirteenth transistor T13 is continuously turned off. The signals of the first low-level power supply end VL1, the second low-level power supply end VL2, and the third low-level power supply end VL3 are all low-level signals. The fifth transistor T5 is continuously turned on.

[0365] FIG. 51 is a driving timing diagram of the shift register provided in FIG. 50 in a refresh frame. As shown in FIG. 51, the working process of the shift register provided in FIG. 50 is described below to illustrate the example embodiment of the present disclosure.

[0366] In the first stage P1, the signals of the signal input end IN and the clock signal end CK are low-level signals. The first transistor T1, the second transistor T2, and the third transistor T3 are turned on.

[0367] The first transistor T1 is turned on, and the low-level signal of the signal input end IN is written to the second node ND2 and the third node N3 through the turned-on first transistor T1 and the turned-on fifth transistor T5. The signal of the third node N3 is a low-level signal, the fourth transistor T4 is turned off, and the seventh transistor T7 and the ninth transistor T9 are turned on. The seventh transistor T7 is turned on, and the signal of the second low-level power supply end VL2 is written to the cascade output end CR. The ninth transistor T9 is turned on, and the signal of the first low-level power supply end VL1 is written to the signal output end OUT. The second transistor T2 and the third transistor T3 are turned on, and the signal of the second high-level power supply end VH2 is written to the fourth node ND4 and the first node ND1 through the turned-on second transistor T2 and the turned-on third transistor T3. The signal of the first node ND1 is a high-level signal, and the sixth transistor T6 and the eighth transistor T8 are turned off.

[0368] In this stage, the cascade output end CR and the signal output end OUT output low-level signals.

[0369] The signals of the second stage P2, the signal input terminal IN and the clock signal terminal CK are high level signals. The first transistor T1, the second transistor T2 and the third transistor T3 are turned off.

[0370] Under the action of the first capacitor C1, the signal of the first node ND1 is the same as that of the previous stage. Under the action of the second capacitor C2, the signal of the third node ND3 remains a low level signal of the previous stage. The fourth transistor T4 is turned off, and the seventh transistor T7 and the ninth transistor T9 are turned on. The seventh transistor T7 is turned on, and the signal of the second low level power supply terminal VL2 is written into the cascade output terminal CR. The ninth transistor T9 is turned on, and the signal of the first low level power supply terminal VL1 is written into the signal output terminal OUT.

[0371] In this stage, the cascade output terminal CR and the signal output terminal OUT output low level signals.

[0372] The signal of the third stage P3 and the signal input terminal IN is a high level signal, and the signal of the clock signal terminal CK is a low level signal. The first transistor T1 and the third transistor T3 are turned on, and the second transistor T2 is turned off.

[0373] The first transistor T1 is turned on, and the high level signal of the signal input terminal IN is written into the second node ND2 and the third node N3 through the turned-on first transistor T1 and the turned-on fifth transistor T5. The signal of the third node N3 is a high level signal, the fourth transistor T4 is turned on, and the seventh transistor T7 and the eighth transistor T8 are turned off. The fourth transistor T4 is turned on, and the signal of at least one signal terminal of the first low level power supply terminal VL1 and the second low level power supply terminal VL2 is written into the first node ND1, and the sixth transistor T6 and the eighth transistor T8 are turned on. The sixth transistor T6 is turned on, and the signal of the second high level power supply terminal VH2 is written into the cascade output terminal CR. The eighth transistor T8 is turned on, and the signal of the first low level power supply terminal VL1 is written into the signal output terminal OUT. The third transistor T3 is turned on, and the low level signal of the first node ND1 is written into the third node ND3.

[0374] In this stage, the cascade output terminal CR and the signal output terminal OUT output high level signals.

[0375] The signals of the fourth stage P4, the signal input terminal IN and the clock signal terminal CK are high level signals. The first transistor T1, the second transistor T2 and the third transistor T3 are turned off.

[0376] Under the action of the first capacitor C1, the signal of the first node ND1 is the same as that in the previous stage, and the sixth transistor T6 and the eighth transistor T8 continue to be turned on. The sixth transistor T6 is turned on, the signal of the second high-level power supply end VH2 is written into the cascade output end CR, the eighth transistor T8 is turned on, and the signal of the first low-level power supply end VL1 is written into the signal output end OUT. Under the action of the second capacitor C2, the signal of the third node ND3 remains the high-level signal in the previous stage.

[0377] In this stage, the cascade output end CR and the signal output end OUT output high-level signals.

[0378] The working process of the fifth stage P5 is the same as that of the third stage P3, which will not be repeated here.

[0379] In the sixth stage P6, the signal of the signal input end IN is a low-level signal, and the signal of the clock signal end CK is a high-level signal. The first transistor T1 and the third transistor T3 are turned off, and the second transistor T2 is turned on.

[0380] The first transistor T1 is turned off, and the low-level signal of the signal input end IN cannot be written into the second node ND2 and the third node ND3. Under the action of the second capacitor C2, the signal of the third node ND3 remains the high-level signal in the previous stage, and the fourth transistor T4 is turned on. The second transistor T2 is turned on, and the fourth node ND4 is written by the second high-level power supply end VH2. The fourth transistor T4 is turned on, and the signal of at least one signal end in the first low-level power supply end VL1 and the second low-level power supply end VL2 is written into the first node ND1, and the sixth transistor T6 and the eighth transistor T8 are turned on. The sixth transistor T6 is turned on, the signal of the second high-level power supply end VH2 is written into the cascade output end CR, the eighth transistor T8 is turned on, and the signal of the first low-level power supply end VL1 is written into the signal output end OUT.

[0381] In this stage, the cascade output end CR and the signal output end OUT output high-level signals.

[0382] The working process of the seventh stage P7 is the same as that of the first stage P1, which will not be repeated here.

[0383] In the eighth stage P8, the signal of the signal input end IN is a low-level signal, and the signal of the clock signal end CK is a high-level signal. The first transistor T1 and the third transistor T3 are turned off, and the second transistor T2 is turned on.

[0384] The first transistor T1 is off, the low level signal of the signal input terminal IN cannot be written into the second node ND2 and the third node ND3, and the signal of the third node ND3 keeps the low level signal of the last stage under the action of the second capacitor C2. The fourth transistor T4 is off, the seventh transistor T7 and the ninth transistor T9 are turned on, the seventh transistor T7 is turned on, the signal of the second low level power supply terminal VL2 is written into the cascade output terminal CR, the ninth transistor T9 is turned on, and the signal of the first low level power supply terminal VL1 is written into the signal output terminal OUT. The second transistor T2 is turned on, and the fourth node ND4 is written by the second high level power supply terminal VH2. Under the action of the first capacitor C1, the first node ND1 keeps the high level signal of the last stage, and the sixth transistor T6 and the eighth transistor T8 are off.

[0385] In this stage, the cascade output terminal CR and the signal output terminal OUT output low level signals.

[0386] Figure 52 is an equivalent circuit diagram two of the shift register provided in Figure 31. The shift register provided in Figure 52 is different from the shift register provided in Figure 50 in that the connection mode of the second plate of the first capacitor. In the shift register provided in Figure 52, the second plate of the first capacitor C1 is electrically connected with the first high level power supply terminal VH1.

[0387] The driving timing of the shift register provided in Figure 51 can be applied to the shift register provided in Figure 52. The working process of the shift register provided in Figure 52 under the driving timing provided in Figure 51 is the same as the working process of the shift register provided in Figure 50 under the driving timing provided in Figure 51, which will not be described here.

[0388] Figure 53 is an equivalent circuit diagram three of the shift register provided in Figure 31. The shift register provided in Figure 53 is different from the shift register provided in Figure 50 in that the shift register provided in Figure 53 further comprises a tenth transistor T10. Wherein, the tenth transistor T10 is a single gate structure, or the control electrode of the tenth transistor T10 comprises a first control electrode and a second control electrode. Wherein, when the tenth transistor T10 is a single gate structure, the control electrode of the tenth transistor T10 is electrically connected with the first node ND1, the first electrode of the tenth transistor T10 is electrically connected with the second low level power supply terminal VL2, and the second electrode of the tenth transistor T10 is electrically connected with the cascade output terminal CR. When the control electrode of the tenth transistor T10 comprises a first control electrode and a second control electrode, the first control electrode of the tenth transistor T10 is electrically connected with the first node ND1, the second control electrode of the tenth transistor T10 is electrically connected with at least one signal terminal of the first low level power supply terminal VL1, the second low level power supply terminal VL2 and the third low level power supply terminal VL3, the first electrode of the tenth transistor T10 is electrically connected with the second low level power supply terminal VL2, and the second electrode of the tenth transistor T10 is electrically connected with the cascade output terminal CR.

[0389] In exemplary embodiments, the tenth transistor T10 is an N-type transistor.

[0390] The driving timing of the shift register provided in FIG. 51 can be applied to the shift register provided in FIG. 53. The working processes of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 53 under the driving timing provided in FIG. 51 are the same as the working processes of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 50 under the driving timing provided in FIG. 51, which will not be repeated here.

[0391] In the shift register provided in FIG. 53, since the first node ND1 is a high-level signal in the first stage P1, the second stage P2, the seventh stage P7 and the eighth stage P8, in the first stage P1, the second stage P2, the seventh stage P7 and the eighth stage P8, the tenth transistor T10 is turned on, and the signal of the second low-level power supply end VL2 is written into the cascade output end CR through the tenth transistor T10. At this time, the seventh transistor T7 is also turned on, and the signal of the second low-level power supply end VL2 is written into the cascade output end CR through the seventh transistor T7. Since the first node ND1 is a low-level signal in the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage P6, the tenth transistor T10 is turned off, and the second low-level power supply end VL2 cannot be written into the cascade output end CR, which can ensure that the signal of the cascade output end CR in the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage P6 is a high-level signal.

[0392] FIG. 54 is an equivalent circuit diagram four of the shift register provided in FIG. 31. The shift register provided in FIG. 54 is different from the shift register provided in FIG. 50 in that the shift register provided in FIG. 54 further includes an eleventh transistor T11. The eleventh transistor T11 is a single-gate structure, or the control electrode of the eleventh transistor T11 includes a first control electrode and a second control electrode. When the eleventh transistor T11 is a single-gate structure, the control electrode of the eleventh transistor T11 is electrically connected with the first node ND1, the first electrode of the eleventh transistor T11 is electrically connected with the first low-level power supply end VL1, and the second electrode of the eleventh transistor T11 is electrically connected with the signal output end OUT. When the control electrode of the eleventh transistor T11 includes a first control electrode and a second control electrode, the first control electrode of the eleventh transistor T11 is electrically connected with the first node ND1, the second control electrode of the eleventh transistor T11 is electrically connected with at least one signal end of the first low-level power supply end VL1, the second low-level power supply end VL2 and the third low-level power supply end VL3, the first electrode of the eleventh transistor T11 is electrically connected with the first low-level power supply end VL1, and the second electrode of the eleventh transistor T11 is electrically connected with the signal output end OUT.

[0393] In an exemplary embodiment, the eleventh transistor T11 is an N-type transistor.

[0394] The driving timing of the shift register provided in FIG. 51 can be applied to the shift register provided in FIG. 54. The working processes of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 54 under the driving timing provided in FIG. 51 are the same as the working processes of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 50 under the driving timing provided in FIG. 51, which will not be repeated here.

[0395] In the shift register provided in FIG. 54, since the first node ND1 is a high-level signal in the first stage P1, the second stage P2, the seventh stage P7 and the eighth stage P8, in the first stage P1, the second stage P2, the seventh stage P7 and the eighth stage P8, the eleventh transistor T11 is turned on, and the signal of the first low-level power supply end VL1 is written into the signal output end OUT through the turned-on eleventh transistor T11. At this time, the ninth transistor T9 is also turned on, and the signal of the first low-level power supply end VL1 is written into the signal output end OUT through the turned-on ninth transistor T9. Since the first node ND1 is a low-level signal in the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage P6, the eleventh transistor T11 is turned off, and the first low-level power supply end VL1 cannot write the signal into the signal output end OUT, which can ensure that the signal of the signal output end OUT in the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage P6 is a high-level signal.

[0396] FIG. 55 is an equivalent circuit diagram five of the shift register provided in FIG. 31. The shift register provided in FIG. 55 is different from the shift register provided in FIG. 50 in that the shift register provided in FIG. 55 further includes a tenth transistor T10 and an eleventh transistor T11. The tenth transistor T10 in FIG. 55 is the same as the tenth transistor T10 in FIG. 53, which will not be repeated here. The eleventh transistor T11 in FIG. 55 is the same as the eleventh transistor T11 in FIG. 54, which will not be repeated here.

[0397] The driving timing of the shift register provided in FIG. 51 can be applied to the shift register provided in FIG. 55. The working processes of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 55 under the driving timing provided in FIG. 51 are the same as those of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 50 under the driving timing provided in FIG. 51, which will not be repeated here. The working process of the tenth transistor T10 in the shift register provided in FIG. 55 under the driving timing provided in FIG. 51 is the same as that of the tenth transistor T10 in the shift register provided in FIG. 53 under the driving timing provided in FIG. 51, which will not be repeated here. The working process of the eleventh transistor T11 in the shift register provided in FIG. 55 under the driving timing provided in FIG. 51 is the same as that of the eleventh transistor T11 in the shift register provided in FIG. 54 under the driving timing provided in FIG. 51, which will not be repeated here.

[0398] FIG. 56 is an equivalent circuit diagram six of the shift register provided in FIG. 31. The shift register provided in FIG. 56 is different from the shift register provided in FIG. 50 in the transistor type of the fifth transistor and the connection manner of the control electrode of the fifth transistor. In the shift register provided in FIG. 55, the fifth transistor T5 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected to at least one signal terminal of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be repeated here.

[0399] The driving timing of the shift register provided in FIG. 51 can be applied to the shift register provided in FIG. 56. The working processes of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 56 under the driving timing provided in FIG. 51 are the same as those of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 50 under the driving timing provided in FIG. 51, which will not be repeated here.

[0400] FIG. 57 is an equivalent circuit diagram seven of the shift register provided in FIG. 31. The shift register provided in FIG. 57 is different from the shift register provided in FIG. 52 in the transistor type of the fifth transistor and the connection manner of the control electrode of the fifth transistor. In the shift register provided in FIG. 57, the fifth transistor T5 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected to at least one signal terminal of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be repeated here.

[0401] The driving timing of the shift register provided in FIG. 51 can be applied to the shift register provided in FIG. 57. The working processes of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 57 under the driving timing provided in FIG. 51 are the same as the working processes of the first transistor T1 to the ninth transistor T9 in the shift register provided in FIG. 52 under the driving timing provided in FIG. 51, which will not be repeated here.

[0402] FIG. 58 is an equivalent circuit diagram eight of the shift register provided in FIG. 31. The shift register provided in FIG. 58 is different from the shift register provided in FIG. 53 in the transistor type of the fifth transistor and the connection manner of the control electrode of the fifth transistor. In the shift register provided in FIG. 58, the fifth transistor T5 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected to at least one signal terminal of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be repeated here.

[0403] The driving timing of the shift register provided in FIG. 51 can be applied to the shift register provided in FIG. 58. The working processes of the first transistor T1 to the tenth transistor T10 in the shift register provided in FIG. 58 under the driving timing provided in FIG. 51 are the same as the working processes of the first transistor T1 to the tenth transistor T10 in the shift register provided in FIG. 53 under the driving timing provided in FIG. 51, which will not be repeated here.

[0404] FIG. 59 is an equivalent circuit diagram nine of the shift register provided in FIG. 31. The shift register provided in FIG. 59 is different from the shift register provided in FIG. 54 in the transistor type of the fifth transistor and the connection manner of the control electrode of the fifth transistor. In the shift register provided in FIG. 59, the fifth transistor T5 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected to at least one signal terminal of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be repeated here.

[0405] The driving timing of the shift register provided in FIG. 51 can be applied to the shift register provided in FIG. 59. The working processes of the first transistor T1 to the ninth transistor T9 and the eleventh transistor T11 in the shift register provided in FIG. 59 under the driving timing provided in FIG. 51 are the same as the working processes of the first transistor T1 to the ninth transistor T9 and the eleventh transistor T11 in the shift register provided in FIG. 54 under the driving timing provided in FIG. 51, which will not be repeated here.

[0406] Figure 60 is an equivalent circuit diagram ten of the shift register provided in Figure 31. The shift register provided in Figure 60 is different from the shift register provided in Figure 55 in that the transistor type of the fifth transistor and the connection mode of the control electrode of the fifth transistor, the fifth transistor T5 in the shift register provided in Figure 60 is an N-type transistor, and the control electrode of the fifth transistor T5 is electrically connected with at least one signal terminal of the first high-level power supply terminal VH1 and the second high-level power supply terminal VH2, which will not be described herein again.

[0407] The driving timing of the shift register provided in Figure 51 can be applicable to the shift register provided in Figure 60. The working processes of the first transistor T1 to the eleventh transistor T11 in the shift register provided in Figure 60 under the driving timing provided in Figure 51 are the same as the working processes of the first transistor T1 to the eleventh transistor T11 in the shift register provided in Figure 55 under the driving timing provided in Figure 51, which will not be described herein again.

[0408] Figure 61 is an equivalent circuit diagram one of the shift register provided in figure 42. As shown in figure 61, at least one output signal end includes: signal output end OUT, the shift register can further include: control sub-circuit and output sub-circuit, or, control sub-circuit, output sub-circuit and power-on control sub-circuit. Wherein, the power-on control sub-circuit, the control sub-circuit includes: the first transistor T1 to the fourth transistor T4, the output transistor includes: the fifth transistor T5 to the seventh transistor T7, the first capacitor C1 and the second capacitor C2, the power-on control sub-circuit includes: the thirteenth transistor T13. Wherein, the fourth transistor T4 is single gate structure, or, the control electrode of the fourth transistor T4 includes: the first control electrode and the second control electrode. Wherein, the control electrode of the first transistor T1 is electrically connected with the clock signal end CK, the first electrode of the first transistor T1 is electrically connected with the signal input end IN, the second electrode of the first transistor T1 is electrically connected with the second node ND2; the control electrode of the second transistor T2 is electrically connected with the signal input end IN, the first electrode of the second transistor T2 is electrically connected with the high level power supply end VH, the second electrode of the second transistor T2 is electrically connected with the fourth node ND4; the control electrode of the third transistor T3 is electrically connected with the clock signal end CK, the first electrode of the third transistor T3 is electrically connected with the fourth node ND4, the second electrode of the third transistor T3 is electrically connected with the first node ND1, when the fourth transistor T4 is single gate structure, the control electrode of the fourth transistor T4 is electrically connected with the third node ND3, the first electrode of the fourth transistor T4 is electrically connected with the first low level power supply end VL1, the second electrode of the fourth transistor T4 is electrically connected with the first node ND1. When the control electrode of the fourth transistor T4 includes: the first control electrode and the second control electrode, the first control electrode of the fourth transistor T4 is electrically connected with the third node ND3, the second control electrode of the fourth transistor T4 is electrically connected with one of the first low level power supply end VL1 and the second low level power supply end VL2, the first electrode of the fourth transistor T4 is electrically connected with the first low level power supply end VL1, the second electrode of the fourth transistor T4 is electrically connected with the first node ND1; the control electrode of the fifth transistor T5 is electrically connected with the first low level power supply end VL1, the first electrode of the fifth transistor T5 is electrically connected with the second node ND2, the second electrode of the fifth transistor T5 is electrically connected with the third node ND3, the control electrode of the sixth transistor T6 is electrically connected with the first node ND1, the first electrode of the sixth transistor T6 is electrically connected with the high level power supply end VH, the second electrode of the sixth transistor T6 is electrically connected with the signal output end OUT; the control electrode of the seventh transistor T7 is electrically connected with the third node ND3, the first electrode of the seventh transistor T7 is electrically connected with the first low level power supply end VL1, the second electrode of the seventh transistor T7 is electrically connected with the signal output end OUT; the first plate of the first capacitor C1 is electrically connected with the first node ND1, the second plate of the first capacitor C1 is electrically connected with the high level power supply end VH; the first plate of the second capacitor C2 is electrically connected with the third node ND3, the second plate of the second capacitor C2 is electrically connected with the signal output end OUT.

[0409] In the example embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 in the shift register provided in FIG. 61 are P-type transistors. The fourth transistor T4 is an N-type transistor.

[0410] The driving timing of the shift register provided in FIG. 51 can be applied to the shift register provided in FIG. 61.

[0411] The working process of the shift register provided in FIG. 61 is described below to illustrate the example embodiment of the present disclosure.

[0412] The signals of the first phase P1, the signal input terminal IN and the clock signal terminal CK are low-level signals. The first transistor T1, the second transistor T2 and the third transistor T3 are turned on.

[0413] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the second node ND2 and the third node N3 through the turned-on first transistor T1 and the turned-on fifth transistor T5. The signal of the third node N3 is a low-level signal, the fourth transistor T4 is turned off, and the seventh transistor T7 is turned on. The seventh transistor T7 is turned on, and the signal of the first low-level power supply terminal VL1 is written into the signal output terminal OUT. The second transistor T2 and the third transistor T3 are turned on, and the signal of the high-level power supply terminal VH is written into the fourth node ND4 and the first node ND1 through the turned-on second transistor T2 and the turned-on third transistor T3. The signal of the first node ND1 is a high-level signal, and the sixth transistor T6 is turned off.

[0414] In this phase, the signal output terminal OUT outputs a low-level signal.

[0415] The signals of the second phase P2, the signal input terminal IN and the clock signal terminal CK are high-level signals. The first transistor T1, the second transistor T2 and the third transistor T3 are turned off.

[0416] Under the action of the first capacitor C1, the signal of the first node ND1 is the same as that in the previous phase. Under the action of the second capacitor C2, the signal of the third node ND3 remains a low-level signal in the previous phase. The fourth transistor T4 is turned off, and the seventh transistor T7 is turned on. The seventh transistor T7 is turned on, and the signal of the first low-level power supply terminal VL1 is written into the signal output terminal OUT.

[0417] In this phase, the signal output terminal OUT outputs a low-level signal.

[0418] The signal of the third phase P3 is a high-level signal, and the signal of the clock signal terminal CK is a low-level signal. The first transistor T1 and the third transistor T3 are turned on, and the second transistor T2 is turned off.

[0419] The first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the second node ND2 and the third node N3 through the turned-on first transistor T1 and the turned-on fifth transistor T5. The signal of the third node N3 is a high-level signal, the fourth transistor T4 is turned on, and the seventh transistor T7 is turned off. The fourth transistor T4 is turned on, the signal of the first low-level power supply terminal VL1 is written into the first node ND1, and the sixth transistor T6 and the eighth transistor T8 are turned on. The sixth transistor T6 is turned on, and the signal of the high-level power supply terminal VH is written into the signal output terminal OUT. The third transistor T3 is turned on, and the low-level signal of the first node ND1 is written into the third node ND3.

[0420] In this phase, the signal output terminal OUT outputs a high-level signal.

[0421] In the fourth phase P4, the signals of the signal input terminal IN and the clock signal terminal CK are high-level signals. The first transistor T1, the second transistor T2, and the third transistor T3 are turned off.

[0422] Under the action of the first capacitor C1, the signal of the first node ND1 is the same as that in the previous phase, and the sixth transistor T6 and the eighth transistor T8 remain turned on. The sixth transistor T6 is turned on, and the signal of the high-level power supply terminal VH is written into the signal output terminal OUT. Under the action of the second capacitor C2, the signal of the third node ND3 remains a high-level signal in the previous phase.

[0423] In this phase, the signal output terminal OUT outputs a high-level signal.

[0424] The working process of the fifth phase P5 is the same as that of the third phase P3, which will not be described here.

[0425] In the sixth phase P6, the signal of the signal input terminal IN is a low-level signal, and the signal of the clock signal terminal CK is a high-level signal. The first transistor T1 and the third transistor T3 are turned off, and the second transistor T2 is turned on.

[0426] The first transistor T1 is turned off, and the low-level signal of the signal input terminal IN cannot be written into the second node ND2 and the third node ND3. Under the action of the second capacitor C2, the signal of the third node ND3 remains a high-level signal in the previous phase, and the fourth transistor T4 is turned on. The second transistor T2 is turned on, and the high-level power supply terminal VH is written into the fourth node ND4. The fourth transistor T4 is turned on, and the signal of at least one of the first low-level power supply terminal VL1 and the first low-level power supply terminal VL1 is written into the first node ND1, and the sixth transistor T6 is turned on. The sixth transistor T6 is turned on, and the signal of the high-level power supply terminal VH is written into the signal output terminal OUT.

[0427] In this phase, the signal output terminal OUT outputs a high level signal.

[0428] The working process of the seventh phase P7 is the same as that of the first phase P1, and will not be repeated here.

[0429] In the eighth phase P8, the signal of the signal input terminal IN is a low level signal, and the signal of the clock signal terminal CK is a high level signal. The first transistor T1 and the third transistor T3 are turned off, and the second transistor T2 is turned on.

[0430] The first transistor T1 is turned off, and the low level signal of the signal input terminal IN cannot be written into the second node ND2 and the third node ND3. Under the action of the second capacitor C2, the signal of the third node ND3 remains the low level signal of the previous phase. The fourth transistor T4 is turned off, the seventh transistor T7 is turned on, the signal of the first low level power supply terminal VL1 is written into the signal output terminal OUT. The second transistor T2 is turned on, and the fourth node ND4 is written by the high level power supply terminal VH. Under the action of the first capacitor C1, the first node ND1 remains the high level signal of the previous phase, and the sixth transistor T6 is turned off.

[0431] In this phase, the signal output terminal OUT outputs a low level signal.

[0432] Figure 62 is an equivalent circuit diagram four of the shift register provided in Figure 42. The shift register provided in Figure 62 is different from the shift register provided in Figure 61 in that the shift register provided in Figure 62 further comprises a twelfth transistor T12. The twelfth transistor T12 is a single-gate structure, or the control electrode of the twelfth transistor T12 comprises a first control electrode and a second control electrode. When the twelfth transistor T12 is a single-gate structure, the control electrode of the twelfth transistor T12 is electrically connected with the first node ND1, the first electrode of the twelfth transistor T12 is electrically connected with the first low level power supply terminal VL1, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output terminal OUT. When the control electrode of the twelfth transistor T12 comprises a first control electrode and a second control electrode, the first control electrode of the twelfth transistor T12 is electrically connected with the first node ND1, the second control electrode of the twelfth transistor T12 is electrically connected with at least one signal terminal of the first low level power supply terminal VL1, the second low level power supply terminal VL2 and the third low level power supply terminal VL3, the first electrode of the twelfth transistor T12 is electrically connected with the first low level power supply terminal VL1, and the second electrode of the twelfth transistor T12 is electrically connected with the signal output terminal OUT.

[0433] In an exemplary embodiment, the twelfth transistor T12 is an N-type transistor.

[0434] The driving timing of the shift register provided in FIG. 51 can be applied to the shift register provided in FIG. 62. The working processes of the first transistor T1 to the seventh transistor T7 in the shift register provided in FIG. 62 under the driving timing provided in FIG. 51 are the same as the working processes of the first transistor T1 to the seventh transistor T7 in the shift register provided in FIG. 61 under the driving timing provided in FIG. 51, which will not be described herein again.

[0435] In the shift register provided in FIG. 62, since the first node ND1 is a high-level signal in the first stage P1, the second stage P2, the seventh stage P7 and the eighth stage P8, in the first stage P1, the second stage P2, the seventh stage P7 and the eighth stage P8, the twelfth transistor T12 is turned on, and the signal of the first low-level power supply end VL1 is written into the signal output end OUT through the turned-on twelfth transistor T12. At this time, the ninth transistor T9 is also turned on, and the signal of the first low-level power supply end VL1 is written into the signal output end OUT through the turned-on ninth transistor T9. Since the first node ND1 is a low-level signal in the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage P6, the twelfth transistor T12 is turned off, and the first low-level power supply end VL1 cannot write the signal into the signal output end OUT, so that the signal of the signal output end OUT in the third stage P3, the fourth stage P4, the fifth stage P5 and the sixth stage P6 can be ensured as a high-level signal.

[0436] Compared with the shift registers provided in FIGS. 50, 52 to 60, the shift registers provided in FIGS. 61 and 62 have a smaller number of transistors, can reduce the area occupied by the shift register, and are beneficial to narrow the frame.

[0437] The shift register provided in FIG. 62 has a smaller number of transistors, can reduce the area occupied by the shift register, and is beneficial to narrow the frame.

[0438] The shift register provided in FIG. 62 has a smaller number of transistors, can reduce the area occupied by the shift register, and is beneficial to narrow the frame.

[0439] The shift register provided in FIG. 62 has a smaller number of transistors, can reduce the area occupied by the shift register, and is beneficial to narrow the frame.

[0440] The shift register provided in FIG. 62 has a smaller number of transistors, can reduce the area occupied by the shift register, and is beneficial to narrow the frame. The shift register provided in FIG. 62 has a smaller number of transistors, can reduce the area occupied by the shift register, and is beneficial to narrow the frame.

[0441] FIG. 64 is a schematic diagram of a cascade of shift registers 1. As shown in FIG. 64, the at least one output signal terminal includes a signal output terminal OUT, and the signal output terminal OUT of the at least one shift register GOA is electrically connected to the signal input terminal IN of the at least one shift register GOA. GOA(i) refers to the i-th shift register.

[0442] FIG. 65 is a schematic diagram of a cascade of shift registers 2. As shown in FIG. 65, the at least one output signal terminal includes a cascade output terminal CR and a signal output terminal OUT, and the cascade output terminal CR of the at least one shift register GOA is electrically connected to the signal input terminal IN of the at least one shift register GOA.

[0443] The display device provided by the embodiments of the present disclosure is shown in FIG. 66. As shown in FIG. 66, the display device provided by the embodiments of the present disclosure has a display area AA and a non-display area BB, wherein the display area AA is provided with pixel driving circuits 100 arranged in an array, and the non-display area BB is provided with a gate driving circuit 200 according to any one of the foregoing embodiments.

[0444] In exemplary embodiments, the gate driving circuit 200 can be located on at least one of the first side and the second side of the display area.

[0445] In exemplary embodiments, the signal timing diagram of the clock signal terminal in a refresh frame and a hold frame is shown in FIG. 67. As shown in FIG. 67, the signal of the clock signal terminal CK connected to the at least one shift register in the gate driving circuit is a constant voltage signal in at least one hold frame.

[0446] The signal of the clock signal terminal connected to the at least one shift register in the gate driving circuit in the present disclosure is a constant voltage signal in at least one hold frame, which can save the power consumption of the shift register without affecting the output signal of the shift register.

[0447] In exemplary embodiments, the display device can be any device that displays images whether in motion (e.g., video) or stationary (e.g., a still image) and whether textual or pictorial. More specifically, it is contemplated that embodiments can be implemented in or in association with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants, handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, navigation systems, audio / video head units for cars, etc. The embodiments of the present disclosure are not limited in this context.

[0448] The drawings in the present disclosure only involve the structures related to the embodiments of the present disclosure, and other structures can be referred to the general design.

[0449] For clarity, the thickness and dimensions of the layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intervening element can also be present.

[0450] Although the embodiments disclosed in the present disclosure are as above, the content described is only the embodiments adopted for the convenience of understanding the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A shift register comprising: The control sub-circuit and the output sub-circuit; The control sub-circuit is electrically connected with the signal input end, the clock signal end, at least one low-level power supply end, at least one high-level power supply end, the first node, the second node and the third node respectively, and is configured to provide signals to the first node and the second node under the control of signals of the signal input end, the clock signal end, at least one low-level power supply end, at least one high-level power supply end and the third node. The output sub-circuit is electrically connected with at least one output signal end, at least one high-level power supply end, at least one low-level power supply end, the first node, the second node and the third node respectively, and is configured to provide signals to the third node and at least one output signal end under the control of signals of at least one high-level power supply end, at least one low-level power supply end, the first node and the second node.

2. The shift register of claim 1, wherein, The control sub-circuit comprises a first node control sub-circuit and a second node control sub-circuit; The first node control sub-circuit is electrically connected with the signal input end, the clock signal end, at least one high-level power supply end, the first node and the second node respectively, and is configured to provide signals of at least one high-level power supply end to the first node and signals of the signal input end to the second node under the control of signals of at least one signal end of the signal input end and the clock signal end. The second node control sub-circuit is electrically connected with at least one low-level power supply end, the first node and the third node respectively, and is configured to provide signals of at least one low-level power supply end to the first node under the control of signals of the third node.

3. The shift register of claim 2, wherein, The output sub-circuit comprises a first output control sub-circuit and a second output control sub-circuit; The first output control sub-circuit is electrically connected with at least one signal end of at least one high-level power supply end and at least one low-level power supply end, the second node and the third node respectively, and is configured to provide signals of the second node to the third node under the control of signals of at least one signal end of at least one high-level power supply end and at least one low-level power supply end. The second output control sub-circuit is electrically connected with at least one high-level power supply end, at least one low-level power supply end, at least one output signal end, the first node and the third node respectively, and is configured to provide signals of at least one signal end of at least one high-level power supply end and at least one low-level power supply end to at least one output signal end under the control of signals of the first node and the third node.

4. The shift register of claim 3, wherein, At least one output signal end comprises a cascade output end and a signal output end, at least one high-level power supply end connected with the output sub-circuit comprises a first high-level power supply end and a second high-level power supply end, at least one low-level power supply end connected with the output sub-circuit comprises a first low-level power supply end and a second low-level power supply end, at least one high-level power supply end connected with the control sub-circuit comprises the second high-level power supply end, and at least one low-level power supply end connected with the control sub-circuit comprises at least one signal end of the first low-level power supply end and the second low-level power supply end.

5. The shift register of claim 4, wherein, The first node control sub-circuit comprises a first transistor, a second transistor and a third transistor. The control electrode of the first transistor is electrically connected with the clock signal end, the first electrode of the first transistor is electrically connected with the signal input end, and the second electrode of the first transistor is electrically connected with the second node; The control electrode of the second transistor is electrically connected with the signal input end, the first electrode of the second transistor is electrically connected with the second high-level power supply end, and the second electrode of the second transistor is electrically connected with the fourth node; The control electrode of the third transistor is electrically connected with the clock signal end, the first electrode of the third transistor is electrically connected with the fourth node, and the second electrode of the third transistor is electrically connected with the first node; At least one of the first transistor to the third transistor is a P-type transistor.

6. The shift register of claim 5, wherein, The fourth transistor is a single-gate structure, or the control electrode of the fourth transistor includes a first control electrode and a second control electrode, the shift register is arranged on a substrate, and the second control electrode is arranged on a side of the first control electrode close to the substrate; When the fourth transistor is a single-gate structure, the control electrode of the fourth transistor is electrically connected with the third node, the first electrode of the fourth transistor is electrically connected with one of the first low-level power supply end and the second low-level power supply end, and the second electrode of the fourth transistor is electrically connected with the first node; When the control electrode of the fourth transistor includes a first control electrode and a second control electrode, the first control electrode of the fourth transistor is electrically connected with the third node, the second control electrode of the fourth transistor is electrically connected with one of the first low-level power supply end, the second low-level power supply end and the third low-level power supply end, the first electrode of the fourth transistor is electrically connected with one of the first low-level power supply end and the second low-level power supply end, and the second electrode of the fourth transistor is electrically connected with the first node; The fourth transistor is an N-type transistor; The voltage value of the signal of the third low-level power supply end is higher than the voltage value of the signal of at least one of the first low-level power supply end and the second low-level power supply end.

7. The shift register of claim 4, wherein, The first output control sub-circuit includes a fifth transistor; The control electrode of the fifth transistor is electrically connected with one of the first low-level power supply end and the second low-level power supply end, the first electrode of the fifth transistor is electrically connected with the second node, and the second electrode of the fifth transistor is electrically connected with the third node; The fifth transistor is a P-type transistor.

8. The shift register of claim 4, wherein, The first output control sub-circuit includes a fifth transistor; The control electrode of the fifth transistor is electrically connected with the third low-level power supply end, the first electrode of the fifth transistor is electrically connected with the second node, and the second electrode of the fifth transistor is electrically connected with the third node; The fifth transistor is a P-type transistor. The difference between the voltage value of the signal of the third low-level power supply end and the voltage value of the signal of the second low-level power supply end is greater than the threshold voltage of the fifth transistor.

9. The shift register of claim 4, wherein, The first output control sub-circuit includes a fifth transistor; The control electrode of the fifth transistor is electrically connected with one of the first high-level power supply end and the second high-level power supply end, the first electrode of the fifth transistor is electrically connected with the second node, and the second electrode of the fifth transistor is electrically connected with the third node; The fifth transistor is an N-type transistor.

10. The shift register of claim 4, wherein, The second output control sub-circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor and a second capacitor, at least one of the first capacitor and the second capacitor comprises a first pole plate and a second pole plate; The control electrode of the sixth transistor is electrically connected with the first node, the first electrode of the sixth transistor is electrically connected with the second high-level power supply end, and the second electrode of the sixth transistor is electrically connected with the cascade output end; The control electrode of the seventh transistor is electrically connected with the third node, the first electrode of the seventh transistor is electrically connected with the second low-level power supply end, and the second electrode of the seventh transistor is electrically connected with the cascade output end; The control electrode of the eighth transistor is electrically connected with the first node, the first electrode of the eighth transistor is electrically connected with the first high-level power supply end, and the second electrode of the eighth transistor is electrically connected with the signal output end; The control electrode of the ninth transistor is electrically connected with the third node, the first electrode of the ninth transistor is electrically connected with the first low-level power supply end, and the second electrode of the ninth transistor is electrically connected with the signal output end; The first pole plate of the first capacitor is electrically connected with the first node, and the second pole plate of the first capacitor is electrically connected with one of the first high-level power supply end and the second high-level power supply end; The first pole plate of the second capacitor is electrically connected with the third node, and the second pole plate of the second capacitor is electrically connected with the cascade output end; At least one of the sixth transistor to the ninth transistor is a P-type transistor.

11. The shift register of claim 10, wherein, The second output control sub-circuit further comprises at least one of a tenth transistor and an eleventh transistor; at least one of the tenth transistor and the eleventh transistor is a single-gate structure, or the control electrode of at least one of the tenth transistor and the eleventh transistor comprises a first control electrode and a second control electrode, the shift register is arranged on a substrate, and the second control electrode is arranged on the side of the first control electrode close to the substrate; When the tenth transistor is a single-gate structure, the control electrode of the tenth transistor is electrically connected with the first node, the first electrode of the tenth transistor is electrically connected with the second low-level power supply end, and the second electrode of the tenth transistor is electrically connected with the cascade output end; When the control electrode of the tenth transistor comprises a first control electrode and a second control electrode, the first control electrode of the tenth transistor is electrically connected with the first node, the second control electrode of the tenth transistor is electrically connected with at least one of the first low-level power supply end, the second low-level power supply end and the third low-level power supply end, the first electrode of the tenth transistor is electrically connected with the second low-level power supply end, and the second electrode of the tenth transistor is electrically connected with the cascade output end; When the eleventh transistor is a single-gate structure, the control electrode of the eleventh transistor is electrically connected with the first node, the first electrode of the eleventh transistor is electrically connected with the first low-level power supply end, and the second electrode of the eleventh transistor is electrically connected with the signal output end; The first control electrode of the eleventh transistor is electrically connected with the first node, the second control electrode of the eleventh transistor is electrically connected with at least one signal terminal of the first low-level power supply terminal, the second low-level power supply terminal and the third low-level power supply terminal, the first electrode of the eleventh transistor is electrically connected with the first low-level power supply terminal, and the second electrode of the eleventh transistor is electrically connected with the signal output terminal when the control electrode of the eleventh transistor comprises the first control electrode and the second control electrode; At least one transistor of the tenth transistor and the eleventh transistor is an N-type transistor.

12. The shift register of claim 4, wherein, The signal received by the first high-level power supply terminal is the same as the signal received by the second high-level power supply terminal, or the signal received by the first low-level power supply terminal is the same as the signal received by the second low-level signal terminal.

13. The shift register of claim 3, wherein, The at least one output signal terminal comprises a signal output terminal, the at least one high-level power supply terminal connected with the output sub-circuit comprises a high-level power supply terminal, the at least one low-level power supply terminal connected with the output sub-circuit comprises a first low-level power supply terminal, the at least one high-level power supply terminal connected with the control sub-circuit comprises a high-level power supply terminal, and the at least one low-level power supply terminal connected with the control sub-circuit comprises a first low-level power supply terminal.

14. The shift register of claim 13, wherein, The first node control sub-circuit comprises a first transistor, a second transistor and a third transistor; The control electrode of the first transistor is electrically connected with the clock signal terminal, the first electrode of the first transistor is electrically connected with the signal input terminal, and the second electrode of the first transistor is electrically connected with the second node; The control electrode of the second transistor is electrically connected with the signal input terminal, the first electrode of the second transistor is electrically connected with the high-level power supply terminal, and the second electrode of the second transistor is electrically connected with the fourth node; The control electrode of the third transistor is electrically connected with the clock signal terminal, the first electrode of the third transistor is electrically connected with the fourth node, and the second electrode of the third transistor is electrically connected with the first node; At least one transistor of the first transistor to the third transistor is a P-type transistor.

15. The shift register of claim 14, wherein, The second node control sub-circuit comprises a fourth transistor, the fourth transistor is a single-gate structure, or the control electrode of the fourth transistor comprises a first control electrode and a second control electrode, the shift register is arranged on a substrate, and the second control electrode is arranged on the side of the first control electrode close to the substrate; The control electrode of the fourth transistor is electrically connected with the third node when the fourth transistor is a single-gate structure, the first electrode of the fourth transistor is electrically connected with the first low-level power supply terminal, and the second electrode of the fourth transistor is electrically connected with the first node; The first control electrode of the fourth transistor is electrically connected with the third node, the second control electrode of the fourth transistor is electrically connected with at least one signal terminal of the first low-level power supply terminal and the second low-level power supply terminal, the first electrode of the fourth transistor is electrically connected with the first low-level power supply terminal, and the second electrode of the fourth transistor is electrically connected with the first node when the control electrode of the fourth transistor comprises the first control electrode and the second control electrode; The fourth transistor is an N-type transistor.

16. The shift register of claim 13, wherein, The first output control sub-circuit comprises a fifth transistor; A control electrode of the fifth transistor is electrically connected with the first low-level power supply end, a first electrode of the fifth transistor is electrically connected with the second node, and a second electrode of the fifth transistor is electrically connected with the third node. The fifth transistor is a P-type transistor.

17. The shift register of claim 13, wherein, The second output control sub-circuit comprises a sixth transistor, a seventh transistor, a first capacitor and a second capacitor, at least one of the first capacitor and the second capacitor comprises a first electrode plate and a second electrode plate. A control electrode of the sixth transistor is electrically connected with the first node, a first electrode of the sixth transistor is electrically connected with the high-level power supply end, and a second electrode of the sixth transistor is electrically connected with the signal output end. A control electrode of the seventh transistor is electrically connected with the third node, a first electrode of the seventh transistor is electrically connected with the first low-level power supply end, and a second electrode of the seventh transistor is electrically connected with the signal output end. The first electrode plate of the first capacitor is electrically connected with the first node, and the second electrode plate of the first capacitor is electrically connected with the high-level power supply end. The first electrode plate of the second capacitor is electrically connected with the third node, and the second electrode plate of the second capacitor is electrically connected with the signal output end. At least one of the sixth transistor and the seventh transistor is a P-type transistor.

18. The shift register of claim 17, wherein, The second output control sub-circuit further comprises a twelfth transistor, the twelfth transistor is a single-gate structure, or a control electrode of the twelfth transistor comprises a first control electrode and a second control electrode, the shift register is arranged on a substrate, and the second control electrode is arranged on a side of the first control electrode close to the substrate. When the twelfth transistor is a single-gate structure, a control electrode of the twelfth transistor is electrically connected with the first node, a first electrode of the twelfth transistor is electrically connected with the signal output end, and a second electrode of the twelfth transistor is electrically connected with the first low-level power supply end. When the control electrode of the twelfth transistor comprises the first control electrode and the second control electrode, the first control electrode of the twelfth transistor is electrically connected with the first node, the second control electrode of the twelfth transistor is electrically connected with one of the first low-level power supply end and the second low-level power supply end, the first electrode of the twelfth transistor is electrically connected with the signal output end, and the second electrode of the twelfth transistor is electrically connected with the first low-level power supply end. The twelfth transistor is an N-type transistor.

19. The shift register of claim 1, further comprising: A power-on control sub-circuit; The power-on control sub-circuit is electrically connected with a power-on control signal end, at least one high-level power supply end and the first node respectively, and is configured to provide a signal of the at least one high-level power supply end to the first node under control of a signal of the power-on control signal end.

20. The shift register of claim 19, wherein, The power-on control sub-circuit comprises a thirteenth transistor. A control electrode of the thirteenth transistor is electrically connected with the power-on control signal end, a first electrode of the thirteenth transistor is electrically connected with the at least one high-level power supply end, and a second electrode of the thirteenth transistor is electrically connected with the first node.

21. A gate drive circuit comprising: A plurality of cascaded shift registers as claimed in any one of claims 1 to 20.

22. The gate drive circuit of claim 21, wherein, The at least one output signal end comprises a cascade output end and a signal output end, and the cascade output end of the at least one stage of shift registers is electrically connected with the signal input end of the at least one stage of shift registers. The at least one output signal end comprises a signal output end, and the signal output end of the at least one stage of shift registers is electrically connected with the signal input end of the at least one stage of shift registers.

23. A display device having a display area and a non-display area, wherein, The display region is provided with pixel driving circuits arranged in an array, and the non-display region is provided with the gate driving circuit according to claim 21 or 22.

24. The display device of claim 23, wherein, The content displayed by the display device comprises a plurality of display frames, and the driving mode of the display device comprises: a first driving mode and a second driving mode, the refresh rate of the display device in the first driving mode being less than the refresh rate of the display device in the second driving mode. In the first driving mode, at least one display frame comprises: at least one holding frame, and the signal of the clock signal end connected to at least one stage of the shift register in the gate driving circuit in the at least one holding frame is a constant voltage signal.

25. A driving method of a shift register configured to drive the shift register according to any one of claims 1 to 20, the method comprising: the control sub-circuit providing signals to the first node and the second node under the control of the signals at the signal input end, the clock signal end, at least one low-level power supply end, at least one high-level power supply end, and the third node; the output sub-circuit providing signals to the third node and at least one output signal end under the control of the signals at at least one high-level power supply end, at least one low-level power supply end, the first node, and the second node.

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