MOS device for nuclear radiation measurement and fabrication process

Abstract

The application discloses a MOS device for nuclear radiation measurement and a preparation process, and relates to the technical field of nuclear radiation measurement, and the device comprises an SOI substrate and an active region; the SOI substrate comprises a silicon substrate, a buried oxygen layer and a top silicon film from bottom to top; the active region is in a mesa structure and comprises a source electrode region, a drain electrode region, a channel region, a metal contact layer and a gate oxide layer; the source electrode and the drain electrode are distributed at two ends of the mesa; the channel region is located between the source electrode and the drain electrode; the upper surface and the outer side of the source electrode and the drain electrode are deposited with the metal contact layer; metal leads are arranged on the metal contact layer and correspond to the positions of the source electrode region and the drain electrode region, so as to realize the electrical connection between the device and an external circuit; the gate oxide layer covers the uppermost layer of the whole active region; contact holes are formed on the gate oxide layer and correspond to the positions of the source electrode region and the drain electrode region; and the contact holes expose the top surface of the metal contact layer. The device and the preparation process can be flexibly integrated into the system on chip of equipment, so that the on-chip accurate measurement of the nuclear radiation absorbed dose can be realized.

Description

Technical Field

[0001] This invention belongs to the field of nuclear radiation measurement technology, specifically relating to a MOS device for nuclear radiation measurement and its fabrication process. Background Technology

[0002] Nuclear radiation measurement technology is crucial in many fields. Currently widely used nuclear radiation dose monitoring equipment, such as cavity ionization chambers, scintillator detectors, and traditional semiconductor detectors, has many shortcomings. These devices often require independent nuclear electronics systems, resulting in large size, high power consumption, and significant weight, making effective integration with the electronic systems of some devices difficult and failing to meet their requirements for small payloads and low power consumption. Research on chip-level nuclear radiation absorbed dose measurement technology is currently lacking, still relying on traditional radiation detectors and unable to achieve miniaturized on-chip absorbed dose measurement functions, indicating a significant generational gap compared to the US and Europe. Traditional MOS devices in nuclear radiation measurement suffer from unstable threshold voltage drift, insufficient radiation resistance, and limited measurement range, making them unsuitable for the complex measurement needs of nuclear radiation environments.

[0003] Silicon-on-Insulator (SOI) technology, as an advanced all-dielectric isolation technology, exhibits many advantages that traditional bulk silicon technology cannot match. A typical SOI CMOS structure ( Figure 1 a) Compared with traditional bulk silicon CMOS structure ( Figure 1 The significant difference in b) lies in the fact that in SOI technology, devices are fabricated only on a very thin silicon film on the surface, with a buried oxide layer (BOX) introduced between the traditional Si top layer and the back substrate. This unique structure endows SOI CMOS devices with numerous advantages, such as low power consumption, high interference immunity, high integration density, fast response, small parasitic capacitance, simplified process, strong radiation resistance, and complete elimination of the parasitic latch-up effect in bulk silicon CMOS devices. Due to these excellent characteristics, SOI technology has rapidly developed and matured, and is widely used in aerospace, high temperature and high pressure, radiation resistance, low voltage and low power consumption, memory, and 3D integration, among other fields. Furthermore, due to the presence of the SOI BOX layer, there are multiple Si-oxide interfaces, making SOI devices more sensitive to total dose irradiation compared to traditional bulk silicon devices, thus making the study of their irradiation effects particularly important.

[0004] Although research on the radiation effects and damage mechanisms of SOI devices is relatively comprehensive, studies on the feasibility of using BOX layers, especially in PMOS dosimeters, remain relatively limited. Current research findings include: Sandia National Laboratories investigated the radiation response characteristics of SOI-based PMOS dosimeters under the influence of bias and dose rate; Watson Research Center achieved better sensitivity response than traditional bulk silicon dosimeters and boasted a BOX charge retention time of up to 90 days using a radiation dosimeter fabricated on an FDSOI substrate.

[0005] Given that SOI has a thicker BOX layer, is extremely sensitive to total dose irradiation, and is compatible with SOI device processes with lower production costs, PMOSFETs using the BOX layer as the gate oxide layer can replace traditional thick-gate Si devices, providing a completely new possibility for the development of high-sensitivity radiation dosimeters. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a MOS device and its fabrication process for nuclear radiation measurement. This device can be flexibly integrated into the system-on-a-chip of an equipment, enabling precise on-chip measurement of nuclear radiation absorbed dose. This provides a technical foundation for the study of radiation damage effects on semiconductor devices and radiation hardening in complex space particle environments, thereby improving the reliability of related equipment.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A MOS device for nuclear radiation measurement, characterized in that the device comprises: an SOI substrate and an active region formed on the surface of the SOI substrate;

[0009] The SOI substrate comprises, from bottom to top, a silicon substrate, a buried oxide layer, and a top silicon film, wherein the buried oxide layer is configured as a sensitive region for trapping radiation-induced charges.

[0010] The top silicon film serves as the substrate for the active region, comprising at least one active region. The active region has a mesa structure and includes a source region, a drain region, a channel region, a metal contact layer, and a gate oxide layer. The source and drain regions are symmetrically distributed at both ends of a mesa, serving as the current input and output terminals, respectively. The channel region is located between the source and drain regions and acts as a channel for carrier migration.

[0011] The metal contact layer is deposited on the upper surface and outer side of the source region and the drain region; metal leads are respectively provided on the metal contact layer at the positions corresponding to the source region and the drain region, for realizing the electrical connection between the device and the external test / application circuit;

[0012] The gate oxide layer covers the top layer of the entire active region. Contact holes are formed on the gate oxide layer at positions corresponding to the source and drain regions. The contact holes expose the top surface of the metal contact layer and are used for the metal leads to pass through the contact holes to achieve electrical connection with external test / application circuits.

[0013] Furthermore, in the MOS device for nuclear radiation measurement as described above, the silicon substrate is made of monocrystalline silicon; the buried oxide layer is made of silicon dioxide; and the top silicon film is made of monocrystalline silicon.

[0014] Furthermore, in the MOS device for nuclear radiation measurement as described above, the thickness of the buried oxide layer is 100~300nm, and the thickness of the top silicon film is 10~100nm.

[0015] Furthermore, in the MOS device for nuclear radiation measurement as described above, the top silicon film has multiple active regions.

[0016] Furthermore, in the MOS device for nuclear radiation measurement as described above, the active region is a raised structure formed by dry etching of the top silicon film, with a cross-shaped horizontal cross section. The cross-shaped cross section includes a first extension extending along a first direction and a second extension extending along a second direction, the first direction and the second direction intersecting perpendicularly. The source region includes a first end region of the first extension and a portion of the second extension adjacent to the first end of the first extension, forming an overall T-shape. The drain region includes a second end region of the first extension and a portion of the second extension adjacent to the second end of the first extension, forming an overall T-shape. The region between the two T-shapes is the channel region.

[0017] Furthermore, in the MOS device for nuclear radiation measurement as described above, the metal contact layer is offset outward in the horizontal direction relative to the source and drain regions by a certain distance to avoid short circuits.

[0018] Furthermore, in the MOS device for nuclear radiation measurement described above, the material of the metal contact layer is a Ti / Au composite metal.

[0019] Furthermore, in the MOS device for nuclear radiation measurement described above, the gate oxide layer is made of HfO2 and has a thickness of 20 nm.

[0020] Another technical solution adopted in this invention is as follows:

[0021] A fabrication process for a MOS device for nuclear radiation measurement as described above includes the following steps:

[0022] S1. Cleaning SOI wafers: The standard RCA cleaning process is used to remove organic impurities and metal particles from the surface of SOI wafers.

[0023] S2. Mesa fabrication: The active region of the mesa structure is fabricated on the top silicon film using photolithography exposure and development technology and dry etching process;

[0024] S3, Implanting impurity ions: for N + After photoresist exposure and development in the injection area, N-type implantation is performed. + Type I impurity ions, for P + After photoresist exposure and development in the injection area, P-type implantation is performed. + Type Ion;

[0025] S4. Deposit metal contact layer: Evaporate a Ti / Au composite metal film on the upper surface of the device, and form a metal contact layer on the upper and outer surfaces of the source and drain regions through photolithography exposure and development technology and metal lift-off process.

[0026] S5. Preparation of gate oxide layer: The active region is thermally oxidized under high temperature to grow an HfO2 oxide layer on the upper surface of the active region; then the contact hole is etched by photolithography exposure and development technology and dry etching process.

[0027] Furthermore, the fabrication process of the MOS device for nuclear radiation measurement as described above further includes, after step S3: performing a high-temperature rapid thermal annealing process to repair lattice damage caused by ion implantation and activate the implanted impurity ions; after step S4: performing a metal contact layer thermal annealing process to ensure the electrical quality of the contact.

[0028] Compared with the prior art, the MOS device and fabrication process for nuclear radiation measurement provided by the present invention have the following beneficial effects:

[0029] Miniaturization and integration: Using a fine etching process with a photolithography machine, the device size can reach 15mm×25mm×5mm, which can be flexibly integrated into the system-on-a-chip of the equipment, solving the problems of large size and difficulty in integration of traditional equipment;

[0030] Low power consumption: The power consumption is much lower than that of traditional nuclear radiation detectors, meeting the low power consumption requirements of some devices;

[0031] Radiation resistance and high measurement upper limit: Based on the SOI structure, the trapped charges in the buried oxide layer are not easily annealed, resulting in good radiation resistance. The dose measurement upper limit can reach the kGy level, making it suitable for gamma absorbed dose measurement in the high-dose environment of space. The measurement is achieved by utilizing the threshold voltage change caused by radiation. By optimizing the device structure and process, the linearity and sensitivity of the measurement are improved. Attached Figure Description

[0032] To further illustrate the above and other advantages and features of this application, the specific embodiments of this application will be described in more detail below with reference to the accompanying drawings. The accompanying drawings, together with the following detailed description, are included in and form a part of this specification. It should be understood that these drawings only depict typical examples of this application and should not be considered as limiting the scope of this application.

[0033] Figure 1 a and b are schematic diagrams of a typical SOI CMOS structure and a traditional bulk silicon CMOS structure, respectively;

[0034] Figure 2 This is a schematic cross-sectional view of a MOS device for nuclear radiation measurement provided in an embodiment of the present invention.

[0035] Figure 3 for Figure 2 Top view of the MOS device;

[0036] Figures 4-15 They are respectively Figure 1 A schematic diagram of the MOS device structure for each step in the fabrication process of the MOS device;

[0037] Figure 16 The I_DS-V_GS curves of the MOS device prepared in this example before and after irradiation are shown to illustrate the shift in the threshold voltage. Detailed Implementation

[0038] Exemplary embodiments of this application will be described below with reference to the accompanying drawings. For clarity and brevity, not all features of actual implementations are described in the specification. However, it should be understood that many implementation-specific decisions must be made in the development of any such actual embodiment to achieve the developer's specific goals, such as complying with constraints related to the system and business, and these constraints may vary depending on the implementation. Furthermore, it should be understood that while development work can be very complex and time-consuming, such development work is merely a routine task for those skilled in the art who benefit from the content of this application.

[0039] It should also be noted that, in order to avoid obscuring this application with unnecessary details, only the equipment structure and / or processing steps closely related to the solution according to this application are shown in the accompanying drawings, while other details that are not closely related to this application are omitted.

[0040] The embodiments or examples disclosed below are used to implement this application. To simplify the disclosure of this application, the components and methods of specific examples are described below. Of course, they are merely examples and are not intended to limit this application.

[0041] Figure 2 A schematic cross-sectional view of a MOS device for nuclear radiation measurement provided in an embodiment of the present invention is shown. Figure 3 The top view shows that the device is based on an SOI-MOSFET (silicon-on-insulator-metal-oxide-semiconductor field-effect transistor) structure, which mainly includes an SOI substrate and an active region formed on the surface of the SOI substrate. The structure of each part is described in detail below.

[0042] SOI layer substrate: Serving as the support and radiation-sensitive foundation for this MOS device, it is constructed from bottom to top by sequentially stacking a silicon substrate 1, a buried oxide layer 2, and a top silicon film, wherein:

[0043] The silicon substrate 1 is located at the bottom layer and is made of silicon, providing a stable substrate for the entire device.

[0044] The buried oxide layer 2, or BOX layer for short, is located above the silicon substrate 1. Its lower surface is in direct contact with and completely covers the upper surface of the silicon substrate 1. The material is silicon dioxide (SiO2), and the thickness of this layer is 100~300nm. The buried oxide layer 2 is the core radiation-sensitive region of the device. After nuclear radiation, oxide trap charges will be generated in this layer, which will affect the threshold voltage of the device.

[0045] The top silicon film is located above the buried oxide layer 2, with its lower surface directly contacting and completely covering the upper surface of the buried oxide layer 2. The material is a silicon thin film with a thickness of 10~100nm. The top silicon film is the substrate for the active region, and the core conductive structure of the device is subsequently formed on this layer through etching, doping and other processes.

[0046] Active region: Located on the upper surface of the top silicon film, it is the core area for the device to achieve current conduction and radiation response. Multiple active regions can exist on the top silicon film. Each active region is a raised structure formed by dry etching of the top silicon film. The horizontal cross-section of the raised structure is cross-shaped. Each active region includes a source region 4, a drain region 5, a channel region 6, a metal contact layer 7, and a gate oxide layer 8, wherein:

[0047] Source region 4 and drain region 5 are symmetrically distributed at both ends of a mesa on the top silicon film, serving as the current input and output terminals, respectively; channel region 6 is located between source region 4 and drain region 5, and is the channel for carrier (electron) migration. For example Figure 9The top view shown shows that the horizontal cross-sectional profile of an active region is shaped like a cross. The cross-shaped cross-section includes a first extension extending along a first direction and a second extension extending along a second direction, with the first and second directions intersecting perpendicularly. The source region 4 includes a first end region of the first extension and a portion of the second extension adjacent to the first end of the first extension, forming an overall T-shape. The drain region 5 includes a second end region of the first extension and a portion of the second extension adjacent to the second end of the first extension, forming an overall T-shape. The region between the two T-shapes is the channel region 6.

[0048] For NMOS devices, both source region 4 and drain region 5 are N. + Highly doped regions; for PMOS devices, both source region 4 and drain region 5 are P-doped. + Highly doped region. The doping concentration can be controlled through implantation process parameters to ensure current transfer efficiency. Channel region 6 can be selected for dedicated channel region doping implantation based on actual back gate turn-on threshold requirements. The doping type and concentration directly affect the conductivity characteristics of the channel region.

[0049] A metal contact layer 7, made of Ti / Au composite metal, is deposited on the upper surface and outer side of the source region 4 and drain region 5. Metal leads are provided on the metal contact layers 7 corresponding to the source region 4 and drain region 5 to achieve electrical connection between the device and external test / application circuits. In one specific embodiment, the metal contact layer 7 on the upper surface of the source region 4 and drain region 5 is a 10nm / 50nm Ti / Au composite metal. To avoid short circuits due to process errors, the metal contact layer 7 does not completely cover the upper surface of the source region 4 and drain region 5, but is offset outwards in the horizontal direction relative to the source region 4 and drain region 5 by a certain distance. The metal contact layer 7 on the outer side of the source region 4 and drain region 5 is thicker, which increases the contact area and reduces the contact resistance.

[0050] The gate oxide layer 8 covers the top layer of the entire active region. The gate oxide layer 8 is made of HfO2 and has a thickness of 20 nm. Contact holes are formed on the gate oxide layer 8 at the positions corresponding to the source region 4 and the drain region 5, exposing the top surface of the metal contact layer 7. These holes are used for metal leads to pass through and make electrical connections with external test / application circuits.

[0051] The working principle of the above-mentioned MOS device for nuclear radiation measurement is as follows:

[0052] When the aforementioned MOS device is exposed to nuclear radiation (such as gamma rays), electron-hole pairs are generated in the buried oxide layer and the gate oxide layer. Electrons, with their high mobility, are rapidly swept out of the oxide layer, while holes slowly drift towards the Si / SiO2 interface. Some holes are trapped, forming positive space charges. These trapped charges cause a shift in the device's threshold voltage. This shift is measured by the amount of ΔV. thCombined with the pre-calibrated ΔV th Relationship with absorbed dose D (ΔV) th =kD n , where k and n are coefficients related to the device structure), to achieve the measurement of nuclear radiation absorbed dose.

[0053] In a specific embodiment of the present invention, a fabrication process for the above-mentioned MOS device for nuclear radiation measurement is also provided, which specifically includes the following steps:

[0054] (1) Cleaning SOI Wafers: SOI wafers are constructed from bottom to top by sequentially stacking a silicon substrate, a buried oxide layer, and a top silicon film. A standard RCA cleaning process is used to remove organic impurities and metal particles from the SOI wafer surface, resulting in a clean, hydrophilic silicon surface. The cross-sectional and top views of the SOI wafer are shown below. Figure 4 , 5 As shown.

[0055] (2) Mesa fabrication: A photoresist film is spin-coated onto the top silicon film, and the active area is exposed and developed using photolithography. After development and removal of residual photoresist, a dry etching process is used to etch the underlying silicon until the top silicon film is etched through, thus forming isolated mesas from the remaining silicon film. These mesas are isolated by the etched trenches. The cross-sectional and top views of the mesas are shown below. Figure 6 , 7 As shown.

[0056] (3) Inject N + N-type impurity ions: A layer of photoresist is spin-coated onto the surface of the device. The implantation region of the N-type device is exposed and developed using photolithography. After removing residual photoresist, the photoresist is used as a mask for N-type impurity ion removal. + Type Ion implantation forms the source and drain regions of the NMOS device. The region between the source and drain regions forms the channel region. Cross-sectional and top views are shown below. Figure 8 , 9 As shown;

[0057] (4) Inject P + P-type impurity ions: A layer of photoresist is spin-coated onto the surface of the device. The implantation region of the P-type device is exposed and developed using photolithography. After removing residual photoresist, the photoresist is used as a mask for P-type impurity ion removal. + Type Ion implantation forms the source and drain of the PMOS device, and the region between the source and drain forms the channel region. Cross-sectional and top views are shown below. Figure 10 , 11 As shown;

[0058] After ion implantation, residual adhesive is removed, followed by a high-temperature rapid thermal annealing process to repair lattice damage caused by ion implantation and activate the implanted impurity ions.

[0059] (5) Deposition of metal contact layer: A Ti / Au composite metal film is evaporated on the upper surface of the device, and then a layer of photoresist is spin-coated on the upper surface of the device. The metal contact area is exposed and developed by photolithography. Then, a metal lift-off process is performed to form a metal contact layer on the upper and outer surfaces of the source and drain regions. The cross-sectional view and top view are shown below. Figure 12 , 13 As shown; finally, metal contact thermal annealing is performed to ensure the electrical quality of the contact.

[0060] (6) Preparation of gate oxide layer and contact hole: After the doping process of the active region is completed, the wafer is placed in an oxidation furnace and the active region is thermally oxidized at a high temperature of 900-1000℃ to grow a 20nm thick HfO2 oxide layer on the upper surface of the active region.

[0061] Then, a layer of photoresist is spin-coated onto the entire surface of the gate oxide layer. The contact hole area is exposed and developed using photolithography. After removing the residual photoresist, the contact hole area is etched out, thus forming the contact hole. Finally, the residual photoresist is removed. The cross-sectional and top views are shown below. Figure 14 , 15 As shown.

[0062] Example

[0063] In this embodiment, the specific steps and parameters involved in the device fabrication process are shown in Table 1 below.

[0064]

[0065] Performance testing: The fabricated device is placed in... 60 In a Co-γ radiation field, the threshold voltage changes before and after irradiation were measured with different doses. Figure 16 As shown.

[0066] The MOS device and fabrication process for nuclear radiation measurement provided by this invention can be flexibly integrated into the system-on-a-chip of equipment, enabling precise on-chip measurement of nuclear radiation absorbed dose. This provides a technical foundation for the study of radiation damage effects on semiconductor devices and radiation hardening in complex space particle environments, and improves the reliability of related equipment.

[0067] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention is also intended to include these modifications and variations.

Claims

1. A MOS device for nuclear radiation measurement, characterized in that, The device includes: an SOI substrate and an active region formed on the surface of the SOI substrate; The SOI substrate comprises, from bottom to top, a silicon substrate, a buried oxide layer, and a top silicon film, wherein the buried oxide layer is configured as a sensitive region for trapping radiation-induced charges. The top silicon film serves as the substrate for the active region, comprising at least one active region. The active region has a mesa structure and includes a source region, a drain region, a channel region, a metal contact layer, and a gate oxide layer. The source and drain regions are symmetrically distributed at both ends of a mesa, serving as the current input and output terminals, respectively. The channel region is located between the source and drain regions and acts as a channel for carrier migration. The metal contact layer is deposited on the upper surface and outer side of the source region and the drain region; metal leads are respectively provided on the metal contact layer at the positions corresponding to the source region and the drain region, for realizing the electrical connection between the device and the external test / application circuit; The gate oxide layer covers the top layer of the entire active region. Contact holes are formed on the gate oxide layer at positions corresponding to the source and drain regions. The contact holes expose the top surface of the metal contact layer and are used for the metal leads to pass through the contact holes to achieve electrical connection with external test / application circuits.

2. The MOS device for nuclear radiation measurement according to claim 1, characterized in that, The silicon substrate is made of monocrystalline silicon; the buried oxide layer is made of silicon dioxide; and the top silicon film is made of monocrystalline silicon.

3. The MOS device for nuclear radiation measurement according to claim 2, characterized in that, The thickness of the buried oxide layer is 100~300nm, and the thickness of the top silicon film is 10~100nm.

4. The MOS device for nuclear radiation measurement according to claim 3, characterized in that, The top silicon film has multiple active regions.

5. The MOS device for nuclear radiation measurement according to claim 4, characterized in that, The active region is a raised structure formed by dry etching of the top silicon film, with a horizontal cross-section in the shape of a cross. The cross-section includes a first extension extending along a first direction and a second extension extending along a second direction, with the first and second directions intersecting perpendicularly. The source region includes a first end region of the first extension and a portion of the second extension adjacent to the first end of the first extension, forming an overall T-shape. The drain region includes a second end region of the first extension and a portion of the second extension adjacent to the second end of the first extension, forming an overall T-shape. The region between the two T-shapes is the channel region.

6. The MOS device for nuclear radiation measurement according to claim 5, characterized in that, The metal contact layer is offset outward in the horizontal direction from the source and drain regions by a certain distance to avoid short circuits.

7. The MOS device for nuclear radiation measurement according to claim 1, characterized in that, The material of the metal contact layer is a Ti / Au composite metal.

8. The MOS device for nuclear radiation measurement of claim 1, wherein, The gate oxide layer is made of HfO2 and has a thickness of 20 nm.

9. A fabrication process for a MOS device for nuclear radiation measurement according to any one of claims 1-8, comprising the following steps: S1. Cleaning SOI wafers: The standard RCA cleaning process is used to remove organic impurities and metal particles from the surface of SOI wafers. S2. Mesa fabrication: The active region of the mesa structure is fabricated on the top silicon film using photolithography exposure and development technology and dry etching process; S3, Implanting impurity ions: for N + After photoresist exposure and development in the injection area, N-type implantation is performed. + Type I impurity ions, for P + After photoresist exposure and development in the injection area, P-type implantation is performed. + Type Ion; S4. Deposit metal contact layer: Evaporate a Ti / Au composite metal film on the upper surface of the device, and form a metal contact layer on the upper and outer surfaces of the source and drain regions through photolithography exposure and development technology and metal lift-off process. S5. Preparation of gate oxide layer: The active region is thermally oxidized under high temperature to grow an HfO2 oxide layer on the upper surface of the active region; then the contact hole is etched by photolithography exposure and development technology and dry etching process.

10. The fabrication process of a MOS device for nuclear radiation measurements according to claim 9, characterized in that, Step S3 is followed by: performing a high-temperature rapid thermal annealing process to repair lattice damage caused by ion implantation and activate the implanted impurity ions; Step S4 is followed by: performing a metal contact layer thermal annealing process to ensure the electrical quality of the contact.

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