Chip power consumption estimation method and device, electronic equipment and storage medium

Abstract

The embodiment of the application provides a chip power consumption estimation method and device, electronic equipment and a storage medium, and belongs to the technical field of chip testing. The method comprises the following steps: based on static power consumption influencing factors, performing static power consumption calculation on a test chip to obtain chip static power consumption; based on the static power consumption influencing factors and the chip static power consumption, performing relationship function construction to obtain a static factor power consumption relationship function; based on the static power consumption influencing factors and dynamic power consumption influencing factors, performing dynamic power consumption calculation on the test chip to obtain chip dynamic power consumption; based on the dynamic power consumption influencing factors and the chip dynamic power consumption, performing relationship function construction to obtain a dynamic factor power consumption relationship function; based on the static factor power consumption relationship function and the dynamic factor power consumption relationship function, constructing a chip power consumption estimation model; and based on the chip power consumption estimation model, performing power consumption estimation on a preset target chip to obtain chip estimated power consumption. The embodiment of the application can improve the estimation accuracy of chip power consumption.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip power consumption estimation method and apparatus, electronic equipment and storage medium. Background Technology

[0002] Chip power consumption estimation is used to predict the power consumption of a chip under specific conditions. For example, by estimating the power consumption of a mobile phone chip under specific conditions, mobile phone manufacturers can optimize heat dissipation design and battery life strategies.

[0003] Currently, common chip power consumption estimation methods mostly involve constructing a circuit simulation model of the chip using electronic design automation methods, and then calculating the simulated power consumption of the chip on the circuit simulation model. However, this chip power consumption estimation method does not take into account the influence of various factors in real life, resulting in inaccurate power consumption estimates. Therefore, how to improve the accuracy of chip power consumption estimation has become an urgent technical problem to be solved. Summary of the Invention

[0004] The main objective of this application is to provide a chip power consumption estimation method, apparatus, electronic device, and storage medium, aiming to improve the accuracy of chip power consumption estimation.

[0005] To achieve the above objectives, a first aspect of this application proposes a chip power consumption estimation method, the method comprising: Obtain the factors affecting the static power consumption and dynamic power consumption of the test chip; Based on the aforementioned factors affecting static power consumption, the static power consumption of the test chip is calculated to obtain the chip's static power consumption. Based on the static power consumption influencing factors and the chip's static power consumption, a relationship function is constructed to obtain the static factor power consumption relationship function; Based on the static power consumption influencing factors and the dynamic power consumption influencing factors, the dynamic power consumption of the test chip is calculated to obtain the chip's dynamic power consumption. Based on the dynamic power consumption influencing factors and the chip's dynamic power consumption, a relationship function is constructed to obtain the dynamic factor power consumption relationship function; Based on the static factor power consumption relationship function and the dynamic factor power consumption relationship function, a chip power consumption estimation model is constructed; Based on the chip power consumption estimation model, the power consumption of the preset target chip is estimated to obtain the chip estimated power consumption.

[0006] In some embodiments, the step of calculating the dynamic power consumption of the test chip based on the static power consumption influencing factors and the dynamic power consumption influencing factors to obtain the chip's dynamic power consumption includes: The test chip is analyzed by functional module power domain to obtain the module power domain form, wherein the module power domain form includes module shared power domain form or module independent power domain form. Based on the independent power domain configuration of the module, the static power consumption influencing factors and the dynamic power consumption influencing factors, the power consumption of the test chip is directly read to obtain the dynamic power consumption of the chip's independent module. Based on the shared power domain configuration of the modules, the static power consumption influencing factors, and the dynamic power consumption influencing factors, the power consumption difference of the test chip is read to obtain the dynamic power consumption of the chip shared modules.

[0007] In some embodiments, the step of directly reading the power consumption of the test chip based on the module's independent power domain configuration, the static power consumption influencing factors, and the dynamic power consumption influencing factors to obtain the chip's independent module dynamic power consumption includes: Based on the independent power domain configuration of the module, the static power consumption influencing factors, and the dynamic power consumption influencing factors, a dynamic power consumption test scheme for the independent module is determined. Based on the chip dynamic power consumption test scheme, the test chip is subjected to dynamic power consumption test to obtain the chip dynamic power consumption.

[0008] In some embodiments, the dynamic power consumption influencing factors include service load influencing factors and clock frequency influencing factors. The step of determining an independent module's dynamic power consumption test scheme based on the module's independent power domain configuration, the static power consumption influencing factors, and the dynamic power consumption influencing factors includes: Based on the static power consumption influencing factors, the module influencing factor values ​​of the test chip are frozen to obtain fixed values ​​of the chip's static factors. Based on the independent power domain configuration of the module, the values ​​of the factors affecting the service load are frozen to obtain fixed values ​​for the service load, and the values ​​of the factors affecting the clock frequency are frozen to obtain fixed values ​​for the clock frequency. Based on the fixed values ​​of the chip's static factors and the fixed values ​​of the service load, a test plan for the impact of frequency power consumption is generated. Based on the fixed values ​​of the chip's static factors and the fixed values ​​of the clock frequency, a test scheme for the impact of load power consumption is generated. The frequency power consumption impact test scheme and the load power consumption impact test scheme are combined to obtain the chip dynamic power consumption test scheme.

[0009] In some embodiments, the test chip includes a set of shared power functional modules. The step of reading the power difference of the test chip based on the shared power domain configuration of the modules, the static power consumption influencing factors, and the dynamic power consumption influencing factors to obtain the dynamic power consumption of the chip's shared modules includes: Based on the shared power domain configuration of the modules, the static power consumption influencing factors and the dynamic power consumption influencing factors, dynamic power consumption tests are performed on the shared power functional module set to obtain the module dynamic power consumption set. The dynamic power consumption of the chip is obtained by merging the dynamic power consumption sets of the modules.

[0010] In some embodiments, the shared power functional module set includes a functional module to be tested and a silent functional module. The dynamic power consumption test is performed on the shared power functional module set based on the shared power domain configuration of the modules, the static power consumption influencing factors, and the dynamic power consumption influencing factors, to obtain a module dynamic power consumption set, including: Based on the static power consumption influencing factors, the module influencing factor values ​​of the shared power function module set are frozen to obtain fixed values ​​of module static factors; The module state of the silent function module is adjusted to obtain the module silent state; Based on the fixed values ​​of the static factors of the module and the silent state of the module, the dynamic power consumption of the functional module to be tested is calculated to obtain the dynamic power consumption of the first module. The dynamic factor values ​​of the functional module to be tested are frozen to obtain fixed values ​​of the module's dynamic factors; Based on the fixed values ​​of the static factors and the fixed values ​​of the dynamic factors of the module, the dynamic power consumption of the silent function module is calculated to obtain the dynamic power consumption of the second module. The dynamic power consumption of the first module and the dynamic power consumption of the second module are combined to obtain the dynamic power consumption set of the modules.

[0011] In some embodiments, the step of calculating the dynamic power consumption of the silent function module based on the fixed values ​​of the module's static factors and the fixed values ​​of the module's dynamic factors to obtain the dynamic power consumption of the second module includes: Based on the fixed values ​​of the module's static factors and the fixed values ​​of the module's dynamic factors, the incremental dynamic power consumption of the functional module to be tested is determined. Based on the fixed values ​​of the module's static factors and the fixed values ​​of the module's dynamic factors, the power consumption of the silent function module is calculated to obtain the module's total incremental power consumption. The dynamic power consumption of the second module is obtained by performing a difference calculation on the total incremental power consumption of the module, the incremental dynamic power consumption of the module, and the static power consumption of the chip.

[0012] To achieve the above objectives, a second aspect of this application provides a chip power consumption estimation device, the device comprising: The influencing factor acquisition module is used to acquire the static power consumption influencing factors and dynamic power consumption influencing factors of the test chip; The static power consumption calculation module is used to perform static power consumption calculation on the test chip based on the static power consumption influencing factors to obtain the chip's static power consumption. The static function construction module is used to construct a relationship function based on the static power consumption influencing factors and the static power consumption of the chip, so as to obtain the static factor power consumption relationship function; The dynamic power consumption calculation module is used to perform dynamic power consumption calculation on the test chip based on the static power consumption influencing factors and the dynamic power consumption influencing factors to obtain the chip's dynamic power consumption. The dynamic function construction module is used to construct a relationship function based on the dynamic power consumption influencing factors and the chip's dynamic power consumption, thereby obtaining a dynamic factor power consumption relationship function. The power consumption model construction module is used to construct a chip power consumption estimation model based on the static factor power consumption relationship function and the dynamic factor power consumption relationship function; The chip power consumption estimation module is used to estimate the power consumption of a preset target chip based on the chip power consumption estimation model, and obtain the chip estimated power consumption.

[0013] To achieve the above objectives, a third aspect of the present application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method of the first aspect described above.

[0014] To achieve the above objectives, a fourth aspect of the present application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method of the first aspect described above.

[0015] The chip power consumption estimation method, apparatus, electronic device, and storage medium proposed in this application provide a clear direction for chip power consumption estimation by acquiring the static and dynamic power consumption influencing factors of the test chip, thereby improving the efficiency of chip power consumption estimation. Furthermore, based on the static power consumption influencing factors, static power consumption calculation is performed on the test chip to obtain the chip's static power consumption. Then, based on the static power consumption influencing factors and the chip's static power consumption, a relationship function is constructed to obtain the static factor power consumption relationship function. This avoids the influence of dynamic power consumption influencing factors on the static power consumption test of the test chip, thus improving the accuracy of the static factor power consumption relationship function. Secondly, based on the static and dynamic power consumption influencing factors, dynamic power consumption calculation is performed on the test chip... The dynamic power consumption of the chip is calculated, and a relationship function is constructed based on the influencing factors of dynamic power consumption and the chip's dynamic power consumption. This results in a dynamic factor power consumption relationship function, which considers both the influencing factors of dynamic power consumption and the cross-influence of static power consumption factors during the dynamic power consumption measurement process. This makes the dynamic factor power consumption relationship function more in line with actual physical laws, thereby improving the accuracy of the dynamic factor power consumption relationship function. Finally, based on the static factor power consumption relationship function and the dynamic factor power consumption relationship function, a chip power consumption estimation model is constructed. Based on the chip power consumption estimation model, the power consumption of a preset target chip is estimated, resulting in the estimated chip power consumption. This reduces the chip power consumption estimation time and improves the efficiency and accuracy of chip power consumption estimation. Attached Figure Description

[0016] Figure 1 This is a flowchart of the chip power consumption estimation method provided in the embodiments of this application; Figure 2 yes Figure 1 The flowchart of step S104 in the process; Figure 3 yes Figure 2 The flowchart of step S202 in the text; Figure 4 yes Figure 3 The flowchart of step S301 in the process; Figure 5 yes Figure 2 The flowchart of step S203 in the process; Figure 6 yes Figure 5 The flowchart of step S501 in the process; Figure 7 yes Figure 6 The flowchart of step S605 in the process; Figure 8 This is a schematic diagram of the chip power consumption estimation device provided in the embodiments of this application; Figure 9 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0020] First, let's analyze some of the terms used in this application: Chip functional modules: Chip functional modules refer to independent circuit units or logic units within a chip that are divided to achieve specific functions. Each module undertakes its own task. Chip functional modules work together through the chip's internal bus or interconnection structure. The performance, power consumption, and other characteristics of chip functional modules directly affect the overall functional performance of the chip. They are the basic analytical units in chip design, power optimization, performance evaluation, and other related processes.

[0021] Business load: Business load refers to the amount of tasks or processing demands undertaken by a chip's functional modules when running specific business scenarios. Business load is a core indicator for measuring the workload of a module and is directly related to dynamic power consumption and performance scheduling. Business load is usually reflected by task parameters in specific business scenarios, such as the amount of instructions processed by the CPU when running social software, the amount of frame data when the GPU renders game screens, the amount of image pixel data when the ISP processes photos, or the data transfer rate when the storage controller reads and writes files. The higher the business load, the more computing resources the module needs to call, and the more dynamic power consumption increases. Therefore, business load is one of the key dynamic influencing factors in chip power consumption estimation and performance optimization.

[0022] Clock frequency: Clock frequency refers to the oscillation frequency of the internal clock signal of a chip, measured in Hertz. Clock frequency is a key indicator for measuring the operating rhythm of a chip's digital circuits. It determines the speed at which a chip executes instructions and transmits data, and is also directly related to power consumption and heat generation. For example, the clock frequency of common mobile phone processors can reach over 2GHz, and computer CPUs can even exceed 5GHz. It is one of the core parameters for balancing chip performance and power consumption in design.

[0023] Chip power consumption estimation is used to predict the power consumption of a chip under specific conditions. For example, by estimating the power consumption of a mobile phone chip under specific conditions, mobile phone manufacturers can optimize heat dissipation design and battery life strategies.

[0024] Currently, common chip power consumption estimation methods mostly involve constructing a circuit simulation model of the chip using electronic design automation methods, and then calculating the simulated power consumption of the chip on the circuit simulation model. However, this chip power consumption estimation method does not take into account the influence of various factors in real life, resulting in inaccurate power consumption estimates. Therefore, how to improve the accuracy of chip power consumption estimation has become an urgent technical problem to be solved.

[0025] Based on this, embodiments of this application provide a chip power consumption estimation method and apparatus, electronic device and storage medium, aiming to improve the accuracy of chip power consumption estimation.

[0026] The chip power consumption estimation method, apparatus, electronic device, and storage medium provided in this application are specifically described through the following embodiments. First, the chip power consumption estimation method in this application is described.

[0027] The embodiments of this application can acquire and process relevant data based on artificial intelligence technology. Artificial intelligence (AI) refers to the theories, methods, technologies, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0028] Foundational technologies for artificial intelligence generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies mainly encompass computer vision, robotics, biometrics, speech processing, natural language processing, and machine learning / deep learning.

[0029] The chip power consumption estimation method provided in this application relates to the field of chip testing technology. This method can be applied to terminals, servers, or software running on either a terminal or server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, etc.; the server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application implementing the chip power consumption estimation method, but is not limited to the above forms.

[0030] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0031] Figure 1 This is an optional flowchart of the chip power consumption estimation method provided in the embodiments of this application. Figure 1 The method may include, but is not limited to, steps S101 to S107.

[0032] Step S101: Obtain the static power consumption influencing factors and dynamic power consumption influencing factors of the test chip; Step S102: Based on the factors affecting static power consumption, perform static power consumption calculation on the test chip to obtain the chip's static power consumption; Step S103: Based on the factors affecting static power consumption and the static power consumption of the chip, construct the relationship function to obtain the static factor power consumption relationship function; Step S104: Based on the factors affecting static power consumption and dynamic power consumption, perform dynamic power consumption calculation on the test chip to obtain the dynamic power consumption of the chip. Step S105: Based on the factors affecting dynamic power consumption and the dynamic power consumption of the chip, construct the relationship function to obtain the dynamic factor power consumption relationship function; Step S106: Construct a chip power consumption estimation model based on the static factor power consumption relationship function and the dynamic factor power consumption relationship function; Step S107: Based on the chip power consumption estimation model, perform power consumption estimation on the preset target chip to obtain the chip estimated power consumption.

[0033] Steps S101 to S107, as illustrated in this embodiment, provide a clear direction for chip power consumption estimation by acquiring the static and dynamic power consumption influencing factors of the test chip, thus improving the efficiency of chip power consumption estimation. Furthermore, based on the static power consumption influencing factors, static power consumption calculation is performed on the test chip to obtain the chip's static power consumption. Then, based on the static power consumption influencing factors and the chip's static power consumption, a relationship function is constructed to obtain the static factor power consumption relationship function. This avoids the impact of dynamic power consumption influencing factors on the static power consumption test of the test chip, thereby improving the accuracy of the static factor power consumption relationship function. Next, based on the static and dynamic power consumption influencing factors, dynamic power consumption calculation is performed on the test chip. The dynamic power consumption of the chip is obtained, and a relationship function is constructed based on the influencing factors of dynamic power consumption and the chip's dynamic power consumption. This results in a dynamic factor power consumption relationship function, which considers both the influencing factors of dynamic power consumption and the cross-influence of static power consumption factors during the dynamic power consumption measurement process. This makes the dynamic factor power consumption relationship function more in line with actual physical laws, thereby improving the accuracy of the dynamic factor power consumption relationship function. Finally, based on the static factor power consumption relationship function and the dynamic factor power consumption relationship function, a chip power consumption estimation model is constructed. Based on the chip power consumption estimation model, the power consumption of a preset target chip is estimated, resulting in the chip estimated power consumption. This reduces the chip power consumption estimation time and improves the efficiency and accuracy of chip power consumption estimation.

[0034] In step S101 of some embodiments, the test chip refers to a chip sample used for power consumption calculation. The test chip usually includes multiple functional modules. It should be noted that the test chip and the chip for which power consumption estimation is required are the same type of chip.

[0035] Static power consumption influencing factors refer to the key variables that cause changes in the static power consumption of a chip, such as junction temperature, supply voltage, and chip process corner.

[0036] Dynamic power consumption influencing factors refer to the key variables that cause changes in the dynamic power consumption of a chip, such as workload, clock frequency, supply voltage, and chip process corner. It is important to know that the chip process corner of the test chip affects both the static power consumption and the dynamic power consumption of the chip.

[0037] In this embodiment, factors affecting the static power consumption of a chip can be determined based on the leakage principle of the chip transistor, such as junction temperature, supply voltage, and chip process corner, i.e., static power consumption influencing factors. Furthermore, factors that can affect the dynamic power consumption of a chip can be identified based on the known crystal switching principle, such as service load, clock frequency, supply voltage, and chip process corner, i.e., dynamic power consumption influencing factors.

[0038] Furthermore, after identifying the chip model for which power consumption estimation is required, a sample chip of the same model can be used as the test chip.

[0039] In step S102 of some embodiments, the chip static power consumption refers to the base power consumption generated by transistor leakage when the chip is in an idle state.

[0040] In this embodiment, the static power consumption of the test chip can be calculated using the controlled variable method. Specifically, the test chip is adjusted to an idle state, i.e., the running module is stopped, to ensure that no dynamic power consumption is generated. Then, based on the static power consumption influencing factors, the combination of static influencing factors is determined. For example, when it is necessary to measure the impact of junction temperature on the test chip, the data of factors such as power supply voltage and chip process corner can be kept unchanged, and only the junction temperature data can be changed. The static power consumption of the test chip for each combination of static influencing factors can be recorded, and the corresponding static power consumption of the chip when the junction temperature factor is adjusted can be obtained. Similarly, by keeping the data of junction temperature and chip process corner constant, and only changing the power supply voltage, the corresponding static power consumption of the chip when the power supply voltage changes can be obtained. By keeping the data of junction temperature and power supply voltage constant, and only changing the chip process corner, the corresponding static power consumption of the chip when the chip process corner is adjusted can be obtained.

[0041] In step S103 of some embodiments, the static factor power consumption relationship function refers to a mathematical expression relating the chip's static power consumption to the factors influencing static power consumption.

[0042] In this embodiment, after determining the relationship between each static power consumption influencing factor and the chip's static power consumption, a target function can be selected from a pre-built function database based on the relationship between each static power consumption influencing factor and the chip's static power consumption to roughly represent the relationship between the static power consumption influencing factors and the chip's static power consumption. Furthermore, by using each static power consumption influencing factor and its corresponding chip static power consumption, the target function can be fitted to clarify the specific value of each function coefficient in the target function, thereby transforming the target function into a specific static factor power consumption relationship function.

[0043] In step S104 of some embodiments, chip dynamic power consumption refers to the additional power consumption generated when the chip functional module is in operation.

[0044] In this embodiment, power domain analysis can be performed on each functional module of the test chip to determine the power domain configuration of each functional module. Then, based on the power domain configuration, different processing can be performed on the test chip to obtain the dynamic power consumption of the chip corresponding to different power domain configurations.

[0045] For details, please refer to Figure 2 In some embodiments, step S104 may include, but is not limited to, steps S201 to S204: Step S201: Perform functional module power domain analysis on the test chip to obtain the module power domain configuration, wherein the module power domain configuration includes module shared power domain configuration or module independent power domain configuration. Step S202: Based on the independent power domain configuration of the module, the factors affecting static power consumption and the factors affecting dynamic power consumption, the power consumption of the test chip is directly read to obtain the dynamic power consumption of the independent module of the chip. Step S203: Based on the module shared power domain configuration, static power consumption influencing factors and dynamic power consumption influencing factors, the power consumption difference of the test chip is read to obtain the dynamic power consumption of the chip shared module. Step S204: Combine the dynamic power consumption of the chip's independent modules and the dynamic power consumption of the chip's shared modules to obtain the chip's dynamic power consumption.

[0046] In step S201 of some embodiments, the module power domain type refers to the type of power domain to which the functional module in the test chip belongs. The module power domain type includes the module independent power domain type and the module shared power domain type. The module independent power domain type means that each functional module in the test chip can occupy a power supply independently and does not need to share a power supply with other functional modules. The module shared power domain type means that multiple functional modules in the test chip share a power supply.

[0047] In this embodiment, by reading the power management documentation, schematic diagram, and other information of the test chip, the power domain type of each functional module can be determined, i.e., the power domain form of the module. In addition, the power domain structure of the test chip can be analyzed by reading the chip's power management register or detecting the power rail connection relationship, thereby obtaining the power domain form of the module.

[0048] In step S202 of some embodiments, if the module power domain configuration of the functional module in the test chip is a module-independent power domain configuration, the dynamic power consumption test scheme of this type of functional module in the test chip can be determined by controlling variables based on the module-independent power domain configuration and the above-mentioned static power consumption influencing factors and dynamic power consumption influencing factors. Furthermore, the dynamic power consumption of this type of functional module in the test chip can be calculated based on the dynamic power consumption test scheme of this type of functional module in the module-independent power domain configuration, thereby obtaining the dynamic power consumption of the chip-independent module.

[0049] For details, please refer to Figure 3 In some embodiments, step S202 may include, but is not limited to, steps S301 to S302: Step S301: Based on the module's independent power domain configuration, static power consumption influencing factors, and dynamic power consumption influencing factors, determine the independent module's dynamic power consumption test scheme. Step S302: Based on the chip dynamic power consumption test scheme, perform dynamic power consumption test on the test chip to obtain the dynamic power consumption of the chip's independent modules.

[0050] In step S301 of some embodiments, the independent module dynamic power consumption test scheme refers to the specific execution plan for calculating the dynamic power consumption of a module when the functional module in the test chip is in the form of an independent power domain.

[0051] In this embodiment of the application, when the test chip is in the form of a module independent power domain, the frequency power consumption impact test scheme and the load power consumption impact test scheme can be generated by controlling the values ​​of static power consumption impact factors, service load and clock frequency impact factors, respectively. Furthermore, by merging the frequency power consumption impact test scheme and the load power consumption impact test scheme, an independent module dynamic power consumption test scheme can be obtained.

[0052] For details, please refer to Figure 4 In some embodiments, the factors affecting dynamic power consumption include service load factors and clock frequency factors, and step S301 may include, but is not limited to, steps S401 to S405: Step S401: Based on the static power consumption influencing factors, freeze the module influencing factor values ​​of the test chip to obtain the fixed values ​​of the chip's static factors. Step S402: Based on the module's independent power domain configuration, freeze the values ​​of factors affecting service load to obtain fixed values ​​for service load, and freeze the values ​​of factors affecting clock frequency to obtain fixed values ​​for clock frequency. Step S403: Based on the fixed values ​​of chip static factors and fixed values ​​of service load, generate a test plan for the impact of frequency power consumption. Step S404: Based on the fixed values ​​of chip static factors and clock frequency, generate a test plan for the impact of load power consumption. Step S405: The frequency power consumption impact test scheme and the load power consumption impact test scheme are merged to obtain an independent module dynamic power consumption test scheme.

[0053] In step S401 of some embodiments, the fixed value of chip static factors refers to the specific value when freezing the values ​​of static power consumption influencing factors such as junction temperature, supply voltage, and chip process corner.

[0054] In this embodiment of the application, a set of reference values ​​can be arbitrarily selected as fixed values ​​for static power consumption influencing factors, or a set of reference values ​​can be selected as fixed values ​​for static power consumption influencing factors according to the test target, such as junction temperature 25°C, power supply voltage 1.0V, chip process angle TT, etc. Specifically, the values ​​of static power consumption influencing factors can be fixed by environmental control equipment such as constant temperature chamber and power management tools.

[0055] In step S402 of some embodiments, the factors affecting the service load can be variables that reflect the amount of service processed by the test chip, such as CPU task utilization, ISP image pixel processing volume, etc.

[0056] Clock frequency can be a variable that reflects the operating speed of the chip being tested, such as the operating frequency of DDR memory or the core frequency of the CPU.

[0057] In this embodiment of the application, when the power domain of the functional module in the test chip is in the form of an independent power domain, the parameter values ​​of the service load influencing factors can be fixed to obtain a fixed service load value, or the parameter values ​​of the clock frequency influencing factors can be fixed to obtain a fixed clock frequency value.

[0058] In steps S403 and S404 of some embodiments, the frequency power consumption impact test scheme refers to a scheme that tests the relationship between the clock frequency impact factor and the dynamic power consumption of the chip when the static power consumption impact factor and the service load impact factor of the test chip are kept constant, and only the clock frequency impact factor is changed. For example, the junction temperature is fixed at 25°C, the power supply voltage is fixed at 1.0V, and the service load is fixed at 50%, and the dynamic power consumption of the chip's independent modules at frequencies of 1GHz, 2GHz, and 3GHz is tested respectively.

[0059] The load power consumption impact test scheme refers to a scheme that tests the relationship between the static power consumption impact factors and the clock frequency impact factors of the test chip while keeping the static power consumption impact factors and clock frequency impact factors constant, and only changing the service load impact factors. For example, the junction temperature is fixed at 25℃, the power supply voltage is fixed at 1.0V, and the clock frequency is fixed at 2GHz, and the dynamic power consumption of the chip's independent modules is tested under 20%, 30%, and 40% load respectively.

[0060] In this embodiment of the application, when the fixed values ​​of the chip's static factors are combined with the fixed values ​​of the service load, a test scheme for adjusting the clock frequency to obtain different dynamic power consumption of the chip can be generated, namely, a frequency power consumption impact test scheme. When the fixed values ​​of the chip's static factors are combined with the fixed values ​​of the clock frequency, a test scheme for adjusting the service load to obtain different dynamic power consumption of the chip can be generated, namely, a load power consumption impact test scheme.

[0061] In step S405 of some embodiments, by storing the above-mentioned frequency power consumption impact test scheme and load power consumption impact test scheme into a blank set, the two schemes can be merged to form an independent module dynamic power consumption test scheme for functional modules in the test chip whose module power domain form is a module independent power domain form.

[0062] Steps S401 to S405, as illustrated in this embodiment, obtain fixed values ​​by freezing the values ​​of static power consumption influencing factors. This establishes a stable static environmental benchmark for testing the dynamic power consumption of functional modules in the independent power domain configuration of the chip, thereby avoiding interference from fluctuations in static power consumption influencing factors on the dynamic power consumption test results of the functional modules and ensuring the accuracy of power consumption data. Next, the values ​​of service load or clock frequency influencing factors are frozen under the independent power domain configuration, providing controllable conditions for single-variable testing. This ensures that the impact of clock frequency and service load influencing factors on the chip's dynamic power consumption can be analyzed separately, further... Based on fixed values ​​of chip static factors and fixed values ​​of service load, a test scheme for the impact of frequency power consumption is generated. Based on fixed values ​​of chip static factors and fixed values ​​of clock frequency, a test scheme for the impact of load power consumption is generated. This allows for precise focus on the correlation between a single dynamic power consumption influencing factor variable and dynamic power consumption during the dynamic power consumption test of the chip, avoiding the confusion caused by multiple dynamic power consumption influencing factors being tested simultaneously. Finally, the frequency power consumption impact test scheme and the load power consumption impact test scheme are merged to obtain an independent module dynamic power consumption test scheme, ensuring the comprehensiveness of the independent module dynamic power consumption test scheme, thereby improving the accuracy of chip power consumption estimation.

[0063] In step S302 of some embodiments, after clarifying the independent module dynamic power consumption test scheme, the dynamic power consumption of the functional module under different dynamic power consumption influencing factors can be recorded according to the variable control method provided in the independent module dynamic power consumption test scheme, so as to obtain the chip independent module dynamic power consumption. Specifically, according to the independent module dynamic power consumption test scheme, the parameters of the static power consumption influencing factors can be set to fixed values ​​first, for example, the junction temperature is fixed at 50°C and the voltage is fixed at 1.0V. Then, the parameters of some factors in the dynamic power consumption influencing factors are set to fixed values, for example, the service load influencing factor is fixed at 20%. Further, according to the parameter gradient of the dynamic power consumption influencing factors, for example, the parameter gradient of the clock frequency influencing factor from 1GHz to 3GHz, the only adjustable dynamic power consumption influencing factor can be adjusted to obtain the chip dynamic power consumption corresponding to the dynamic power consumption influencing factors under different parameter gradients. Finally, by changing the dynamic power consumption influencing factors that need to be fixed and the dynamic power consumption influencing factors that need to be adjusted, the chip independent module dynamic power consumption corresponding to each dynamic power consumption influencing factor can be obtained.

[0064] Steps S301 to S302 shown in the embodiments of this application, by combining the independent power domain configuration of the module, static power consumption influencing factors, and dynamic power consumption influencing factors, determine the independent module dynamic power consumption test scheme. This allows the independent module dynamic power consumption test scheme to accurately adapt to different dynamic power consumption influencing factors, and can avoid errors in the calculation of the chip's independent module dynamic power consumption caused by test logic confusion or parameter omissions. Furthermore, based on the independent module dynamic power consumption test scheme, dynamic power consumption tests are performed on the functional modules with independent power domain configurations in the test chip to obtain the chip's independent module dynamic power consumption, thereby improving the accuracy and reliability of the chip's independent module dynamic power consumption.

[0065] In step S203 of some embodiments, when the test chip is in the module shared power domain mode, the power consumption value obtained when reading the power consumption of the test chip is the sum of the power consumption of all functional modules in the test chip that use the shared power domain. When the test chip is in the module shared power domain mode, the power consumption of any one functional module among the functional modules using the shared power domain cannot be obtained directly using the power consumption reading method. Therefore, based on the static power consumption influencing factors and the dynamic power consumption influencing factors, dynamic power consumption test can be performed on the set of functional modules sharing the same power domain in the test chip to obtain the module dynamic power consumption set. Furthermore, by merging the power consumption in the module dynamic power consumption set, the dynamic power consumption of the chip shared module can be obtained.

[0066] For details, please refer to Figure 5 In some embodiments, the test chip includes a set of shared power function modules, and step S203 may include, but is not limited to, steps S501 to S502: Step S501: Based on the shared power domain form, static power consumption influencing factors and dynamic power consumption influencing factors, perform dynamic power consumption test on the shared power functional module set to obtain the module dynamic power consumption set. Step S502: Merge the dynamic power consumption sets of the modules to obtain the dynamic power consumption of the chip-shared modules.

[0067] In step S501 of some embodiments, the shared power functional module set refers to the whole of all functional modules in the test chip that are in the same shared power domain. For example, if the CPU functional module, ISP functional module and GPU functional module in the test chip share the same power domain, then the shared power functional module set can be (CPU, ISP, GPU).

[0068] The module dynamic power consumption set refers to the summary of dynamic power consumption data of each module obtained after performing dynamic power consumption tests on each module in the shared power function module set individually.

[0069] In this embodiment, the static factors of the shared power functional modules can be frozen to obtain fixed values. Then, the functional modules other than those requiring dynamic power consumption testing are adjusted to a stopped state, and the dynamic power consumption of the modules undergoing dynamic power consumption testing can be tested. Further, the values ​​of the modules that have undergone dynamic power consumption testing are frozen to fixed values, and a designated module is selected from the functional modules that have not undergone dynamic power consumption testing according to the dynamic power consumption testing order of the modules to obtain the dynamic power consumption of the functional module. This process is repeated until all functional modules sharing the same power domain have undergone dynamic power consumption testing, and then the dynamic power consumption of all functional modules can be merged into a module dynamic power consumption set.

[0070] For details, please refer to Figure 6 In some embodiments, the shared power function module set includes the function module to be tested and the silent function module, and step S501 may include, but is not limited to, steps S601 to S606: Step S601: Based on the static power consumption influencing factors, freeze the module influencing factor values ​​of the shared power supply functional module set to obtain fixed values ​​of module static factors; Step S602: Adjust the module state of the silent function module to obtain the module silent state; Step S603: Based on the fixed values ​​of the module's static factors and the module's silent state, perform dynamic power consumption testing on the functional module to be tested to obtain the correlation between the module's dynamic influencing factors and dynamic power consumption. Step S604: Freeze the dynamic factor values ​​of the functional module to be tested to obtain the fixed values ​​of the module's dynamic factors, and calculate the dynamic power consumption of the first module based on the fixed values ​​of the module's dynamic factors and the correlation between the module's dynamic influencing factors and dynamic power consumption. Step S605: Based on the fixed values ​​of the module's static factors and the fixed values ​​of the module's dynamic factors, perform dynamic power consumption calculation on the silent function module to obtain the dynamic power consumption of the second module. Step S606: Combine the dynamic power consumption of the first module and the dynamic power consumption of the second module to obtain a set of module dynamic power consumption.

[0071] In step S601 of some embodiments, the fixed value of the module static factor refers to the specific value obtained after freezing the static power consumption influencing factors of the power domain of the test chip corresponding to the set of shared power function modules.

[0072] In this embodiment of the application, the method for freezing the static power consumption influencing factors of the shared power function module set is similar to the method of step S401 above, so it will not be described in detail.

[0073] In step S602 of some embodiments, the silent function module refers to other modules in the shared power function module set that need to remain in a non-operating state when testing the "function module to be tested". For example, if the shared power function module set is (CPU, GPU, ISP) and the module to be tested is CPU, then the silent function module can be GPU or ISP.

[0074] The module silent state refers to the state reached by the silent function module after state adjustment, in which there is no dynamic switching action and only static power consumption. It should be noted that when the module is in silent state, the module's service load influence factor and clock frequency influence factor are both 0.

[0075] In this embodiment of the application, the silent function module can be adjusted from the running state to a state with no dynamic switching action and only static power consumption through the module control interface in the test chip, i.e., the module silent state. Specifically, this can be achieved by stopping the task scheduling of the silent function module, turning off the clock signal of the silent function module, and clearing the service load of the silent function module.

[0076] In step S603 of some embodiments, the relationship between the dynamic influencing factors of the module and the dynamic power consumption refers to the mapping relationship between the dynamic influencing factors of each functional module under test in the shared power functional module set and the dynamic power consumption of the functional module under test.

[0077] In this embodiment, under the condition that the static factors of the module are fixed and the module is in a silent state, the total power consumption obtained by the test of the functional module under test is the sum of the static power consumption of the power domain of the test chip and the dynamic power consumption of the functional module under test. Therefore, the dynamic power consumption of the functional module under test can be obtained by subtracting the static power consumption of the power domain of the test chip from the power consumption data read in this state. Furthermore, the mapping relationship between the dynamic influencing factors of each functional module under test in the shared power functional module set and the dynamic power consumption of the functional module under test can be calculated based on the dynamic power consumption read in this state, that is, the correlation between the module dynamic influencing factors and the dynamic power consumption.

[0078] In this embodiment of the application, under the condition that the static factors of the module are fixed and the module is in a silent state, the total power consumption obtained by the test of the functional module under test is the sum of the static power consumption of the power domain of the test chip and the dynamic power consumption of the functional module under test. Therefore, the dynamic power consumption of the functional module under test, i.e. the dynamic power consumption of the first module, can be obtained by subtracting the static power consumption of the power domain of the test chip from the power consumption data read in this state.

[0079] In step S604 of some embodiments, the fixed value of the module dynamic factor refers to the specific value obtained after freezing the value of the dynamic power consumption influencing factors of the functional module to be tested. For example, when the functional module to be tested is a CPU, the fixed value of the module dynamic factor can be a set of fixed parameters such as a CPU workload of 50% and a clock frequency of 2GHz.

[0080] The first module's dynamic power consumption refers to the result obtained by calculating the dynamic power consumption of the functional module under test when the silent functional module is in a silent state.

[0081] In this embodiment of the application, after obtaining the correlation between the dynamic influencing factors and the dynamic power consumption of the module, the operating state of the functional module to be tested can be maintained, and the dynamic power consumption influencing factors of the functional module to be tested can be fixed to any value, that is, the fixed value of the module dynamic factors. Then, based on the fixed value of the module dynamic factors and the correlation between the module dynamic influencing factors and the dynamic power consumption, the first module dynamic power consumption of the functional module to be tested can be calculated.

[0082] In step S605 of some embodiments, the second module dynamic power consumption refers to the result obtained by performing dynamic power consumption calculation on the silent functional module after the dynamic power consumption influencing factors of the functional module under test are fixed.

[0083] In this embodiment, the dynamic power consumption of the functional module under test under the fixed values ​​of the module's static and dynamic factors can be determined first based on the fixed values ​​of the module's static and dynamic factors. Secondly, through dynamic power consumption testing, the total power consumption of the power domain of the functional module under test and the silent functional module under the fixed values ​​of the module's static and dynamic factors can be read. Finally, by subtracting the dynamic power consumption of the functional module under test under the fixed values ​​of the module's dynamic factors and the static power consumption of the power domain of the test chip from the total power consumption of the power domain, the actual dynamic power consumption of the silent functional module, i.e., the dynamic power consumption of the second module, can be obtained.

[0084] For details, please refer to Figure 7 In some embodiments, step S605 may include, but is not limited to, steps S701 to S703: Step S701: Determine the incremental dynamic power consumption of the module to be tested based on the fixed values ​​of the module's static factors and the fixed values ​​of the module's dynamic factors. Step S702: Based on the fixed values ​​of the module's static factors and the fixed values ​​of the module's dynamic factors, calculate the power consumption of the silent function module to obtain the total incremental power consumption of the module. Step S703: Perform a difference calculation on the total incremental power consumption of the module, the incremental dynamic power consumption of the module, and the static power consumption of the chip to obtain the dynamic power consumption of the second module.

[0085] In step S701 of some embodiments, the incremental dynamic power consumption of the module refers to the dynamic power consumption increment of the functional module under test under the conditions of fixed values ​​of module static factors and fixed values ​​of module dynamic factors.

[0086] In this embodiment, the dynamic power consumption of the functional module to be tested, i.e., the incremental dynamic power consumption of the module, can be determined based on the above-mentioned correlation between the dynamic influencing factors and the dynamic power consumption of the module, under the condition that the static factors of the module are fixed and the dynamic factors of the module are fixed.

[0087] In step S702 of some embodiments, the total incremental power consumption of the module refers to the total dynamic power consumption caused by the functional module under test and the silent functional module under the conditions of fixed values ​​of module static factors and fixed values ​​of module dynamic factors.

[0088] In this embodiment, the total dynamic power consumption of the tested functional module and the silent functional module can be obtained by directly reading the data from the power consumption measuring instrument, under the conditions of fixed values ​​of module static factors and fixed values ​​of module dynamic factors, i.e., the total incremental power consumption of the module.

[0089] In step S703 of some embodiments, by subtracting the module's incremental dynamic power consumption and the chip's static power consumption from the module's total incremental power consumption, the dynamic power consumption of the silent function module under the condition of fixed values ​​for module static factors and fixed values ​​for module dynamic factors can be obtained, namely, the dynamic power consumption of the second module.

[0090] Steps S701 to S703, as illustrated in the embodiments of this application, determine the incremental dynamic power consumption of the functional module to be tested based on the fixed values ​​of the module's static factors and dynamic factors. Then, based on the fixed values ​​of the module's static factors and dynamic factors, perform power consumption testing on the silent functional module to obtain the total incremental power consumption of the module. Finally, perform a difference calculation on the total incremental power consumption of the module, the incremental dynamic power consumption of the module, and the static power consumption of the chip to obtain the second module dynamic power consumption. This solves the problem of power consumption coupling of various functional modules in the module shared power domain configuration, thereby improving the accuracy of the dynamic power consumption test results of each functional module.

[0091] In step S606 of some embodiments, the dynamic power consumption of the first module and the dynamic power consumption of the second module are embedded into a pre-built blank set, thereby realizing the power consumption merging of the dynamic power consumption of the first module and the dynamic power consumption of the second module, and thus obtaining the module dynamic power consumption set.

[0092] Steps S601 to S606, as illustrated in this embodiment, freeze the module influencing factor values ​​of the shared power supply functional module set according to the static power consumption influencing factors, obtaining fixed values ​​for the module static factors. This ensures that the dynamic power consumption test is not affected by the static power consumption influencing factors, thereby improving the accuracy of the dynamic power consumption test. Furthermore, the module state of the silent functional module is adjusted to obtain the module silent state. Based on the fixed values ​​of the module static factors and the module silent state, the dynamic power consumption of the functional module to be tested is calculated to obtain the dynamic power consumption of the first module. This avoids interference from the dynamic power consumption of other functional modules within the test chip, making the dynamic power consumption of the first module more accurate. The first module's dynamic power consumption is more accurate. Secondly, the dynamic factor values ​​of the functional module under test are frozen to obtain fixed values ​​for the module's dynamic factors. Based on the fixed values ​​of the module's static factors and dynamic factors, the dynamic power consumption of the silent functional module is calculated to obtain the dynamic power consumption of the second module. This resolves the coupling between various functional modules in the shared power domain configuration, thereby improving the accuracy of chip power consumption estimation. Finally, the dynamic power consumption of the first module and the dynamic power consumption of the second module are merged to obtain a set of module dynamic power consumption, ensuring the integrity of the dynamic power consumption test results of the tested chip and thus improving the accuracy of chip power consumption estimation.

[0093] In step S502 of some embodiments, the dynamic power consumption of all modules in the module dynamic power consumption set is accumulated to obtain the chip shared module dynamic power consumption. For example, if the module dynamic power consumption set includes the dynamic power consumption of the CPU module, ISP module, and GPU module, where the dynamic power consumption of the CPU module is 2.3W, the dynamic power consumption of the ISP module is 1.1W, and the dynamic power consumption of the GPU module is 3.2W, then the chip dynamic power consumption can be 2.3W + 1.1W + 3.2W = 6.6W.

[0094] Steps S501 to S502, as shown in the embodiments of this application, involve performing dynamic power consumption tests on the set of shared power functional modules based on the shared power domain configuration, static power consumption influencing factors, and dynamic power consumption influencing factors. This yields a set of dynamic power consumption for each module, which is then merged to obtain the dynamic power consumption of the chip-shared modules. This reduces power consumption interference between various functional modules within the test chip under the shared power domain configuration, thereby ensuring that the dynamic power consumption of each functional module is its true and valid power consumption data, thus improving the accuracy of chip power consumption estimation.

[0095] In step S204 of some embodiments, after obtaining the dynamic power consumption of each functional module in the test chip, the dynamic total power consumption of the test chip can be obtained by merging the dynamic power consumption of each functional module. That is, the chip dynamic power consumption of the chip-independent module of the functional module whose module power domain mode is module-independent power domain mode is merged with the chip-shared module dynamic power consumption of the functional module whose module power domain mode is module-shared power domain mode.

[0096] Steps S201 to S204 of this embodiment involve analyzing the power domain of the test chip to determine the power domain configuration of each functional module within the test chip. This allows for accurate matching of the dynamic power consumption calculation method. Furthermore, when the test chip contains functional modules with independent power domain configurations, the power consumption data of the functional modules under different dynamic power consumption influencing factors is directly read based on the aforementioned static power consumption influencing factors. This is the dynamic power consumption of the independent modules. When the test chip contains functional modules with shared power domain configurations, the dynamic power consumption of the shared modules is read based on the aforementioned static power consumption influencing factors using a difference calculation method. Finally, the dynamic power consumption of the independent modules and the dynamic power consumption of the shared modules are combined to obtain the dynamic power consumption of the chip. This achieves dynamic power consumption calculation for each functional module in the test chip under different power domain configurations, ensuring the accuracy of the chip's dynamic power consumption.

[0097] In step S105 of some embodiments, the dynamic factor power consumption relationship function refers to a mathematical expression relating the chip's dynamic power consumption to the factors influencing dynamic power consumption.

[0098] In this embodiment of the application, a fitting method can be used to construct a functional relationship between dynamic power consumption influencing factors and chip dynamic power consumption, wherein the dynamic power consumption influencing factors are used as independent variables and the corresponding chip dynamic power consumption is used as the dependent variable.

[0099] In step S106 of some embodiments, the chip power consumption estimation model refers to a model that can output the estimated power consumption of the chip based on the actual input data of the chip.

[0100] In this embodiment of the application, a chip power consumption estimation function can be obtained by merging the static factor power consumption relationship function and the dynamic factor power consumption relationship function. Furthermore, by encapsulating the chip power consumption estimation function into a model, a chip power consumption estimation model can be obtained.

[0101] In step S107 of some embodiments, the target chip refers to a chip whose working conditions and operating business scenarios are preset and whose power consumption needs to be estimated. It should be noted that the target chip and the test chip are the same model of chip.

[0102] Chip power estimation refers to the total power consumption of a target chip calculated by a chip power estimation model based on the actual operating factors of the target chip. For example, when the actual operating factors of the target chip include junction temperature of 50°C, voltage of 1.0V, CPU utilization of 30%, and DDR frequency of 1.6GHz, the chip power estimation can be the total power consumption data output by the chip power estimation model after inputting the above data into the chip power estimation model.

[0103] In this embodiment, the operating environment of the target chip can be obtained by collecting parameters such as junction temperature, power supply voltage, chip process corner, CPU load, and CPU frequency in the actual application scenario. Furthermore, by substituting the collected operating environment into the chip power consumption estimation model, the power consumption data of the target chip in the operating environment can be obtained, i.e., the chip estimated power consumption.

[0104] This application provides a clear direction for chip power consumption estimation by obtaining the static and dynamic power consumption influencing factors of the test chip, thus improving the efficiency of chip power consumption estimation. Furthermore, based on the static power consumption influencing factors, static power consumption calculation is performed on the test chip to obtain the chip's static power consumption. Then, based on the static power consumption influencing factors and the chip's static power consumption, a relationship function is constructed to obtain a static factor power consumption relationship function. This avoids the influence of dynamic power consumption influencing factors on the static power consumption test of the test chip, thereby improving the accuracy of the static factor power consumption relationship function. Secondly, based on the static and dynamic power consumption influencing factors, dynamic power consumption calculation is performed on the test chip to obtain the chip's dynamic power consumption, and... A relationship function is constructed based on the influencing factors of dynamic power consumption and the dynamic power consumption of the chip, resulting in a dynamic factor power consumption relationship function. This ensures that the dynamic power consumption measurement of the test chip considers both the influencing factors of dynamic power consumption and the cross-influence of static power consumption factors, making the dynamic factor power consumption relationship function more consistent with actual physical laws and thus improving its accuracy. Finally, based on the static factor power consumption relationship function and the dynamic factor power consumption relationship function, a chip power consumption estimation model is constructed. Based on the chip power consumption estimation model, the power consumption of a preset target chip is estimated, resulting in the estimated chip power consumption. This reduces the chip power consumption estimation time and improves the efficiency and accuracy of chip power consumption estimation.

[0105] Please see Figure 8 This application also provides a chip power consumption estimation device that can implement the above-described chip power consumption estimation method. The device includes: The influencing factor acquisition module 801 is used to acquire the static power consumption influencing factors and dynamic power consumption influencing factors of the test chip; The static power consumption calculation module 802 is used to calculate the static power consumption of the test chip based on the factors affecting static power consumption, and obtain the static power consumption of the chip. The static function construction module 803 is used to construct a relational function based on the static power consumption influencing factors and the chip's static power consumption, and obtain the static factor power consumption relational function. The dynamic power consumption calculation module 804 is used to perform dynamic power consumption calculation on the test chip based on static power consumption influencing factors and dynamic power consumption influencing factors, so as to obtain the dynamic power consumption of the chip. The dynamic function construction module 805 is used to construct a relationship function based on the dynamic power consumption influencing factors and the chip's dynamic power consumption, and obtain the dynamic factor power consumption relationship function. The power consumption model construction module 806 is used to construct a chip power consumption estimation model based on the power consumption relationship function of static factors and the power consumption relationship function of dynamic factors. The chip power consumption estimation module 807 is used to estimate the power consumption of a preset target chip based on a chip power consumption estimation model, and obtain the chip estimated power consumption.

[0106] The specific implementation of this chip power consumption estimation device is basically the same as the specific implementation of the chip power consumption estimation method described above, and will not be repeated here.

[0107] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the aforementioned chip power consumption estimation method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0108] Please see Figure 9 , Figure 9 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 902 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902 and is called and executed by the processor 901 using the chip power consumption estimation method of the embodiments of this application. The input / output interface 903 is used to implement information input and output; The communication interface 904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 905 transmits information between various components of the device (e.g., processor 901, memory 902, input / output interface 903, and communication interface 904); The processor 901, memory 902, input / output interface 903, and communication interface 904 are connected to each other within the device via bus 905.

[0109] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described chip power consumption estimation method.

[0110] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0111] The chip power consumption estimation method, chip power consumption estimation device, electronic device, and storage medium provided in this application embodiment obtain the static power consumption influencing factors and dynamic power consumption influencing factors of the test chip. Based on the static power consumption influencing factors, the static power consumption of the test chip is calculated to obtain the static power consumption of the chip. Based on the static power consumption influencing factors and the static power consumption of the chip, a relational function is constructed to obtain the static factor power consumption relational function. Based on the static power consumption influencing factors and the dynamic power consumption influencing factors, the dynamic power consumption of the test chip is calculated to obtain the dynamic power consumption of the chip. Based on the dynamic power consumption influencing factors and the dynamic power consumption of the chip, a relational function is constructed to obtain the dynamic factor power consumption relational function. Based on the static factor power consumption relational function and the dynamic factor power consumption relational function, a chip power consumption estimation model is constructed. Based on the chip power consumption estimation model, the power consumption of a preset target chip is estimated to obtain the estimated chip power consumption.

[0112] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0113] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0114] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0115] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0116] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0117] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, or indirect coupling or communication connection between the apparatus or units, and may be electrical, mechanical, or other forms.

[0119] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0120] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0121] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0122] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for estimating chip power consumption, characterized in that, The method includes: Obtain the factors affecting the static power consumption and dynamic power consumption of the test chip; Based on the aforementioned factors affecting static power consumption, the static power consumption of the test chip is calculated to obtain the chip's static power consumption. Based on the static power consumption influencing factors and the chip's static power consumption, a relationship function is constructed to obtain the static factor power consumption relationship function; Based on the static power consumption influencing factors and the dynamic power consumption influencing factors, the dynamic power consumption of the test chip is calculated to obtain the chip's dynamic power consumption. Based on the dynamic power consumption influencing factors and the chip's dynamic power consumption, a relationship function is constructed to obtain the dynamic factor power consumption relationship function; Based on the static factor power consumption relationship function and the dynamic factor power consumption relationship function, a chip power consumption estimation model is constructed; Based on the chip power consumption estimation model, power consumption is estimated for a preset target chip to obtain the chip estimated power consumption. The step of calculating the dynamic power consumption of the test chip based on the static power consumption influencing factors and the dynamic power consumption influencing factors to obtain the chip's dynamic power consumption includes: The test chip is analyzed by functional module power domain to obtain the module power domain form, wherein the module power domain form includes module shared power domain form and module independent power domain form. Based on the independent power domain configuration of the module, the static power consumption influencing factors and the dynamic power consumption influencing factors, the power consumption of the test chip is directly read to obtain the dynamic power consumption of the chip's independent module. Based on the shared power domain configuration of the module, the static power consumption influencing factors, and the dynamic power consumption influencing factors, the power consumption difference of the test chip is read to obtain the dynamic power consumption of the chip shared module. The dynamic power consumption of the chip is obtained by merging the dynamic power consumption of the independent modules of the chip and the dynamic power consumption of the shared modules of the chip.

2. The method according to claim 1, characterized in that, The process of directly reading the power consumption of the test chip based on the independent power domain configuration of the module, the static power consumption influencing factors, and the dynamic power consumption influencing factors, to obtain the dynamic power consumption of the chip's independent modules, includes: Based on the independent power domain configuration of the module, the static power consumption influencing factors, and the dynamic power consumption influencing factors, a dynamic power consumption test scheme for the independent module is determined. Based on the independent module dynamic power consumption test scheme, the test chip is subjected to dynamic power consumption test to obtain the independent module dynamic power consumption of the chip.

3. The method according to claim 2, characterized in that, The dynamic power consumption influencing factors include service load influencing factors and clock frequency influencing factors. The determination of the independent module dynamic power consumption test scheme based on the module's independent power domain configuration, the static power consumption influencing factors, and the dynamic power consumption influencing factors includes: Based on the static power consumption influencing factors, the module influencing factor values ​​of the test chip are frozen to obtain fixed values ​​of the chip's static factors. Based on the independent power domain configuration of the module, the values ​​of the factors affecting the service load are frozen to obtain fixed values ​​for the service load, and the values ​​of the factors affecting the clock frequency are frozen to obtain fixed values ​​for the clock frequency. Based on the fixed values ​​of the chip's static factors and the fixed values ​​of the service load, a test plan for the impact of frequency power consumption is generated. Based on the fixed values ​​of the chip's static factors and the fixed values ​​of the clock frequency, a test scheme for the impact of load power consumption is generated. The frequency power consumption impact test scheme and the load power consumption impact test scheme are combined to obtain the independent module dynamic power consumption test scheme.

4. The method according to claim 1, characterized in that, The test chip includes a set of shared power functional modules. Based on the shared power domain configuration of the modules, the static power consumption influencing factors, and the dynamic power consumption influencing factors, the test chip is subjected to power consumption difference readings to obtain the dynamic power consumption of the chip's shared modules, including: Based on the shared power domain configuration of the modules, the static power consumption influencing factors and the dynamic power consumption influencing factors, dynamic power consumption tests are performed on the shared power functional module set to obtain the module dynamic power consumption set. The dynamic power consumption sets of the modules are merged to obtain the dynamic power consumption of the chip shared modules.

5. The method according to claim 4, characterized in that, The shared power functional module set includes a functional module to be tested and a silent functional module. Based on the shared power domain configuration of the modules, the static power consumption influencing factors, and the dynamic power consumption influencing factors, dynamic power consumption testing is performed on the shared power functional module set to obtain a module dynamic power consumption set, including: Based on the static power consumption influencing factors, the module influencing factor values ​​of the shared power function module set are frozen to obtain fixed values ​​of module static factors; The module state of the silent function module is adjusted to obtain the module silent state; Based on the fixed values ​​of the static factors of the module and the silent state of the module, dynamic power consumption test is performed on the functional module to be tested to obtain the correlation between the dynamic influencing factors and dynamic power consumption of the module. The dynamic factor values ​​of the functional module to be tested are frozen to obtain fixed values ​​of the module's dynamic factors. Based on the fixed values ​​of the module's dynamic factors and the correlation between the module's dynamic influencing factors and dynamic power consumption, the dynamic power consumption of the first module is calculated. Based on the fixed values ​​of the static factors and the fixed values ​​of the dynamic factors of the module, the dynamic power consumption of the silent function module is calculated to obtain the dynamic power consumption of the second module. The dynamic power consumption of the first module and the dynamic power consumption of the second module are combined to obtain the dynamic power consumption set of the modules.

6. The method according to claim 5, characterized in that, The step of calculating the dynamic power consumption of the silent function module based on the fixed values ​​of the module's static factors and the fixed values ​​of the module's dynamic factors to obtain the dynamic power consumption of the second module includes: Based on the fixed values ​​of the module's static factors and the fixed values ​​of the module's dynamic factors, the incremental dynamic power consumption of the functional module to be tested is determined. Based on the fixed values ​​of the module's static factors and the fixed values ​​of the module's dynamic factors, the power consumption of the silent function module is calculated to obtain the module's total incremental power consumption. The dynamic power consumption of the second module is obtained by performing a difference calculation on the total incremental power consumption of the module, the incremental dynamic power consumption of the module, and the static power consumption of the chip.

7. A chip power consumption estimation device, applied to the chip power consumption estimation method as described in any one of claims 1-6, characterized in that, The device includes: The influencing factor acquisition module is used to acquire the static power consumption influencing factors and dynamic power consumption influencing factors of the test chip; The static power consumption calculation module is used to perform static power consumption calculation on the test chip based on the static power consumption influencing factors to obtain the chip's static power consumption. The static function construction module is used to construct a relationship function based on the static power consumption influencing factors and the static power consumption of the chip, so as to obtain the static factor power consumption relationship function; The dynamic power consumption calculation module is used to perform dynamic power consumption calculation on the test chip based on the static power consumption influencing factors and the dynamic power consumption influencing factors to obtain the chip's dynamic power consumption. The dynamic function construction module is used to construct a relationship function based on the dynamic power consumption influencing factors and the chip's dynamic power consumption, thereby obtaining a dynamic factor power consumption relationship function. The power consumption model construction module is used to construct a chip power consumption estimation model based on the static factor power consumption relationship function and the dynamic factor power consumption relationship function; The chip power consumption estimation module is used to estimate the power consumption of a preset target chip based on the chip power consumption estimation model, and obtain the chip estimated power consumption.

8. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the chip power consumption estimation method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the chip power consumption estimation method according to any one of claims 1 to 6.

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