A bridge device and method for AHB bus and PLB bus based on SoC platform
By introducing a bridging device between the AHB bus and the PLB bus on the SoC platform, the problem of poor compatibility between the two is solved, achieving high-performance, low-latency data transmission and improving system integration flexibility and the integration of industrial servo chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HE FEI SINO WEALTH ELECTRONICS LTD
- Filing Date
- 2026-03-04
- Publication Date
- 2026-06-05
AI Technical Summary
In industrial servo SOC chip design, the AHB bus and PLB bus have poor compatibility and high integration difficulty, and cannot be directly interconnected, especially due to significant differences in protocol, timing and electrical characteristics.
A bridging device for AHB bus and PLB bus based on SoC platform is provided, including a protocol conversion module, a clock domain crossing module, an address mapping module, a data buffer module and an error handling module. Protocol conversion and data transmission are realized through a protocol conversion state machine, supporting high-performance and low-latency data transmission.
It achieves seamless protocol conversion and efficient data transmission between AHB and PLB buses, improves system compatibility and IP core reuse capabilities, and enhances the system integration and competitiveness of chips in fields such as industrial servo systems.
Smart Images
Figure CN122152747A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer system bus design, and more specifically, to a bridging device and method for AHB bus and PLB bus based on a SoC platform. Background Technology
[0002] In System-on-Chip (SoC) design, the choice of bus architecture is crucial to system performance, power consumption, and peripheral integration. Common SoC bus specifications include the AMBA (Advanced Microcontroller Bus Architecture) protocol and the Core Connect protocol.
[0003] Due to its high performance and low power consumption, the AMBA bus is widely used in various SoC chip designs. In the industrial servo field, for monolithic integrated circuits (SoCs) with extremely high requirements for computing performance and integration, the system core often adopts the Advanced High-Performance Bus (AHB) in the AMBA bus architecture.
[0004] In reference designs and SoPCs for Xilinx FPGAs, the Processor Local Bus (PLB) under the Core Connect bus specification is often used as the core interconnect architecture. High-speed communication interface controllers such as PCIe and Ethernet controllers, widely used in industrial scenarios, typically have their IP cores designed based on the PLB bus and implemented on the FPGA platform. This necessitates an efficient bridging solution (i.e., an AHB-to-PLB bus bridge) in SoC designs for industrial servo applications to enable critical functions such as industrial Ethernet communication.
[0005] However, the AHB bus and PLB bus differ in protocol, timing, and electrical characteristics, posing significant technical challenges to directly interconnecting the two. For example, in terms of data transmission mechanisms, the AHB bus typically uses time-division multiplexing (TDM) to transmit addresses and data, while the PLB bus uses parallel transmission.
[0006] Therefore, in response to the interconnection requirements of AHB bus and PLB bus in industrial servo SOC chip design, and the problems of poor compatibility and high integration difficulty between the two in the existing technology, there is an urgent need for a new AHB bus and PLB bus bridging device and method to solve the bus protocol adaptation problem and improve system integration flexibility and transmission reliability. Summary of the Invention
[0007] The purpose of this invention is to provide a bridging device and method for AHB bus and PLB bus based on a SoC platform, which solves the problems of poor compatibility and high integration difficulty of AHB and PLB buses in existing SoC chip designs, and the inability to directly achieve interconnection.
[0008] To achieve the above objectives, the present invention provides a bridging device for AHB bus and PLB bus based on a SoC platform, including a protocol conversion module, a clock domain crossing module, an address mapping module, a data buffering module, and an error handling module: The protocol conversion module is connected to the AHB bus and the PLB bus respectively, and is used to convert the protocol signal of the AHB bus into the protocol signal of the PLB bus, and convert the response signal of the PLB bus into the response signal of the AHB bus. The clock domain crossing module is connected to the protocol conversion module and is used to synchronize the cross-clock domain signals of the AHB bus and PLB bus. The address mapping module is connected to the protocol conversion module and is used to realize the mapping and address decoding from the AHB address space to the PLB address space. The data caching module is connected to the protocol conversion module and is used to cache read / write requests from the AHB bus, data to be transmitted, and response data from the PLB bus. The error handling module, connected to the protocol conversion module, is used to detect and handle abnormalities during data transmission and generate corresponding error response signals.
[0009] In some embodiments, the protocol conversion module includes a protocol conversion state machine: The protocol conversion state machine is used to control the transmission process between the AHB and PLB buses by switching states, based on the request signals from the AHB bus and the response signals from the PLB bus.
[0010] In some embodiments, the protocol transition state machine includes at least an idle state and a transmission state; When an AHB master device initiates a read or write request through the AHB bus, the protocol transition state machine switches from the idle state to the transmission state.
[0011] In some embodiments, the protocol transition state machine further includes a waiting state: The protocol conversion state machine monitors the status signal of the AHB bus in real time during the transmission state. When the AHB bus status signal is detected to be in a busy state, the protocol conversion state machine switches from the transmission state to the waiting state.
[0012] In some embodiments, the protocol conversion state machine monitors the feedback response signal from the slave device on the PLB bus in real time during the transmission state; When the PLB slave device detects that it has completed processing the read or write request, the protocol transition state machine switches from the transmission state to the idle state.
[0013] In some embodiments, the protocol conversion module, in response to an AHB master device initiating a read or write request via the AHB bus, parses the corresponding AHB request signal and generates a PLB bus-compatible read or write request signal; and
[0014] The protocol conversion module receives the read response signal or write response signal returned by the PLB bus, converts it into an AHB bus-compatible response signal, and feeds it back to the AHB master device.
[0015] In some embodiments, the data caching module is implemented using a first-in-first-out (FIFO) structure or a dual-trigger synchronous structure.
[0016] In some embodiments, the bridging device further includes a data width adjustment module connected to the protocol conversion module, used to perform bit width expansion, truncation, alignment, or byte order adjustment on the data transmitted between the AHB bus and the PLB bus to adapt to data width differences.
[0017] In some embodiments, the bridging device further includes a clock and reset management module connected to the protocol conversion module, for providing clock signals and reset signals to each module.
[0018] In some embodiments, the bridging device further includes a configuration and performance optimization module connected to the protocol conversion module; The configuration and performance optimization module includes configurable registers for configuring operating modes, clock frequencies, or data width parameters, and for optimizing transmission performance through optimized caching mechanisms or pipelined bus technology.
[0019] To achieve the above objectives, the present invention provides a SoC system platform architecture, including: The AHB master device layer contains at least one AHB master device; AHB slave device layer, containing at least one AHB slave device; The PLB slave device layer includes at least one PLB slave device; AHB bus connects the AHB master device layer and the AHB slave device layer; The PLB bus is connected to the PLB slave device layer; and A bridging device is connected between the AHB bus and the PLB bus; The bridging device is the aforementioned bridging device between the AHB bus and the PLB bus based on the SoC platform, used to realize protocol conversion and data transmission between the AHB bus and the PLB bus.
[0020] To achieve the above objectives, the present invention provides a bridging method for the AHB bus and PLB bus based on a SoC platform, employing the aforementioned bridging device, and comprising the following steps: It parses the protocol signals of the AHB bus, converts them into PLB bus-compatible protocol signals, and manages the transmission process; Synchronization processing is performed on address, request, and data signals transmitted between the AHB bus clock domain and the PLB bus clock domain. Map the AHB address to the PLB address and cache the relevant requests and data; Check if the transmission is normal; If the transmission is detected as normal, the request completion response signal of the PLB bus is converted into a transmission normal response signal compatible with the AHB bus and fed back to the AHB master device. If a transmission error is detected, the error response signal of the PLB bus is converted into an AHB bus-compatible transmission error response signal and fed back to the AHB master device.
[0021] The bridging device and method for AHB and PLB buses based on the SoC platform provided by this invention achieves seamless protocol conversion and efficient data transmission between the two buses, AHB and PLB, through a protocol conversion state machine and a multi-module collaborative architecture design. This effectively improves system compatibility, enhances IP core reuse capabilities, and achieves high-performance, low-latency communication. Attached Figure Description
[0022] The above and other features, properties and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings and embodiments, in which the same reference numerals always denote the same features, wherein: Figure 1 A schematic diagram of the connection between the AHB bus and the PLB bus based on a SoC platform according to an embodiment of the present invention is disclosed; Figure 2 An internal functional architecture block diagram of a bridging device for AHB bus and PLB bus based on a SoC platform according to an embodiment of the present invention is disclosed. Figure 3 A block diagram of the signal data flow for a write request of a bridging device for the AHB bus and PLB bus based on a SoC platform according to an embodiment of the present invention is disclosed. Figure 4A signal data flow block diagram of a read request for a bridging device for AHB bus and PLB bus based on a SoC platform according to an embodiment of the present invention is disclosed. Figure 5 A step diagram of a bridging method for AHB bus and PLB bus based on a SoC platform according to an embodiment of the present invention is disclosed.
[0023] The meanings of the labels in the figures are as follows: 100 AHB main equipment layer; 101 CPUs; 102 DMA controller; 200 AHB from the device layer; 201 RAM; 202 GPIO controller; 20. A bridging device between AHB bus and PLB bus; 210 protocol conversion module; 220 Data Cache Module; 230 address mapping module; 240 data width adjustment module; 250 clock domains spanning modules; 260 clock and reset management module; 270 Error Handling Module; 280 configuration and performance optimization module; 291 AHB bus signals; 292 PLB bus signals; 300 PLBs from the equipment layer; 301 EtherCAT; 302 PCIe; 401 AHB bus; 402 PLB bus. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.
[0025] This invention relates to the field of computer system bus design, and particularly to a bridging scheme for implementing a high-performance, low-latency Advanced High-Performance Bus (AHB) to Processor Local Bus (PLB) in ARM processor systems. In some embodiments, this bridging scheme can be widely applied to various SoC chip architectures such as industrial servo and communication control, solving the system compatibility and scalability limitations caused by the differences in protocols, timing, and electrical characteristics between AHB and PLB buses, improving system integration flexibility, and achieving high-performance, low-latency data transmission.
[0026] This invention proposes a SoC system platform architecture, which includes an AHB master device layer, an AHB slave device layer, and a PLB slave device layer that work independently and collaboratively, as well as an AHB bus and a PLB bus that are adapted to each device layer respectively, and a bridging device is configured between the AHB bus and the PLB bus as the core hub for bus interconnection. The AHB master layer, AHB slave layer, and PLB slave layer can all be flexibly configured with device types and quantities according to the needs of actual industrial application scenarios. The bit width, clock frequency, and other parameters of the AHB bus and PLB bus can also be adjusted for adaptability. The bridging device is the AHB bus and PLB bus bridging device based on the SoC platform proposed in this invention. As a core functional component of this SoC system platform architecture, it undertakes key tasks such as protocol conversion, data transmission, clock domain synchronization, and error handling between the AHB master layer and the PLB slave layer, realizing seamless interconnection and high-performance data interaction between the AHB bus domain and the PLB bus domain.
[0027] Figure 1 A schematic diagram illustrating the connection between the AHB bus and PLB bus based on a SoC according to an embodiment of the present invention is disclosed, as follows: Figure 1 The SoC platform architecture shown may include an AHB master layer 100, an AHB slave layer 200, a PLB slave layer 300, and a bridge device 20 connecting the AHB bus and the PLB bus. The AHB master device layer 100 includes at least one AHB master device as the initiator of data transmission; Specifically, the AHB master device layer 100 may include multiple AHB master devices such as CPU 101 and DMA (Direct Memory Access) controller 102, which serve as the initiator of data transmission and initiate read and write requests through the AHB bus 401.
[0028] The AHB bus 401 connects the AHB master layer 100 and the AHB slave layer 200, and can support 32-bit, 64-bit or 128-bit data widths. It serves as a high-speed transmission channel between the AHB master and slave devices to meet the high bandwidth and low latency transmission requirements in industrial scenarios.
[0029] The AHB slave device layer 200 includes at least one AHB slave device; More specifically, the AHB slave layer 200 may include multiple AHB slave devices such as RAM 201 and GPIO (General Purpose Input / Output) controller 202.
[0030] The PLB bus 402 is connected to the PLB slave device layer 300 and can also support 32-bit, 64-bit or 128-bit data widths. It serves as a transmission channel between the bridging device 20 and the PLB slave device, adapting to the bus requirements of commonly used industrial communication interfaces.
[0031] The PLB slave device layer 300 includes at least one PLB slave device; More specifically, the PLB slave device layer 300 can include multiple PLB slave devices such as EtherCAT 301 and PCIe 302. EtherCAT refers to Ethernet for Control Automation Technology, a high-speed real-time industrial Ethernet fieldbus technology for industrial control, which is adapted to the high real-time communication requirements of industrial servo, motion control and other scenarios. PCIe refers to Peripheral Component Interconnect Express, a high-bandwidth, low-latency high-speed peripheral interconnect bus technology, which is adapted to the high-bandwidth transmission requirements of high-speed data acquisition and external device interconnection in industrial control.
[0032] In traditional SoC systems, upper-layer AHB master devices (such as CPU, DMA, etc.) and lower-layer PLB slave devices (such as EtherCAT, PCIe, etc.) cannot be directly interconnected due to differences in bus protocols, timing, and electrical characteristics.
[0033] like Figure 1 As shown, the present invention introduces a bridging device 20 into the SoC system to realize protocol conversion and data transmission between the AHB bus and the PLB bus, effectively breaking the compatibility barrier between the AHB and PLB buses.
[0034] The bridging device 20 is connected between the AHB bus 401 and the PLB bus 402, serving as a protocol conversion hub between the AHB bus 401 and the PLB bus 402, and can realize key functions such as address mapping, timing adjustment, data width matching and error handling.
[0035] In this architecture, the bridging device 20 plays a core role in protocol adaptation and data path conversion, thereby achieving high-performance, low-latency data transmission.
[0036] Figure 2 The internal functional architecture block diagram of a bridging device for AHB bus and PLB bus based on a SoC platform according to an embodiment of the present invention is disclosed, such as... Figure 2 As shown, the bridging device 20 for AHB bus and PLB bus based on a SoC platform proposed in this invention includes at least a protocol conversion module 210, a data buffer module 220, an address mapping module 230, a clock domain crossing module 250, and an error handling module 270, wherein: The protocol conversion module 210 is used to convert the protocol signal of the AHB bus into the protocol signal of the PLB bus, and to convert the response signal of the PLB bus into the response signal of the AHB bus. The clock domain crossing module 250 is used to synchronize the cross-clock domain signals of the AHB bus and the PLB bus. The address mapping module 230 is used to implement the mapping and address decoding from the AHB address space to the PLB address space; The data caching module 220 is used to cache read / write requests from the AHB bus, data to be transmitted, and response data from the PLB bus. The error handling module 270 is used to detect and handle abnormalities during data transmission and generate corresponding error response signals.
[0037] The bridging device 20 based on the AHB bus and PLB bus proposed in this invention, through the coordinated operation of the aforementioned modules, realizes functions such as protocol conversion, clock domain synchronization, data buffering, and error handling between the AHB bus and PLB bus, thereby supporting high-performance, low-latency data transmission. This device is particularly suitable for SoC systems integrating various industrial communication slave device controllers (such as EtherCAT slave controllers), enabling efficient and reliable bus access to these peripheral IPs, and helping to improve the system integration and competitiveness of chips in fields such as industrial servo systems.
[0038] The following section will further explain the specific implementation and working method of each module.
[0039] The protocol conversion module 210 is connected to the AHB bus via AHB bus signal 291 and to the PLB bus via PLB bus signal 292.
[0040] Furthermore, the protocol conversion module 210 internally includes an AHB master interface submodule and a PLB slave interface submodule. The AHB master interface submodule is connected to the AHB bus 401 and is used to receive and parse read / write request signals from the AHB master device, as well as to send the converted response signals back to the AHB master device. The PLB slave interface submodule is connected to the PLB bus 402 and is used to generate PLB bus compatible read / write request signals based on the parsing results, and to receive and process response signals returned by the PLB slave device.
[0041] The AHB master interface submodule and the PLB slave interface submodule work together to complete the protocol conversion between the AHB and PLB buses.
[0042] It is understood that the above sub-module division is an exemplary internal logic division used to clearly describe the functions; in actual hardware implementation, its circuit structure may not be limited to this division method.
[0043] The core function of the protocol conversion module 210 is to convert the protocol signals of the AHB bus into protocol signals that can be recognized by the PLB bus, and at the same time convert the response signals of the PLB bus into response signals that are compatible with the AHB bus, so as to realize the signal interaction and adaptation between the two types of buses.
[0044] Preferably, the protocol conversion module 210 needs to fully handle the different signal definitions, timing requirements and transaction types of the two buses to ensure protocol consistency during transmission.
[0045] Furthermore, the protocol conversion module 210 contains a protocol conversion state machine: this protocol conversion state machine is used to manage the transmission process between the AHB and PLB buses through state switching, specifically to realize the orderly state transition of the protocol conversion process according to the request signal of the AHB bus and the response signal of the PLB bus.
[0046] In some embodiments, the protocol conversion state machine includes at least an idle state and a transmission state. The idle state is a standby state where the bridging device waits for a request, and the transmission state is an operating state for performing protocol conversion and data transmission. When an AHB master device initiates a read or write request via the AHB bus, the protocol conversion state machine switches from the idle state to the transmission state, entering the protocol conversion and data transmission process.
[0047] More specifically, when the AHB main interface submodule initiates a read request or write request, the protocol conversion state machine switches from the idle state to the transmission state. In the transmission state, the conversion processing of AHB to PLB related protocol interface signals is completed first.
[0048] For example, the 32-bit AHB bus uses the hsize[2:0] interface to indicate byte / half_word / word access, and the corresponding interface signal for the 32-bit PLB bus is plb_be[3:0]. The AHB to PLB protocol conversion module will complete the logical control conversion between the two.
[0049] Furthermore, the protocol transition state machine also includes a waiting state, which is a pause or hold state during the protocol transition process. This waiting state is used to temporarily wait for the AHB bus or PLB slave device to become ready during the transmission process, so as to ensure the continuity of timing synchronization and protocol operation.
[0050] The protocol conversion state machine monitors the status signals of the AHB bus in real time during the transmission state. When the AHB bus status signal is detected to be busy, the protocol conversion state machine switches from the transmission state to the waiting state, and resumes the transmission process after the AHB bus is ready.
[0051] In some embodiments, the protocol conversion state machine monitors the feedback response signals from the slave device on the PLB bus in real time during the transmission state; When the PLB slave device detects that it has completed processing a read or write request, the protocol transition state machine switches from the transmission state to the idle state, waiting for the next request to be triggered.
[0052] More specifically, during transmission, the protocol conversion state machine synchronously monitors the AHB bus status and the feedback response from the PLB slave device: when the AHB bus is detected to be busy, it switches to the waiting state; when the PLB slave device successfully processes the read / write request from the AHB master device, it switches back to the idle state, ensuring a closed loop in the transmission process.
[0053] In this embodiment, the clock domain crossing module 250 is connected to the protocol conversion module 210 and is used to synchronize the cross-clock domain signals of the AHB bus 401 and the PLB bus 402.
[0054] More specifically, since the AHB bus 401 and the PLB bus 402 may operate at different clock frequencies, the clock domain spanning module 250 is responsible for synchronizing and transmitting data between clock domains to avoid data errors or transmission anomalies caused by clock asynchrony.
[0055] Optionally, the clock domain crossing module 250 will perform comprehensive cross-clock processing on the addresses, read / write requests, read / write data and related control signals of the AHB bus and PLB bus to ensure the stability of cross-clock domain transmission.
[0056] In this embodiment, the address mapping module 230 is connected to the protocol conversion module 210 and is used to implement the mapping and address decoding from the AHB address space to the PLB address space.
[0057] More specifically, the address mapping module 230 core implements precise mapping from the AHB address space to the PLB address space, and also supports address decoding function. Based on the PLB peripheral address access range, it accurately maps the required AHB address range to the PLB bus. For example, the address mapping module 230 can map AHB address 0x1000 to PLB address 0x2000, achieving compatibility adaptation for address access.
[0058] In this embodiment, the data caching module 220 is connected to the protocol conversion module 210 and is used to cache the read / write requests of the AHB bus 401, the data to be transmitted, and the response data returned by the PLB bus 402.
[0059] More specifically, the data caching module 220 can cache the read / write requests of the AHB main interface submodule, the write data received by the PLB from the interface submodule, and the read data read by the AHB main interface submodule, thereby smoothing the transmission rhythm and reducing transmission latency.
[0060] In some embodiments, the data caching module 220 is implemented using a first-in-first-out (FIFO) structure or a dual-flip-flop synchronization structure: The FIFO structure is a first-in-first-out serial data buffer queue, which can realize continuous caching and ordered reading and writing of multiple sets of read and write requests, data to be transmitted and response data, and has a certain data buffer depth. The dual-flip-flop synchronization structure is a timing synchronization architecture with two levels of cascaded flip-flops. It performs timing synchronization processing on cached data across clock domains through two levels of flip-flops, without a data cache queue, and with a simplified logic chain.
[0061] Optionally, when the amount of data to be transmitted is large, a FIFO structure should be preferred to improve caching efficiency, while in low-latency scenarios, a dual-trigger synchronous structure can be used to simplify the design.
[0062] More specifically, during the write request, the AHB master interface submodule address and read request are cached in the address phase of the AHB bus, and the data written to the PLB slave interface submodule is cached in the data phase.
[0063] When a read request is made, the address and read request are cached during the address phase of the AHB bus. After the PLB returns a signal indicating that the read operation has been successfully completed, the read data from the PLB is cached.
[0064] In this embodiment, the error handling module 270 is connected to the protocol conversion module 210 and is used to detect and process abnormal errors during data transmission and generate corresponding error response signals.
[0065] More specifically, the error handling module 270 is responsible for detecting and handling various errors that may occur during data transmission, such as address out of bounds, data verification errors, timeout errors, etc., and taking corresponding error recovery measures.
[0066] For example, when an address out-of-bounds error is detected, the request can be ignored, and the AHB hresp signal can be set to return an error response to ensure stable system operation. When a data verification error is detected, the transmission request can be determined to have failed, and the AHB hresp signal can be set to return an error response to ensure stable system operation. When a timeout error is detected, the transmission request can be terminated, and the AHB hresp signal can be set to return an error response.
[0067] Furthermore, the bridging device 20 for the AHB bus and PLB bus based on the SoC platform also includes a data width adjustment module 240, which is connected to the protocol conversion module 210. It is used to perform bit width expansion, truncation, alignment and byte order adjustment on the different bit width data transmitted between the AHB bus and the PLB bus to adapt to the data width difference between the two.
[0068] More specifically, since the data widths of the AHB bus and PLB bus may differ (for example, the AHB bus is typically 32-bit or 64-bit, while the PLB bus is typically 64-bit or 128-bit), the data width adjustment module is responsible for expanding, truncating, and aligning the data to ensure that the data can be transmitted correctly.
[0069] For example, if the data width of PLB is less than that of AHB, the data can be expanded by padding with zeros or repeating data; if the data width of PLB is greater than that of AHB, the high-order data can be truncated; if the byte order of the two is different (e.g., AHB is little-endian, PLB is big-endian), then byte swapping is required. Little-endian means that the least significant byte is stored at the lowest memory address, while big-endian means that the most significant byte is stored at the lowest memory address.
[0070] The above-mentioned bit width and byte order adaptation operations together ensure the integrity and semantic correctness of data transmitted between the AHB bus and the PLB bus.
[0071] Furthermore, the bridging device 20 based on the SoC platform for the AHB bus and PLB bus also includes a clock and reset management module 260, which is connected to the protocol conversion module 210 and is used to provide stable clock and reset signals for each module.
[0072] More specifically, the clock and reset management module 260 is responsible for managing the clock signals of AHB and PLB to ensure stability when the clock domains cross; at the same time, it processes the reset signals of AHB and PLB to ensure that the bridging module can be correctly initialized after reset, thus ensuring normal startup of the system after power-on or reset.
[0073] Furthermore, the bridging device 20 for the AHB bus and PLB bus based on the SoC platform also includes a configuration and performance optimization module 280, which is connected to the protocol conversion module 210. It includes configurable registers for configuring the working mode, clock frequency or data width parameters, and optimizes the transmission performance through caching mechanisms, pipeline technology and other means.
[0074] More specifically, the configuration and performance optimization module 280 provides a set of configuration registers that allow users to configure parameters such as the working mode, clock frequency, and data width of the bridging device according to the actual application scenario; at the same time, it integrates a series of performance optimization measures, such as optimizing the caching mechanism, introducing pipeline technology, and optimizing data and control paths.
[0075] Specifically, optimizing the caching mechanism means either increasing the cache depth to cache more read and write access requests, or introducing access request priority control to process read and write requests in the cache according to priority order.
[0076] In traditional bus access methods, the master device must wait for the previous transmission to complete before starting the next transmission. However, with pipelined bus design, the master device can continuously send multiple read and write access requests to the slave device until the buffer FIFO is full.
[0077] Given the characteristics of AHB and PLB buses, optimizing data and control paths involves shortening the transmission paths of response signals and data access as much as possible. For example, when the PLB bus receives a read request and the read data is valid, it performs the read data buffering operation and the return of the response signal in parallel, and synchronously controls the protocol transition state machine to switch states, thereby further improving transmission efficiency.
[0078] In this embodiment, the data width adjustment module 240, the clock and reset management module 260, and the configuration and performance optimization module 280 are optimization modules that match the flexibility and scalability of SoC design. Optionally, the basic bridging function between the AHB bus and the PLB bus can still be achieved even if the above modules are omitted. Such omissions or simplifications should be considered variations of the present invention and fall within the protection scope of the present invention.
[0079] Figure 3 A block diagram of the signal data flow for a write request in a bridging device for the AHB bus and PLB bus based on a SoC platform according to an embodiment of the present invention is disclosed, such as... Figure 3 As shown, the bridging device of the present invention clearly demonstrates the signal mapping, conversion, and interaction relationship between the AHB bus 401 and the PLB bus 402 when performing a write request operation. This reflects the mapping and conversion logic of key interface signals in the protocol conversion module 210 during the AHB to PLB protocol adaptation process. The specific signal definitions and interaction functions are as follows: The input signals from the AHB bus 401 to the protocol conversion module 210 include: hwrite (indicating that the current transfer is a read / write operation); htrans (indicating the transfer type, such as non-sequential transfer, idle, etc.); hsize (indicating the size of the transferred data, such as bytes / half-words / words); haddr (the transfer address initiated by the AHB master device); hready (indicating that the AHB bus transfer is ready); and hwdata (the write data output by the AHB master device).
[0080] The output signals from the protocol conversion module 210 to the AHB bus 401 include: hresp (a transmission response returned to the AHB master device, such as success / error); hreadyout (indicating that the protocol conversion module output is ready, used to synchronize the AHB bus timing).
[0081] The output signals from the protocol conversion module 210 to the PLB bus 402 include: plb_rnw (converted PLB read / write operation indication); plb_size (converted PLB transmission data size); plb_be (converted PLB byte enable signal, corresponding to the AHB hsize signal); plb_abus (mapped PLB transmission address); plb_pavalid (indicating PLB address is valid); and plb_wrdbus (write data output to the PLB slave device).
[0082] The input signals from the PLB bus 402 to the protocol conversion module 210 include: plb_sl_addrack (address response returned by the PLB slave device); plb_sl_wait (wait signal returned by the PLB slave device); plb_sl_wrdack (write data response returned by the PLB slave device); plb_sl_wrcomp (write completion signal returned by the PLB slave device); plb_sl_mbusy (busy signal returned by the PLB slave device); and plb_sl_wrerr (write error signal returned by the PLB slave device).
[0083] As the core processing unit for write request data streams, the protocol conversion module 210 mainly performs two types of key conversions: Request Conversion: Parse the AHB write request signal and generate a write request signal that conforms to the PLB bus timing. For example, convert AHB hsize[2:0] to PLB plb_be[3:0] (byte enable), convert haddr to plb_abus (PLB write address) through address mapping, convert hwrite to plb_rnw (write operation indicator, low level for write), and generate plb_pavalid (PLB address valid signal).
[0084] Response Conversion: Receive write response signals from the PLB slave device and convert them into AHB-compatible response signals. For example, convert the PLB's plb_sl_wrerr (write error) to the AHB hresp error response, and convert plb_sl_wrcomp (write complete) to the AHB hreadyout ready signal, ensuring that the AHB master device accurately recognizes the transmission result.
[0085] The complete data flow of a write request is as follows: the AHB master device initiates a write request, the protocol conversion module parses and generates a PLB write request, the PLB slave device processes the request and returns a write response, the protocol conversion module converts the PLB write response signal into an AHB write response signal, and the AHB master device receives the write response signal, completing the write operation. The entire process is managed by the state switching (idle, transmit, wait) of the protocol conversion state machine, ensuring timing synchronization and protocol compatibility between the AHB and PLB buses.
[0086] Figure 4 A signal data flow block diagram of a read request for a bridging device between the AHB bus and PLB bus based on a SoC platform according to an embodiment of the present invention is disclosed, such as... Figure 4As shown, when the bridging device of the present invention performs a read request operation, it clearly demonstrates the signal mapping, conversion and interaction relationship between the AHB bus 401 and the PLB bus 402, reflecting the mapping and conversion logic of key interface signals in the process of AHB to PLB protocol adaptation by the protocol conversion module 210. The specific signal definitions and interaction functions are as follows.
[0087] The input signals from the AHB bus 401 to the protocol conversion module 210 include: hwrite (low level when a read request is made, indicating that a read operation is currently in progress); htrans (indicating the transfer type, such as non-sequential transfer, indicating that the read request is valid); hsize (indicating the size of the read data, such as bytes / half-words / words); haddr (the address of the read operation initiated by the AHB master device); and hready (indicating that the AHB bus is ready for transmission, allowing the protocol conversion module to receive requests).
[0088] The output signals from the protocol conversion module 210 to the AHB bus 401 include: hrdata (read data returned from the PLB slave device and converted); hresp (read operation response returned to the AHB master device, such as success / error); and hreadyout (indicating that the protocol conversion module output is ready, used to synchronize the AHB bus timing and complete the read data transmission).
[0089] The output signals from the protocol conversion module 210 to the PLB bus 402 include: plb_rnw (high level indicates that the current operation is a read operation); plb_size (converted PLB data size); plb_be (converted PLB byte enable signal); plb_abus (mapped PLB read address); and plb_pavalid (indicates that the PLB read address is valid).
[0090] The input signals from the PLB bus 402 to the protocol conversion module 210 include: plb_sl_addrack (an address response returned by the PLB slave device, confirming the address is valid); plb_rddbus (read data returned by the PLB slave device); plb_sl_wait (a wait signal returned by the PLB slave device, indicating that the read operation is not ready); plb_sl_rddack (a read data response returned by the PLB slave device, confirming the data is valid); plb_sl_rdcomp (a read completion signal returned by the PLB slave device, indicating that the read operation has ended); plb_sl_mbusy (a busy signal returned by the PLB slave device, indicating that the device is busy); and plb_sl_rderr (a read error signal returned by the PLB slave device, indicating that the read operation is abnormal).
[0091] As the core processing unit for the read request data stream, the protocol conversion module 210 mainly performs two types of key conversions: Request Conversion: Parse the AHB read request signal and generate a read request signal that conforms to the PLB bus timing. For example, convert AHB hsize[2:0] to PLB plb_be[3:0] (byte enable), convert haddr to plb_abus (PLB read address) through address mapping, convert hwrite to plb_rnw (read operation indicator, high level for read), and generate plb_pavalid (PLB address valid signal).
[0092] Response Conversion: Receives read response signals from the PLB slave device and converts them into AHB-compatible response signals and data. For example, it converts the PLB's plb_sl_rderr (read error) to the AHB's hresp error response, and plb_sl_rdcomp (read complete) to the AHB's hreadyout ready signal, ensuring that read data and responses are accurately fed back to the AHB master device.
[0093] The complete data flow of a read request is as follows: the AHB master device initiates a read request; the protocol conversion module parses and generates a PLB read request; the PLB slave device processes the request and returns read data and a response; the protocol conversion module converts the PLB response signal into an AHB response signal; and the AHB master device receives the read data and response, completing the read operation. The entire process is also managed by switching between the states (idle, transmitting, waiting) of the protocol conversion state machine to ensure the efficiency and reliability of the read operation.
[0094] Based on the above-mentioned bridging device between the AHB bus and the PLB bus, this invention proposes a bridging method between the AHB bus and the PLB bus based on a SoC platform.
[0095] Figure 5 The diagram illustrates the steps of a bridging method between the AHB bus and the PLB bus based on a SoC platform according to an embodiment of the present invention. Figure 5 As shown, this invention proposes a bridging method between the AHB bus and the PLB bus based on a SoC platform, including the following steps: Step S1: parse the protocol signals of the AHB bus, convert them into PLB bus-compatible protocol signals, and manage the transmission process; In some embodiments, in step S1, the protocol conversion module 210 parses the protocol signals such as read and write requests of the AHB bus and converts them into PLB bus compatible protocol signals, and the transmission process is controlled by the protocol conversion state machine.
[0096] Step S2: Synchronize the address, request, and data signals transmitted between the AHB bus clock domain and the PLB bus clock domain. In some embodiments, step S2 is implemented via clock domain traversal module 250.
[0097] Step S3: Map the AHB address to the PLB address and cache the requests and data; In some embodiments, step S3 is implemented by the address mapping module 230, which maps the AHB address to the PLB address, and by the data caching module, which caches requests and data.
[0098] Step S4: Check if the transmission is normal and generate an error or correct response signal accordingly; In some embodiments, step S4 is implemented by error handling module 270.
[0099] Step S5: If the transmission is detected as normal, the request completion response signal of the PLB bus is converted into a transmission normal response signal compatible with the AHB bus and fed back to the AHB master device.
[0100] In some embodiments, step S5 is implemented by protocol conversion module 210.
[0101] Step S6: If a transmission abnormality is detected, the error response signal of the PLB bus is converted into an AHB bus-compatible transmission error response signal and fed back to the AHB master device.
[0102] In some embodiments, step S6 is implemented by protocol conversion module 210.
[0103] Furthermore, the bridging method also includes performing an initialization step after the system is powered on or reset to configure and start the bridging device.
[0104] The initialization steps specifically include: First, the clock and reset management module generates and distributes a reset signal, causing each module inside the device to enter a defined initial state. Subsequently, by writing to the configuration register in the configuration and performance optimization module, parameters such as the working mode, clock frequency, and data width of the bridging device are set. Finally, after completing the above configuration, the clock and reset management module releases the reset and puts the bridge device into a ready state, begins to respond to read and write requests from the AHB bus, and performs protocol conversion and data transmission according to the configuration.
[0105] The implementation methods, technical details, and optional embodiments involved in each step of this method that are not described in detail can be directly referred to the description of the relevant modules in the aforementioned bridging device embodiments, and will not be repeated here.
[0106] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.
[0107] The bridging device and method for AHB bus and PLB bus based on SoC platform proposed in this invention have the following beneficial effects: 1) High performance: Through optimized protocol conversion and clock domain crossing technology, signal conversion time is reduced, enabling high-performance data transmission between the AHB bus and PLB bus to meet the high bandwidth requirements of industrial scenarios; 2) Low latency: By simplifying protocol conversion logic and optimizing data caching mechanisms, the latency of protocol conversion and clock domain crossing is reduced, thereby lowering the overall data transmission latency; 3) High reliability: The error handling module monitors the transmission process in real time, promptly handles various abnormal errors and provides feedback, which significantly improves the reliability of data transmission; 4) Flexibility: Through the configurable registers of the configuration and performance optimization module, flexible configuration options are provided, supporting adaptation to different data widths, clock frequencies and operating modes, making it suitable for a variety of application scenarios; 5) Compatibility: It perfectly achieves protocol, timing and address compatibility between AHB bus and PLB bus, solves the interconnection problem of peripherals on different buses, and expands the flexibility and scalability of SoC design.
[0108] Those skilled in the art will understand that information, signals, and data can be represented using any of a variety of different techniques and skills. For example, the data, instructions, commands, information, signals, bits, symbols, and chips described throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.
[0109] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described above in a generalized manner in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the invention.
[0110] The various illustrative logic modules and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration.
[0111] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read and write information to / from the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and storage medium may reside as discrete components in the user terminal.
[0112] In one or more exemplary embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functionality may be stored or transmitted as one or more instructions or code on or through a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, encompassing any medium that facilitates the transfer of a computer program from one location to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Any connection is also legitimately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used in this article, disk and disc include compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.
[0113] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.
[0114] The above embodiments are provided for those skilled in the art to implement or use the present invention. Those skilled in the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the protection scope of the present invention is not limited to the above embodiments, but should be the maximum scope that conforms to the innovative features mentioned in the claims.
Claims
1. A bridging device for AHB bus and PLB bus based on a SoC platform, characterized in that, It includes a protocol conversion module, a clock domain crossing module, an address mapping module, a data buffering module, and an error handling module: The protocol conversion module is connected to the AHB bus and the PLB bus respectively, and is used to convert the protocol signal of the AHB bus into the protocol signal of the PLB bus, and convert the response signal of the PLB bus into the response signal of the AHB bus. The clock domain crossing module is connected to the protocol conversion module and is used to synchronize the cross-clock domain signals of the AHB bus and PLB bus. The address mapping module is connected to the protocol conversion module and is used to realize the mapping and address decoding from the AHB address space to the PLB address space. The data caching module is connected to the protocol conversion module and is used to cache read / write requests from the AHB bus, data to be transmitted, and response data from the PLB bus. The error handling module, connected to the protocol conversion module, is used to detect and handle abnormalities during data transmission and generate corresponding error response signals.
2. The bridging device for AHB bus and PLB bus based on a SoC platform according to claim 1, characterized in that, The protocol conversion module includes a protocol conversion state machine: The protocol conversion state machine is used to control the transmission process between the AHB and PLB buses by switching states, based on the request signals from the AHB bus and the response signals from the PLB bus.
3. The bridging device for AHB bus and PLB bus based on a SoC platform according to claim 2, characterized in that, The protocol transition state machine includes at least an idle state and a transmission state; When an AHB master device initiates a read or write request through the AHB bus, the protocol transition state machine switches from the idle state to the transmission state.
4. The bridging device for AHB bus and PLB bus based on a SoC platform according to claim 3, characterized in that, The protocol transition state machine also includes a waiting state: The protocol conversion state machine monitors the status signal of the AHB bus in real time during the transmission state. When the AHB bus status signal is detected to be in a busy state, the protocol conversion state machine switches from the transmission state to the waiting state.
5. The bridging device for AHB bus and PLB bus based on a SoC platform according to claim 3, characterized in that, The protocol conversion state machine monitors the feedback response signal from the slave device on the PLB bus in real time during the transmission state; When the PLB slave device detects that it has completed processing the read or write request, the protocol transition state machine switches from the transmission state to the idle state.
6. The bridging device for AHB bus and PLB bus based on a SoC platform according to claim 1, characterized in that, The protocol conversion module, in response to the AHB master device initiating a read request or write request through the AHB bus, parses the corresponding AHB request signal and generates a PLB bus-compatible read request signal or write request signal. as well as The protocol conversion module receives the read response signal or write response signal returned by the PLB bus, converts it into an AHB bus-compatible response signal, and feeds it back to the AHB master device.
7. The bridging device for AHB bus and PLB bus based on a SoC platform according to claim 1, characterized in that, The data caching module is implemented using a first-in-first-out (FIFO) structure or a dual-trigger synchronous structure.
8. The bridging device for AHB bus and PLB bus based on a SoC platform according to claim 1, characterized in that, It also includes a data width adjustment module, which is connected to the protocol conversion module, and is used to perform bit width expansion, truncation, alignment or byte order adjustment on the data transmitted between the AHB bus and the PLB bus to adapt to the data width difference.
9. The bridging device for AHB bus and PLB bus based on a SoC platform according to claim 1, characterized in that, It also includes a clock and reset management module, which is connected to the protocol conversion module and is used to provide clock signals and reset signals to each module.
10. The bridging device for AHB bus and PLB bus based on a SoC platform according to claim 1, characterized in that, It also includes a configuration and performance optimization module, which is connected to the protocol conversion module; The configuration and performance optimization module includes configurable registers for configuring operating modes, clock frequencies, or data width parameters, and for optimizing data transmission performance through optimized caching mechanisms or pipelined bus technology.
11. A SoC system platform architecture, characterized in that, include: The AHB master device layer contains at least one AHB master device; AHB slave device layer, containing at least one AHB slave device; The PLB slave device layer includes at least one PLB slave device; AHB bus connects the AHB master device layer and the AHB slave device layer; The PLB bus is connected to the PLB slave device layer; as well as A bridging device is connected between the AHB bus and the PLB bus; The bridging device is a bridging device for the AHB bus and PLB bus based on the SoC platform as described in any one of claims 1-10, used to realize protocol conversion and data transmission between the AHB bus and the PLB bus.
12. A bridging method between AHB bus and PLB bus based on a SoC platform, characterized in that, The bridging device based on the SoC platform and the PLB bus as described in any one of claims 1-10 includes the following steps: It parses the protocol signals of the AHB bus, converts them into PLB bus-compatible protocol signals, and manages the transmission process; Synchronization processing is performed on address, request, and data signals transmitted between the AHB bus clock domain and the PLB bus clock domain. Map the AHB address to the PLB address and cache the relevant requests and data; Check if the transmission is normal; If the transmission is detected as normal, the request completion response signal of the PLB bus is converted into a transmission normal response signal compatible with the AHB bus and fed back to the AHB master device. If a transmission error is detected, the error response signal of the PLB bus is converted into an AHB bus-compatible transmission error response signal and fed back to the AHB master device.