A circuit feature-based hardening strategy optimization method, device and computer readable storage medium
By using circuit feature analysis based on compiler principles and optimizing automated hardening strategies, the problems of low automation and resource waste in existing hardening designs are solved, achieving efficient and reliable functional safety hardening.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING UNIV OF POSTS & TELECOMM
- Filing Date
- 2026-02-09
- Publication Date
- 2026-06-05
AI Technical Summary
Existing functional safety hardening design methods have low automation in very large-scale digital integrated circuits, rely on manual operation which is prone to errors, and lack perception of circuit characteristics and differentiated adaptation, resulting in resource waste or insufficient reliability.
By generating an abstract syntax tree model through lexical and syntactic analysis based on compiler principles, the system identifies control-intensive and data-intensive circuits, matches spatial redundancy or information redundancy strategies, and performs security and cost assessments, thus achieving automated transformation from RTL design to hardened circuitry.
It achieves full-process automation from RTL design to hardened code, avoids human error, optimizes hardware resource utilization, balances reliability and cost, and meets functional safety level requirements.
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Figure CN122154579A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design automation (EDA) technology, and in particular to a method, apparatus and computer-readable storage medium for hardening strategy optimization based on circuit characteristics. Background Technology
[0002] In high-reliability applications such as aerospace, industrial control, medical equipment, and automotive electronics, functional safety of electronic and electrical systems is paramount. Its core objective is to reduce functional anomalies caused by random hardware failures or systemic failures, thereby avoiding potential hazards and ensuring the safety of equipment and personnel. With increasing chip integration, countries and related industries have issued stringent functional safety standards. Taking the automotive sector as an example, the ISO 26262 standard issued by the International Organization for Standardization provides a framework for functional safety development throughout the product lifecycle, making the implementation of functional safety in complex integrated circuit design a mandatory industry principle.
[0003] To ensure chips achieve a predetermined safety integrity level (such as ASIL in the automotive field or SIL in the industrial field), designers must implement corresponding safety mechanisms in the circuit, i.e., perform functional safety hardening. However, existing functional safety hardening design methods have two major problems when dealing with modern very large-scale digital integrated circuits:
[0004] 1) The hardening process has a low degree of automation, relies heavily on human experience, and is inefficient and prone to errors. Currently, the industry mainly relies on design engineers to manually modify code or write temporary scripts to introduce security mechanisms (such as Triple Modular Redundancy Reduction (TMR) and Error Correction Code (ECC) into RTL (Register Transfer Level). This approach is not only labor-intensive and time-consuming, but also highly susceptible to human error when dealing with large-scale, hierarchical, and complex designs, leading to problems such as incorrect signal connections, inconsistent voting logic, or incompatible interfaces of redundant modules. This not only introduces secondary design flaws but may also reduce the inherent reliability of the system. The existing process severely lacks a standardized, end-to-end fully automated toolchain, making it impossible to achieve efficient and error-free conversion from the "original RTL design" to the "high-reliability hardened RTL".
[0005] 2) The "one-size-fits-all" approach to hardening strategies lacks awareness of circuit characteristics and differentiated adaptation, resulting in a mismatch between resource overhead and reliability improvement. Traditional methods generally employ a single, coarse-grained hardening strategy (e.g., system-level triple redundancy for the entire chip or its large subsystems). This approach completely ignores the essential differences in function and structure between different modules within the chip: control-intensive circuits (such as state machines, instruction decoding units, and control logic) are extremely sensitive to logic errors such as instantaneous single-event flips and are more suitable for protection using spatial redundancy technologies such as TMR or DMR; while the core risk of data-intensive circuits (such as on-chip memory, data paths, and DSP computing units) lies in the destruction of data integrity, and information redundancy technologies such as ECC and parity checks are more direct and efficient. This indiscriminate "one-size-fits-all" approach to hardening cannot achieve precise protection tailored to individual needs, inevitably leading to serious consequences: either a large amount of valuable hardware resources (area, power consumption) are wasted on modules that do not require hardening, significantly increasing chip costs; or in order to control the cost budget, the protection level of key modules is forced to be reduced, thereby sacrificing the reliability of the overall system and making it difficult to meet the stringent requirements of the target vehicle safety integrity level (ASIL). Summary of the Invention
[0006] The present invention aims to at least partially solve one of the technical problems in the related art.
[0007] Therefore, the first objective of this invention is to propose a hardening strategy optimization method based on circuit characteristics, comprising: S1, based on compiler principles, performs lexical and syntactic analysis on the code of the circuit to be hardened in the chip, and generates an abstract syntax tree model that reflects the design hierarchy and semantics of the circuit to be hardened. S2, traverse the abstract syntax tree model to extract key circuit information, and layer the circuit to be hardened according to the extracted circuit information, dividing each circuit module in the circuit to be hardened at different levels into control-intensive circuits and data-intensive circuits. S3. Match the corresponding reinforcement strategy according to the classification of each circuit module, and generate the corresponding reinforcement scheme according to the reinforcement strategy. When the circuit module is a dense circuit, match the spatial redundancy strategy for the circuit module. When the circuit module is a data-intensive circuit, match the information redundancy strategy for the circuit module. Both the spatial redundancy strategy and the information redundancy strategy contain at least one reinforcement method. S4. Arrange and combine the methods in the strategy corresponding to each circuit module in all circuit layers of the chip to generate multiple circuit layer optimization schemes, and perform security and cost assessments on the optimization schemes.
[0008] In one embodiment of the present invention, S2 further includes: S21, Traverse the abstract syntax tree model to extract key circuit information, which includes the hierarchical structure, port definitions, internal signal connection relationships and circuit functional characteristics of the circuit to be hardened; S22. Based on the analysis of circuit functional characteristics and code structure, the circuit to be hardened is classified. If the circuit functional characteristics and code structure are mainly control flow and state logic, the corresponding circuit to be hardened is a control-intensive circuit. If the circuit functional characteristics and code structure are mainly data storage, transmission and processing, the corresponding circuit to be hardened is a data-intensive circuit.
[0009] In one embodiment of the present invention, S3 further includes: S31, when the hardening strategy matched by the circuit to be hardened is the spatial redundancy strategy, the circuit to be hardened is hardened by the three-mode redundancy method or the two-mode redundancy method. S32, when the hardening strategy matched by the circuit to be hardened is the information redundancy strategy, the circuit to be hardened is hardened by ECC parity check code or ECC Hamming code.
[0010] In one embodiment of the present invention, the method for functional safety assessment and improvement of the hardening scheme for the circuit to be hardened in step S4 is as follows: S41, the methods in the strategy corresponding to each circuit module in all circuit layers of the chip are arranged and combined, each arrangement and combination is an optimization scheme, and the circuit reinforced according to the optimization scheme is generated in the simulation software. S42, by injecting faults into the hardened circuit through simulation experiments, the fault coverage rate of the hardened circuit is obtained, and the fault coverage rate is used as the functional safety indicator of the hardening scheme. S43 uses the lookup table and register resource usage growth rate obtained from the logic synthesis report of the hardened circuit to evaluate hardware cost overhead, and uses hardware cost overhead as a cost indicator of the hardening solution. S44 evaluates the optimization scheme based on functional safety indicators and cost indicators.
[0011] In one embodiment of the present invention, S4 further includes: The circuit to be hardened is hardened according to the hardening scheme, and the hardware cost is evaluated by obtaining the lookup table and register resource usage growth rate from the logic synthesis report of the hardened circuit. Combined with the security assessment results, the corresponding "performance-cost" trade-off view of the hardening scheme is output.
[0012] To achieve the above objectives, a second aspect of the present invention provides a hardening strategy optimization device based on circuit characteristics, characterized in that it includes: The design code analysis module is used to perform lexical and syntactic analysis on the code of the circuit to be hardened in the chip based on compiler principles, and generate an abstract syntax tree model that reflects the design hierarchy and semantics of the circuit to be hardened. The module classification and strategy matching module is used to traverse the abstract syntax tree model to extract key circuit information, and to layer the circuit to be hardened according to the extracted circuit information, classifying each circuit module in the circuit to be hardened at different levels into control-intensive circuits and data-intensive circuits. The hardening code generation module is used to match the corresponding hardening strategy according to the classification of each circuit module, and generate the corresponding hardening scheme according to the hardening strategy. When the circuit module is a dense circuit, a spatial redundancy strategy is matched for the circuit module. When the circuit module is a data-intensive circuit, an information redundancy strategy is matched for the circuit module. Both the spatial redundancy strategy and the information redundancy strategy contain at least one hardening method. The fault assessment and strategy optimization module is used to arrange and combine the methods in the strategy corresponding to each circuit module in all circuit layers of the chip to generate optimization schemes for multiple circuit layers, and to perform safety and cost assessments on the optimization schemes.
[0013] In one embodiment of the present invention, the module classification and strategy matching module is further used for: The abstract syntax tree model is traversed to extract key circuit information, which includes the hierarchical structure, port definitions, internal signal connection relationships and circuit functional characteristics of the circuit to be hardened. Based on the analysis of circuit functional characteristics and code structure, the circuits to be hardened are classified. If the circuit functional characteristics and code structure are mainly control flow and state logic, the corresponding circuit to be hardened is a control-intensive circuit. If the circuit functional characteristics and code structure are mainly data storage, transmission and processing, the corresponding circuit to be hardened is a data-intensive circuit.
[0014] In one embodiment of the present invention, the hardened code generation module is further configured to: When the hardening strategy matched with the circuit to be hardened is the spatial redundancy strategy, the circuit to be hardened is hardened by the triple redundancy method or the dual redundancy method. When the hardening strategy matched with the circuit to be hardened is the information redundancy strategy, the circuit to be hardened is hardened by ECC parity check code or ECC Hamming code.
[0015] In one embodiment of the present invention, the fault assessment and strategy optimization module is used for: The methods in the strategy corresponding to each circuit module in all circuit layers of the chip will be arranged and combined, and each arrangement and combination will be used as an optimization scheme. The circuit hardened according to the optimization scheme will be generated in the simulation software. By injecting faults into the hardened circuit through simulation experiments, the fault coverage rate of the hardened circuit is obtained, and the fault coverage rate is used as the functional safety indicator of the hardening scheme. Hardware cost is assessed by using the lookup table and register resource usage growth rate obtained from the logic synthesis report of the hardened circuit, and the hardware cost is used as a cost indicator for the hardening solution. The optimization scheme is evaluated based on functional safety and cost indicators.
[0016] In one embodiment of the present invention, the fault assessment and strategy optimization module is further configured to: The circuit to be hardened is hardened according to the hardening scheme, and the hardware cost is evaluated by obtaining the lookup table and register resource usage growth rate from the logic synthesis report of the hardened circuit. Combined with the security assessment results, the corresponding "performance-cost" trade-off view of the hardening scheme is output.
[0017] To achieve the above objectives, a third aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the first aspect.
[0018] The methods, systems, and storage media of this invention have several key advantages. First, by automating the entire process from RTL parsing to hardening code generation, this invention completely replaces the traditional manual operation mode, significantly improving design efficiency, avoiding human error, and ensuring the reliability of the hardening mechanism. Second, the tool can automatically identify control-intensive and data-intensive circuits and match differentiated hardening strategies, solving the resource waste or insufficient protection problems caused by the traditional "one-size-fits-all" approach and achieving optimal utilization of hardware resources. Finally, by integrating quantitative evaluation and iterative optimization mechanisms, a data-driven design closed loop is established, enabling functional safety hardening to shift from experience-based decision-making to scientific optimization, and systematically finding the optimal balance between reliability improvement and cost control.
[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0020] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a flowchart of a hardening strategy optimization method based on circuit characteristics according to an embodiment of the present invention; Figure 2 This is an RTL design analysis and interpretation architecture diagram of a circuit feature-based hardening strategy optimization method according to an embodiment of the present invention. Figure 3 This is a schematic diagram of a TMR hardening principle for a hardening strategy optimization method based on circuit characteristics according to an embodiment of the present invention. Figure 4 This is an automated TMR / DMR hardening flowchart of a hardening strategy optimization method based on circuit characteristics according to an embodiment of the present invention. Figure 5 This is an ECC hardening principle diagram of a hardening strategy optimization method based on circuit characteristics according to an embodiment of the present invention; Figure 6 This is an ECC automatic hardening flowchart of a hardening strategy optimization method based on circuit characteristics according to an embodiment of the present invention; Figure 7 This is a flowchart of functional safety and cost assessment and multi-objective optimization of a hardening strategy optimization method based on circuit characteristics according to an embodiment of the present invention; Figure 8 This is a structural diagram of a hardening strategy optimization device based on circuit characteristics according to an embodiment of the present invention. Detailed Implementation
[0021] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0022] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0023] The following description, with reference to the accompanying drawings, describes a method and apparatus for optimizing a hardening strategy based on circuit characteristics, according to an embodiment of the present invention.
[0024] Example 1 Figure 1 This is a flowchart of a circuit feature-based hardening strategy optimization method according to an embodiment of the present invention.
[0025] like Figure 1 As shown, the hardening strategy optimization method based on circuit characteristics includes the following steps: S1 performs lexical and syntactic analysis on the code of the circuit to be hardened in the chip based on compiler principles, and generates an abstract syntax tree model that reflects the design hierarchy and semantics of the circuit to be hardened.
[0026] Specifically, in existing technologies, the code for the circuit to be hardened is generally Verilog HDL source code. Figure 2 The internal working principles and technology chain of the "RTL Design Analysis Technology" module are described in detail. For example... Figure 2 As shown, the analysis of Verilog HDL source code design is a hierarchical and progressively in-depth process. First, in the lexical analysis stage, the source code character stream is decomposed into lexical units with explicit meaning. Subsequently, in the syntax analysis stage, based on the context-free grammar of the Verilog language, these lexical units are organized into an abstract syntax tree (AST) with a hierarchical structure.
[0027] At the technical implementation level, the process first employs a compiler-based lexical analyzer to scan the input Verilog HDL source code, identifying and classifying basic syntactic units such as keywords, identifiers, operators, and constants. Subsequently, the parser, based on Verilog's context-free grammar (CFG), organizes these lexical units into a hierarchical abstract syntax (AST). The construction of the AST must adhere to the syntactic structure defined in the IEEE 1800-2017 standard, ensuring complete parsing of key elements such as modules, ports, signal declarations, combinational and sequential logic. After AST generation, the system further performs circuit information extraction and analysis, including module hierarchy traversal, signal connection topology extraction, and port characteristic identification, to construct a structured model containing both circuit structure and semantic information.
[0028] At the application level, this step is widely used in the functional safety design process of high-reliability chips, especially in ASIL-B / C / D level designs that meet the requirements of the ISO 26262 standard. By automatically parsing the original RTL code, the system can quickly identify control-intensive modules (such as state machines and control logic) and data-intensive modules (such as memory and data paths), providing a basis for subsequent hardening strategies such as triple-mode redundancy (TMR), dual-mode redundancy (DMR), ECC parity check codes, or ECC Hamming codes.
[0029] From a technical perspective, this step achieves a seamless conversion from the original design to the structured model, eliminating the uncertainty and error risks of manual analysis and significantly improving the automation and design consistency of the hardening process. Simultaneously, by accurately extracting circuit features, it lays the foundation for implementing differentiated hardening strategies, thereby achieving an optimal balance between resource consumption and reliability improvement.
[0030] S2, traverse the abstract syntax tree model to extract key circuit information, and layer the circuit to be hardened according to the extracted circuit information, dividing each circuit module in the circuit to be hardened at different levels into control-intensive circuits and data-intensive circuits.
[0031] Further, step S2 includes: S21, Traverse the abstract syntax tree model to extract key circuit information, which includes the hierarchical structure, port definitions, internal signal connection relationships and circuit functional characteristics of the circuit to be hardened; S22. Based on the analysis of circuit functional characteristics and code structure, the circuit to be hardened is classified. If the circuit functional characteristics and code structure are mainly control flow and state logic, the corresponding circuit to be hardened is a control-intensive circuit. If the circuit functional characteristics and code structure are mainly data storage, transmission and processing, the corresponding circuit to be hardened is a data-intensive circuit.
[0032] Specifically, after the Abstract Syntax Tree (AST) is generated, the system enters the crucial circuit information analysis stage. This stage does not simply extract syntactic elements; instead, it identifies combinational and sequential logic blocks through circuit function analysis, extracts signal bit widths, types, and connection topologies through circuit signal analysis, and clarifies interface characteristics through circuit port analysis. These three analysis processes work together to transform the original AST into a structured design model rich in circuit semantics, usable for automated decision-making and operation, laying a solid foundation for subsequent feature-aware reinforcement.
[0033] At the technical implementation level, the system first performs a depth-first traversal of the Abstract Syntax Tree (AST) generated in the first stage to extract the structural and behavioral characteristics of the modules. Control-intensive circuit modules typically exhibit a high proportion of combinational logic, finite state machine (FSM) structures, complex control signal paths, and timing sensitivity. Key characteristics include: a high proportion of state registers (REG Registers), a large number of control signals (such as enable, reset, and sel), and numerous conditional branches and state transition logic within the signal paths. Data-intensive circuit modules, on the other hand, are primarily data-driven, featuring a high proportion of memory (such as RAM and ROM), register files, and data buses. Characteristics include: data signals (such as data_in and data_out) dominate the module, signal bit widths are relatively large, control logic is relatively simple, and high requirements for data integrity.
[0034] At the application level, this step is widely used in the functional safety hardening process of high-reliability chip design, especially in hybrid systems involving complex control logic (such as ECU control units) and high-bandwidth data processing (such as image processing modules). Through this step, the system can automatically identify critical modules and match them with the optimal hardening strategy, thereby significantly reducing redundancy overhead and improving design efficiency while meeting the requirements of the ISO26262 standard.
[0035] At the technical level, this step achieves "feature awareness" and "dynamic adaptation" of the hardening strategy, effectively solving the problems of single strategy, resource waste, or insufficient protection in traditional hardening methods. By accurately matching spatial redundancy and information redundancy strategies, the system achieves high fault tolerance and efficient error correction capabilities in the control logic and data path, respectively, thereby improving the overall functional safety level of the chip and optimizing the utilization efficiency of hardware resources.
[0036] S3. Match the corresponding hardening strategy according to the classification of each circuit module, and generate the corresponding hardening scheme according to the hardening strategy. When the circuit module is a dense circuit, match the spatial redundancy strategy for the circuit module. When the circuit module is a data-intensive circuit, match the information redundancy strategy for the circuit module. Both the spatial redundancy strategy and the information redundancy strategy contain at least one hardening method.
[0037] Further, step S3 includes: S31, when the hardening strategy matched by the circuit to be hardened is the spatial redundancy strategy, the circuit to be hardened is hardened by the three-mode redundancy method or the two-mode redundancy method. S32, when the hardening strategy matched by the circuit to be hardened is the information redundancy strategy, the circuit to be hardened is hardened by ECC parity check code or ECC Hamming code.
[0038] As one implementation method, when the hardening strategy matched with the circuit to be hardened is a spatial redundancy strategy, the circuit to be hardened is subjected to signal replication, redundancy module scaling, and generation and insertion of majority voter circuits. The circuit to be hardened retains the timing logic of the original design after processing. When the hardening strategy matched with the circuit to be hardened is an information redundancy strategy, the corresponding encoder and decoder modules are generated according to the data bit width of the circuit to be hardened, and the encoder and decoder are seamlessly integrated into the input port and output port of the target data path, respectively. The control signals and error status flags corresponding to the encoder and decoder are set.
[0039] Specifically, in some implementations, the step of "automatically generating hardening code based on the matching hardening strategy" is the core execution link of the entire system. Its technical implementation is based on the type identification of circuit modules and the dynamic matching of hardening strategies. Specifically, after completing the automatic parsing and structured modeling of register-transfer level RTL design, the system divides the circuit modules into two categories: control-intensive and data-intensive, and processes them with different hardening techniques respectively.
[0040] For control-intensive circuit modules, the system performs signal duplication, redundant module instantiation, and majority voter circuit insertion. During signal duplication, the tool generates multiple redundant copies of critical signals (such as control signals and state machine outputs), typically triple-mode redundancy (TMR) or dual-mode redundancy (DMR), depending on the user-configured security level requirements. Redundant module instantiation generates two or more functionally identical redundant modules based on the original module, with their interfaces and signal connections fully aligned. The insertion of the majority voter circuit involves automatically generating comparison logic to vote on the outputs of the redundant modules in real time, ensuring the system still outputs correct results in the event of single-event upsets (SEUs). The voter logic typically uses three-input majority gates or two-input XOR gates for error detection and correction.
[0041] For data-intensive circuit modules, the system automatically generates encoder and decoder modules and inserts parity bits into the data path. The encoder is configured according to the user-specified ECC scheme (such as Hamming code or parity check code) and data bit width. Automatically calculate the number of check bits required. It satisfies the encoding conditions of Hamming code. The decoder module contains error detection and correction logic, capable of identifying and correcting single-bit errors and detecting double-bit errors. The parity bit is typically inserted between the input and output ports of the data path to ensure data is always protected during transmission or storage.
[0042] This step is widely applicable in practical applications to critical control logic and data storage units in high-reliability chip design, such as state machines, instruction decoders, and on-chip memory. By automatically matching hardening strategies, the system design process significantly reduces manual intervention and improves the efficiency and consistency of hardened code generation. Furthermore, this step provides an executable hardened design foundation for subsequent functional safety assessments and multi-objective optimizations, making it a key step in achieving "intelligent differentiated hardening."
[0043] As one implementation method, such as Figure 3 The diagram illustrates the hardening principle of spatial redundancy, represented by triple modular redundancy (TMR). Figure 4This section details how an automated tool transforms the original module into a Triple Modular Redundancy Rectifier (TMR) hardened module during spatial redundancy hardening. As shown in the diagram, the process is a standardized five-step sequence. The first step is information matching, where the tool precisely aligns the port and variable information obtained in the parsing phase to establish a complete signal mapping table. The second step is signal redundancy, automatically declaring multiple identical copies of all critical signals for the module based on the mapping table. The third step is module redundancy, completely replicating the functional module to be hardened to generate multiple functionally consistent instances. The fourth step is majority voter circuit generation, the core of the TMR fault tolerance mechanism. The tool automatically generates a voter for each output port. This circuit compares the outputs of each redundant instance in real time and generates correct outputs and possible error indications based on the majority consensus principle. The final step is TMR source code generation, automatically integrating and connecting all the redundancy declarations, instantiation statements, and voter logic generated in the preceding steps to output complete TMR hardened code that conforms to coding standards and is functionally correct. This flowchart reveals how this invention transforms the complex manual TMR design work into a reliable and error-free automated process.
[0044] Figure 5 This is the basic principle of ECC hardening technology. Table 1 shows the two ECC encoding and decoding schemes supported by this invention and their characteristics. Figure 6 This document demonstrates the redundancy hardening process for automated ECC (Electronic Code Correction). As shown in the figure, the process begins with the analysis of the target circuit. The first step involves encoding circuit generation. The tool automatically calculates the required number of parity bits based on the user-configured ECC scheme (such as parity check or Hamming code) and the bit width of the data to be protected, and generates the corresponding encoder hardware description. The second step involves automatic port connection. The tool intelligently identifies the data bus interface of the target module and seamlessly inserts the generated encoder into the data stream, ensuring that the data is protected before entering error-prone units (such as memory) while maintaining the correct connection of control signals. The third step involves decoding circuit generation. At the data reading end, the tool generates the corresponding decoder module, which contains error detection and correction logic (for Hamming code). The final step is post-hardening source code generation. The tool integrates the encoder, decoder, original circuit module, and necessary error status interfaces into a new, protected RTL module. This flowchart illustrates how this invention achieves "plug-and-play" automated hardening for data integrity protection.
[0045] Table 1 ECC Encoding / Decoding Scheme
[0046] S4. Arrange and combine the methods in the strategy corresponding to each circuit module in all circuit layers of the chip to generate multiple circuit layer optimization schemes, and perform security and cost assessments on the optimization schemes.
[0047] Furthermore, step S4 also includes: S41, the methods in the strategy corresponding to each circuit module in all circuit layers of the chip are arranged and combined, each arrangement and combination is an optimization scheme, and the circuit reinforced according to the optimization scheme is generated in the simulation software. S42, by injecting faults into the hardened circuit through simulation experiments, the fault coverage rate of the hardened circuit is obtained, and the fault coverage rate is used as the functional safety indicator of the hardening scheme. S43 uses the lookup table and register resource usage growth rate obtained from the logic synthesis report of the hardened circuit to evaluate hardware cost overhead, and uses hardware cost overhead as a cost indicator of the hardening solution. S44 evaluates the optimization scheme based on functional safety indicators and cost indicators.
[0048] As one implementation method, the circuit to be hardened is hardened according to the hardening scheme, and the hardware cost is evaluated by using the lookup table and register resource usage growth rate obtained from the logic synthesis report of the hardened circuit. Combined with the security assessment results, the "performance-cost" trade-off view corresponding to the hardening scheme is output.
[0049] In some implementations, the fault injection verification platform employs FPGA-based hardware acceleration to evaluate its fault tolerance by simulating typical faults such as single-event upsets (SEUs) in the hardened register-transfer-level (RTL) design. Specifically, the platform first performs logic synthesis and place-and-route on the hardened Verilog code to generate a bitstream file that can run on the FPGA. Subsequently, during runtime, the system injects random or targeted faults into critical signals (such as register REG, control signals, and the data bus), recording the system's response behavior after a fault occurs, including whether error detection mechanisms are triggered, whether error outputs are generated, and whether the system recovers to a normal state. By statistically analyzing fault coverage (FC) and error recovery rate (ERR), the degree of improvement in functional safety can be quantified.
[0050] In application scenarios, this step is suitable for the development and verification phase of high-reliability chips, especially in modules involving complex control logic and data paths, such as state machines, instruction decoders, and memory arrays. Through quantitative evaluation, the system can identify areas where hardening strategies do not match circuit characteristics, such as misusing TMR strategies on data-intensive modules, leading to resource waste.
[0051] From a technical perspective, this step enables objective evaluation of the hardening effect and dynamic feedback optimization of the strategy, allowing the system to minimize hardware resource overhead while meeting functional safety requirements. Through a multi-objective optimization model, the system can automatically adjust the type (such as TMR, DMR, ECC) or granularity (such as module-level, sub-module-level) of the hardening strategy, thereby achieving precise hardening tailored to individual needs and significantly improving design efficiency and system reliability.
[0052] The circuit feature-based hardening strategy optimization method of this invention realizes automated parsing and feature recognition based on RTL. By combining differentiated hardening strategies and multi-objective optimization evaluation, it significantly improves the efficiency and resource utilization of functional safety hardening of high-reliability chips, and effectively balances reliability and hardware cost.
[0053] Figure 7 This invention elucidates the data-driven design optimization concept and method advocated by this invention. As shown in the figure, this process constitutes a complete feedback loop. The hardened design first enters the parallel evaluation channel: on the one hand, key hardware cost indicators (such as the increase in the number of LUTs and FFs) are obtained through logic synthesis; on the other hand, functional safety improvement indicators (such as improved fault coverage) are obtained through fault injection verification (e.g., on an FPGA platform). These two quantitative results are summarized into a multi-objective optimization evaluation model for comprehensive analysis. This model can score the current hardening scheme according to the user's preset preferences (such as prioritizing extreme reliability or strict cost control). The evaluation results are then used as feedback signals to input into the hardening strategy decision-making stage, driving the system to adjust the initial scheme (e.g., change the hardening strategy of specific modules, adjust the hardening granularity, or try different strategy combinations), and start a new round of "generation-evaluation" cycle. Through this multi-granularity iterative search, the system can automatically find the optimal balance point for a specific circuit context in the complex "reliability-cost" design space, thereby achieving a leap from "experience-based trial and error" to "intelligent optimization".
[0054] Example 2 Figure 8 This is a structural diagram of a circuit feature-based hardening strategy optimization device according to an embodiment of the present invention.
[0055] like Figure 8 As shown, a hardening strategy optimization device based on circuit characteristics includes: The design code analysis module is used to perform lexical and syntactic analysis on the code of the circuit to be hardened in the chip based on compiler principles, and generate an abstract syntax tree model that reflects the design hierarchy and semantics of the circuit to be hardened. The module classification and strategy matching module is used to traverse the abstract syntax tree model to extract key circuit information, and to layer the circuit to be hardened according to the extracted circuit information, classifying each circuit module in the circuit to be hardened at different levels into control-intensive circuits and data-intensive circuits. The hardening code generation module is used to match the corresponding hardening strategy according to the classification of each circuit module, and generate the corresponding hardening scheme according to the hardening strategy. When the circuit module is a dense circuit, a spatial redundancy strategy is matched for the circuit module. When the circuit module is a data-intensive circuit, an information redundancy strategy is matched for the circuit module. Both the spatial redundancy strategy and the information redundancy strategy contain at least one hardening method. The fault assessment and strategy optimization module is used to arrange and combine the methods in the strategy corresponding to each circuit module in all circuit layers of the chip to generate optimization schemes for multiple circuit layers, and to perform safety and cost assessments on the optimization schemes.
[0056] Furthermore, the module classification and strategy matching module is also used for: The abstract syntax tree model is traversed to extract key circuit information, which includes the hierarchical structure, port definitions, internal signal connection relationships and circuit functional characteristics of the circuit to be hardened. Based on the analysis of circuit functional characteristics and code structure, the circuits to be hardened are classified. If the circuit functional characteristics and code structure are mainly control flow and state logic, the corresponding circuit to be hardened is a control-intensive circuit. If the circuit functional characteristics and code structure are mainly data storage, transmission and processing, the corresponding circuit to be hardened is a data-intensive circuit.
[0057] Furthermore, the hardened code generation module is also used for: When the hardening strategy matched with the circuit to be hardened is the spatial redundancy strategy, the circuit to be hardened is hardened by the triple redundancy method or the dual redundancy method. When the hardening strategy matched with the circuit to be hardened is the information redundancy strategy, the circuit to be hardened is hardened by ECC parity check code or ECC Hamming code.
[0058] Furthermore, the fault assessment and strategy optimization module is also used for: The methods in the strategy corresponding to each circuit module in all circuit layers of the chip will be arranged and combined, and each arrangement and combination will be used as an optimization scheme. The circuit hardened according to the optimization scheme will be generated in the simulation software. By injecting faults into the hardened circuit through simulation experiments, the fault coverage rate of the hardened circuit is obtained, and the fault coverage rate is used as the functional safety indicator of the hardening scheme. Hardware cost is assessed by using the lookup table and register resource usage growth rate obtained from the logic synthesis report of the hardened circuit, and the hardware cost is used as a cost indicator for the hardening solution. The optimization scheme is evaluated based on functional safety and cost indicators.
[0059] The circuit to be hardened is hardened according to the hardening scheme, and the hardware cost is evaluated by obtaining the lookup table and register resource usage growth rate from the logic synthesis report of the hardened circuit. Combined with the security assessment results, the corresponding "performance-cost" trade-off view of the hardening scheme is output.
[0060] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described method for optimizing hardening strategies based on circuit characteristics.
[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0062] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
Claims
1. A method for optimizing hardening strategies based on circuit characteristics, characterized in that, include: S1, based on compiler principles, performs lexical and syntactic analysis on the code of the circuit to be hardened in the chip, and generates an abstract syntax tree model that reflects the design hierarchy and semantics of the circuit to be hardened. S2, traverse the abstract syntax tree model to extract key circuit information, and layer the circuit to be hardened according to the extracted circuit information, dividing each circuit module in the circuit to be hardened at different levels into control-intensive circuits and data-intensive circuits. S3. Match the corresponding reinforcement strategy according to the classification of each circuit module, and generate the corresponding reinforcement scheme according to the reinforcement strategy. When the circuit module is a dense circuit, match the spatial redundancy strategy for the circuit module. When the circuit module is a data-intensive circuit, match the information redundancy strategy for the circuit module. Both the spatial redundancy strategy and the information redundancy strategy contain at least one reinforcement method. S4. Arrange and combine the methods in the strategy corresponding to each circuit module in all circuit layers of the chip to generate multiple circuit layer optimization schemes, and perform security and cost assessments on the optimization schemes.
2. The method as described in claim 1, characterized in that, S2 further includes: S21, Traverse the abstract syntax tree model to extract key circuit information, which includes the hierarchical structure, port definitions, internal signal connection relationships and circuit functional characteristics of the circuit to be hardened; S22. Based on the analysis of circuit functional characteristics and code structure, the circuit to be hardened is classified. If the circuit functional characteristics and code structure are mainly control flow and state logic, the corresponding circuit to be hardened is a control-intensive circuit. If the circuit functional characteristics and code structure are mainly data storage, transmission and processing, the corresponding circuit to be hardened is a data-intensive circuit.
3. The method as described in claim 1, characterized in that, S3 further includes: S31, when the hardening strategy matched by the circuit to be hardened is the spatial redundancy strategy, the circuit to be hardened is hardened by the three-mode redundancy method or the two-mode redundancy method. S32, when the hardening strategy matched by the circuit to be hardened is the information redundancy strategy, the circuit to be hardened is hardened by ECC parity check code or ECC Hamming code.
4. The method as described in claim 1, characterized in that, S4 further includes: S41, the methods in the strategy corresponding to each circuit module in all circuit layers of the chip are arranged and combined, each arrangement and combination is an optimization scheme, and the circuit reinforced according to the optimization scheme is generated in the simulation software. S42, by injecting faults into the hardened circuit through simulation experiments, the fault coverage rate of the hardened circuit is obtained, and the fault coverage rate is used as the functional safety indicator of the hardening scheme. S43 uses the lookup table and register resource usage growth rate obtained from the logic synthesis report of the hardened circuit to evaluate hardware cost overhead, and uses hardware cost overhead as a cost indicator of the hardening solution. S44 evaluates the optimization scheme based on functional safety indicators and cost indicators.
5. The method as described in claim 1, characterized in that, S4 further includes: The circuit to be hardened is hardened according to the hardening scheme, and the hardware cost is evaluated by obtaining the lookup table and register resource usage growth rate from the logic synthesis report of the hardened circuit. Combined with the security assessment results, the corresponding "performance-cost" trade-off view of the hardening scheme is output.
6. A device for optimizing hardening strategies based on circuit characteristics, characterized in that, include: The design code analysis module is used to perform lexical and syntactic analysis on the code of the circuit to be hardened in the chip based on compiler principles, and generate an abstract syntax tree model that reflects the design hierarchy and semantics of the circuit to be hardened. The module classification and strategy matching module is used to traverse the abstract syntax tree model to extract key circuit information, and to layer the circuit to be hardened according to the extracted circuit information, classifying each circuit module in the circuit to be hardened at different levels into control-intensive circuits and data-intensive circuits. The hardening code generation module is used to match the corresponding hardening strategy according to the classification of each circuit module, and generate the corresponding hardening scheme according to the hardening strategy. When the circuit module is a dense circuit, a spatial redundancy strategy is matched for the circuit module. When the circuit module is a data-intensive circuit, an information redundancy strategy is matched for the circuit module. Both the spatial redundancy strategy and the information redundancy strategy contain at least one hardening method. The fault assessment and strategy optimization module is used to arrange and combine the methods in the strategy corresponding to each circuit module in all circuit layers of the chip to generate optimization schemes for multiple circuit layers, and to perform safety and cost assessments on the optimization schemes.
7. The apparatus as claimed in claim 6, characterized in that, The module classification and strategy matching module is also used for: The abstract syntax tree model is traversed to extract key circuit information, which includes the hierarchical structure, port definitions, internal signal connection relationships and circuit functional characteristics of the circuit to be hardened. Based on the analysis of circuit functional characteristics and code structure, the circuits to be hardened are classified. If the circuit functional characteristics and code structure are mainly control flow and state logic, the corresponding circuit to be hardened is a control-intensive circuit. If the circuit functional characteristics and code structure are mainly data storage, transmission and processing, the corresponding circuit to be hardened is a data-intensive circuit.
8. The apparatus as claimed in claim 6, characterized in that, The hardened code generation module is also used for: When the hardening strategy matched with the circuit to be hardened is the spatial redundancy strategy, the circuit to be hardened is hardened by the triple mode redundancy method or the dual mode redundancy method. When the hardening strategy matched with the circuit to be hardened is the information redundancy strategy, the circuit to be hardened is hardened by ECC parity check code or ECC Hamming code.
9. The apparatus as claimed in claim 6, characterized in that, The fault assessment and strategy optimization module is also used for: The methods in the strategy corresponding to each circuit module in all circuit layers of the chip will be arranged and combined, and each arrangement and combination will be used as an optimization scheme. The circuit hardened according to the optimization scheme will be generated in the simulation software. By injecting faults into the hardened circuit through simulation experiments, the fault coverage rate of the hardened circuit is obtained, and the fault coverage rate is used as the functional safety indicator of the hardening scheme. Hardware cost is assessed by using the lookup table and register resource usage growth rate obtained from the logic synthesis report of the hardened circuit, and the hardware cost is used as a cost indicator for the hardening solution. The optimization scheme is evaluated based on functional safety and cost indicators.
10. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the method as claimed in any one of claims 1-5.