Large-size package substrate warpage prediction and residual stress analysis simulation method

Abstract

The application provides a large-size packaging substrate warpage prediction and residual stress analysis simulation method, and belongs to the field of microelectronic advanced packaging technology. Trace Mapping spatial partitioning is used to replace simple homogenization to reduce local structure characteristics, and RVE homogenization is combined to realize coupling description of cross-scale properties, which can significantly improve the accuracy of large-size substrate warpage prediction. The method comprises the following steps: a packaging substrate cross-scale processing step for obtaining hierarchical equivalent material properties of each wiring layer; a wiring layer reference temperature correction step for calculating the reference temperature of each wiring layer; and a packaging substrate manufacturing process simulation step, thereby outputting the substrate full-process warpage and residual stress.

Description

Technical Field

[0001] This invention relates to a simulation method, specifically a simulation method for predicting warpage and analyzing residual stress of large-size packaging substrates, belonging to the field of advanced microelectronic packaging technology. Background Technology

[0002] Warpage deformation of packaging substrates is a critical issue in the field of microelectronic packaging. A typical packaging substrate structure usually consists of multiple layers stacked together, including a thick core layer, a trace layer, a dielectric layer, and a solder resist layer. The substrate directly affects chip bonding yield, interconnect reliability, and product lifespan. With advanced packaging moving towards larger sizes (80x80mm),... 2 ~120x120mm 2 With the development of high-density organic substrates, the warpage of packaging substrates has become a core issue restricting yield and reliability.

[0003] As packaging substrates become larger and denser, warpage control becomes significantly more challenging. Existing substrate warpage modeling methods mainly employ simple homogenization of material properties, assuming each substrate layer is a homogeneous body and establishing a finite element model using material property parameters such as equivalent elastic modulus and coefficient of thermal expansion.

[0004] The existing solution has the following drawbacks: (1) Ignoring local structural differences: Simple homogenization does not take into account the differences in the pattern distribution of Cu traces, plane areas and via areas in the substrate, resulting in inaccurate calculation of material property parameters, especially for warpage prediction of large-size substrates with large error. (2) Insufficient description of dual-scale effect: It cannot simultaneously take into account trace-level local properties and hierarchical homogeneous properties, and it is difficult to fully reflect the relationship between substrate microstructure and macroscopic deformation; (3) Residual stress calculation is unreliable: the reference temperature (T) caused by asynchronous curing between different layers is not taken into account. ref The differences are significant, and the process requires explicit modeling and solidification, which leads to problems such as numerical instability and unclear physical meaning. (4) Poor process correlation: The residual stress accumulation effect of the entire manufacturing process is not systematically integrated, and the simulation results are out of touch with the actual process scenario.

[0005] To meet the demand for accurate warpage prediction of large-size, high-density packaging substrates, there is an urgent need for a modeling and simulation method that takes into account both microstructural details and macroscopic process procedures. Summary of the Invention

[0006] In view of this, the present invention provides a simulation method for warpage prediction and residual stress analysis of large-size packaging substrates. It adopts Trace Mapping spatial partitioning to replace simple homogenization to restore local structural features, and combines RVE homogenization to realize the coupled description of cross-scale properties, which can significantly improve the accuracy of warpage prediction of large-size substrates.

[0007] The technical solution of this invention is: a simulation method for predicting warpage and analyzing residual stress of large-size packaging substrates, comprising the following steps: S1: Cross-scale processing of packaging substrate: 101: Equivalent space grid for layout of wiring layer design on package substrate: Divide each wiring layer into several grids and calculate the equivalent material properties of each grid; 102: Equivalent material properties of wiring layer: Select a typical region on the wiring layer to establish an RVE model and calculate the homogeneous material properties of the selected typical region; then further obtain the equivalent material properties of the wiring layer by area weighting. S2: Wiring layer reference temperature correction: Calculate the reference temperature of each wiring layer based on the layer-equivalent material properties calculated in S1; S3: Simulation of packaging substrate manufacturing process: Based on the calculated equivalent material properties of each grid on the wiring layer and the reference temperature of each wiring layer, the manufacturing process of the packaging substrate is simulated, and the warpage and residual stress of the substrate throughout the entire process are output.

[0008] As a preferred embodiment of the present invention, in step S3, the entire process of the packaging substrate is integrated during simulation, and birth and death cell technology and gravity influence factor are introduced.

[0009] As a preferred embodiment of the present invention, when calculating the equivalent material properties of each grid: import the design layout of the packaging substrate, extract the Cu patterns on each wiring layer and the substrate structure dimensions, divide the packaging substrate plane into grids, and input the intrinsic property parameters of ABF and Cu; then calculate the equivalent material properties of each grid.

[0010] As a preferred embodiment of the present invention, the calculation of the equivalent material properties of the mesh is performed using an analytical model based on coverage / volume content or based on circuit layout, and obtained through simulation and machine learning methods.

[0011] As a preferred embodiment of the present invention, the wiring layer reference temperature The calculation formula is:

[0012] in:

[0013]

[0014]

[0015] in: and These represent the volume percentages of ABF and copper in the wiring layer, respectively. and These represent the coefficients of thermal expansion of ABF and copper, respectively. Indicates the equivalent thermal expansion coefficient of the wiring layer; and These are the stress-free temperatures of ABF and copper, respectively, and also the respective processing temperatures of ABF and copper. Indicates the current ambient temperature; Indicates the equivalent elastic modulus of the wiring layer; and The elastic moduli of ABF and copper are respectively. Indicates the thickness of the packaging substrate. Indicates the thickness of the wiring layer.

[0016] Beneficial effects: (1) The present invention has high prediction accuracy: Trace Mapping spatial partitioning is used to replace simple homogenization, local structural differences are restored, and RVE homogenization is combined to realize dual-scale attribute description, improve the integrity and accuracy of material parameter extraction, significantly improve the accuracy of warpage prediction of large-size substrates, and solve the problem of inaccurate warpage prediction of large-size substrates by traditional simple homogenization methods.

[0017] (2) The numerical values ​​of this invention are stable and reliable: based on the reference temperature T ref The method achieves implicit introduction of residual stress without the need to model complex curing processes, and has clear physical meaning and stable numerical calculations.

[0018] (3) The process of this invention is highly correlated: it integrates the multi-stage process of the entire manufacturing process, considers key influencing factors such as gravity and birth and death units, and realizes the simulation of residual stress accumulation. The simulation results are closer to the actual production scenario.

[0019] (4) The simulation method of the present invention has wide applicability: it supports modeling of different types of substrates (organic substrates, ceramic substrates, glass substrates, PCBs, etc.) and different Cu pattern distributions, is compatible with mainstream simulation software such as ANSYS / Abaqus, and is easy to apply in engineering. Attached Figure Description

[0020] Figure 1 This is a flowchart of the simulation method of the present invention; Figure 2 Comparison of substrate warping experimental and simulation contour plots (contour plots reversed). Detailed Implementation

[0021] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0022] This embodiment provides a simulation method for warpage prediction and residual stress analysis of large-size packaging substrates. Through the synergy of trace mapping spatial mesh generation, RVE homogenization, reference temperature correction, and multi-stage process simulation, accurate warpage prediction and residual stress analysis are achieved.

[0023] This simulation method is based on both the design layout and the manufacturing process. "Design layout-based" refers to the spatial meshing of the package substrate's design layout (a digital design file showing the geometry, dimensions, location, and hierarchical relationships of the copper traces within the package substrate) during the calculation of homogeneous material properties of the wiring layers. This generates an "equivalent material property map" that reflects the true structure of the package substrate and its spatial non-uniformity, enabling accurate and efficient simulation. "Manufacturing process-based" refers to integrating multiple stages of the entire manufacturing process during substrate manufacturing simulation, considering key influencing factors such as gravity and cell birth / death, simulating the real production process, significantly improving simulation accuracy, and making the simulation results closer to actual production scenarios.

[0024] like Figure 1 As shown, the simulation method for warpage prediction and residual stress analysis of this large-size packaging substrate includes the following steps: S1: Cross-scale processing of packaging substrate: "Cross-scale processing" refers to the systematic and quantitative equivalence of the microscopic heterogeneous structure of the wiring layer of the packaging substrate into spatially variable material properties that can be used for macroscopic system-level simulation by combining RVE homogenization and trace mapping.

[0025] Considering that the wiring layer of the packaging substrate has two basic materials: dielectric material ABF (insulating medium) and metal Cu (copper conductor); the wiring layer of the packaging substrate is based on a layout partitioning method (here partitioning refers to grid division) (the other layers of the packaging substrate are regarded as uniform materials), that is, it is assumed that the wiring density (copper coverage) of different grids in the wiring layer is different, so the equivalent material properties of each grid are also different; through partitioning calculation, the material property distribution field that varies with position is obtained. Here, "material properties" refers to the material elastic modulus E, coefficient of thermal expansion α, Poisson's ratio ν, etc.

[0026] By performing cross-scale processing on the wiring layers of the packaging substrate, the equivalent material properties between the wiring layers are obtained, thus obtaining a homogeneous model for simulation with non-uniform material properties.

[0027] The cross-scale processing steps of the packaging substrate include: wiring layer design layout spatial mesh equivalence and wiring layer hierarchical equivalence; wherein wiring layer design layout spatial mesh equivalence includes wiring layer design layout spatial mesh division and local parameter calculation to obtain the equivalent material properties of each mesh; wiring layer hierarchical equivalence involves constructing an equivalent model to obtain the hierarchical equivalent material properties of the wiring layer, which are used for subsequent correction of the wiring layer reference temperature.

[0028] 101: Equivalent Space Grid in Routing Layer Design Layout When equivalencing the spatial mesh of the wiring layer design layout, the Trace Mapping spatial partitioning method is adopted to calculate the Cu coverage / volume content of each wiring layer. Based on the selected equivalent model, local equivalent parameters (equivalent material properties of each mesh) are calculated to construct a discrete mesh hierarchical model. Specifically, Cu graphic information of each wiring layer is extracted from the Gerber / ODB++ design file, and each wiring layer is meshed into several fine meshes (a large number of fine meshes). Based on the circuit characteristics (wiring characteristics of copper circuits) within each mesh, the equivalent material properties (elastic modulus E, coefficient of thermal expansion α, Poisson's ratio ν) of the mesh are calculated, and an ANSYS / Abaqus hierarchical model is constructed to solve the modeling error problem caused by local structural differences in large-size substrates.

[0029] Specifically, the process involves: importing the Gerber / ODB++ design file of the packaging substrate (i.e., the design layout of the packaging substrate), extracting the Cu patterns on each wiring layer and the substrate structure dimensions, meshing the substrate plane, and inputting the intrinsic material property parameters (E, α, ν, etc. of ABF and Cu); and then calculating the equivalent material properties of each mesh.

[0030] The equivalent material properties of each grid can be calculated using analytical models based on coverage / volume content; or based on Parallel (Voigt) or Series (Reuss) models; or based on circuit layouts, obtained through simulation and machine learning methods.

[0031] In this example, when calculating the equivalent material properties of the mesh, an analytical model method based on coverage or volume content is used. Taking the analytical model method based on volume content as an example, the volume fraction of copper in each mesh is first calculated. and ABF volume fraction Then calculate value, The values ​​and known intrinsic property parameters (E, α, ν, etc.) of ABF and Cu are substituted into the preset analytical formula to calculate the equivalent material property parameters of the mesh.

[0032] The analytical formulas for the elastic modulus, coefficient of thermal expansion, and Poisson's ratio of a material are as follows: The method for calculating the coefficient of thermal expansion is as follows:

[0033] The formula for calculating the elastic modulus is:

[0034] The formula for calculating Poisson's ratio:

[0035] In the above formula, the subscripts x and y represent the in-plane directions of the substrate, that is, two mutually perpendicular directions parallel to the substrate surface; the subscript z represents the thickness direction of the substrate (vertical direction); it is usually assumed that the material is isotropic (has the same properties) in the xy plane, therefore the coefficients of thermal expansion in the two in-plane directions are the same, i.e. , Indicates the coefficient of thermal expansion in the direction of mesh thickness; , represents the elastic modulus in the xy plane, xz plane, and yz plane, respectively; represents the elastic modulus in the mesh thickness direction (i.e., out-of-plane). , , These represent the Poisson's ratios in the yz plane, xz plane, and xy plane of the grid, respectively.

[0036] Subscript f Indicates dielectric material ABF (insulating medium), subscript m Indicates metal Cu (Copper wire) E For elastic modulus, c It is the volume fraction. v Poisson's ratio, α Where is the coefficient of thermal expansion; then , , These represent the elastic modulus, Poisson's ratio, and coefficient of thermal expansion (intrinsic properties) of the dielectric material ABF, respectively. , , These represent the elastic modulus, Poisson's ratio, and coefficient of thermal expansion (intrinsic properties) of metallic Cu, respectively.

[0037] The above analytical formulas can be used to obtain the equivalent material properties of each mesh based on its own copper volume fraction, i.e., the equivalent material properties of the wiring layer mesh. The equivalent material properties of each mesh include nine parameters, namely... , , The calculated equivalent material properties of each grid are the core of "TraceMapping modeling" and "RVE homogenization" analysis.

[0038] 102: Equivalent Wiring Layers The equivalent processing of the wiring layer adopts the RVE (Representative Volume Unit) homogenization method: select a typical area on the wiring layer of the packaging substrate to establish an RVE model, and solve (such as uniaxial loading solution) the homogeneous material properties of the selected typical area; then further obtain the equivalent material properties of the layer through area weighting.

[0039] RVE homogenization refers to the process of selecting several statistically representative regions on the packaging substrate as RVE units (each RVE unit contains several meshes) and establishing accurate geometric and material models for them. Then, through numerical simulation and averaging calculations, this complex heterogeneous micro-unit (RVE fine model) is equivalent to a homogeneous continuum material with macroscopic properties, thereby obtaining simplified material properties that can be used for overall system-level analysis, i.e., obtaining the homogeneous material properties of each RVE unit.

[0040] As an example, the routing layer is partitioned according to geometric features. The routing area, plane area, and via area of ​​each routing layer are selected for partitioning (that is, the statistically representative area is selected as RVE). Then, the homogeneous material properties of each area are obtained through single-axis loading simulation.

[0041] Then, through area weighting of multiple regions (selected as RVE elements), the hierarchical equivalent material properties are obtained, realizing the conversion between discrete mesh and whole-layer equivalent material properties, with reference temperature T. ref Computation provides the foundation.

[0042] As an example, the Hill average (the arithmetic mean of the lower bound of the series model and the upper bound of the parallel model) is used as the hierarchical equivalent elastic modulus of the wiring layer. Equivalent shear modulus of the hierarchy ,Right now:

[0043] in: The equivalent elastic modulus calculated using the Reuss (series) model assumes that each component material is subjected to the same stress and provides a lower limit for the elastic modulus prediction. The equivalent elastic modulus is calculated using the Voigt (parallel) model, which assumes that each component material is subjected to the same strain and gives an upper limit to the predicted elastic modulus. The meaning is the same.

[0044] As an example, the thermal expansion coefficient of the wiring layer is obtained based on stiffness weighting. :

[0045] in: The i-th constituent phase of the composite material is represented by the ABF dielectric phase and the Cu conductor phase in the wiring layer of the encapsulation substrate. This represents the volume fraction of the i-th constituent phase, such as when i=1 is the ABF dielectric phase and i=2 is the Cu conductor phase. .

[0046] S2: Wiring layer reference temperature correction: In this step, when inputting the material properties of each wiring layer, the input is the layer equivalent material property calculated in step S1 above, and the output is the reference temperature of each wiring layer.

[0047] Considering the difference between process curing temperature and assembly temperature, as well as the asynchronous curing effect between layers, the calculated layer-equivalent material property parameters are substituted into the Timoshenko formula to calculate the reference temperature T for each wiring layer. ref It automatically generates residual stress using stress formulas, eliminating the need for explicit force load and curing process modeling.

[0048] The equivalent reference temperature of the wiring layer is:

[0049] in:

[0050]

[0051]

[0052] in: and These represent the volume percentages of ABF and copper in the wiring layer, respectively. and These represent the coefficients of thermal expansion (intrinsic properties) of ABF and copper, respectively. Indicates the equivalent thermal expansion coefficient of the wiring layer; and These are the stress-free temperatures of ABF and copper, respectively, and also the respective processing temperatures of ABF and copper. Indicates the current ambient temperature; Indicates the equivalent elastic modulus of the wiring layer; and These are the elastic moduli (intrinsic properties) of ABF and copper, respectively. Indicates the thickness of the substrate dielectric layer. Indicates the thickness of the wiring layer.

[0053] The formula for residual stress is: ; in: This represents the residual stress of the wiring layer; thus, the non-uniformly distributed residual stress field in the entire internal space of the packaging substrate can be automatically and efficiently calculated.

[0054] S3: Simulation of substrate manufacturing process: When simulating the substrate manufacturing process, based on the calculated equivalent material properties of each grid and the reference temperature of each wiring layer, the simulation can output the warpage and residual stress of the substrate throughout the entire process.

[0055] During simulation, the entire process, including substrate stacking and curing, copper plating, and solder mask preparation, is integrated. The techniques of cell birth and death and the influence factor of gravity are introduced, combined with the aforementioned Trace Mapping, RVE homogenization, and reference temperature. A modified sensitivity analysis is used to simulate the cumulative residual stress. The simulation can predict the inherent warpage and residual stress in the final product caused by the combined effects of manufacturing sequence and long-term gravity creep.

[0056] The simulation method of this invention provides local structural properties through Trace Mapping and hierarchical equivalent material properties through RVE homogenization; the two work together to describe the dual-scale effect. ref The method for stabilizing the introduction of residual stress based on hierarchical equivalent material properties is improved; the above technologies are integrated into a multi-stage process module to achieve full-process warping simulation.

[0057] Case Study: Simulation verification was performed on a large-size organic packaging substrate of 45mm×45mm, such as... Figure 2 As shown: Compared with traditional homogenization methods, the error of the maximum warpage predicted by the simulation method of this invention is reduced from more than 15% to less than 5%, and the deformation trend in key areas is 92% consistent with the measured results. The cumulative residual stress distribution from multi-stage process simulation can accurately explain the phenomenon that the edge warping of the substrate is greater than that of the center in actual production, providing a reliable basis for process optimization.

[0058] Although the present invention has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to it, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present invention fall within the scope of protection claimed by the present invention.

Claims

1. A simulation method for predicting warpage and analyzing residual stress in large-size packaging substrates, characterized in that, Includes the following steps: S1: Cross-scale processing of packaging substrate: 101: Equivalent space grid for layout of wiring layer design on package substrate: Divide each wiring layer into several grids and calculate the equivalent material properties of each grid; 102: Equivalent wiring layer hierarchy: RVE models are established by selecting several typical regions on the wiring layer, and the homogeneous material properties of the selected typical regions are calculated. The hierarchical equivalent material properties of the wiring layer are then obtained by multi-zone area weighting. S2: Wiring layer reference temperature correction: Calculate the reference temperature of each wiring layer based on the layer-equivalent material properties calculated in S1; S3: Simulation of packaging substrate manufacturing process: Based on the calculated equivalent material properties of each grid on the wiring layer and the reference temperature of each wiring layer, the manufacturing process of the packaging substrate is simulated, and the warpage and residual stress of the substrate throughout the entire process are output.

2. The method for predicting warpage and analyzing residual stress of large-size packaging substrates as described in claim 1, characterized in that, In S3, during simulation, the entire process of the packaging substrate is integrated, and the birth and death cell technology and gravity influence factor are introduced.

3. The method for predicting warpage and analyzing residual stress of large-size packaging substrates as described in claim 1 or 2, characterized in that, When calculating the equivalent material properties of each grid: import the design layout of the packaging substrate, extract the Cu patterns on each wiring layer and the substrate structure dimensions, divide the packaging substrate plane into grids, and input the intrinsic property parameters of ABF and Cu; then calculate the equivalent material properties of each grid.

4. The method for predicting warpage and analyzing residual stress of large-size packaging substrates as described in claim 3, characterized in that, The calculation of the equivalent material properties of the mesh is performed using analytical models based on coverage / volume content or based on circuit layout, obtained through simulation and machine learning methods.

5. The method for predicting warpage and analyzing residual stress of large-size packaging substrates as described in claim 1 or 2, characterized in that, Wiring layer reference temperature The calculation formula is: in: in: and These represent the volume percentages of ABF and copper in the wiring layer, respectively. and These represent the coefficients of thermal expansion of ABF and copper, respectively. Indicates the equivalent thermal expansion coefficient of the wiring layer; and These are the stress-free temperatures of ABF and copper, respectively, and also the respective processing temperatures of ABF and copper. Indicates the current ambient temperature; Indicates the equivalent elastic modulus of the wiring layer; and The elastic moduli of ABF and copper are respectively. Indicates the thickness of the packaging substrate. Indicates the thickness of the wiring layer.

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