Method and apparatus for efficient automated power optimization for chip physical design

Abstract

The application discloses a method and device for efficient automatic power consumption optimization of chip physical design, solves the problem that the prior art cannot balance the time cost and optimization effect in design space exploration, realizes efficient exploration of high-dimensional continuous physical design parameters, and thus optimizes design parameters and reduces chip power consumption under the premise of guaranteeing design constraints; the method comprises the following steps: determining physical design parameters and boundaries based on a chip process node, sampling and constructing an initial data set; using a pre-trained large model to establish a small sample power consumption evaluation proxy model through context learning; parameter generation model iterative optimization: generating a candidate parameter combination, inputting the proxy model to obtain predicted power consumption, and updating model parameters until convergence according to the predicted power consumption; after training, the model generates a parameter combination to call an EDA tool to obtain real power consumption, so as to feed back the optimization model, and finally output a chip design with optimized power consumption.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit electronic design automation and artificial intelligence technology, and in particular to a method and apparatus for efficient automated power consumption optimization in chip physical design. Background Technology

[0002] Currently, existing technical solutions for exploring the design space of digital integrated circuits are concentrated in the following three categories: human experience accumulation, reinforcement learning, and heuristic algorithms.

[0003] Human experience accumulation involves physical design engineers using past design and process experience, or typical design parameters provided by foundry vendors, to determine the design parameters required for a new design during the physical design process. This method is currently the mainstream approach for chip design companies. However, it requires engineers to have extensive experience, and it is difficult to find directions for iterative optimization among a large number of physical design parameters.

[0004] Reinforcement learning has become a popular approach for EDA (Electronic Design Automation) software vendors in recent years, with Synopsys' DSO.ai and Cadence's Cerebrus tool being representative examples. The core algorithm of Cerebrus involves constructing a reinforcement learning agent to obtain rewards from the EDA tool and observe its state, optimizing the agent based on the rewards, outputting the most valuable action, and then having the EDA tool execute the action, outputting a new reward and state. Reinforcement learning achieves design space exploration through continuous interaction with the EDA tool. This method relies on multiple iterations of the EDA tool, resulting in significant time and computational costs. Heuristic algorithms are also a key research direction in design space exploration. One type of heuristic algorithm involves direct interaction with the EDA tool, continuously iterating and optimizing. In 2021, FlowTuner integrated the Ant Colony Optimization (ACO) algorithm into an evolutionary framework, achieving efficient design space exploration. The AutoTuner platform integrates various optimization and tuning algorithms, such as evolutionary algorithms and tree-structured Parzen estimators, and combines them with an early stopping mechanism to accelerate FPGA design space exploration. Another approach involves first constructing a surrogate model of the objective using a Gaussian process model, then using a data acquisition function to obtain the next set of parameters with the greatest expected improvement, and finally using an EDA tool to iterate over the next set of parameters. In 2022, PTPT's work established a framework for physical design parameter tuning based on multi-objective Bayesian optimization (MOBO) and a multi-task Gaussian model. In 2025, Donger Luo et al. proposed a physical design parameter exploration tool based on an attention mechanism: it analyzes the importance of physical design parameters through a self-attention mechanism and uses a mixture-space Gaussian process model to jointly optimize continuous and discrete parameters, thereby capturing their complex interaction relationships.

[0005] Traditional commercial EDA tools employ manual iterative methods. When performing physical design of very large-scale digital integrated circuits (VLSI), the time required to complete a single iteration can easily reach several hours or even days. Therefore, the time cost of design space exploration is directly proportional to the number of iterations. Traditional digital chip optimization techniques rely on a large number of design iterations, making their time cost unacceptable in VLSI design.

[0006] Heuristic methods such as simulated annealing and genetic algorithms can explore the parameters for global optimization, but their convergence process is too slow, and they may even fail to converge. Reinforcement learning mainly relies on reward signals obtained through interaction with the design results of EDA tools. In complex tasks such as power optimization, it requires a massive trial-and-error process, and the sample efficiency is very low. Therefore, these methods cannot utilize prior design experience, and each exploration needs to start from scratch, resulting in low efficiency in design space exploration.

[0007] Bayesian methods obtain the parameters for the next optimization operation through statistical judgment of prior knowledge, achieving rapid convergence and efficiently completing the design space exploration process. However, this method is not suitable for exploring high-dimensional design spaces. Physical design processes involve adjusting a large number of design parameters, and the design space for parameter tuning grows exponentially, especially for continuous parameters. For example, with 10 continuous parameters, assuming a minimum step size of 20% for parameter exploration, the design space for these parameters alone reaches [a significant size]. Therefore, exploring high-dimensional design spaces is one of the key issues that must be addressed. Existing technologies have limitations when exploring high-dimensional design spaces.

[0008] In summary, existing solutions struggle to balance time cost and optimization effectiveness in physical design optimization. Due to the two factors mentioned above, current mainstream methods and published machine learning-based optimization methods cannot achieve a balance between time cost and optimization effectiveness in design space exploration. Summary of the Invention

[0009] This invention provides a method and apparatus for efficient automated power consumption optimization in chip physical design, which solves the problem that existing technologies cannot balance the time cost and optimization effect in design space exploration. It enables efficient exploration of high-dimensional continuous physical design parameters, thereby optimizing design parameters and reducing chip power consumption while ensuring design constraints.

[0010] In a first aspect, the present invention provides a method for efficient automated power consumption optimization in chip physical design, comprising: S101, Based on the process node of the digital chip to be designed, determine the set of physical design parameters and the boundaries of each physical design parameter, and sample and generate multiple sets of parameter combination samples to form the initial dataset; S102, using a pre-trained general pedestal-type large model, based on the parameter combination samples in the initial dataset, a small sample power consumption evaluation proxy model is obtained through a context learning mechanism; S103: Generate multiple candidate parameter combinations using a parameter generation model, input the multiple candidate parameter combinations into the small sample power consumption evaluation proxy model to obtain the corresponding predicted power consumption results, update the model parameters of the parameter generation model according to the predicted power consumption results, iterate S103 until the parameter generation model converges, and obtain the trained parameter generation model. S104: The trained parameter generation model is used to generate a combination of physical design parameters, and the EDA tool is called to execute the physical design process to obtain the actual power consumption result. The actual power consumption result is used as feedback to optimize and adjust the parameter generation model, and the optimized and adjusted combination of physical design parameters is output as the chip design result with optimized power consumption.

[0011] In conjunction with the first aspect, in one possible implementation, the step of determining the set of physical design parameters and the boundaries of each physical design parameter based on the process node of the digital chip to be designed, and sampling to generate multiple sets of parameter combination samples to form an initial dataset, includes: Based on the process node and design scale of the digital chip to be designed, a set of physical design parameters for power consumption optimization is determined. These physical design parameters include density and maximum fan-out in the placement stage, maximum fan-out of the clock tree in the clock tree synthesis stage, target transition time, target clock skew and maximum clock tree line length, as well as maximum signal transition time, maximum capacitance and maximum line length in the routing stage. Each physical design parameter has its own defined range of values. The Latin hypercube sampling method is used to generate multiple sets of parameter combination samples in a multidimensional parameter space defined by the boundaries of the range of values ​​of each parameter; For each set of parameter combinations, electronic design automation tools are called to execute the corresponding physical design process to obtain design results including power consumption, area, and timing. The parameter combination samples are associated with and stored with the corresponding design results to construct a physical design dataset.

[0012] In conjunction with the first aspect, in one possible implementation, the method of utilizing a pre-trained general-purpose pedestal-type large model, based on parameter combination samples in the initial dataset, to obtain a small-sample power consumption evaluation proxy model through a context learning mechanism, includes: Obtain a pre-trained general pedestal-type large model, which is a tabular data large model based on the Transformer architecture and has been pre-trained on a synthetic dataset; The parameter combination samples and corresponding power consumption results in the initial dataset are used as context examples and input into the pedestal-type large model; Based on the pedestal-type large model, the association between the parameter combination samples represented by the context examples and the corresponding power consumption results is learned through the context learning mechanism, based on the training weights and the context examples, to obtain the small sample power consumption evaluation proxy model; wherein, the small sample power consumption evaluation proxy model can output the corresponding power consumption prediction result for any combination of input physical design parameters.

[0013] In conjunction with the first aspect, in one possible implementation, the generation of multiple candidate parameter combinations using a parameter generation model includes: A parameter generation model based on the Transformer decoder structure is constructed. The parameter generation model generates parameters one by one in an autoregressive manner according to the preset physical design parameter order. When generating the parameters, the parameter generation model outputs the generation distribution information corresponding to the parameters, wherein the generation distribution information includes: Gaussian distribution mean. and variance ; Based on the generated distribution information corresponding to each parameter, Gaussian distribution random sampling is performed to generate multiple candidate parameter combinations; at the same time, during the sampling process, the log probability density corresponding to each candidate parameter combination is calculated; wherein, the log probability density is the sum of the logarithms of the sampling probability densities of each parameter.

[0014] In conjunction with the first aspect, in one possible implementation, the step of inputting the combination of the multiple candidate parameters into the small-sample power consumption evaluation proxy model to obtain the corresponding predicted power consumption result, and updating the model parameters of the parameter generation model based on the predicted power consumption result, includes: The multiple candidate parameters are combined to form a group, and the group is input into the small sample power consumption evaluation proxy model to obtain the predicted power consumption result corresponding to each candidate parameter combination; The negative of each predicted power consumption result is used as the reward value corresponding to each candidate parameter combination, and the mean and variance of the group reward value corresponding to the group are calculated based on the reward value corresponding to each candidate parameter combination. The dominance function value corresponding to each candidate parameter combination is determined based on the reward value of each candidate parameter combination, the mean of the group reward value, and the variance of the group. Based on the advantage function value and the log probability density corresponding to each candidate parameter combination, a loss function is constructed, and the parameters of the parameter generation model are updated with the goal of minimizing the loss function.

[0015] In conjunction with the first aspect, in one possible implementation, determining the dominance function value corresponding to each candidate parameter combination based on the reward value of each candidate parameter combination, the mean of the group reward value, and the variance of the group includes: The advantage function value corresponding to each candidate parameter combination is calculated using the following formula: ; in, Indicates the first Each batch of rewards; This represents the average reward across K batches; This represents the variance of rewards for the K batches; To represent a constant, preventing the dividend from being zero; Indicates the first The dominant function values ​​for each batch.

[0016] In conjunction with the first aspect, in one possible implementation, the loss function is expressed as: ; in, Indicates the first The log probability density of each batch; Indicates the first The dominant function values ​​for each batch; This is the expected value of the formula, which is the average value after summation; This represents the training loss value.

[0017] In conjunction with the first aspect, in one possible implementation, the step of using the actual power consumption result as feedback to optimize and adjust the parameter generation model, and outputting the optimized and adjusted combination of physical design parameters as the power-optimized chip design result, includes: The negative of the actual power consumption result is used as the reward value, and the advantage function value of each parameter combination is calculated using the group relative strategy optimization method. A constraint mechanism is introduced to update the parameters of the parameter generation model based on the value of the advantage function and the generation probability of each parameter combination.

[0018] In conjunction with the first aspect, in one possible implementation, the introduction of a constraint mechanism to fine-tune the parameter generation model includes: Calculate the generation probability ratio of each candidate parameter combination under the current parameter generation model and the parameter generation model before the update; wherein, the generation probability ratio is the ratio of the probability of the current parameter generation model generating the first candidate parameter combination to the probability of the parameter generation model before the update generating the second candidate parameter combination. Calculate the KL divergence of the policy distribution between the current parameter generation model and the trained parameter generation model; A fine-tuning objective function is constructed based on the generation probability ratio, the KL divergence, and the dominance function value. The parameters of the parameter generation model are updated with the goal of minimizing the fine-tuning objective function.

[0019] Secondly, the present invention provides an apparatus for efficient automated power consumption optimization in chip physical design, comprising: The dataset construction module is used to determine the set of physical design parameters and the boundaries of each physical design parameter according to the process node of the digital chip to be designed, and to sample and generate multiple sets of parameter combination samples to form the initial dataset. The proxy model building module is used to obtain a small-sample power consumption evaluation proxy model by utilizing a pre-trained general pedestal-type large model and based on the parameter combination samples in the initial dataset through a context learning mechanism. The parameter generation model training module is used to generate multiple candidate parameter combinations using the parameter generation model, input the multiple candidate parameter combinations into the small sample power consumption evaluation proxy model to obtain the corresponding predicted power consumption results, update the model parameters of the parameter generation model according to the predicted power consumption results, and iteratively execute the parameter generation model training module until the parameter generation model converges to obtain the trained parameter generation model. The strategy migration optimization module is used to generate a combination of physical design parameters using the trained parameter generation model and call the EDA tool to execute the physical design process to obtain the actual power consumption result. The actual power consumption result is used as feedback to optimize and adjust the parameter generation model, and the optimized and adjusted combination of physical design parameters is output as the chip design result with power optimization.

[0020] One or more technical solutions provided in this invention have at least the following technical effects or advantages: This invention determines the set of physical design parameters and the boundaries of each parameter based on the process node of the digital chip to be designed, and generates multiple sets of parameter combination samples to form an initial dataset. Latin hypercube sampling ensures the uniformity and representativeness of the parameter space coverage, providing a high-quality data foundation for subsequent model construction. Simultaneously, by calling EDA tools to obtain real power consumption results, reliable labels are provided for model learning in small-sample scenarios. Utilizing a pre-trained general-purpose pedestal-type large model, based on the parameter combination samples in the initial dataset, a small-sample power consumption evaluation proxy model is obtained through a context learning mechanism. This step leverages the powerful prior knowledge and context learning capabilities of the pedestal-type large model to quickly build a high-precision power consumption prediction model with only a small number of samples, avoiding the huge time overhead of repeatedly calling EDA tools and significantly improving the efficiency of design space exploration. Multiple candidate parameter combinations are generated using a parameter generation model. These combinations are then input into a small-sample power consumption evaluation surrogate model to obtain the corresponding predicted power consumption results. The model parameters of the parameter generation model are updated based on the predicted power consumption results. This process is iterated until the parameter generation model converges, resulting in a trained parameter generation model. This step uses an autoregressive Transformer to jointly model the high-dimensional continuous parameter sequence, introduces an uncertainty sampling mechanism to balance exploration and utilization, and combines a group relative strategy optimization method to calculate the advantage function to guide model updates. This allows for efficient searching of parameter regions with better power consumption within the surrogate model environment, overcoming the shortcomings of traditional methods such as low search efficiency and susceptibility to local optima in high-dimensional spaces. The trained parameter generation model is then used to generate physical design parameter combinations, and EDA tools are called to execute the physical design process to obtain real power consumption results. These real power consumption results are used as feedback to optimize and adjust the parameter generation model. The optimized physical design parameter combinations are then output as the power-optimized chip design results. This step uses the execution results of real EDA tools as a reward signal to fine-tune the parameter generation model and introduces constraint mechanisms such as KL divergence to ensure the stability of policy migration. This achieves a smooth transition from the surrogate model environment to the real physical design environment, and finally obtains the parameter combination with optimal power consumption in actual chip design, ensuring the reliability and practicality of the optimization results. Attached Figure Description

[0021] Figure 1 A flowchart illustrating a method for efficient automated power consumption optimization in chip physical design, provided in an embodiment of the present invention. Figure 2 A flowchart illustrating a specific usage embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] In a first aspect, the present invention provides a method for efficient automated power consumption optimization in chip physical design, see [link to relevant documentation]. Figure 1 The method includes: S101, Based on the process node of the digital chip to be designed, determine the set of physical design parameters and the boundaries of each physical design parameter, and sample and generate multiple sets of parameter combination samples to form the initial dataset; Specifically, in step S101, the set of physical design parameters is determined according to the process node of the digital chip to be designed, including the following steps S1011 to S1015.

[0024] S1011, based on the process node and design scale of the digital chip to be designed, determines the set of physical design parameters involved in power consumption optimization. The physical design parameters include: density and maximum fan-out in the placement stage, maximum fan-out of the clock tree in the clock tree synthesis stage, target transition time, target clock skew and maximum clock tree line length, and maximum signal transition time, maximum capacitance and maximum line length in the routing stage. S1012, respectively defines the range boundaries of each physical design parameter; S1013 uses the Latin hypercube sampling method to generate multiple sets of parameter combination samples in a multidimensional parameter space defined by the boundaries of the range of values ​​of each parameter. S1014, for each set of parameter combination samples, calls the electronic design automation tool to execute the corresponding physical design process and obtain design results including power consumption, area, and timing. S1015 associates and stores the parameter combination samples with the corresponding design results to construct a physical design dataset.

[0025] For example, firstly, based on the process node, design scale, and constraints of the digital chip to be designed, the physical design parameters involved in power optimization are determined. These physical design parameters are not only inputs to the power evaluation model but also optimized parameters output by the Transformer model. Because datasets in physical design scenarios are extremely scarce, parameter selection mechanisms from machine learning cannot be used to select design parameters. Instead, physical design engineers must select the parameters to be optimized based on their own design workflow. Continuous design parameters related to power optimization include, but are not limited to, the following nine: density and maximum fan-out in the placement phase; maximum fan-out, target transition time, target clock skew, and maximum clock tree length in the clock tree synthesis phase; and maximum signal transition time, maximum capacitance, and maximum line length in the routing phase.

[0026] For the set of physical design parameters, the boundaries of each parameter are determined, and several sets of parameter combination samples are generated in the multidimensional parameter space using the Latin hypercube sampling method to ensure the uniformity and representativeness of the parameter space coverage.

[0027] For each set of parameter combinations, the corresponding physical design process is executed by calling the EDA tool to extract power consumption results. These results include power consumption, area, timing, and DRC results. The parameter combinations and their corresponding results are then combined to construct a physical design power consumption dataset.

[0028] S102 utilizes a pre-trained general pedestal-type large model and, based on parameter combination samples in the initial dataset, obtains a small-sample power consumption evaluation proxy model through a context learning mechanism. Specifically, in step S102, a small-sample power consumption evaluation proxy model is obtained by using a pre-trained general pedestal-type large model and based on the parameter combination samples in the initial dataset through a context learning mechanism, including the following steps S1021 to S1023.

[0029] S1021, Obtain the pre-trained general pedestal-type large model; wherein, the pedestal-type large model is a tabular data large model based on the Transformer architecture, which has been pre-trained on a synthetic dataset; S1022, the parameter combination samples and corresponding power consumption results in the initial dataset are used as context examples and input into the pedestal-type large model; S1023, the pedestal-type large model, based on training weights, learns the correlation between parameter combination samples represented by context examples and corresponding power consumption results through a context learning mechanism to obtain a small-sample power consumption evaluation proxy model; wherein, the small-sample power consumption evaluation proxy model can output the corresponding power consumption prediction result for any combination of input physical design parameters.

[0030] For example, based on a physical design power consumption dataset, a general-purpose pedestal-style large model is transferred to a label-sparse physical design to construct a power consumption evaluation surrogate model. The power consumption evaluation surrogate model is used to characterize the mapping relationship between physical design parameters and power consumption results.

[0031] Specifically, the power consumption assessment proxy model is built on a pre-trained general-purpose pedestal-type large model. By using a small number of physical design parameters and their corresponding power consumption results as context samples, the model has the ability to predict power consumption for the current chip design scenario during the inference stage. This enables rapid assessment of power consumption for new parameter combinations without repeatedly calling EDA tools.

[0032] S103: Use the parameter generation model to generate multiple candidate parameter combinations, input the multiple candidate parameter combinations into the small sample power consumption evaluation proxy model to obtain the corresponding predicted power consumption results, update the model parameters of the parameter generation model according to the predicted power consumption results, and iterate S103 until the parameter generation model converges to obtain the trained parameter generation model. Specifically, in step S103, multiple candidate parameter combinations are generated using a parameter generation model, including the following steps S1031 to S1033.

[0033] S1031, Construct a parameter generation model based on the Transformer decoder structure. The parameter generation model generates parameters one by one in an autoregressive manner according to the preset physical design parameter order. S1032, When generating parameters, the parameter generation model outputs the generation distribution information corresponding to the parameters. This generation distribution information includes: the mean of the Gaussian distribution. and variance ; S1033, Gaussian distribution random sampling is performed based on the generation distribution information corresponding to each parameter to generate multiple candidate parameter combinations; at the same time, during the sampling process, the log probability density corresponding to each candidate parameter combination is calculated; where the log probability density is the sum of the logarithms of the sampling probability densities of each parameter.

[0034] Specifically, in step S103, multiple candidate parameters are combined and input into the small-sample power consumption evaluation proxy model to obtain the corresponding predicted power consumption results. The model parameters of the parameter generation model are then updated based on the predicted power consumption results, including: (1) Combine multiple candidate parameters to form a group, input the group into the small sample power consumption evaluation proxy model, and obtain the predicted power consumption results corresponding to each candidate parameter combination; (2) Take the negative of each predicted power consumption result as the reward value corresponding to each candidate parameter combination, and calculate the mean and variance of the group reward value corresponding to the group based on the reward value corresponding to each candidate parameter combination. (3) Determine the dominance function value corresponding to each candidate parameter combination based on the reward value of each candidate parameter combination, the mean of the group reward value, and the group variance; Here, the dominance function value corresponding to each candidate parameter combination is determined based on the reward value of each candidate parameter combination, the mean of the group reward value, and the group variance, including: The advantage function value corresponding to each candidate parameter combination is calculated using the following formula: ; in, Indicates the first Each batch of rewards; This represents the average reward across K batches; This represents the variance of rewards for the K batches; It represents a very small constant greater than zero (such as 1e-8) to prevent the dividend from being zero; Indicates the first The dominant function values ​​for each batch.

[0035] (4) Based on the advantage function value and the log probability density corresponding to each candidate parameter combination, construct the loss function and update the parameters of the parameter generation model with the goal of minimizing the loss function.

[0036] Here, the loss function is expressed as: ; in, Indicates the first The log probability density of each batch; Indicates the first The dominant function values ​​for each batch; This is the expected value of the formula, which is the average value after summation; This represents the training loss value.

[0037] For example, firstly, a parameter sequence generation model of the Transformer structure is constructed to perform ordered modeling and joint generation of physical design parameters.

[0038] The Transformer model has the following structure: the parameters generated in the previous step are embedded and input into a four-layer decoder structure, and then input into a linear layer. The output of the linear layer is 2-dimensional.

[0039] The parameter sequence generation model outputs the generation distribution information of each physical design parameter one by one according to the preset parameter order.

[0040] The generated distribution information consists of the mean μ and variance σ of the generated parameter sequence. The mean μ represents the final result generated by the model, and the variance σ is used to characterize the uncertainty in the parameter generation process.

[0041] Then, based on the generated distribution information, each physical design parameter is sampled according to a Gaussian distribution with mean μ and variance σ to generate K batch candidate physical design parameter combination sequences, and the sampling probability information corresponding to each output in the sequence is output.

[0042] The batch size K is a hyperparameter that is fixed during training. Its suitability needs to be judged based on the stability of the model's training loss curve; its range is generally [range missing]. Typical values ​​are: 4, 8, 16.

[0043] The final log probability density of each batch of sequences is calculated as follows: take the logarithm of the sampled probability density of each output in the sequence, and the sum of the logarithms of all sampled probability densities in the sequence is used as the log probability density of that sequence. .

[0044] The next step is to group the K batches of candidate physical design parameter combinations into a group, and use the power consumption assessment proxy model as the reward model to predict the power consumption results corresponding to each parameter combination sequence in the group.

[0045] Finally, an improved group-relative strategy optimization method is used to calculate the advantage function of each parameter combination within the group relative to the power consumption target. Then, the loss function is calculated, and the Transformer model is updated via backpropagation. The specific steps are as follows: Within the same parameter combination group, by comparing the power consumption prediction results of different parameter combinations, the advantage function of each parameter combination relative to the group average power consumption is calculated to reflect the relative advantage of the parameter combination within the group.

[0046] Within a group, relative advantage is a dynamically changing quantity, referring to the superiority of each batch's power consumption compared to the average of the K batches across K combinations of parameters. The calculation process for the advantage function is as follows: (1) Rewards for each batch This is the inverse of the predicted power consumption value for this batch. (2) Calculate the average reward for the K batches: ; (3) Calculate the variance of rewards for the K batches: ; (4) Calculate the dominance function for each batch, see formula (3); where, for The calculated advantage function does not contain gradient information. The loss function is then calculated using formula (4). The calculated loss function contains gradient information, and the Transformer model is updated by backpropagation of this loss function. By minimizing... This enables the combination of parameters output by the Transformer model to optimize the output of the power consumption assessment proxy model, thus achieving the exploration of the physical design parameters with optimal power consumption.

[0047] S104 uses the trained parameter generation model to generate a combination of physical design parameters and calls the EDA tool to execute the physical design process to obtain the actual power consumption result. The actual power consumption result is used as feedback to optimize and adjust the parameter generation model. The optimized and adjusted combination of physical design parameters is output as the chip design result with optimized power consumption.

[0048] Specifically, in step S104, the parameter generation model is optimized and adjusted using the actual power consumption result as feedback, and the combination of physical design parameters generated after optimization and adjustment is output as the chip design result of power consumption optimization, including the following steps S1041 to S1042.

[0049] S1041, using the inverse of the actual power consumption result as the reward value, and employing the group relative strategy optimization method to calculate the advantage function value of each parameter combination; S1042 introduces a constraint mechanism to update the parameters of the parameter generation model based on the dominance function value and the generation probability of each parameter combination.

[0050] Here, a constraint mechanism is introduced to fine-tune the parameter generation model, including: (1) Calculate the generation probability ratio of each candidate parameter combination under the current parameter generation model and the parameter generation model before the update; where the generation probability ratio is the ratio of the probability of the current parameter generation model generating the first candidate parameter combination to the probability of the parameter generation model before the update generating the second candidate parameter combination. (2) Calculate the KL divergence of the policy distribution between the current parameter generation model and the trained parameter generation model; (3) Construct a fine-tuning objective function based on the generation probability ratio, KL divergence, and dominance function value; (4) Update the parameters of the parameter generation model with the goal of minimizing the fine-tuning objective function.

[0051] For example, firstly, using the autoregressive Transformer model trained in step three and the sampling strategy in step three, N batches of physical design parameter combinations are sampled.

[0052] The batch size N is a hyperparameter for the fine-tuning phase. This value needs to take into account the stability of model fine-tuning and the number of processes running the physical process in parallel. The value of N should be greater than the required number of processes, typically 4 or 8.

[0053] Then, for the parameter combinations obtained from sampling, the EDA tool is called in parallel to execute the physical design process and obtain the actual PPA and DRC results.

[0054] The next step is to select the optimal combination of physical design parameters based on the actual power consumption assessment results, which will be used as the current optimization result.

[0055] Simultaneously, the actual evaluation results are fed back to the autoregressive Transformer model, and the model is fine-tuned using a group relative strategy optimization method, gradually converging to the power-optimal design parameter distribution. The specific process is as follows: Calculate the probability ratio of the old and new strategies at each sampling point, using... This indicates step three. The output process, the probability ratio of the new and old strategies is calculated using the following formula: ; in, This is the old model before the update, which does not contain gradient information; Calculate the dominance function for each batch according to the procedure in step three. ; Calculate the KL divergence of the probabilities of the sampling points between the new model and the reference model: ; in, This is the reference model frozen after training in step three; The formula for calculating the loss function during the fine-tuning process is as follows: ; ; in, It is 0.2. It is 0.1.

[0056] By minimizing This enables the Transformer model to migrate from a proxy model to a real EDA environment, thereby efficiently finding the optimal combination of design parameters in the design space.

[0057] In a second aspect, the present invention provides an apparatus for efficient automated power consumption optimization in chip physical design, the apparatus comprising: The dataset construction module is used to determine the set of physical design parameters and the boundaries of each physical design parameter according to the process node of the digital chip to be designed, and to sample and generate multiple sets of parameter combination samples to form the initial dataset. The proxy model building module is used to obtain a small-sample power consumption evaluation proxy model by utilizing a pre-trained general-purpose pedestal-type large model and based on the parameter combination samples in the initial dataset through a context learning mechanism. The parameter generation model training module is used to generate multiple candidate parameter combinations using the parameter generation model, input the multiple candidate parameter combinations into the small sample power consumption evaluation proxy model to obtain the corresponding predicted power consumption results, update the model parameters of the parameter generation model according to the predicted power consumption results, and iteratively execute the parameter generation model training module until the parameter generation model converges to obtain the trained parameter generation model. The strategy transfer optimization module is used to generate physical design parameter combinations using the trained parameter generation model and call EDA tools to execute the physical design process to obtain real power consumption results. The real power consumption results are used as feedback to optimize and adjust the parameter generation model, and the optimized and adjusted physical design parameter combinations are output as the power-optimized chip design results.

[0058] For example, the dataset construction module is specifically used to: determine the set of physical design parameters involved in power consumption optimization based on the process node and design scale of the digital chip to be designed. The physical design parameters include at least one of the following: density and maximum fan-out in the placement stage; maximum fan-out of the clock tree in the clock tree synthesis stage; target transition time; target clock skew and maximum clock tree line length; and maximum signal transition time, maximum capacitance, and maximum line length in the routing stage. The value range boundaries of each physical design parameter are defined respectively. Several sets of parameter combination samples are generated in the multidimensional parameter space defined by the value range boundaries of each parameter using the Latin hypercube sampling method. For each set of parameter combination samples, the corresponding physical design process is executed by calling electronic design automation tools to obtain design results including power consumption, area, and timing. The parameter combination samples are associated and stored with the corresponding design results to construct a physical design dataset. The proxy model construction module is specifically used for: obtaining a pre-trained general-purpose pedestal-type large model; wherein the pedestal-type large model is a tabular data large model based on the Transformer architecture, which has been pre-trained on a synthetic dataset; taking the parameter combination samples and corresponding power consumption results in the initial dataset as context examples and inputting them into the pedestal-type large model; the pedestal-type large model, based on its pre-trained weights, learns the correlation between the parameters and power consumption represented by the context examples through a context learning mechanism, thereby obtaining a power consumption evaluation proxy model that can output corresponding power consumption prediction results for any combination of input physical design parameters. The parameter generation model training module is specifically used for: constructing a parameter generation model based on a Transformer decoder structure, wherein the parameter generation model generates parameters one by one in an autoregressive manner according to a preset physical design parameter order; when generating each parameter, the parameter generation model outputs the generation distribution information corresponding to that parameter, wherein the generation distribution information includes: Gaussian distribution mean μ and variance σ; performing Gaussian distribution random sampling based on the generation distribution information corresponding to each parameter to obtain specific parameter values ​​and generate multiple candidate parameter combinations; during the sampling process, calculating the log probability density corresponding to each candidate parameter combination, wherein the log probability density is the sampling probability density of each parameter included in the candidate parameter combination. The sum of the logarithms of the degrees; the multiple candidate parameters are combined to form a group, and the group is input into the small sample power consumption evaluation proxy model to obtain the predicted power consumption result corresponding to each candidate parameter combination; the negative of each predicted power consumption result is used as the reward value corresponding to each candidate parameter combination, and the mean and variance of the group reward value corresponding to the group are calculated based on the reward value corresponding to each candidate parameter combination; the advantage function value corresponding to each candidate parameter combination is determined based on the reward value of each candidate parameter combination, the mean of the group reward value, and the variance of the group; the loss function is constructed based on the advantage function value and the log probability density corresponding to each candidate parameter combination, and the parameters of the parameter generation model are updated with the goal of minimizing the loss function.The strategy migration optimization module is specifically used to: generate a combination of physical design parameters using the trained parameter generation model, call the EDA tool to execute the physical design process to obtain the corresponding real power consumption results, use the real power consumption results as feedback to optimize and adjust the parameter generation model, and output the optimized and adjusted combination of physical design parameters as the chip design result with power consumption optimization.

[0059] In a specific embodiment of the present invention, to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0060] See Figure 2 Step one involves a cold start under a completely new design or process, constructing a physical design training set. When selecting parameters, those skilled in the art should choose based on experience; these parameters are generally fixed. In the physical design process, the continuous design parameters related to power consumption are generally the following nine: density and maximum fan-out in the placement stage; maximum fan-out of the clock tree, target transition time, target clock skew, and maximum clock tree line length in the clock tree synthesis stage; and maximum signal transition time, maximum capacitance, and maximum line length in the routing stage. This embodiment selects the above nine design parameters and the Latin hypercube sampling method for three designs D1, D2, and D3, sampling approximately 20 parameter combinations. The Innovus tool is used to run these parameter combinations to obtain power consumption labels.

[0061] Step 2: Construction of the power consumption assessment proxy model. This embodiment uses the general data processing pedestal-style large model TabPFN, which has a 12-layer encoder structure with a total of 25.82M parameters. Each encoder layer includes a multi-head attention mechanism and a feedforward neural network, where the embedding dimension of the multi-head attention mechanism is 192 and the number of attention heads is 6. This model has been pre-trained by the original researchers on a synthetic dataset of hundreds of millions of data points, and this embodiment directly uses these pre-trained model weights. In the physical design process, obtaining datasets is extremely difficult. For example, in the D2 design in this embodiment, the acquisition time for a single data point exceeded 1 hour, and only 24 data samples were obtained in total. Therefore, this invention does not directly fine-tune the pedestal-style large model. Instead, it adopts implicit fine-tuning through a context learning mechanism. Based on the pre-trained model weights, the obtained 20 or so data samples are input into the model for training during inference, achieving a kind of fine-tuning. The fine-tuned model is saved as the power consumption assessment proxy model.

[0062] Step 3: Train the Transformer model for power consumption optimization. Construct a Transformer model with 4 decoders and 4 attention heads. Then, iterate the training of the model 200 times using a group relative policy optimization approach. Specifically, sample the design parameter outputs of 16 batches from the model, use the power consumption prediction of the power consumption assessment surrogate model from Step 2 as the reward, and then calculate the loss function and backpropagate to update the model.

[0063] Step 4: Transformer model policy transfer and guided physical design power optimization. Load two models trained in Step 3, freezing all parameters in one and using the other for fine-tuning. Then, iterate five times using a group-relative policy optimization approach to fine-tune the model. Specifically, sample four batches of design parameters from the model, run these four parameter combinations using the Innovus tool, use the tool's power consumption result as a reward, and fine-tune the model using a group-relative policy optimization approach. The design parameters corresponding to the optimal power consumption result are the final design space parameter combinations.

[0064] The feasibility of the method was verified in three designs and compared with current state-of-the-art (SOTA) methods, as shown in Table 1. The baseline design adjusted the design parameters based on accumulated experience. Bayesian optimization, ant colony optimization, and the method of this invention all used the same dataset of approximately 20 samples before algorithm iteration. The results show that the power consumption optimization effect of this invention on the test circuit reached 5%-8%, which is superior to Bayesian optimization, ant colony optimization, and other algorithms. Furthermore, the number of iterations required by this invention is significantly less than other methods.

[0065] Table 1. Power consumption optimization effect of the present invention on different designs and comparison with the optimization effect of other methods.

[0066] The various embodiments described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. All or part of this invention can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0067] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A method for efficient automated power consumption optimization in chip physical design, characterized in that, include: S101, Based on the process node of the digital chip to be designed, determine the set of physical design parameters and the boundaries of each physical design parameter, and sample and generate multiple sets of parameter combination samples to form the initial dataset; S102, using a pre-trained general pedestal-type large model, based on the parameter combination samples in the initial dataset, a small sample power consumption evaluation proxy model is obtained through a context learning mechanism; S103: Generate multiple candidate parameter combinations using a parameter generation model, input the multiple candidate parameter combinations into the small sample power consumption evaluation proxy model to obtain the corresponding predicted power consumption results, update the model parameters of the parameter generation model according to the predicted power consumption results, iterate S103 until the parameter generation model converges, and obtain the trained parameter generation model. S104: The trained parameter generation model is used to generate a combination of physical design parameters, and the EDA tool is called to execute the physical design process to obtain the actual power consumption result. The actual power consumption result is used as feedback to optimize and adjust the parameter generation model, and the optimized and adjusted combination of physical design parameters is output as the chip design result with optimized power consumption.

2. The method for efficient automated power consumption optimization in chip physical design according to claim 1, characterized in that, The step of determining the set of physical design parameters based on the process node of the digital chip to be designed includes: Based on the process node and design scale of the digital chip to be designed, determine the set of physical design parameters involved in power consumption optimization. The physical design parameters include at least one of the following: density and maximum fan-out in the placement stage, maximum fan-out of the clock tree in the clock tree synthesis stage, target transition time, target clock skew and maximum clock tree line length, and maximum signal transition time, maximum capacitance and maximum line length in the routing stage. Each physical design parameter has its own defined range of values. The Latin hypercube sampling method is used to generate multiple sets of parameter combination samples in a multidimensional parameter space defined by the boundaries of the range of values ​​of each parameter; For each set of parameter combinations, electronic design automation tools are called to execute the corresponding physical design process to obtain design results including power consumption, area, and timing. The parameter combination samples are associated with and stored with the corresponding design results to construct a physical design dataset.

3. The method for efficient automated power consumption optimization in chip physical design according to claim 1, characterized in that, The method utilizes a pre-trained general-purpose pedestal-type large model, based on parameter combination samples in the initial dataset, and obtains a small-sample power consumption evaluation proxy model through a context learning mechanism, including: Obtain a pre-trained general pedestal-type large model; wherein, the pedestal-type large model is a tabular data large model based on the Transformer architecture, which has been pre-trained on a synthetic dataset; The parameter combination samples and corresponding power consumption results in the initial dataset are used as context examples and input into the pedestal-type large model; The pedestal-type large model, based on training weights, learns the correlation between the parameter combination samples represented by the context examples and the corresponding power consumption results through a context learning mechanism to obtain the small sample power consumption evaluation proxy model; wherein, the small sample power consumption evaluation proxy model can output the corresponding power consumption prediction result for any combination of input physical design parameters.

4. The method for efficient automated power consumption optimization in chip physical design according to claim 1, characterized in that, The method of generating multiple candidate parameter combinations using a parameter generation model includes: A parameter generation model based on the Transformer decoder structure is constructed. The parameter generation model generates parameters one by one in an autoregressive manner according to the preset physical design parameter order. When generating the parameters, the parameter generation model outputs the generation distribution information corresponding to the parameters, wherein the generation distribution information includes: Gaussian distribution mean. and variance ; Based on the generated distribution information corresponding to each parameter, Gaussian distribution random sampling is performed to generate multiple candidate parameter combinations; at the same time, during the sampling process, the log probability density corresponding to each candidate parameter combination is calculated; wherein, the log probability density is the sum of the logarithms of the sampling probability densities of each parameter.

5. The method for efficient automated power consumption optimization in chip physical design according to claim 4, characterized in that, The step of combining the multiple candidate parameters and inputting them into the small-sample power consumption evaluation proxy model to obtain the corresponding predicted power consumption result, and updating the model parameters of the parameter generation model based on the predicted power consumption result, includes: The multiple candidate parameters are combined to form a group, and the group is input into the small sample power consumption evaluation proxy model to obtain the predicted power consumption result corresponding to each candidate parameter combination; The negative of each predicted power consumption result is used as the reward value corresponding to each candidate parameter combination, and the mean and variance of the group reward value corresponding to the group are calculated based on the reward value corresponding to each candidate parameter combination. The dominance function value corresponding to each candidate parameter combination is determined based on the reward value of each candidate parameter combination, the mean of the group reward value, and the variance of the group. Based on the advantage function value and the log probability density corresponding to each candidate parameter combination, a loss function is constructed, and the parameters of the parameter generation model are updated with the goal of minimizing the loss function.

6. The method for efficient automated power consumption optimization for chip physical design according to claim 5, characterized in that, The step of determining the dominance function value corresponding to each candidate parameter combination based on the reward value of each candidate parameter combination, the mean of the group reward value, and the variance of the group includes: The advantage function value corresponding to each candidate parameter combination is calculated using the following formula: ； in, Indicates the first Each batch of rewards; This represents the average reward across K batches; This represents the variance of the rewards for the K batches; To represent a constant, preventing the dividend from being zero; Indicates the first The dominant function values ​​for each batch.

7. The method for efficient automated power consumption optimization in chip physical design according to claim 5, characterized in that, The loss function is expressed as: ； in, Indicates the first The log probability density of each batch; Indicates the first The dominant function values ​​for each batch; This is the expected value of the formula, which is the average value after summation; This represents the training loss value.

8. The method for efficient automated power consumption optimization in chip physical design according to claim 5, characterized in that, The step of using the actual power consumption results as feedback to optimize and adjust the parameter generation model, and outputting the optimized and adjusted combination of physical design parameters as the power-optimized chip design result, includes: The negative of the actual power consumption result is used as the reward value, and the advantage function value of each parameter combination is calculated using the group relative strategy optimization method. A constraint mechanism is introduced to update the parameters of the parameter generation model based on the value of the advantage function and the generation probability of each parameter combination.

9. The method for efficient automated power consumption optimization in chip physical design according to claim 8, characterized in that, The introduction of a constraint mechanism to fine-tune the parameter generation model includes: Calculate the generation probability ratio of each candidate parameter combination under the current parameter generation model and the parameter generation model before the update; wherein, the generation probability ratio is the ratio of the probability of the current parameter generation model generating the first candidate parameter combination to the probability of the parameter generation model before the update generating the second candidate parameter combination. Calculate the KL divergence of the policy distribution between the current parameter generation model and the trained parameter generation model; A fine-tuning objective function is constructed based on the generation probability ratio, the KL divergence, and the dominance function value. The parameters of the parameter generation model are updated with the goal of minimizing the fine-tuning objective function.

10. A device for efficient automated power consumption optimization in chip physical design, characterized in that, include: The dataset construction module is used to determine the set of physical design parameters and the boundaries of each physical design parameter according to the process node of the digital chip to be designed, and to sample and generate multiple sets of parameter combination samples to form the initial dataset. The proxy model building module is used to obtain a small-sample power consumption evaluation proxy model by utilizing a pre-trained general pedestal-type large model and based on the parameter combination samples in the initial dataset through a context learning mechanism. The parameter generation model training module is used to generate multiple candidate parameter combinations using the parameter generation model, input the multiple candidate parameter combinations into the small sample power consumption evaluation proxy model to obtain the corresponding predicted power consumption results, update the model parameters of the parameter generation model according to the predicted power consumption results, and iteratively execute the parameter generation model training module until the parameter generation model converges to obtain the trained parameter generation model. The strategy migration optimization module is used to generate a combination of physical design parameters using the trained parameter generation model and call the EDA tool to execute the physical design process to obtain the actual power consumption result. The actual power consumption result is used as feedback to optimize and adjust the parameter generation model, and the optimized and adjusted combination of physical design parameters is output as the chip design result with power optimization.

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