A method, apparatus, device, and storage medium for predicting wafer surface flatness

Abstract

The present application relates to the field of integrated circuit manufacturing, in particular to a method, device, equipment and storage medium for predicting wafer surface flatness, which receives a chip layout to be measured; divides the chip layout to be measured into multiple calculation target areas according to a preset target resolution; determines a simulation area corresponding to each calculation target area; rasterizes the chip layout to be measured corresponding to the simulation area to obtain a simulation raster image; inputs the simulation raster image into a wafer surface flatness model to obtain a simulation output image; determines a flatness simulation image corresponding to each calculation target area; and determines a simulation height value of each position of the chip layout to be measured according to the flatness simulation image corresponding to each calculation target area. The present application considers the influence of the graphics of the periphery of the area on the simulation result in the simulation process, greatly improves the accuracy of the flatness prediction, and also improves the resolution of the flatness prediction.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method, apparatus, device, and storage medium for predicting the surface flatness of a wafer. Background Technology

[0002] The surface flatness of wafers is typically predicted using chemical mechanical polishing (CMP) models. Traditional CMP models generally rely on a semi-physical, semi-empirical relationship between polishing rate and the average geometric features of the design layout. This results in low simulation accuracy and resolution, failing to meet the requirements for surface flatness simulation and related hotspot prediction at advanced nodes. Furthermore, calibrating the parameters of traditional CMP models requires collecting wafer data after each process step, including etching, thin film deposition, and CMP, leading to a lengthy modeling cycle.

[0003] Wafer surface flatness refers to the height difference between various locations on a wafer. In the manufacturing of large-scale integrated circuits, wafer surface flatness is crucial. Poor wafer surface flatness can lead to "out-of-focus" defects during photolithography, causing breakpoints, bridging, and other defects, thus reducing yield. To achieve better wafer surface flatness, chemical mechanical polishing (CMP) is typically performed at the end of each layer process to planarize the uneven wafer surface. To verify the wafer surface flatness after CMP, the industry has introduced CMP-related models, generally using simulation grids of a few micrometers to predict the height of various locations on the wafer. When the height difference between different locations on the wafer is large, the CMP process can be improved, or appropriate dummy patterns can be added to the design layout to improve wafer surface flatness.

[0004] When using existing chemical mechanical polishing (CMP) models to predict wafer surface flatness, the geometric features such as equivalent linewidth, equivalent spacing, and density of the chip design layout of a simulation unit are first extracted. Then, a semi-physical, semi-empirical relationship model of the geometric features is simulated based on a calibrated polishing rate to obtain the average wafer height of the simulation unit. However, in reality, the wafer height varies for patterns with different linewidths and spacings within the simulation unit. Therefore, the simulation accuracy and resolution of existing methods are not high, and they cannot meet the requirements for wafer surface flatness simulation and related hotspot prediction at advanced nodes.

[0005] Therefore, how to improve the accuracy and resolution of wafer surface flatness prediction is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a method, apparatus, device, and storage medium for predicting wafer surface flatness, in order to solve the problem that the accuracy and resolution of wafer surface flatness prediction in the prior art are both poor.

[0007] To address the aforementioned technical problems, this invention provides a method for predicting wafer surface flatness, comprising:

[0008] Receive the layout of the chip under test;

[0009] The layout of the chip under test is divided into multiple target computing regions according to a preset target resolution;

[0010] Centered on the target computation region, a simulation region corresponding to each target computation region is determined according to a preset processing resolution; the processing resolution is greater than the target resolution, and the edge distance between the target computation region and the simulation region is the effective range of the pre-trained wafer surface flatness model;

[0011] The layout of the chip under test corresponding to the simulation area is rasterized to obtain a simulation raster image;

[0012] The simulated raster image is input into the wafer surface flatness model to obtain the simulated output image;

[0013] A portion of the simulated output image is cropped from the center according to the target resolution, and used as the flatness simulation image corresponding to the calculated target region.

[0014] Based on the flatness simulation images corresponding to each of the calculated target regions, the simulation height values ​​of each position on the chip layout under test are determined.

[0015] Optionally, in the method for predicting wafer surface flatness, the training method for the wafer surface flatness model includes:

[0016] Receive template modeling pattern layout;

[0017] Based on the template modeling pattern layout, prepare a modeling pattern wafer;

[0018] Scan the modeled pattern wafer to obtain a wafer surface flatness measurement image; each pixel in the wafer surface flatness measurement image has a corresponding height value;

[0019] Based on the processing resolution, the template modeling pattern layout is divided into multiple areas to be processed;

[0020] The template modeling pattern layout corresponding to the area to be processed is rasterized to obtain a template raster image;

[0021] The template grid image is input into the wafer surface flatness model to be trained, so that the wafer surface flatness model to be trained outputs an output image of the processing resolution, and each pixel in the output image has a corresponding height value; then, the evaluation region image of the target resolution is cropped from the center of the output image.

[0022] The wafer surface flatness model is iterated based on the wafer surface flatness measurement image and the evaluation region image until the height difference between the corresponding regions on the evaluation region image and the wafer surface flatness measurement image is less than a preset tolerance threshold.

[0023] Optionally, in the method for predicting wafer surface flatness, after scanning the modeled pattern wafer to obtain a wafer surface flatness measurement image, the method further includes:

[0024] The height values ​​corresponding to each pixel in the wafer surface flatness measurement image are normalized and represented by grayscale values.

[0025] Accordingly, the template grid image is input into the wafer surface flatness model to be trained, so that the wafer surface flatness model to be trained outputs an output image at the processing resolution, wherein each pixel in the output image has a corresponding height value, including:

[0026] The template grid image is input into the wafer surface flatness model to be trained, and the wafer surface flatness model to be trained outputs an output image at the processing resolution. The gray value of each pixel in the output image is a normalized height value.

[0027] Accordingly, the simulated raster image is input into the wafer surface flatness model to obtain a simulated output image, including:

[0028] The simulated raster image is input into the wafer surface flatness model to obtain a simulated output image; the grayscale value of each pixel in the simulated output image is a normalized height value.

[0029] Accordingly, based on the flatness simulation images corresponding to each of the calculated target regions, the simulation height values ​​at each location of the chip layout under test are determined, including:

[0030] The grayscale values ​​of the pixels in the flatness simulation image corresponding to each of the calculated target regions are restored to height values, which are then used as the simulated height values ​​for each position of the chip layout under test.

[0031] Optionally, in the method for predicting wafer surface flatness, the height values ​​corresponding to each pixel in the wafer surface flatness measurement image are normalized and represented by grayscale values, including:

[0032] The height values ​​corresponding to each pixel in the wafer surface flatness measurement image are normalized using the following formula, and represented by grayscale values:

[0033] ;

[0034] Among them, WI i Let ΔWH be the grayscale value of pixel i in the image. i Here, HF0 is the height value corresponding to pixel i, HT0 is the preset reference height, and HT0 is the film thickness corresponding to the lowest position on the surface in the wafer surface flatness measurement image.

[0035] Optionally, in the method for predicting wafer surface flatness, the grayscale values ​​of pixels in the flatness simulation image corresponding to each of the calculated target regions are restored to height values, which are then used as the simulated height values ​​for each location of the chip layout under test, including:

[0036] The grayscale values ​​of pixels in the flatness simulation image corresponding to each of the calculated target regions are converted into height values ​​using the following formula, which are then used as the simulated height values ​​for each location on the chip layout under test:

[0037] ;

[0038] Among them, SH i SI is the simulated height value at the corresponding position of pixel i. i Here, HF0 is the grayscale value of pixel i in the flatness simulation image, HT0 is the preset reference height, and HT0 is the film thickness corresponding to the lowest position on the surface in the wafer surface flatness measurement image.

[0039] Optionally, in the method for predicting wafer surface flatness, the wafer surface flatness model is iterated based on the wafer surface flatness measurement image and the evaluation region image until the height difference between corresponding regions on the evaluation region image and the wafer surface flatness measurement image is less than a preset tolerance threshold, including:

[0040] The wafer surface flatness model is iterated based on the wafer surface flatness measurement image and the evaluation region image. When the loss function in the formula is less than a preset first threshold, the height difference between the corresponding regions on the evaluation region image and the wafer surface flatness measurement image is considered to be less than a preset tolerance threshold.

[0041] ;

[0042] Where CF is the function value of the loss function, SI iLet WI be the grayscale value of pixel i in the flatness simulation image. i Let w be the image grayscale value of the pixel corresponding to pixel i in the measured image on the flatness of the wafer surface. i is the weight coefficient corresponding to pixel i.

[0043] Optionally, in the method for predicting wafer surface flatness, the method for determining the height value corresponding to the pixel in the wafer surface flatness measurement image includes:

[0044] The modeled pattern wafer was scanned using an atomic force microscope to obtain the height values ​​of each scanning point on the modeled pattern wafer;

[0045] The height value corresponding to the pixel is obtained by averaging the height values ​​of all scan points in the region corresponding to the pixel in the flatness measurement image of the wafer surface.

[0046] An apparatus for predicting wafer surface flatness, comprising:

[0047] The receiving module is used to receive the layout of the chip under test;

[0048] The region division module is used to divide the layout of the chip under test into multiple computing target regions according to a preset target resolution.

[0049] The region expansion module is used to determine the simulation region corresponding to each of the computation target regions according to a preset processing resolution, with the computation target region as the center; the processing resolution is greater than the target resolution, and the edge distance between the computation target region and the simulation region is the effective range of the pre-trained wafer surface flatness model;

[0050] The rasterization module is used to rasterize the layout of the chip under test corresponding to the simulation area to obtain a simulation raster image.

[0051] The model calculation module is used to input the simulated raster image into the wafer surface flatness model to obtain a simulated output image.

[0052] The cropping module is used to crop a portion of the center of the simulation output image according to the target resolution, as the flatness simulation image corresponding to the calculated target region;

[0053] The height value determination module is used to determine the simulated height value of each position of the chip layout under test based on the flatness simulation image corresponding to each of the calculated target areas.

[0054] An apparatus for predicting wafer surface flatness includes:

[0055] Memory, used to store computer programs;

[0056] A processor, configured to implement the steps of any of the above-described methods for predicting wafer surface flatness when executing the computer program.

[0057] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above-described methods for predicting wafer surface flatness.

[0058] The method for predicting wafer surface flatness provided by this invention involves receiving a chip layout under test; dividing the chip layout under test into multiple computational target regions according to a preset target resolution; determining a simulation region corresponding to each computational target region according to a preset processing resolution, with the computational target region as the center; the processing resolution being greater than the target resolution, and the edge distance between the computational target region and the simulation region being the effective range of a pre-trained wafer surface flatness model; rasterizing the chip layout under test corresponding to the simulation region to obtain a simulation raster image; inputting the simulation raster image into the wafer surface flatness model to obtain a simulation output image; cropping a portion of the center of the simulation output image according to the target resolution as the flatness simulation image corresponding to the computational target region; and determining the simulation height value at each position of the chip layout under test based on the flatness simulation images corresponding to each computational target region.

[0059] This invention takes a rasterized image of a chip layout as input and uses a pre-trained convolutional neural network model (i.e., the wafer surface flatness model) to output a simulated image of the wafer surface flatness. Instead of directly using the output as the simulated height value of the chip layout under test, it extracts a flatness simulation image of the target resolution from the simulated output image based on the model's effective range. The influence of surrounding graphics on the simulation results is considered during the simulation process, significantly improving both the accuracy and resolution of flatness prediction. This invention also provides an apparatus, device, and storage medium for predicting wafer surface flatness with the aforementioned beneficial effects. Attached Figure Description

[0060] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 A flowchart illustrating a specific embodiment of the method for predicting wafer surface flatness provided by the present invention;

[0062] Figure 2 A flowchart illustrating the training method of a specific embodiment of the method for predicting wafer surface flatness provided by the present invention;

[0063] Figure 3 A schematic diagram of the positional relationships in a specific embodiment of the method for predicting wafer surface flatness provided by the present invention;

[0064] Figure 4 This is a schematic diagram of a specific embodiment of the device for predicting wafer surface flatness provided by the present invention.

[0065] Figure label:

[0066] 100 - Receiver module, 200 - Region division module, 300 - Region expansion module, 400 - Rasterization module, 500 - Model calculation module, 600 - Capture module, 700 - Height value determination module. Detailed Implementation

[0067] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0068] The core of this invention is to provide a method for predicting wafer surface flatness, and a flowchart of one specific embodiment is shown below. Figure 1 As shown, this is referred to as Specific Implementation Method One, which includes:

[0069] S101: Receives the layout of the chip under test.

[0070] The chip layout to be tested is the chip layout for which the wafer surface flatness prediction is about to be performed.

[0071] S102: Divide the layout of the chip under test into multiple target computing regions according to a preset target resolution.

[0072] It should be noted that before the chip under test layout is divided into multiple computing target regions according to the preset target resolution, the chip under test layout needs to be converted into a pixel layout. That is, the chip under test layout will be divided into pixels using a preset pixel size. For example, if the pixel size is set to 200 nanometers, the chip under test layout will be converted into a layout composed of pixels with a side length of 200 nanometers.

[0073] After pixelating the layout of the chip under test, this step can be performed to divide the layout into multiple calculation target regions according to the target resolution. For example, if the target resolution is 300*300, then the calculation target region is a region composed of 300*300 pixels. Continuing with the example, if the overall resolution of the chip under test layout is 900*900, then according to the target resolution of 300*300, the chip under test layout can be divided into 9 calculation target regions.

[0074] S103: Taking the target computation region as the center, determine the simulation region corresponding to each target computation region according to the preset processing resolution; the processing resolution is greater than the target resolution, and the edge distance between the target computation region and the simulation region is the effective range of the pre-trained wafer surface flatness model.

[0075] Specifically, the wafer surface flatness model can use a convolutional neural network model. The effective range is the radius of the graphic area that the model needs to calculate when predicting wafer surface flatness. In other words, for the calculation of the simulation value of the target region, graphics outside the simulation region will not affect its simulation value. The relationship between the simulation region, the target region, and the effective range is illustrated in the diagram below. Figure 2 As shown.

[0076] For example, if the target calculation area is a 300*300 area (that is, the target resolution is 300*300) and the processing resolution is 512*512, then a 106-pixel wide square ring needs to be added around the original 300*300 target calculation area to obtain the simulation area.

[0077] S104: Rasterize the layout of the chip under test corresponding to the simulation area to obtain a simulation raster image.

[0078] The rasterization method can be found in related technologies, and will not be elaborated upon here.

[0079] S105: Input the simulated raster image into the wafer surface flatness model to obtain the simulated output image.

[0080] The resolution of the simulated output image should be consistent with the resolution of the input simulated raster image, and of course, also consistent with the resolution of the simulated area.

[0081] S106: A portion of the simulated output image is cropped from the center according to the target resolution, and used as the flatness simulation image corresponding to the calculated target region.

[0082] Although the simulation output image of the wafer surface flatness model has the same resolution as the input simulation raster image, it should be noted that when calculating the simulation values ​​corresponding to the edge positions of the simulation raster image, the influence of the surrounding graphics on the simulation values ​​cannot be calculated for positions near the edge due to the lack of surrounding graphics. Therefore, in this step, only the simulation values ​​of the simulation image of a portion of the center of the simulation output image are retained. In other words, only the simulation values ​​of positions where graphics exist at all locations within the effective range are retained, thereby ensuring the accuracy and precision of the simulation.

[0083] S107: Based on the flatness simulation image corresponding to each of the calculated target areas, determine the simulation height value of each position of the chip layout under test.

[0084] By stitching together the flatness simulation images of all the target areas, the flatness simulation image of the chip layout under test can be obtained, which includes the simulation height values ​​of each position on the chip layout under test.

[0085] As one specific implementation method, a flowchart illustrating a specific embodiment of the training method for the wafer surface flatness model is shown below. Figure 3 As shown, it includes:

[0086] A1: Receive template modeling pattern layout.

[0087] The template modeling pattern layout is determined based on the modeling pattern set of the wafer surface flatness model, including one-dimensional and two-dimensional periodic patterns with different geometric features, as well as two-dimensional complex patterns.

[0088] A2: Prepare a modeled pattern chip based on the template modeling pattern layout.

[0089] Based on the template modeling pattern layout, a corresponding test mask is first generated, and then processes such as thin film deposition, photolithography, etching, and chemical mechanical polishing are run to obtain the modeled pattern wafer. This step can refer to relevant technologies and will not be described in detail here.

[0090] A3: Scan the modeled pattern wafer to obtain a wafer surface flatness measurement image; each pixel in the wafer surface flatness measurement image has a corresponding height value.

[0091] Preferably, in this step, an atomic force microscope is used to measure and obtain a measurement image of the wafer surface flatness. To save measurement time, for one-dimensional graphics, only one scan is performed along the direction perpendicular to the graphic during measurement; for two-dimensional graphics, multiple scans are performed according to a preset sampling interval during measurement. The measurement result is the height difference between different positions on the modeled pattern and a reference height. The reference height can be a preset fixed height (generally not less than the thickness of the thickest position on the film), or it can be the thickness of the oxide film in a large oxide region (usually the thickest position on the film, i.e., the highest point of the upper surface).

[0092] As one specific implementation, the method for determining the height value corresponding to a pixel in the wafer surface flatness measurement image includes:

[0093] B1: The modeled pattern wafer is scanned using an atomic force microscope to obtain the height values ​​of each scanning point on the modeled pattern wafer.

[0094] B2: The height values ​​of all scan points in the region corresponding to the pixel in the flatness measurement image of the wafer surface are averaged to obtain the height value corresponding to the pixel.

[0095] In this preferred embodiment, the atomic force microscope is used to determine the height of the upper surface of the modeled pattern wafer. This method offers fast data acquisition, high efficiency, and high accuracy. It should be noted that in this specific embodiment, the scanning points of the atomic force microscope may not be the same as the pixels. For example, if the measurement step of the atomic force microscope is 20 nanometers, while the side length of a pixel is 200 nanometers, then the height value corresponding to a pixel should be the average of the height values ​​corresponding to 100 scanning points within the pixel's coverage area. This makes this specific embodiment more flexible and adaptable to more scenarios while ensuring the accuracy of the measurement results.

[0096] A4: Based on the processing resolution, the template modeling pattern layout is divided into multiple areas to be processed.

[0097] It is important to note here that not only is the processing resolution during training the same as the processing resolution during the use of the trained model mentioned earlier, but the target resolution during training, as mentioned below, is also the same as the target resolution during the use of the model mentioned earlier. In addition, the pixel size during model training should also be the same as the pixel size during model use (e.g., the pixel side length is 200 nanometers).

[0098] A5: Rasterize the template modeling pattern layout corresponding to the area to be processed to obtain a template raster image.

[0099] The rasterization method can be found in related technologies, and will not be elaborated here.

[0100] A6: Input the template grid image into the wafer surface flatness model to be trained, so that the wafer surface flatness model to be trained outputs an output image of the processing resolution, wherein each pixel in the output image has a corresponding height value; then, extract the evaluation region image of the target resolution from the center of the output image.

[0101] As mentioned above, the evaluation of the simulation accuracy of the wafer surface flatness model only considers the evaluation area image. This is because the pixels located at the edge of the output image do not take into account the influence of other graphics that were truncated when determining the area to be processed within the effective range, which reduces the simulation accuracy of the pixels at the edge of the area to be processed. Therefore, pixels in the non-evaluation area image should be discarded.

[0102] A7: Iterate the wafer surface flatness model based on the wafer surface flatness measurement image and the evaluation region image until the height difference between the corresponding regions on the evaluation region image and the wafer surface flatness measurement image is less than a preset tolerance threshold.

[0103] In this specific embodiment, the target image (i.e., the surface flatness measurement image) is established using atomic force microscopy measurement data for model training, which greatly improves the accuracy and resolution of wafer surface flatness prediction. In addition, the model training in this specific embodiment only requires measuring the data of the wafer after chemical mechanical polishing (i.e., the modeled pattern wafer), which greatly shortens the modeling cycle.

[0104] In a preferred embodiment, after scanning the modeled pattern wafer to obtain a wafer surface flatness measurement image, the method further includes:

[0105] C1: Normalize the height values ​​corresponding to each pixel in the flatness measurement image of the wafer surface and represent them with grayscale values.

[0106] Accordingly, the template grid image is input into the wafer surface flatness model to be trained, so that the wafer surface flatness model to be trained outputs an output image at the processing resolution, wherein each pixel in the output image has a corresponding height value, including:

[0107] C2: Input the template raster image into the wafer surface flatness model to be trained, so that the wafer surface flatness model to be trained outputs the output image at the processing resolution, wherein the gray value of each pixel in the output image is a normalized height value.

[0108] Accordingly, the simulated raster image is input into the wafer surface flatness model to obtain a simulated output image, including:

[0109] C3: Input the simulated raster image into the wafer surface flatness model to obtain a simulated output image; the grayscale value of each pixel in the simulated output image is a normalized height value.

[0110] Accordingly, based on the flatness simulation images corresponding to each of the calculated target regions, the simulation height values ​​at each location of the chip layout under test are determined, including:

[0111] C4: Restore the grayscale values ​​of the pixels in the flatness simulation image corresponding to each of the calculated target regions to height values, and use them as the simulated height values ​​of each position in the layout of the chip under test.

[0112] In this preferred embodiment, the height values ​​corresponding to each pixel are normalized. This not only simplifies the calculation process and improves the calculation efficiency, but also avoids the problem of limited applicability caused by using the absolute value of the height for calculation. This allows the model calculation to focus on the relative relationship of the height and not be affected by the absolute value of the height. While improving the calculation accuracy, it can further improve the versatility of the present invention.

[0113] Furthermore, the height values ​​corresponding to each pixel in the wafer surface flatness measurement image are normalized and represented by grayscale values, including:

[0114] The height values ​​corresponding to each pixel in the wafer surface flatness measurement image are normalized using the following formula (1), and represented by grayscale values:

[0115] ; (1)

[0116] Among them, WI i Let ΔWH be the grayscale value of pixel i in the image. i Here, HF0 is the height value corresponding to pixel i, HT0 is the preset reference height, and HT0 is the film thickness corresponding to the lowest position on the surface in the wafer surface flatness measurement image.

[0117] Of course, the reference height should not be lower than the film thickness corresponding to the highest position of the surface in the wafer surface flatness measurement image. Alternatively, the film thickness corresponding to the highest position of the surface in the wafer surface flatness measurement image can be directly used as the reference height. This can be determined according to the actual situation, and the present invention does not limit it here. In addition, the film thickness corresponding to the lowest position of the surface in the wafer surface flatness measurement image can be directly selected as the film thickness corresponding to the large area metal region in the wafer. Since metal is consumed the fastest in chemical mechanical polishing, especially large areas of continuous metal, the film thickness corresponding to the large area metal region is usually the film thickness corresponding to the lowest position of the surface. Equation (1) has high computational efficiency and low computing power. Of course, other methods can also be used to achieve the normalization of the height value, which will not be elaborated here.

[0118] In the wafer surface flatness measurement image obtained in equation (1), the highest position is the brightest and the lowest position is the darkest. Of course, it can also be the other way around, with the highest position being the darkest and the lowest position being the brightest. The corresponding calculation formula is shown in equation (2) below:

[0119] ; (2)

[0120] Among them, WI i Let ΔWH be the grayscale value of pixel i in the image. i Here, HF0 is the height value corresponding to pixel i, HT0 is the preset reference height, and HT0 is the film thickness corresponding to the lowest position of the surface in the wafer surface flatness measurement image. It can be referred to formula (1), and will not be repeated here.

[0121] Furthermore, the grayscale values ​​of pixels in the flatness simulation image corresponding to each of the calculated target regions are restored to height values, which are then used as the simulated height values ​​for each location on the chip layout under test, including:

[0122] The grayscale values ​​of the pixels in the flatness simulation image corresponding to each of the calculated target regions are restored to height values ​​using the following formula (3), which are then used as the simulated height values ​​for each location on the chip layout under test:

[0123] ; (3)

[0124] Among them, SH i SI is the simulated height value at the corresponding position of pixel i. i Here, HF0 is the grayscale value of pixel i in the flatness simulation image, HT0 is the preset reference height, and HT0 is the film thickness corresponding to the lowest position on the surface in the wafer surface flatness measurement image.

[0125] For a detailed explanation of the reference height and the film thickness corresponding to the lowest position on the surface in the wafer surface flatness measurement image, please refer to the previous text. It will not be repeated here. Equation (3) corresponds to Equation (1) and can restore the gray value to the height value. It has high computational efficiency and low computational power consumption.

[0126] The method for predicting wafer surface flatness provided by this invention involves receiving a chip layout under test; dividing the chip layout under test into multiple computational target regions according to a preset target resolution; determining a simulation region corresponding to each computational target region according to a preset processing resolution, with the computational target region as the center; the processing resolution being greater than the target resolution, and the edge distance between the computational target region and the simulation region being the effective range of a pre-trained wafer surface flatness model; rasterizing the chip layout under test corresponding to the simulation region to obtain a simulation raster image; inputting the simulation raster image into the wafer surface flatness model to obtain a simulation output image; cropping a portion of the center of the simulation output image according to the target resolution as the flatness simulation image corresponding to the computational target region; and determining the simulation height value at each position of the chip layout under test based on the flatness simulation images corresponding to each computational target region. This invention takes a rasterized image of a chip layout as input and uses a pre-trained convolutional neural network model (i.e., the wafer surface flatness model) to output a simulated image of the wafer surface flatness. Instead of directly using the output as the simulated height value of the chip layout under test, the flatness simulation image of the target resolution is extracted from the simulated output image according to the effective range of the model. The influence of the surrounding graphics on the simulation results is considered during the simulation process, which greatly improves the accuracy and resolution of flatness prediction.

[0127] In a preferred embodiment, the wafer surface flatness model is iterated based on the wafer surface flatness measurement image and the evaluation region image until the height difference between corresponding regions on the evaluation region image and the wafer surface flatness measurement image is less than a preset tolerance threshold, including:

[0128] The wafer surface flatness model is iterated based on the wafer surface flatness measurement image and the evaluation region image. When the loss function in equation (4) is less than a preset first threshold, it is considered that the height difference between the corresponding regions on the evaluation region image and the wafer surface flatness measurement image is less than a preset tolerance threshold.

[0129] ; (4)

[0130] Where CF is the function value of the loss function, SI iLet WI be the grayscale value of pixel i in the flatness simulation image. i Let w be the image grayscale value of the pixel corresponding to pixel i in the measured image on the flatness of the wafer surface. i is the weight coefficient corresponding to pixel i.

[0131] In this specific embodiment, the specific calculation method of the loss function is given. It should be noted that since the pixel size of the flatness simulation image and the wafer surface flatness measurement image is the same, for each pixel in the flatness simulation image, there is a corresponding pixel in the wafer surface flatness measurement image. Equation (4) compares each pixel in the flatness simulation image with the corresponding pixel in the wafer surface flatness measurement image and considers the weight of each pixel to obtain the loss function. Naturally, when the function value of the loss function is the smallest, the result of the model simulation is closest to the actual situation. While completing the model iterative training, the amount of computation is greatly reduced and the model training cycle is shortened.

[0132] The method for predicting wafer surface flatness provided by this invention involves receiving a chip layout under test; dividing the chip layout under test into multiple computational target regions according to a preset target resolution; determining a simulation region corresponding to each computational target region according to a preset processing resolution, with the computational target region as the center; the processing resolution being greater than the target resolution, and the edge distance between the computational target region and the simulation region being the effective range of a pre-trained wafer surface flatness model; rasterizing the chip layout under test corresponding to the simulation region to obtain a simulation raster image; inputting the simulation raster image into the wafer surface flatness model to obtain a simulation output image; cropping a portion of the center of the simulation output image according to the target resolution as the flatness simulation image corresponding to the computational target region; and determining the simulation height value at each position of the chip layout under test based on the flatness simulation images corresponding to each computational target region. This invention takes a rasterized image of a chip layout as input and uses a pre-trained convolutional neural network model (i.e., the wafer surface flatness model) to output a simulated image of the wafer surface flatness. Instead of directly using the output as the simulated height value of the chip layout under test, the flatness simulation image of the target resolution is extracted from the simulated output image according to the effective range of the model. The influence of the surrounding graphics on the simulation results is considered during the simulation process, which greatly improves the accuracy and resolution of flatness prediction.

[0133] The apparatus for predicting wafer surface flatness provided in the embodiments of the present invention will be described below. The apparatus for predicting wafer surface flatness described below and the method for predicting wafer surface flatness described above can be referred to in correspondence with each other.

[0134] Figure 4 This is a structural block diagram of the apparatus for predicting wafer surface flatness provided in an embodiment of the present invention, with reference to... Figure 4 Apparatus for predicting wafer surface flatness may include:

[0135] Receiver module 100 is used to receive the layout of the chip under test;

[0136] The region division module 200 is used to divide the layout of the chip under test into multiple computing target regions according to a preset target resolution.

[0137] The region expansion module 300 is used to determine the simulation region corresponding to each of the computing target regions according to a preset processing resolution, with the computing target region as the center; the processing resolution is greater than the target resolution, and the edge distance between the computing target region and the simulation region is the effective range of the pre-trained wafer surface flatness model;

[0138] The rasterization module 400 is used to rasterize the layout of the chip under test corresponding to the simulation area to obtain a simulation raster image.

[0139] The model calculation module 500 is used to input the simulation grid image into the wafer surface flatness model to obtain a simulation output image.

[0140] The cropping module 600 is used to crop a portion of the center of the simulation output image according to the target resolution, as the flatness simulation image corresponding to the calculated target region.

[0141] The height value determination module 700 is used to determine the simulated height value of each position of the chip layout under test based on the flatness simulation image corresponding to each of the calculated target areas.

[0142] As one specific implementation, the training device for the wafer surface flatness model includes:

[0143] The modeling receiving module is used to receive template modeling patterns.

[0144] A wafer fabrication module is used to fabricate a patterned wafer based on the template pattern layout.

[0145] The scanning module is used to scan the modeled pattern wafer to obtain a wafer surface flatness measurement image; each pixel in the wafer surface flatness measurement image has a corresponding height value.

[0146] The modeling and partitioning module is used to divide the template modeling pattern layout into multiple regions to be processed according to the processing resolution.

[0147] The modeling rasterization module is used to rasterize the template modeling pattern layout corresponding to the area to be processed to obtain a template raster image;

[0148] The model training module is used to input the template grid image into the wafer surface flatness model to be trained, so that the wafer surface flatness model to be trained outputs an output image of the processing resolution, wherein each pixel in the output image has a corresponding height value; and then, the evaluation region image of the target resolution is cropped from the center of the output image.

[0149] The model iteration module is used to iterate the wafer surface flatness model based on the wafer surface flatness measurement image and the evaluation region image until the height difference between the corresponding regions on the evaluation region image and the wafer surface flatness measurement image is less than a preset tolerance threshold.

[0150] In one specific implementation, the scanning module further includes:

[0151] The normalization unit is used to normalize the height values ​​corresponding to each pixel in the wafer surface flatness measurement image and represent them with gray values.

[0152] Accordingly, the model training module includes:

[0153] The normalized model training unit is used to input the template grid image into the wafer surface flatness model to be trained, so that the wafer surface flatness model to be trained outputs the output image at the processing resolution, and the gray value of each pixel in the output image is a normalized height value.

[0154] Accordingly, the model calculation module 500 includes:

[0155] The normalization model calculation unit is used to input the simulated raster image into the wafer surface flatness model to obtain a simulated output image; the gray value of each pixel in the simulated output image is a normalized height value.

[0156] Accordingly, the height value determination module 700 includes:

[0157] The normalization and restoration unit is used to restore the gray values ​​of pixels in the flatness simulation image corresponding to each of the calculation target regions to height values, which are used as the simulation height values ​​of each position of the chip layout under test.

[0158] In one specific implementation, the scanning module includes:

[0159] The normalization calculation unit is used to normalize the height values ​​corresponding to each pixel in the wafer surface flatness measurement image using the following formula, and represent them as grayscale values:

[0160] ;

[0161] Among them, WI i Let ΔWH be the grayscale value of pixel i in the image. i Here, HF0 is the height value corresponding to pixel i, HT0 is the preset reference height, and HT0 is the film thickness corresponding to the lowest position on the surface in the wafer surface flatness measurement image.

[0162] In one specific implementation, the height value determination module 700 includes:

[0163] The normalization and restoration calculation unit is used to restore the grayscale values ​​of pixels in the flatness simulation image corresponding to each of the calculation target regions to height values ​​using the following formula, which are then used as the simulation height values ​​for each location on the chip layout under test:

[0164] ;

[0165] Among them, SH i SI is the simulated height value at the corresponding position of pixel i. i Here, HF0 is the grayscale value of pixel i in the flatness simulation image, HT0 is the preset reference height, and HT0 is the film thickness corresponding to the lowest position on the surface in the wafer surface flatness measurement image.

[0166] As one specific implementation, the model iteration module includes:

[0167] The loss function unit is used to iterate the wafer surface flatness model based on the wafer surface flatness measurement image and the evaluation region image. When the loss function in the formula is less than a preset first threshold, it is considered that the height difference between the corresponding regions on the evaluation region image and the wafer surface flatness measurement image is less than a preset tolerance threshold.

[0168] ;

[0169] Where CF is the function value of the loss function, SI i Let WI be the grayscale value of pixel i in the flatness simulation image. i Let w be the image grayscale value of the pixel corresponding to pixel i in the measured image on the flatness of the wafer surface. i is the weight coefficient corresponding to pixel i.

[0170] As one specific implementation, the scanning module includes:

[0171] An atomic force microscope scanning unit is used to scan the modeled pattern wafer using an atomic force microscope to obtain the height value of each scanning point on the modeled pattern wafer;

[0172] The height averaging unit is used to average the height values ​​of all scan points in the region corresponding to the pixel in the wafer surface flatness measurement image to obtain the height value corresponding to the pixel.

[0173] The device for predicting wafer surface flatness provided by the present invention includes a receiving module 100 for receiving a chip layout under test; a region division module 200 for dividing the chip layout under test into multiple calculation target regions according to a preset target resolution; a region expansion module 300 for determining a simulation region corresponding to each of the calculation target regions according to a preset processing resolution, with the calculation target regions as the center; the processing resolution is greater than the target resolution, and the edge distance between the calculation target regions and the simulation regions is the effective range of a pre-trained wafer surface flatness model; a rasterization module 400 for rasterizing the chip layout under test corresponding to the simulation regions to obtain a simulation raster image; a model calculation module 500 for inputting the simulation raster image into the wafer surface flatness model to obtain a simulation output image; a cropping module 600 for cropping a portion of the center of the simulation output image according to the target resolution as the flatness simulation image corresponding to the calculation target regions; and a height value determination module 700 for determining the simulation height value of each position of the chip layout under test based on the flatness simulation images corresponding to each of the calculation target regions. This invention takes a rasterized image of a chip layout as input and uses a pre-trained convolutional neural network model (i.e., the wafer surface flatness model) to output a simulated image of the wafer surface flatness. Instead of directly using the output as the simulated height value of the chip layout under test, the flatness simulation image of the target resolution is extracted from the simulated output image according to the effective range of the model. The influence of the surrounding graphics on the simulation results is considered during the simulation process, which greatly improves the accuracy and resolution of flatness prediction.

[0174] The apparatus for predicting wafer surface flatness in this embodiment is used to implement the aforementioned method for predicting wafer surface flatness. Therefore, the specific implementation of the apparatus for predicting wafer surface flatness can be found in the embodiment section of the method for predicting wafer surface flatness described above. For example, the receiving module 100, the region division module 200, the region expansion module 300, the rasterization module 400, the model calculation module 500, the interception module 600, and the height value determination module 700 are respectively used to implement steps S101, S102, S103, S104, S105, S106, and S107 in the method for predicting wafer surface flatness. Therefore, the specific implementation can be referred to the description of the corresponding embodiments, which will not be repeated here.

[0175] The present invention also provides an apparatus for predicting wafer surface flatness, comprising:

[0176] Memory, used to store computer programs;

[0177] A processor is configured to execute the computer program to implement the steps of any of the above-described methods for predicting wafer surface flatness. The method for predicting wafer surface flatness provided by this invention involves: receiving a chip layout under test; dividing the chip layout under test into multiple computational target regions according to a preset target resolution; determining a simulation region corresponding to each computational target region according to a preset processing resolution, with the computational target region as the center; the processing resolution being greater than the target resolution, and the edge distance between the computational target region and the simulation region being the effective range of a pre-trained wafer surface flatness model; rasterizing the chip layout under test corresponding to the simulation region to obtain a simulation raster image; inputting the simulation raster image into the wafer surface flatness model to obtain a simulation output image; cropping a portion of the center of the simulation output image according to the target resolution as the flatness simulation image corresponding to the computational target region; and determining the simulation height value at each position of the chip layout under test based on the flatness simulation images corresponding to each computational target region. This invention takes a rasterized image of a chip layout as input and uses a pre-trained convolutional neural network model (i.e., the wafer surface flatness model) to output a simulated image of the wafer surface flatness. Instead of directly using the output as the simulated height value of the chip layout under test, the flatness simulation image of the target resolution is extracted from the simulated output image according to the effective range of the model. The influence of the surrounding graphics on the simulation results is considered during the simulation process, which greatly improves the accuracy and resolution of flatness prediction.

[0178] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described methods for predicting wafer surface flatness. The method for predicting wafer surface flatness provided by this invention involves: receiving a chip layout under test; dividing the chip layout under test into multiple computational target regions according to a preset target resolution; determining a simulation region corresponding to each computational target region according to a preset processing resolution, with the computational target region as the center; the processing resolution being greater than the target resolution, and the edge distance between the computational target region and the simulation region being the effective range of a pre-trained wafer surface flatness model; rasterizing the chip layout under test corresponding to the simulation region to obtain a simulation raster image; inputting the simulation raster image into the wafer surface flatness model to obtain a simulation output image; cropping a portion of the center of the simulation output image according to the target resolution as the flatness simulation image corresponding to the computational target region; and determining the simulation height value at each position of the chip layout under test based on the flatness simulation images corresponding to each computational target region. This invention takes a rasterized image of a chip layout as input and uses a pre-trained convolutional neural network model (i.e., the wafer surface flatness model) to output a simulated image of the wafer surface flatness. Instead of directly using the output as the simulated height value of the chip layout under test, the flatness simulation image of the target resolution is extracted from the simulated output image according to the effective range of the model. The influence of the surrounding graphics on the simulation results is considered during the simulation process, which greatly improves the accuracy and resolution of flatness prediction.

[0179] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0180] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0181] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0182] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0183] The method, apparatus, device, and storage medium for predicting wafer surface flatness provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A method for predicting wafer surface flatness, characterized in that, include: Receive the layout of the chip under test; The layout of the chip under test is divided into multiple target computing regions according to a preset target resolution; Centered on the target computation region, the simulation region corresponding to each target computation region is determined according to a preset processing resolution; The processing resolution is greater than the target resolution, and the edge distance between the calculation target region and the simulation region is the effective range of the pre-trained wafer surface flatness model. The layout of the chip under test corresponding to the simulation area is rasterized to obtain a simulation raster image; The simulated raster image is input into the wafer surface flatness model to obtain the simulated output image; A portion of the simulated output image is cropped from the center according to the target resolution, and used as the flatness simulation image corresponding to the calculated target region. Based on the flatness simulation images corresponding to each of the calculated target regions, the simulation height values ​​of each position on the chip layout under test are determined.

2. The method for predicting wafer surface flatness as described in claim 1, characterized in that, The training method for the wafer surface flatness model includes: Receive template modeling pattern layout; Based on the template modeling pattern layout, prepare a modeling pattern wafer; Scan the modeled pattern wafer to obtain a wafer surface flatness measurement image; each pixel in the wafer surface flatness measurement image has a corresponding height value; Based on the processing resolution, the template modeling pattern layout is divided into multiple areas to be processed; The template modeling pattern layout corresponding to the area to be processed is rasterized to obtain a template raster image; The template grid image is input into the wafer surface flatness model to be trained, so that the wafer surface flatness model to be trained outputs an output image of the processing resolution, and each pixel in the output image has a corresponding height value; then, the evaluation region image of the target resolution is cropped from the center of the output image. The wafer surface flatness model is iterated based on the wafer surface flatness measurement image and the evaluation region image until the height difference between the corresponding regions on the evaluation region image and the wafer surface flatness measurement image is less than a preset tolerance threshold.

3. The method for predicting wafer surface flatness as described in claim 2, characterized in that, After scanning the modeled pattern wafer to obtain a measurement image of the wafer surface flatness, the process further includes: The height values ​​corresponding to each pixel in the wafer surface flatness measurement image are normalized and represented by grayscale values. Accordingly, the template grid image is input into the wafer surface flatness model to be trained, so that the wafer surface flatness model to be trained outputs an output image at the processing resolution, wherein each pixel in the output image has a corresponding height value, including: The template grid image is input into the wafer surface flatness model to be trained, and the wafer surface flatness model to be trained outputs an output image at the processing resolution. The gray value of each pixel in the output image is a normalized height value. Accordingly, the simulated raster image is input into the wafer surface flatness model to obtain a simulated output image, including: The simulated raster image is input into the wafer surface flatness model to obtain a simulated output image; the grayscale value of each pixel in the simulated output image is a normalized height value. Accordingly, based on the flatness simulation images corresponding to each of the calculated target regions, the simulation height values ​​at each location of the chip layout under test are determined, including: The grayscale values ​​of the pixels in the flatness simulation image corresponding to each of the calculated target regions are restored to height values, which are then used as the simulated height values ​​for each position of the chip layout under test.

4. The method for predicting wafer surface flatness as described in claim 3, characterized in that, The height values ​​corresponding to each pixel in the wafer surface flatness measurement image are normalized and represented by grayscale values, including: The height values ​​corresponding to each pixel in the wafer surface flatness measurement image are normalized using the following formula, and represented by grayscale values: ； Among them, WI i Let ΔWH be the grayscale value of pixel i in the image. i Here, HF0 is the height value corresponding to pixel i, HT0 is the preset reference height, and HT0 is the film thickness corresponding to the lowest position on the surface in the wafer surface flatness measurement image.

5. The method for predicting wafer surface flatness as described in claim 4, characterized in that, The grayscale values ​​of pixels in the flatness simulation image corresponding to each of the calculated target regions are restored to height values, which are then used as the simulated height values ​​for each location on the chip layout under test, including: The grayscale values ​​of pixels in the flatness simulation image corresponding to each of the calculated target regions are converted into height values ​​using the following formula, which are then used as the simulated height values ​​for each location on the chip layout under test: ； Among them, SH i SI is the simulated height value at the corresponding position of pixel i. i Here, HF0 is the grayscale value of pixel i in the flatness simulation image, HT0 is the preset reference height, and HT0 is the film thickness corresponding to the lowest position on the surface in the wafer surface flatness measurement image.

6. The method for predicting wafer surface flatness as described in claim 2, characterized in that, The wafer surface flatness model is iterated based on the wafer surface flatness measurement image and the evaluation region image until the height difference between corresponding regions on the evaluation region image and the wafer surface flatness measurement image is less than a preset tolerance threshold, including: The wafer surface flatness model is iterated based on the wafer surface flatness measurement image and the evaluation region image. When the loss function in the formula is less than a preset first threshold, the height difference between the corresponding regions on the evaluation region image and the wafer surface flatness measurement image is considered to be less than a preset tolerance threshold. ； Where CF is the function value of the loss function, SI i Let WI be the grayscale value of pixel i in the flatness simulation image. i Let w be the image grayscale value of the pixel corresponding to pixel i in the measured image on the flatness of the wafer surface. i is the weight coefficient corresponding to pixel i.

7. The method for predicting wafer surface flatness as described in claim 2, characterized in that, The method for determining the height value corresponding to the pixel in the wafer surface flatness measurement image includes: The modeled pattern wafer was scanned using an atomic force microscope to obtain the height values ​​of each scanning point on the modeled pattern wafer; The height value corresponding to the pixel is obtained by averaging the height values ​​of all scan points in the region corresponding to the pixel in the flatness measurement image of the wafer surface.

8. An apparatus for predicting the flatness of a wafer surface, characterized in that, include: The receiving module is used to receive the layout of the chip under test; The region division module is used to divide the layout of the chip under test into multiple computing target regions according to a preset target resolution. The region expansion module is used to determine the simulation region corresponding to each of the computation target regions according to a preset processing resolution, with the computation target region as the center; the processing resolution is greater than the target resolution, and the edge distance between the computation target region and the simulation region is the effective range of the pre-trained wafer surface flatness model; The rasterization module is used to rasterize the layout of the chip under test corresponding to the simulation area to obtain a simulation raster image. The model calculation module is used to input the simulated raster image into the wafer surface flatness model to obtain a simulated output image. The cropping module is used to crop a portion of the center of the simulation output image according to the target resolution, as the flatness simulation image corresponding to the calculated target region; The height value determination module is used to determine the simulated height value of each position of the chip layout under test based on the flatness simulation image corresponding to each of the calculated target areas.

9. An apparatus for predicting the flatness of a wafer surface, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the method for predicting wafer surface flatness as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for predicting wafer surface flatness as described in any one of claims 1 to 7.

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