Pixel circuit, display panel and display device

Abstract

The application discloses a pixel circuit, a display panel and a display device. In the pixel circuit: a driving transistor, a first transistor and a second transistor are connected in series between a first power supply line and a light emitting element, and the first transistor is connected to a first electrode of the driving transistor, and the second transistor is connected to a second electrode of the driving transistor; a third transistor is connected in parallel with the first transistor and the driving transistor in series; a fourth transistor is connected in parallel with the driving transistor and the second transistor in series; and a working process of the pixel circuit comprises a first stage and a second stage. In the first stage, the first transistor and the second transistor are turned on, and the third transistor and the fourth transistor are turned off. In the second stage, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are turned on. The application can solve the problem that the threshold voltage of the driving transistor is prone to drift, thereby causing the display panel to have residual image, flicker and the like.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel circuit, a display panel, and a display device. Background Technology

[0002] With the development of display technology, the application of display panels is becoming more and more widespread, and users are demanding higher and higher display quality from display panels.

[0003] Display panels typically incorporate pixel circuitry, which includes driving transistors. These transistors generate driving current to power the light-emitting elements. However, the threshold voltage of the driving transistors is prone to drift, leading to issues such as image retention and flickering in the display panel. Summary of the Invention

[0004] This application provides a pixel circuit, a display panel, and a display device, which can solve the problems of image retention and flickering caused by the easy drift of the threshold voltage of the driving transistor.

[0005] In a first aspect, embodiments of this application provide a pixel circuit, including a driving transistor, a first transistor, a second transistor, a third transistor, and a fourth transistor; the driving transistor, the first transistor, and the second transistor are connected in series between a first power line and a light-emitting element, and the first transistor is connected to the first terminal of the driving transistor, and the second transistor is connected to the second terminal of the driving transistor; the third transistor is connected in parallel with the first transistor and the driving transistor connected in series; the fourth transistor is connected in parallel with the driving transistor and the second transistor connected in series; the operation of the pixel circuit includes a first stage and a second stage; in the first stage, the first transistor and the second transistor are turned on, and the third transistor and the fourth transistor are turned off; in the second stage, the first transistor and the second transistor are turned off, and the third transistor and the fourth transistor are turned on.

[0006] Secondly, embodiments of this application provide a display panel including the pixel circuit described in the first aspect embodiment.

[0007] Thirdly, embodiments of this application provide a display device, including a display panel as described in the second aspect embodiment.

[0008] According to the pixel circuit, display panel, and display device provided in the embodiments of this application, in the first stage, since the first transistor and the second transistor are turned on and the third transistor and the fourth transistor are turned off, the current flow on the driving transistor is from the first terminal to the second terminal of the driving transistor; in the second stage, since the first transistor and the second transistor are turned off and the third transistor and the fourth transistor are turned on, the current flow on the driving transistor is from the second terminal to the first terminal of the driving transistor; this makes the current direction of the driving transistor in the first stage and the second stage opposite, so that the charge will not accumulate at one position of the driving transistor for a long time, and the threshold voltage of the driving transistor will not continuously drift in one direction. This allows the drift of the threshold voltage of the driving transistor in the first stage and the second stage to at least partially cancel each other out, improve the stability of the threshold voltage of the driving transistor, and solve the problems of image retention and flickering caused by the easy drift of the threshold voltage of the driving transistor. Attached Figure Description

[0009] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0010] Figure 1 This diagram illustrates a principle for generating threshold voltage drift by a driving transistor. Figure 2 This illustration shows a schematic diagram of a pixel circuit provided in an embodiment of this application; Figure 3 This illustration shows another structural diagram of the pixel circuit provided in an embodiment of this application; Figure 4 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application; Figure 5 Show Figure 2 The diagram shows a state of the transistor in the pixel circuit during the first stage. Figure 6 Show Figure 2 The diagram shows a state of the transistor in the pixel circuit during the second stage. Figure 7 Show Figure 2 A timing diagram; Figure 8 Show Figure 2 Another timing diagram; Figure 9 Show Figure 2 Another timing diagram; Figure 10 Show Figure 2 Another timing diagram; Figure 11 Show Figure 2 Another timing diagram; Figure 12 Show Figure 2 Another timing diagram; Figure 13 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application; Figure 14 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application; Figure 15 Show Figure 13 A timing diagram; Figure 16 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application; Figure 17 Show Figure 3 A timing diagram; Figure 18 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application; Figure 19 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0011] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0012] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0013] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0014] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0015] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0016] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0017] like Figure 1 As shown, the driving transistor includes a channel p, a gate g, a first electrode S, and a second electrode D. During the operation of the pixel circuit, the voltage applied to the first electrode S and the second electrode D of the driving transistor is asymmetrical. For example, in the first state, negative charges or defect charges accumulate on the second electrode D side, and in the second state, positive charges or defect charges accumulate on the first electrode S side, resulting in a large voltage on one side and a small voltage on the other side, or the voltages being opposite in sign. Charges are prone to form asymmetrical accumulation at the interface of the channel, causing the threshold voltage of the driving transistor to drift, which in turn leads to problems such as image retention and flickering in the display panel.

[0018] To address the aforementioned technical problems, this application provides a pixel circuit, a display panel, and a display device. The embodiments of this application will be described below with reference to the accompanying drawings.

[0019] like Figures 2 to 4 As shown in any of the accompanying drawings, the pixel circuit 10 provided in the embodiments of this application includes a driving transistor T0, a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0020] The driving transistor T0, the first transistor T1, and the second transistor T2 are connected in series between the first power line PVDD and the light-emitting element 20, and the first transistor T1 is connected to the first terminal S of the driving transistor T0, and the second transistor T2 is connected to the second terminal D of the driving transistor T0.

[0021] The third transistor T3 is connected in parallel with the first transistor T1 and the driving transistor T0, which are connected in series. That is, the first transistor T1 and the driving transistor T0, which are connected in series, are connected in parallel with the third transistor T3.

[0022] The fourth transistor T4 is connected in parallel with the series-connected driving transistor T0 and the second transistor T2. That is, the series-connected first transistor T1, second transistor T2, and fourth transistor T4 are connected in parallel.

[0023] The operation of a pixel circuit consists of a first stage and a second stage.

[0024] like Figure 5 As shown, in the first stage, the first transistor T1 and the second transistor T2 are turned on, while the third transistor T3 and the fourth transistor T4 are turned off.

[0025] like Figure 6 As shown, in the second stage, the first transistor T1 and the second transistor T2 are turned off, while the third transistor T3 and the fourth transistor T4 are turned on.

[0026] As an example, such as Figure 2 or Figure 3 As shown, the driving transistor T0 is a P-type transistor. The first terminal S of the driving transistor T0 is coupled to the first power line PVDD, the second terminal D of the driving transistor T0 is coupled to the anode of the light-emitting element 20, and the cathode of the light-emitting element 20 is connected to the second power line PVEE.

[0027] As another example, such as Figure 4 As shown, the driving transistor T0 is an N-type transistor. The first terminal S of the driving transistor T0 is coupled to the anode of the light-emitting element 20, the second terminal D of the driving transistor T0 is coupled to the first power line PVDD, and the cathode of the light-emitting element 20 is connected to the second power line PVEE.

[0028] For example, the pixel circuit 10 also includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6. The series-connected driving transistor T0, the first transistor T1 and the second transistor T2 are called a device combination. One end of the device combination is coupled to the first power line PVDD through the first light-emitting control transistor T5, and the other end of the device combination is coupled to the anode of the light-emitting element 20 through the second light-emitting control transistor T6.

[0029] Of course, pixel circuit 10 may also include other transistors, which will be described below. It should be noted that the specific structures of the pixel circuits shown in the accompanying drawings are merely examples and are not intended to limit this application. The technical concepts provided in this application can also be applied to pixel circuits with other structures.

[0030] According to the pixel circuit provided in the embodiments of this application, in the first stage, since the first transistor T1 and the second transistor T2 are turned on, and the third transistor T3 and the fourth transistor T4 are turned off, the current flow on the driving transistor T0 is from its first terminal S to its second terminal D; in the second stage, since the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 and the fourth transistor T4 are turned on, the current flow on the driving transistor T0 is from its second terminal D to its first terminal S; this makes the current direction of the driving transistor T0 in the first stage and the second stage opposite, so that the charge will not accumulate at one position of the driving transistor T0 for a long time, and the threshold voltage of the driving transistor T0 will not continuously drift in one direction. This allows the drift of the threshold voltage of the driving transistor T0 in the first stage and the second stage to at least partially cancel each other out, improving the stability of the threshold voltage of the driving transistor T0. This can solve the problems of image retention and flickering on the display panel caused by the easy drift of the threshold voltage of the driving transistor.

[0031] In some embodiments, the first stage and the second stage alternate. For example, the first transistor T1 and the second transistor T2 are referred to as the first group of transistors, and the third transistor T3 and the fourth transistor T4 are referred to as the second group of transistors. When the first group of transistors is turned on and the second group of transistors is turned off, the direction of the current driving transistor T0 is referred to as the first direction. When the first group of transistors is turned off and the second group of transistors is turned on, the direction of the current driving transistor T0 is referred to as the second direction. The alternation of the first group of transistors and the second group of transistors, with the current direction of the driving transistor T0 alternating between the first direction and the second direction, can better ensure that the charge does not accumulate at one position of the driving transistor T0 for a long time, and the threshold voltage of the driving transistor T0 does not continuously drift in one direction for a long time, thereby improving the stability of the threshold voltage of the driving transistor T0.

[0032] For example, the gates of the first transistor T1 and the second transistor T2 are connected to the first scan line SP1, the gates of the third transistor T3 and the fourth transistor T4 are connected to the second scan line SP2, and the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control line EM. Taking the example that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all P-type transistors, please refer to the reference. Figure 2 and Figure 7When the signal on the first scan line SP1 is low, the first transistor T1 and the second transistor T2 are turned on; when the signal on the second scan line SP2 is low, the third transistor T3 and the fourth transistor T4 are turned on; when the signal on the light emission control line EM is low, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on. Additionally, for P-type transistors, when their gates are connected to a high level, the P-type transistors are turned off.

[0033] When the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, the pixel circuit operates in the light-emitting stage m; when the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned off, the pixel circuit operates in the non-light-emitting stage nm.

[0034] In some embodiments, such as Figure 7 As shown, the operation of the pixel circuit includes multiple cycles c, including a first cycle c1 and a second cycle c2. The first cycle c1 and the second cycle c2 respectively include a non-light-emitting stage nm and a light-emitting stage m. The light-emitting stage m of the first cycle c1 overlaps at least partially with the first stage p1 in time, and the light-emitting stage m of the second cycle c2 overlaps at least partially with the second stage p2 in time.

[0035] During the light-emitting phase m, the driving transistor T0 generates a driving current, driving the light-emitting element 20 to emit light during the light-emitting phase m. The light-emitting element 20 does not emit light during the non-light-emitting phase nm. The current of the driving transistor T0 during the light-emitting phase m is greater than the current of the driving transistor T0 during the non-light-emitting phase nm. The larger the current of the driving transistor T0, the more charge accumulates at a certain position of the driving transistor T0. In this embodiment, the pixel circuit operates in the first phase p1 during at least a portion of the light-emitting phase m; and in the second phase p2 during at least a portion of the light-emitting phase m. This ensures that during the light-emitting phase m when the current of the driving transistor T0 is relatively large, the current direction of the driving transistor T0 will not remain unidirectional for a long time, better guaranteeing that charge will not accumulate at one position of the driving transistor T0 for an extended period, and that the threshold voltage of the driving transistor T0 will not continuously drift in one direction for a long time, thereby improving the stability of the threshold voltage of the driving transistor T0.

[0036] In some embodiments, such as Figure 7 As shown, the emission phase m of the first period c1 does not overlap with the second phase p2 in time, and the emission phase m of the second period c2 does not overlap with the first phase p1 in time.

[0037] For example, the emission phase m of the first period c1 at least partially overlaps with the first phase p1 in time, and the emission phase m of the first period c1 does not overlap with the second phase p2 in time. The emission phase m of the second period c2 at least partially overlaps with the second phase p2 in time, and the emission phase m of the second period c2 does not overlap with the first phase p1 in time. That is, the emission phase m of the first period c1 overlaps only with the first phase p1, and the emission phase m of the second period c2 overlaps only with the second phase p2.

[0038] For example, the entire light-emitting phase m of the first cycle c1 can be the first phase p1. In this way, during the entire light-emitting phase m of the first cycle c1, the first transistor T1 and the second transistor T2 remain on, while the third transistor T3 and the fourth transistor T4 remain off. It is unnecessary to switch the states of these four transistors during the entire light-emitting phase m of the first cycle c1, thus reducing power consumption. Similarly, the entire light-emitting phase m of the second cycle c2 can be the second phase p2. In this way, during the entire light-emitting phase m of the second cycle c2, the first transistor T1 and the second transistor T2 remain off, while the third transistor T3 and the fourth transistor T4 remain on. It is unnecessary to switch the states of these four transistors during the entire light-emitting phase m of the second cycle c2, thus reducing power consumption.

[0039] In other embodiments, such as Figure 8 As shown, the luminescence phase m of the first period c1 and the second phase p2 overlap at least partially in time, and the luminescence phase m of the second period c2 overlap at least partially in time with the first phase p1.

[0040] For example, the emission phase m of the first period c1 at least partially overlaps with the first phase p1 in time, and the emission phase m of the first period c1 at least partially overlaps with the second phase p2 in time. The emission phase m of the second period c2 at least partially overlaps with the second phase p2 in time, and the emission phase m of the second period c2 at least partially overlaps with the first phase p1 in time.

[0041] In other words, a portion of the light-emitting phase m of the first cycle c1 is designated as the first stage p1, and another portion of the light-emitting phase m of the first cycle c1 is designated as the second stage p2. In this way, during the light-emitting phase m of the first cycle c1, the current direction of the driving transistor T0 will not be continuously in a single direction, ensuring that the charge will not accumulate at one position of the driving transistor T0 for a long time, and the threshold voltage of the driving transistor T0 will not continuously drift in one direction for a long time, thereby improving the stability of the threshold voltage of the driving transistor T0 during the light-emitting phase m of the first cycle c1.

[0042] Similarly, a portion of the light-emitting phase m of the second cycle c2 is designated as the second phase p2, and another portion of the light-emitting phase m of the second cycle c2 is designated as the first phase p1. In this way, during the light-emitting phase m of the second cycle c2, the current direction of the driving transistor T0 will not be continuously in a single direction, ensuring that the charge will not accumulate at one position of the driving transistor T0 for a long time, and the threshold voltage of the driving transistor T0 will not continuously drift in one direction for a long time, thereby improving the stability of the threshold voltage of the driving transistor T0 during the light-emitting phase m of the second cycle c2.

[0043] In some embodiments, such as Figure 2 or Figure 4 As shown, the pixel circuit also includes a data writing transistor T7 and a compensation transistor T9; the first terminal of the data writing transistor T7 is connected to the data line data, and the second terminal of the data writing transistor T7 is connected to the first terminal S of the driving transistor T0 through the first transistor T1; the first terminal of the compensation transistor T9 is connected to the second terminal D of the driving transistor T0 through the second transistor T2, and the second terminal of the compensation transistor T9 is connected to the gate of the driving transistor T0.

[0044] As an example, when the data writing transistor T7 writes a data signal on the data line data to the gate of the driving transistor T0, the first transmission path of the data signal can pass through the first transistor T1, the first terminal S of the driving transistor T0, the second terminal D of the driving transistor T0, the second transistor T2, the compensation transistor T9, and then reach the gate of the driving transistor T0; that is, the first transmission path of the data signal on the data line data includes the first transistor T1 and the second transistor T2, and the first transistor T1 and the second transistor T2 must be in the on state when writing the data signal to the gate of the driving transistor T0.

[0045] As another example, when the data writing transistor T7 writes a data signal on the data line data to the gate of the driving transistor T0, the second transmission path of the data signal can pass through the third transistor T3, the second terminal D of the driving transistor T0, the first terminal S of the driving transistor T0, the fourth transistor T4, the compensation transistor T9, and then reach the gate of the driving transistor T0; that is, the second transmission path of the data signal on the data line data includes the third transistor T3 and the fourth transistor T4, and the third transistor T3 and the fourth transistor T4 need to be in the on state when writing the data signal to the gate of the driving transistor T0.

[0046] In some embodiments, please refer to Figure 2 as well as Figures 7 to 11In any of the accompanying drawings, the operation of the pixel circuit includes multiple cycles c, each cycle c including a non-light-emitting phase nm and a light-emitting phase m. The non-light-emitting phase nm includes a data writing phase d, in which the data writing transistor T7 and the compensation transistor T9 are turned on; and the data writing phase d overlaps at least partially in time with one of the first phase p1 and the second phase p2.

[0047] As described above, the path for writing the data signal on the data line data to the gate of the driving transistor T0 may include the first transistor T1 and the second transistor T2, or the path for writing the data signal on the data line data to the gate of the driving transistor T0 may include the third transistor T3 and the fourth transistor T4. The first transistor T1 and the second transistor T2 are turned on in the first stage p1, and the third transistor T3 and the fourth transistor T4 are turned on in the second stage p2. Therefore, the data writing stage d overlaps with either the first stage p1 or the second stage p2, which can ensure that the data signal on the data line data is successfully written to the gate of the driving transistor T0.

[0048] As an example, such as Figure 7 , Figure 8 or Figure 10 As shown, at least one data writing stage d overlaps at least partially in time with the first stage p1, and at least another data writing stage d overlaps at least partially in time with the second stage p2.

[0049] As another example, such as Figure 9 As shown, each data writing stage d overlaps at least partially with the first stage p1 in time. In this example, data writing stage d does not overlap with the second stage p2.

[0050] As yet another example, such as Figure 11 As shown, each data writing stage d overlaps at least partially with the second stage p2 in time. In this example, data writing stage d does not overlap with the first stage p1.

[0051] In some embodiments, please refer to Figure 2 as well as Figure 7 , Figure 8 , Figure 10 In any of the attached figures, period c includes a first period c1 and a second period c2, where the data writing phase d in the first period c1 overlaps at least partially with the first phase p1 in time, and the data writing phase d in the second period c2 overlaps at least partially with the second phase p2 in time.

[0052] In this embodiment, at least a portion of the data writing phase d of the first cycle c1 is designated as the first phase p1, and at least a portion of the data writing phase d of the second cycle c2 is designated as the second phase p2. During the data writing phase d of the two cycles, the current direction of the driving transistor T0 will not be continuously in a single direction, ensuring that the charge will not accumulate at one position of the driving transistor T0 for a long time, and the threshold voltage of the driving transistor T0 will not continuously drift in one direction for a long time, thereby improving the stability of the threshold voltage of the driving transistor T0 during the data writing phase d of the two cycles.

[0053] In some embodiments, such as Figure 7 , Figure 8 , Figure 10 In any of the attached diagrams, the data writing phase d in the first cycle c1 does not overlap with the second phase p2 in time, and the data writing phase d in the second cycle c2 does not overlap with the first phase p1 in time.

[0054] For example, the data writing phase d in the first cycle c1 overlaps at least partially with the first phase p1 in time, and the data writing phase d in the first cycle c1 does not overlap with the second phase p2 in time. The data writing phase d in the second cycle c2 overlaps at least partially with the second phase p2 in time, and the data writing phase d in the second cycle c2 does not overlap with the first phase p1 in time.

[0055] For example, the entire data writing phase d within the first cycle c1 is considered as the first phase p1. In this way, during the data writing phase d of the first cycle c1, the first transistor T1 and the second transistor T2 remain on, while the third transistor T3 and the fourth transistor T4 remain off. It is not necessary to switch the states of these four transistors during the entire data writing phase d of the first cycle c1, thus reducing power consumption. Similarly, the entire data writing phase d within the second cycle c2 is considered as the second phase p2. In this way, during the data writing phase d of the second cycle c2, the first transistor T1 and the second transistor T2 remain off, while the third transistor T3 and the fourth transistor T4 remain on. It is not necessary to switch the states of these four transistors during the entire data writing phase d of the second cycle c2, thus reducing power consumption.

[0056] In some embodiments, the operation of the pixel circuit includes multiple cycles c, where each cycle c includes a non-light-emitting phase nm and a light-emitting phase m; wherein... like Figure 9 As shown, the non-luminescent stage nm overlaps at least partially in time with the first stage p1, the luminescent stage m overlaps at least partially in time with the second stage p2, and the non-luminescent stage nm does not overlap with the second stage p2 in time, and the luminescent stage m does not overlap with the first stage p1 in time. Or, such as Figure 11 As shown, the non-luminescent stage nm and the second stage p2 overlap at least partially in time, the luminescent stage m and the first stage p1 overlap at least partially in time, and the non-luminescent stage nm and the first stage p1 do not overlap in time, and the luminescent stage m and the second stage p2 do not overlap in time.

[0057] Figure 9 In the example shown, for any period c, the non-luminescent phase nm includes the first phase p1, and the luminescent phase m includes the second phase p2. Figure 11 In the example shown, for any period c, the non-light-emitting stage nm includes the second stage p2, and the light-emitting stage m includes the first stage p1. The current direction of the driving transistor T0 in the first stage p1 is opposite to the current direction of the driving transistor T0 in the second stage p2. Therefore, in any period c, the current direction of the driving transistor T0 will not be in a single direction for a long time, ensuring that the charge will not accumulate at one position of the driving transistor T0 for a long time, and the threshold voltage of the driving transistor T0 will not drift unidirectionally for a long time, thereby improving the stability of the threshold voltage of the driving transistor T0 in any period c.

[0058] In other embodiments, such as Figure 12 As shown, the operation of the pixel circuit includes multiple cycles c, including a third cycle c3 and a fourth cycle c4. The third cycle c3 overlaps with the first stage p1 in time, and the fourth cycle c4 overlaps with the second stage p2 in time.

[0059] Period c includes a non-luminescent phase nm and a luminescent phase m. The non-luminescent phase nm and the luminescent phase m of the first period p1 overlap with those of the third period c3, and the non-luminescent phase nm and the luminescent phase m of the second period p2 overlap with those of the fourth period c4.

[0060] The third cycle c3 overlaps with the first stage p1 in time. This means that during the non-light-emitting stage nm and the light-emitting stage m in the third cycle c3, the first transistor T1 and the second transistor T2 remain on, while the third transistor T3 and the fourth transistor T4 remain off. In this way, it is not necessary to switch the state of these four transistors throughout the entire cycle of the third cycle c3, which can reduce power consumption.

[0061] Similarly, the overlap of the fourth cycle c4 with the second stage p2 in time means that during the non-light-emitting stage nm and the light-emitting stage m in the fourth cycle c4, the first transistor T1 and the second transistor T2 remain off, while the third transistor T3 and the fourth transistor T4 remain on. In this way, it is not necessary to switch the state of these four transistors throughout the entire cycle of the fourth cycle c4, which can reduce power consumption.

[0062] In some embodiments, such as Figure 2 , Figure 3 or Figure 4 As shown, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are of the same type.

[0063] The gates of the first transistor T1 and the second transistor T2 can be connected to scan line SP1, and the gates of the third transistor T3 and the fourth transistor T4 can be connected to scan line SP2.

[0064] In one example, such as Figure 2 or Figure 3 As shown, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all P-type transistors. Additionally, in this example, the driving transistor T0 and the data writing transistor T7 can be P-type transistors, and the compensation transistor T9 can be an N-type transistor.

[0065] Or, such as Figure 4 As shown, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type transistors. Additionally, in this example, the drive transistor T0, the data writing transistor T7, and the compensation transistor T9 can also be N-type transistors.

[0066] In other embodiments, such as Figure 13 As shown, the gates of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be connected to the same scan line SP5; in this case, the first transistor T1 and the second transistor T2 are P-type transistors, and the third transistor T3 and the fourth transistor T4 are N-type transistors; or, the first transistor T1 and the second transistor T2 are N-type transistors, and the third transistor T3 and the fourth transistor T4 are P-type transistors.

[0067] by Figure 13 and Figure 15 For example, the first transistor T1 and the second transistor T2 are P-type transistors, and the third transistor T3 and the fourth transistor T4 are N-type transistors. When the signal on the scan line SP5 is low, the first transistor T1 and the second transistor T2 are turned on, and the third transistor T3 and the fourth transistor T4 are turned off, and the pixel circuit operates in the first stage p1. When the signal on the scan line SP5 is high, the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 and the fourth transistor T4 are turned on, and the pixel circuit operates in the second stage p2.

[0068] In this embodiment, the gates of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are connected to the same scan line, which can save the number of scan lines.

[0069] Figure 2 and Figure 4In the example shown, when the data writing transistor T7 writes the data signal on the data line data to the gate of the driving transistor T0, the participation of the first transistor T1 and the second transistor T2 is required, or the participation of the third transistor T3 and the fourth transistor T4 is required. In other embodiments, when the data writing transistor T7 writes the data signal on the data line data to the gate of the driving transistor T0, the participation of the first transistor T1 and the second transistor T2 or the third transistor T3 and the fourth transistor T4 may not be required.

[0070] Please refer to Figure 3 or Figure 16 The pixel circuit also includes a data writing transistor T7 and a compensation transistor T9; the first terminal of the data writing transistor T7 is connected to the data line data, and the second terminal of the data writing transistor T7 is connected to the first terminal S of the driving transistor T0; the first terminal of the compensation transistor T9 is connected to the second terminal D of the driving transistor T0, and the second terminal of the compensation transistor T9 is connected to the gate of the driving transistor T0.

[0071] In this embodiment, the second terminal of the data writing transistor T7 is no longer connected to the first terminal S of the driving transistor T0 through the first transistor T1, and the first terminal of the compensation transistor T9 is no longer connected to the second terminal D of the driving transistor T0 through the second transistor T2. Thus, when writing data signals to the gate of the driving transistor T0, it is only necessary to control the data writing transistor T7 and the compensation transistor T9 to be turned on. At this time, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off.

[0072] For example, please refer to Figure 3 and Figure 17 During the data writing stage d, the data writing transistor T7 and the compensation transistor T9 are turned on, and the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off. The data signal on the data line data is written to the gate of the driving transistor T0 through the data writing transistor T7 and the compensation transistor T9.

[0073] In some embodiments, please refer to Figure 3 and Figure 17 The operation of the pixel circuit includes multiple cycles c, which include a non-light-emitting stage nm and a light-emitting stage m. The non-light-emitting stage nm includes a data writing stage d. In the data writing stage d, the data writing transistor T7 and the compensation transistor T9 are turned on. The data writing stage d does not overlap with either the first stage p1 or the second stage p2 in time.

[0074] In other words, during the data writing phase d, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 remain disconnected to prevent the data signal of the data line from being accurately written to the gate of the driving transistor T0.

[0075] In some embodiments, please refer to Figure 3 and Figure 17 During the non-light-emitting phase, transistors T1, T2, T3, and T4 are all turned off.

[0076] In other words, during the entire non-light-emitting phase nm, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can remain off. Since current only flows through the driving transistor T0 during the data writing phase d within the non-light-emitting phase nm, and generally there is no current in the driving transistor T0 during other non-light-emitting phases nm outside of the data writing phase d, even if the first transistor T1 and the second transistor T2 are turned on, or the third transistor T3 and the fourth transistor T4 are turned on, the threshold voltage drift problem of the driving transistor T0 cannot be solved. In this embodiment, during the entire non-light-emitting phase nm, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can remain off, which can reduce power consumption.

[0077] For example, in one light-emitting stage m, the first transistor T1 and the second transistor T2 are turned on, while the third transistor T3 and the fourth transistor T4 are turned off; in another light-emitting stage m, the third transistor T3 and the fourth transistor T4 are turned on, while the first transistor T1 and the second transistor T2 are turned off. In this way, the current direction of the driving transistor T0 will not be continuously in a single direction in different light-emitting stages m, ensuring that the charge will not accumulate at one position of the driving transistor T0 for a long time, and the threshold voltage of the driving transistor T0 will not continuously drift in one direction for a long time, thereby improving the stability of the threshold voltage of the driving transistor T0.

[0078] In some embodiments, such as Figures 2 to 4 As shown in any of the accompanying drawings, the pixel circuit 10 may further include a first reset transistor T8, which is connected between the first reset signal line Vref1 and the gate of the driving transistor T0. The gate of the first reset transistor T8 is connected to the scan line SN1. Please refer to the reference. Figure 2 and Figure 7 The operation of the pixel circuit may include a first reset stage a. In the first reset stage a, the first reset transistor T8 is turned on, and the first reset signal on the first reset signal line Vref1 is written into the gate of the driving transistor T0 to reset the gate of the driving transistor T0.

[0079] And / or, such as Figures 2 to 4 As shown in any of the accompanying drawings, the pixel circuit 10 may further include a second reset transistor T10, which is connected between the second reset signal line Vref2 and the anode of the light-emitting element 20. The gate of the second reset transistor T10 is connected to the scan line SP4. The signal on the scan line SP4 can be the same as the signal on the scan line SP2, so that while writing a data signal to the gate of the driving transistor T0, the second reset signal on the second reset signal line Vref2 is written to the anode of the light-emitting element 20.

[0080] For example, the first reset transistor T8 and the compensation transistor T9 are both connected to the gate of the driving transistor T0. The first reset transistor T8 and the compensation transistor T9 can both be N-type transistors to reduce the gate leakage current of the driving transistor T0.

[0081] For example, such as Figures 2 to 4 As shown in any of the accompanying drawings, the pixel circuit 10 may further include a storage capacitor Cst. When the driving transistor T0 is a P-type transistor, the storage capacitor Cst is connected between the gate of the driving transistor T0 and the first power supply line PVDD; when the driving transistor T0 is an N-type transistor, the storage capacitor Cst is connected between the gate of the driving transistor T0 and the anode of the light-emitting element 20.

[0082] In this application, the first terminal S of the driving transistor T0 can be the source, and the second terminal D of the driving transistor T0 can be the drain.

[0083] P-type transistors may include low-temperature polysilicon (LTP) Silicon (LTPS) transistors. For a P-type transistor, the P-type transistor is turned on when its gate is connected to a low level, and turned off when its gate is connected to a high level.

[0084] N-type transistors can include indium gallium zinc oxide (IGZO) transistors. For an N-type transistor, it is turned on when its gate is connected to a high level and turned off when its gate is connected to a low level.

[0085] Based on the same technical concept, embodiments of this application also provide a display panel. For example... Figure 18 As shown, the display panel 100 provided in this application embodiment includes the pixel circuit 10 described in any of the above embodiments. The display panel 100 also includes a light-emitting element 20. The pixel circuit 10 is connected to the light-emitting element 20 to drive the light-emitting element 20 to emit light.

[0086] The display panel provided in this application embodiment has the beneficial effects of the pixel circuit provided in this application embodiment. For details, please refer to the specific description of the pixel circuit in the above embodiments. This embodiment will not repeat the description here.

[0087] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 19 , Figure 19 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 19 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 19 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0088] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel circuit, characterized in that, It includes a driving transistor, a first transistor, a second transistor, a third transistor, and a fourth transistor; The driving transistor, the first transistor, and the second transistor are connected in series between the first power line and the light-emitting element, and the first transistor is connected to the first terminal of the driving transistor, and the second transistor is connected to the second terminal of the driving transistor. The third transistor is connected in parallel with the first transistor and the driving transistor, which are connected in series. The fourth transistor is connected in parallel with the driving transistor and the second transistor, which are connected in series. The operation of the pixel circuit includes a first stage and a second stage; In the first stage, the first transistor and the second transistor are turned on, while the third transistor and the fourth transistor are turned off; In the second stage, the first transistor and the second transistor are disconnected, while the third transistor and the fourth transistor are turned on.

2. The pixel circuit according to claim 1, characterized in that, The first phase and the second phase alternate.

3. The pixel circuit according to claim 1, characterized in that, The operation of the pixel circuit includes multiple cycles, each cycle including a non-light-emitting phase and a light-emitting phase. The cycle includes a first cycle and a second cycle. The light-emitting phase of the first cycle overlaps with the first phase in time, and the light-emitting phase of the second cycle overlaps with the second phase in time.

4. The pixel circuit according to claim 3, characterized in that, The luminescence phase of the first cycle does not overlap with the second cycle in time, and the luminescence phase of the second cycle does not overlap with the first cycle in time.

5. The pixel circuit according to claim 3, characterized in that, The emission phase of the first cycle overlaps at least partially in time with the emission phase of the second cycle, and the emission phase of the second cycle overlaps at least partially in time with the emission phase of the first cycle.

6. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a data writing transistor and a compensation transistor; the first terminal of the data writing transistor is connected to a data line, and the second terminal of the data writing transistor is connected to the first terminal of the driving transistor through the first transistor; the first terminal of the compensation transistor is connected to the second terminal of the driving transistor through the second transistor, and the second terminal of the compensation transistor is connected to the gate of the driving transistor.

7. The pixel circuit according to claim 6, characterized in that, The operation of the pixel circuit includes multiple cycles, including a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a data writing stage, in which the data writing transistor and the compensation transistor are turned on. The data writing phase overlaps at least partially in time with one of the first phase and the second phase.

8. The pixel circuit according to claim 7, characterized in that, The cycle includes a first cycle and a second cycle, wherein the data writing phase in the first cycle overlaps at least partially with the first phase in time, and the data writing phase in the second cycle overlaps at least partially with the second phase in time.

9. The pixel circuit according to claim 8, characterized in that, The data writing phase in the first cycle does not overlap with the second cycle in time, and the data writing phase in the second cycle does not overlap with the first cycle in time.

10. The pixel circuit according to claim 6, characterized in that, The operation of the pixel circuit includes multiple cycles, and the cycle includes a non-light-emitting phase and a light-emitting phase. The non-luminescent phase overlaps at least partially with the first phase in time, the luminescent phase overlaps at least partially with the second phase in time, and the non-luminescent phase does not overlap with the second phase in time, nor does the luminescent phase overlap with the first phase in time. Alternatively, the non-luminescent phase overlaps at least partially in time with the second phase, the luminescent phase overlaps at least partially in time with the first phase, and the non-luminescent phase does not overlap in time with the first phase, and the luminescent phase does not overlap in time with the second phase.

11. The pixel circuit according to claim 6, characterized in that, The operation of the pixel circuit includes multiple cycles, including a third cycle and a fourth cycle. The third cycle overlaps with the first stage in time, and the fourth cycle overlaps with the second stage in time.

12. The pixel circuit according to any one of claims 1-11, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are of the same type.

13. The pixel circuit according to claim 11, characterized in that, The gates of the first transistor, the second transistor, the third transistor, and the fourth transistor are connected to the same scan line; The first transistor and the second transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors; or, the first transistor and the second transistor are N-type transistors, and the third transistor and the fourth transistor are P-type transistors.

14. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a data writing transistor and a compensation transistor; the first terminal of the data writing transistor is connected to a data line, and the second terminal of the data writing transistor is connected to the first terminal of the driving transistor; the first terminal of the compensation transistor is connected to the second terminal of the driving transistor, and the second terminal of the compensation transistor is connected to the gate of the driving transistor.

15. The pixel circuit according to claim 14, characterized in that, The operation of the pixel circuit includes multiple cycles, including a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a data writing stage, in which the data writing transistor and the compensation transistor are turned on. The data writing phase does not overlap with either the first phase or the second phase in time.

16. The pixel circuit according to claim 15, characterized in that, During the non-light-emitting phase, the first transistor, the second transistor, the third transistor, and the fourth transistor are all turned off.

17. The pixel circuit according to claim 1, characterized in that, The driving transistor is a P-type transistor, the first terminal of the driving transistor is coupled to the first power line, and the second terminal of the driving transistor is coupled to the light-emitting element; Alternatively, the driving transistor is an N-type transistor, with its first terminal coupled to the light-emitting element and its second terminal coupled to the first power line.

18. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes a first reset transistor, which is connected between the first reset signal line and the gate of the driving transistor. And / or, the pixel circuit further includes a second reset transistor connected between the second reset signal line and the light-emitting element.

19. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1-18.

20. A display device, characterized in that, Includes the display panel as described in 19.

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