Display device

Abstract

A display device according to an embodiment includes a display panel including a pad area in which a first driving voltage line and a second driving voltage line spaced apart from the first driving voltage line are disposed, and a first circuit substrate connected to the pad area, wherein an end of the first driving voltage line is aligned with an end of the display panel, and an end of the second driving voltage line is spaced apart from the end of the display panel.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0179346, filed on December 5, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This specification relates to a display device. Background Technology

[0004] With the development of the information society, the demand for display devices that can display images has increased, and various types of display devices such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) displays are being utilized.

[0005] The display panel of the display device may include multiple organic light-emitting elements, and each organic light-emitting element may include an anode, an organic layer, and a cathode. Summary of the Invention

[0006] One object of this specification is to provide a display device that can improve the short circuit between the drive voltage line and adjacent lines by additionally setting dummy lines on both sides of the drive voltage line.

[0007] Another objective of this specification is to provide a display device that can improve lifespan and reduce power consumption by improving the short circuit between the drive voltage line and adjacent lines.

[0008] The purpose of this specification is not limited to the foregoing, and other purposes can be inferred from the following examples.

[0009] A display device according to an embodiment of this specification includes: a display panel, the display panel including a pad area, a first driving voltage line and a second driving voltage line spaced apart from the first driving voltage line arranged in the pad area; and a first circuit board connected to the pad area, wherein the ends of the first driving voltage lines are aligned with the ends of the display panel, and the ends of the second driving voltage lines are spaced apart from the ends of the display panel.

[0010] A display device according to an embodiment of this specification includes: a display panel, the display panel including a pad area, a first driving voltage line and a second driving voltage line spaced apart from the first driving voltage line arranged in the pad area; and a first circuit board connected to the pad area, wherein the ends of the first driving voltage line and the ends of the second driving voltage line are respectively aligned with the ends of the display panel, and dummy lines are arranged on both sides of the first driving voltage line and both sides of the second driving voltage line.

[0011] Specific details of other embodiments are included in the detailed description and the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a display device according to one embodiment;

[0013] Figure 2 This is a plan view showing the rear of a display device according to one embodiment;

[0014] Figure 3 This is a diagram of the circuitry constituting a pixel in a display device according to one embodiment.

[0015] Figure 4 yes Figure 2 Enlarged plan view of region Q1;

[0016] Figure 5 It is along Figure 4 A sectional view taken by line I-I';

[0017] Figure 6 This is a plan view illustrating one process step in a method of manufacturing a display panel according to one embodiment;

[0018] Figure 7 This is a plan view of a display device according to another embodiment;

[0019] Figure 8 It is along Figure 7 A sectional view taken from line II-II'; and

[0020] Figure 9 This is a plan view of a display device according to yet another embodiment. Detailed Implementation

[0021] In the following description, embodiments are illustrated with reference to the accompanying drawings. In the specification, when a component (or region, layer, portion, etc.) is referred to as being "on top of another component," "connected to," or "joined to" another component, this indicates that it may be directly connected / joined to the other component, or that a third component may be located therebetween.

[0022] The same reference numerals denote the same parts. Furthermore, in the drawings, the thickness, scale, and dimensions of parts are exaggerated for the sake of effective description of the technical content. The expression "and / or" is considered to include one or more combinations that can be defined by the associated parts.

[0023] The terms "first," "second," etc., are used to describe various components, but these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of the embodiment, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0024] Terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the parts depicted in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0025] It should also be understood that the terms “comprising,” “having,” etc., are intended to specify the presence of the stated features, figures, steps, operations, components, parts, or combinations thereof, but are not intended to exclude the presence or possibility of one or more other features, figures, steps, operations, components, parts, or combinations thereof.

[0026] Figure 1 This is a schematic diagram of a display device according to one embodiment.

[0027] Reference Figure 1 According to one embodiment, the display device 1 may include: a display panel 100, which is connected to a plurality of gate lines GL and a plurality of data lines DL and is provided with a plurality of pixels PX, wherein the display panel 100 includes a display area DA and a non-display area NDA; a gate driving circuit 200, which provides signals to the plurality of gate lines GL; a first circuit board 300, which supplies data voltage through the plurality of data lines DL; and a timing controller 400, which controls the gate driving circuit 200 and the first circuit board 300.

[0028] The display panel 100 displays images based on scan signals transmitted from the gate drive circuit 200 via multiple gate lines GL and data voltages transmitted from the first circuit board 300 via multiple data lines DL.

[0029] In the case of a liquid crystal display, the display panel 100 includes a liquid crystal layer formed between two substrates and can operate in any known mode, such as twisted nematic mode (TN), vertical alignment mode (VA), in-plane switching mode (IPS), and edge field switching mode (FFS). Conversely, in the case of an organic light-emitting display, the display panel 100 can be implemented using a top-emitting method, a bottom-emitting method, or a dual-emitting method.

[0030] The display panel 100 may include a plurality of pixels PX, and each pixel PX is composed of pixels of different colors such as white (W) sub-pixels, red (R) sub-pixels, green (G) sub-pixels and blue (B) sub-pixels, wherein each pixel PX is defined by a plurality of data lines DL and a plurality of gate lines GL.

[0031] A pixel PX may include: a thin-film transistor (TFT) disposed in a region formed by a data line DL and a gate line GL; a light-emitting element such as a light-emitting diode that emits light based on a data voltage; and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0032] For example, assuming that display device 1 has a resolution of 2600×3840 and four pixels PX constituting a pixel unit, namely white (W) pixel, red (R) pixel, green (G) pixel and blue (B) pixel, display device 1 may be equipped with 2600 gate lines GL and 3840 data lines DL each connected to the four sub-pixels (WRGB), resulting in a total of 3840×4 equals 15360 data lines DL, where the pixels PX are arranged in the area formed by these gate lines GL and data lines DL.

[0033] The gate driving circuit 200 is controlled by the timing controller 400 to sequentially output scanning signals to multiple gate lines GL arranged in the display panel 100, thereby controlling the driving timing of multiple pixels PX.

[0034] In a display device 1 with a resolution of 2600×3840, sequentially outputting scan signals from the first gate line to the 2600th gate line for 2600 gate lines GL is called 2600-phase driving. Alternatively, sequentially outputting scan signals in units of four gate lines GL, for example, sequentially outputting scan signals from the first gate line to the fourth gate line, and then sequentially outputting scan signals from the fifth gate line to the eighth gate line, is called 4-phase driving. That is, sequentially outputting scan signals for every N gate lines GL is called N-phase driving.

[0035] Here, the gate driving circuit 200 may include one or more gate driving integrated circuits (GDICs), and depending on the driving method, the gate driving circuit 200 may be located only on one side or both sides of the display panel 100. Alternatively, the gate driving circuit 200 may be implemented as an in-panel gate (GIP) directly formed in the bezel area of ​​the display panel 100.

[0036] The first circuit board 300 receives digital image data DATA from the timing controller 400 and converts the received digital image data DATA into analog data voltage. Then, by outputting the data voltage to each data line DL in sync with the moment when the scan signal is applied to the gate line GL, each pixel PX connected to the data line DL displays a light emission signal corresponding to the brightness of the data voltage.

[0037] Similarly, the first circuit board 300 may include one or more source driver integrated circuits (SDICs), which may be connected to the bonding pads of the display panel 100 using tape-automated bonding (TAB) or chip-on-glass (COG) methods, or may be directly disposed on the display panel 100.

[0038] In some cases, each source driver integrated circuit (SDIC) can be integrated into and disposed within the display panel 100. Alternatively, each source driver integrated circuit (SDIC) can be implemented as a chip-on-film (COF) circuit, in which each SDIC is mounted on a circuit film and electrically connected to the data line DL of the display panel 100 via the circuit film.

[0039] The timing controller 400 supplies various control signals to the gate drive circuit 200 and the first circuit board 300 to control their operation. That is, the timing controller 400 controls the gate drive circuit 200 to output a scan signal according to the timing implemented for each frame, and also transmits the digital image data DATA received from the outside to the first circuit board 300.

[0040] In this process, the timing controller 400 receives various timing signals, including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the master clock MCLK, as well as digital image data DATA, from an external source (e.g., a host system). Therefore, the timing controller 400 generates control signals based on the received timing signals and transmits them to the gate drive circuit 200 and the first circuit board 300.

[0041] For example, to control the gate drive circuit 200, the timing controller 400 outputs various gate control signals such as the gate start pulse GSP, the gate clock GCLK, and the gate output enable signal GOE. Here, the gate start pulse GSP controls the timing at which one or more gate driver integrated circuits (GDICs) included in the gate drive circuit 200 begin operation. Additionally, the gate clock GCLK is a clock signal commonly supplied to one or more gate driver integrated circuits (GDICs) and controls the shift timing of the scan signal. Furthermore, the gate output enable signal GOE specifies the timing information for one or more gate driver integrated circuits (GDICs).

[0042] In addition, to control the first circuit board 300, the timing controller 400 outputs various data control signals, including a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE. Here, the source start pulse SSP controls the timing of data sampling initiated by one or more source driver integrated circuits (SDICs) included in the first circuit board 300. The source sampling clock SCLK is a clock signal that controls the timing of data sampling in the source driver integrated circuits (SDICs). The source output enable signal SOE controls the output timing of the first circuit board 300.

[0043] The display device 1 may further include a power management integrated circuit (PMIC) that supplies various voltages or currents to components such as the display panel 100, the gate drive circuit 200, and the first circuit board 300, or controls the voltages or currents to be supplied.

[0044] On the other hand, light-emitting elements can be arranged in each pixel PX. For example, an organic light-emitting display device includes a light-emitting element such as a light-emitting diode in each pixel PX, and displays an image by controlling the current flowing through the light-emitting element according to the data voltage.

[0045] Figure 2 This is a plan view showing the rear surface of a display device according to one embodiment;

[0046] exist Figure 2 In one embodiment, the display device 1 includes a source driver integrated circuit (SDIC) implemented in a first circuit board 300 using a chip-on-film (COF) method, and the gate driver circuit 200 is implemented in the form of a gate-in-panel (GIP) in various ways such as tape-on-board (TAB), chip-on-glass (COG), chip-on-film (COF), and gate-in-panel (GIP).

[0047] When the gate drive circuit 200 ( Figure 1When implemented as a gate in-panel (GIP), the multiple gate driver integrated circuits (GDICs) included in the gate driver circuit 200 can be directly formed in the bezel area of ​​the display panel 100. In this case, the gate driver integrated circuits (GDICs) can receive various signals required to generate the scan signal SCAN, such as clock signals, gate high signals, and gate low signals, through gate-driving related signal lines provided in the bezel area.

[0048] Similarly, one or more source driver integrated circuits (SDICs) included in the first circuit board 300 can be mounted on the source film SF, wherein one side of the source film SF is electrically connected to the display panel 100. Additionally, a line for electrically connecting the source driver integrated circuit SDICs to the display panel 100 can be provided on the top of the source film SF.

[0049] The display device 1 may further include: at least one source printed circuit board SPCB (or second circuit board) for circuit connection between multiple source driver integrated circuits SDIC and other devices; and a control printed circuit board CPCB (or third circuit board) for mounting control components and various electronic devices.

[0050] In this configuration, the opposite side of the source film SF, on which the active driver integrated circuit SDIC is mounted, can be connected to at least one source printed circuit board SPCB. That is, the source film SF, on which the active driver integrated circuit SDIC is mounted, can be electrically connected to the display panel 100 on one side and to the source printed circuit board SPCB on the opposite side. For example, multiple source films SF can be connected to a single source printed circuit board SPCB, but this configuration is not limited to.

[0051] The control printed circuit board (CPCB) may include a timing controller 400 and a power management circuit (PMIC) 500. The timing controller 400 can control the operation of the first circuit board 300 and the gate drive circuit 200. The power management circuit 500 can supply drive voltage or current to the display panel 100, the first circuit board 300, and the gate drive circuit 200, and can also control the supplied voltage or current.

[0052] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be electrically connected via at least one connecting member such as a flexible printed circuit board (FPC) or a flexible flat cable (FFC). For example, there can be multiple source printed circuit boards (SPCBs), and multiple source printed circuit boards (SPCBs) can be connected to a single control printed circuit board (CPCB). In this case, a single source printed circuit board (SPCB) can be connected to the control printed circuit board (CPCB) via multiple flexible flat cables (FFCs).

[0053] The display device 1 may further include a set board 700 electrically connected to a control printed circuit board (CPCB). In this case, the set board 700 may also be referred to as a power board. The set board 700 may include a main power management circuit (M-PMC) 600 that manages the total power of the display device 1. The main power management circuit 600 may interact with the power management circuit 500.

[0054] In the display device 1 configured as described above, a driving voltage is generated in the setting board 700 and transmitted to the power management circuit 500 within the control printed circuit board CPCB. The power management circuit 500 transmits the driving voltage required for display driving or feature value sensing to the source printed circuit board SPCB via a flexible printed circuit board FPC or a flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is supplied to specific pixels PX within the display panel 100 via the source driver integrated circuit SDIC for emission or sensing.

[0055] Each pixel PX arranged in the display panel 100 of the display device 1 can be composed of circuit components such as light-emitting elements and driving transistors for driving the light-emitting elements.

[0056] The type and number of circuit components that make up each pixel PX can vary depending on the provided functions and design methods.

[0057] Figure 3 This is a diagram of the circuitry constituting a pixel in a display device according to one embodiment.

[0058] Reference Figure 3 In a display device 1 according to one embodiment, a pixel PX may include one or more transistors, as well as a capacitor, and an organic light-emitting diode may be arranged as a light-emitting element ED.

[0059] For example, a pixel PX may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and a light-emitting element ED.

[0060] The driving transistor DRT may have a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT may be the gate node where a data voltage Vdata is applied from the first circuit board 300 via the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT may be electrically connected to the anode of the light-emitting element ED, and may be either a source node or a drain node. The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL where a driving voltage EVDD is applied, and may be either a drain node or a source node.

[0061] During the display driving period, the driving voltage EVDD required to display the image can be supplied through the driving voltage line DVL. For example, the driving voltage EVDD required to display the image can be 27V.

[0062] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, wherein the gate line GL is connected to the gate node, and the switching transistor SWT operates according to the scan signal SCAN supplied through the gate line GL. Furthermore, when the switching transistor SWT is turned on, it controls the operation of the driving transistor DRT by transmitting the data voltage Vdata supplied via the data line DL to the gate node of the driving transistor DRT.

[0063] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, wherein the gate line GL is connected to the gate node, and the sensing transistor SENT operates according to the sensing signal SENSE supplied through the gate line GL. When the sensing transistor SENT is turned on, the sensing reference voltage Vref supplied through the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0064] In other words, by controlling the switching transistor SWT and the sensing transistor SENT, the voltage at the first node N1 and the second node N2 of the driving transistor DRT is controlled, thereby enabling current to be supplied to drive the light-emitting element ED.

[0065] The gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to the same gate line GL or different gate lines GL. In this embodiment, the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL, which allows the switching transistor SWT and the sensing transistor SENT to be independently controlled by a scan signal SCAN and a sensing signal SENSE transmitted via different gate lines GL.

[0066] Conversely, when the switching transistor SWT and the sensing transistor SENT are connected to the same gate line GL, the switching transistor SWT and the sensing transistor SENT can be simultaneously controlled by the scan signal SCAN or the sensing signal SENSE transmitted via the same gate line GL, which can improve the aperture ratio of the pixel PX.

[0067] On the other hand, the transistors arranged in the pixel PX can include not only n-type transistors but also p-type transistors, and this example shows a configuration using n-type transistors.

[0068] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT to hold the data voltage Vdata for one frame.

[0069] Depending on the type of driving transistor DRT, the storage capacitor Cst can also be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode of the light-emitting element ED can be electrically connected to the second node N2 of the driving transistor DRT, and the cathode of the light-emitting element ED can be supplied with the base voltage EVSS.

[0070] Here, the base voltage EVSS can be ground voltage or a voltage higher or lower than ground voltage. Furthermore, the base voltage EVSS can vary depending on the driving state; for example, the base voltage EVSS during display driving and the base voltage EVSS during sensing driving can be set differently.

[0071] As an example, the structure of pixel PX described above follows a 3T (transistor) lC (capacitor) structure, and is used only as an example; it may include one or more additional transistors, or in some cases, one or more additional capacitors. Alternatively, multiple pixels PX may have the same structure, or a subset of pixels within a pixel PX may have different structures.

[0072] According to one embodiment, the display device 1 can use a current sensing method to measure the current flowing through it by charging the voltage of the storage capacitor Cst in the characteristic value sensing portion of the driving transistor DRT, so as to effectively sense the characteristic value of the driving transistor DRT, such as its threshold voltage or mobility.

[0073] In other words, by measuring the current flowing through the storage capacitor Cst in the feature value sensing section of the driving transistor DRT, the feature value or the change in feature value of the driving transistor DRT in pixel PX can be determined.

[0074] Here, the reference voltage line RVL is not only used to transmit the reference voltage Vref, but can also be used as a sensing line to sense the characteristic value of the driving transistor DRT in the pixel PX. Therefore, the reference voltage line RVL can be called a sensing line.

[0075] Figure 4 yes Figure 2 A magnified plan view of region Q1. Figure 5 It is along Figure 4 A sectional view taken from line I-I'.

[0076] Reference Figure 4 and Figure 5According to one embodiment, the display panel 100 of the display device 1 may include a pad region PA. The pad region PA may be connected to the source film SF of a first circuit board.

[0077] The display panel 100 may include an end extending along a first direction DR1. From the end of the display panel 100, multiple lines may extend on one side along a second direction DR2. For example, the display panel 100 may include a substrate SUB, an insulating layer IL on the substrate SUB, and multiple lines EVL, DL, DVL1, and DVL2 on the insulating layer IL.

[0078] The substrate SUB can be a rigid substrate such as glass or quartz, or a flexible substrate containing plastic materials. For example, the substrate SUB can be a multi-substrate containing multiple plastic materials such as polyimide, but the embodiments in this specification are not limited thereto.

[0079] The substrate SUB may include a back side facing the insulating layer IL and a front side facing the opposite side of the insulating layer IL. A first circuit board may be disposed on the back side of the substrate SUB. The front side of the substrate SUB may be the light-emitting surface of the display device 1. However, the embodiments of this specification are not limited thereto, and lines may also be arranged on the front side of the substrate SUB, with the front side being the light-emitting surface.

[0080] The insulating layer IL can be disposed on the substrate SUB. The insulating layer IL can be formed by alternately stacking silicon nitride (SiN). x ) and silicon dioxide (SiO) x It may be formed by at least one layer, but the embodiments in this specification are not limited thereto.

[0081] Multiple lines can be disposed on the insulating layer IL. These multiple lines may include drive voltage lines DVL1 and DVL2, base voltage line EVL, and data line DL. The drive voltage lines DVL1 and DVL2, base voltage line EVL, and data line DL can be disposed in the pad area PA and can extend towards the edge of the display panel 100.

[0082] The base voltage line EVL can be located on opposite sides of the first direction DR1. In some embodiments, a gate control line can be further provided next to the base voltage line EVL. The end of the base voltage line EVL can be aligned with the end of the display panel 100 (or the end of the substrate SUB).

[0083] The data line DL can be positioned on one side of the base voltage line EVL in the first direction DR1. Figure 4In this specification, a single data line DL is shown arranged on the first direction DR1 of the base voltage line EVL; however, the embodiments described herein are not limited to this, and multiple data lines DL may be arranged on the first direction DR1 of the base voltage line EVL. The ends of the data lines DL may be aligned with the ends of the display panel 100 (or the substrate SUB).

[0084] A first driving voltage line DVL1 can be arranged on one side of the data line DL in the first direction DR1. The first driving voltage line DVL1 and the second driving voltage line DVL2, which will be described later, can extend toward the second direction DR2 and can be electrically connected to each other. That is, the first driving voltage line DVL1 and the second driving voltage line DVL2 can be electrically connected to the pixel PX. The end of the first driving voltage line DVL1 can be aligned with the end of the display panel 100 (or substrate SUB).

[0085] Multiple data lines DL can be arranged on one side of the first drive voltage line DVL1 in the first direction DR1.

[0086] A second driving voltage line DVL2 may be arranged on one side of the multiple data lines DL in the first direction DR1. The end of the second driving voltage line DVL2 may be spaced apart from the end of the display panel 100 (or substrate SUB).

[0087] Multiple data lines DL can be arranged on one side of the second drive voltage line DVL2 in the first direction DRl.

[0088] On one side of the multiple data lines DL in the first direction DR1, a first driving voltage line DVL1 can be arranged. That is, multiple first driving voltage lines DVL1 can be provided, and a second driving voltage line DVL2 can be arranged between the multiple first driving voltage lines DVL1. The end of the first driving voltage line DVL1 can be aligned with the end of the display panel 100 (or substrate SUB).

[0089] On one side of the first driving voltage line DVL1 in the first direction DR1, a data line DL can be arranged, and on one side of the data line DL, a base voltage line EVL can be arranged.

[0090] Data lines DL can be arranged on both sides of the first driving voltage line DVL1 and the second driving voltage line DVL2, but the embodiments in this specification are not limited thereto.

[0091] The source film SF may include multiple source lines C EVL, C DL, CDVL1, and CDVL2, and each source line CEVL, C DL, CDVL1, and CDVL2 may overlap with and be electrically connected to the lines EVL, DL, EVL1, and CDVL2 of the display panel 100. An anisotropic conductive film ACF may be further disposed between the source lines C EVL, C DL, CDVL1, and CDVL2 and the lines EVL, DL, EVL1, and CDVL2 of the display panel 100.

[0092] The end of the source film SF (or the first circuit board) can be spaced apart from the end of the display panel 100. Therefore, the ends of the source lines C EVL, C DL, C DVL1 and C DVL2 can be spaced apart from the end of the display panel 100.

[0093] Figure 6 This is a plan view illustrating the process steps in a method for manufacturing a display panel according to one embodiment.

[0094] Reference Figures 4 to 6 , Figure 6 The display panel 100a of the display device 1a shown can be a panel before being cut along the cutting line CL. That is, the display panel 100a cut along the cutting line CL can be the final product. The first driving voltage line DVL1a of the display panel 100a can extend further in the second direction DR2 to the opposite side of the cutting line CL. The first driving voltage line DVL1a extending in the second direction DR2 to the opposite side of the cutting line CL can be connected to a test line TL. The test line TL can extend in the first direction DR1 and can be connected to a test pad TP located at one end of the first direction DR1 and the opposite end of the first direction DR1. A predetermined test driving voltage can be applied to the test pad TP, so that defects in the first driving voltage line DVL1a can be tested.

[0095] when Figure 6 When the display panel 100a is cut, the end of the first driving voltage line DVL1a can be aligned with the end of the display panel 100 (or substrate SUB), such as... Figure 4 The display panel 100 is shown.

[0096] In the following description, a display device according to other embodiments will be provided. References will be omitted when explaining the following embodiments. Figures 1 to 6 A detailed description of the same or similar configuration is provided to avoid redundancy.

[0097] Figure 7 This is a plan view of a display device according to another embodiment; Figure 8 It is along Figure 7 The sectional view taken from line II-II'.

[0098] Reference Figure 7 and Figure 8 According to this embodiment, the display panel 101 of the display device 2 may further include dummy lines DML1 and DML2. Each dummy line DML1 and DML2 may be located on opposite sides of the driving voltage lines DVL1 and DVL2. The first dummy line DML1 may be disposed between the first driving voltage line DVL1 and the data line DL, and the second dummy line DML2 may be disposed between the second driving voltage line DVL2 and the data line DL. The dummy lines DML1 and DML2 may not be electrically connected to the pixel PX separately. The dummy lines DML1 and DML2 may overlap with the source film SF. However, the source line of the source film SF that overlaps with the dummy lines DML1 and DML2 may not be provided.

[0099] According to the display device 2 of this embodiment, the display panel 101 can improve the short circuit between the drive voltage lines DVL1 and DVL2 and other adjacent lines (e.g., data lines DL) by further including dummy lines DML1 and DML2.

[0100] The references will be omitted. Figure 4 and Figure 5 Additional descriptions provided.

[0101] Figure 9 This is a plan view of a display device according to yet another embodiment.

[0102] Reference Figure 9 The difference between the display panel 102 of the display device 3 and the display panel 101 of the display device 2 according to this embodiment is that the display panel 102 includes a second driving voltage line DVL2 l.

[0103] More specifically, the end of the second driving voltage line DVL2 1 can be aligned with the end of the display panel 102 (or substrate SUB).

[0104] On the other hand, in the case of the display device 3 according to this embodiment, dummy lines DML1 and DML2 may also be included. Each dummy line DML1 and DML2 may be located on opposite sides of the driving voltage lines DVL1 and DVL2. The first dummy line DML1 may be disposed between the first driving voltage line DVL1 and the data line DL, and the second dummy line DML2 may be disposed between the second driving voltage line DVL2 and the data line DL. Dummy lines DML1 and DML2 may not be electrically connected to the pixel PX separately. Dummy lines DML1 and DML2 may overlap with the source film SF. However, the source line of the source film SF that overlaps with dummy lines DML1 and DML2 may not be provided.

[0105] According to the display device 3 of this embodiment, the display panel 102 can improve the short circuit between the drive voltage lines DVL1 and DVL2 and other adjacent lines (e.g., data lines DL) by further including dummy lines DML1 and DML2.

[0106] Further details are as described above. Figure 7 The above will be omitted in the following text.

[0107] The display device according to various embodiments of this specification can be described as follows.

[0108] A display device according to various embodiments of this specification includes: a display panel including a pad area, a first driving voltage line and a second driving voltage line spaced apart from the first driving voltage line arranged in the pad area; and a first circuit board connected to the pad area, wherein the ends of the first driving voltage lines are aligned with the ends of the display panel, and the ends of the second driving voltage lines are spaced apart from the ends of the display panel.

[0109] In the display device according to various embodiments of this specification, the pad area may further include a third driving voltage line, the third driving voltage line being spaced apart from the first driving voltage line, a second driving voltage line being inserted between the third driving voltage line and the first driving voltage line, and the end of the third driving voltage line being aligned with the end of the display panel.

[0110] In the display device according to various embodiments of this specification, the pad area may further include a plurality of data lines arranged on both sides of the first driving voltage line or the second driving voltage line, and the end of each of the plurality of data lines may be aligned with the end of the display panel.

[0111] In the display device according to various embodiments of this specification, the display panel may further include a display area with pixels arranged thereon, and the first driving voltage line and the second driving voltage line may each be electrically connected to the pixel.

[0112] The display device according to various embodiments of this specification may further include dummy lines arranged on both sides of the first driving voltage line.

[0113] In the display devices according to various embodiments of this specification, the dummy lines may not be electrically connected to the pixels.

[0114] In the display device according to various embodiments of this specification, the dummy line may overlap with the first circuit board.

[0115] In the display device according to various embodiments of this specification, the pad area may further include a plurality of data lines arranged on both sides of the first driving voltage line or the second driving voltage line, and the dummy line may be arranged between the first driving voltage line and the plurality of data lines or between the second driving voltage line and the plurality of data lines.

[0116] In the display devices according to various embodiments of this specification, the pad area is spaced apart from the end of the display panel.

[0117] A display device according to various embodiments of this specification includes: a display panel, the display panel including a pad area, a first driving voltage line and a second driving voltage line spaced apart from the first driving voltage line arranged in the pad area; and a first circuit board connected to the pad area, wherein the ends of the first driving voltage line and the ends of the second driving voltage line are respectively aligned with the ends of the display panel, and dummy lines are arranged on both sides of the first driving voltage line and both sides of the second driving voltage line.

[0118] In the display device according to various embodiments of this specification, the pad area may further include a plurality of data lines arranged on both sides of the first driving voltage line or the second driving voltage line, and the end of each of the plurality of data lines may be aligned with the end of the display panel.

[0119] In the display device according to various embodiments of this specification, the dummy line may be arranged between the first driving voltage line and a plurality of data lines or between the second driving voltage line and a plurality of data lines.

[0120] In the display device according to various embodiments of this specification, the display panel may further include a display area with pixels arranged thereon, and the first driving voltage line and the second driving voltage line may each be electrically connected to the pixel.

[0121] In the display devices according to various embodiments of this specification, the dummy lines may not be electrically connected to the pixels.

[0122] In the display device according to various embodiments of this specification, the dummy line may overlap with the first circuit board.

[0123] In the display devices according to various embodiments of this specification, the pad area is spaced apart from the end of the display panel.

[0124] The embodiments of this specification are advantageous in providing a display device that can improve the short circuit between the driving voltage line and adjacent lines by additionally setting dummy lines on both sides of the driving voltage line.

[0125] The embodiments described herein are advantageous in providing a display device that can improve lifespan and reduce power consumption by improving short circuits between drive voltage lines and adjacent lines.

[0126] The advantages that can be achieved through this specification are not limited to those described above, and those skilled in the art will readily understand from this disclosure other advantages not explicitly described herein.

[0127] Although embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that the described technical configurations can be implemented in other specific forms without altering the technical essence or essential characteristics. Therefore, it should be understood that the above embodiments are exemplary and not limiting in any way. Furthermore, the scope of the embodiments is determined by the appended claims, not by the specific implementation. Any modifications or variations derived from the meaning, scope, and equivalent concepts of the patent claims will be considered to fall within the scope of the embodiments.

[0128] Explanation of reference numerals in the attached figures

[0129] 1, 1a, 2, 3: Display device

[0130] SPCB: Source Printed Circuit Board

[0131] CPCB: Control Printed Circuit Board

[0132] FFC: Flexible Flat Cable

[0133] SF: Source film

[0134] RVL: Reference Voltage Line

[0135] DVL1, DVL2: Drive voltage lines

Claims

1. A display device, comprising: The display panel includes a pad area, in which a first driving voltage line and a second driving voltage line spaced apart from the first driving voltage line are arranged. as well as A first circuit board is connected to the pad area. Wherein, the end of the first driving voltage line is aligned with the end of the display panel, and the end of the second driving voltage line is spaced apart from the end of the display panel.

2. The display device according to claim 1, wherein, The pad area also includes a third driving voltage line, which is spaced apart from the first driving voltage line. A second driving voltage line is located between the third driving voltage line and the first driving voltage line, and the end of the third driving voltage line is aligned with the end of the display panel.

3. The display device according to claim 1, wherein, The pad area also includes multiple data lines arranged on both sides of the first driving voltage line or the second driving voltage line, and the end of each of the multiple data lines is aligned with the end of the display panel.

4. The display device according to claim 1, wherein, The display panel further includes a display area with pixels arranged thereon, and the first driving voltage line and the second driving voltage line are each electrically connected to the pixels.

5. The display device according to claim 4 further includes dummy lines arranged on both sides of the first driving voltage line.

6. The display device according to claim 5, wherein, The dummy line is not electrically connected to the pixel.

7. The display device according to claim 5, wherein, The dummy line overlaps with the first circuit board.

8. The display device according to claim 5, wherein, The pad area also includes multiple data lines arranged on both sides of the first driving voltage line or on both sides of the second driving voltage line, and the dummy line is arranged between the first driving voltage line and the multiple data lines or between the second driving voltage line and the multiple data lines.

9. The display device according to claim 1, wherein, The pad area is spaced apart from the end of the display panel.

10. A display device, comprising: The display panel includes a pad area, a first driving voltage line, and a second driving voltage line spaced apart from the first driving voltage line arranged in the pad area. as well as A first circuit board is connected to the pad area. The ends of the first driving voltage line and the second driving voltage line are respectively aligned with the ends of the display panel, and dummy lines are respectively arranged on both sides of the first driving voltage line and the second driving voltage line.

11. The display device according to claim 10, wherein, The pad area also includes multiple data lines arranged on both sides of the first driving voltage line or the second driving voltage line, and the end of each of the multiple data lines is aligned with the end of the display panel.

12. The display device according to claim 11, wherein, The dummy line is arranged between the first driving voltage line and the plurality of data lines or between the second driving voltage line and the plurality of data lines.

13. The display device according to claim 10, wherein, The display panel further includes a display area with pixels arranged thereon, and the first driving voltage line and the second driving voltage line are each electrically connected to the pixels.

14. The display device according to claim 13, wherein, The dummy line is not electrically connected to the pixel.

15. The display device according to claim 13, wherein, The dummy line overlaps with the first circuit board.

16. The display device according to claim 10, wherein, The pad area is spaced apart from the end of the display panel.

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